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1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/clock/qcom,gcc-msm8960.h>
5#include <dt-bindings/clock/qcom,lcc-msm8960.h>
6#include <dt-bindings/reset/qcom,gcc-msm8960.h>
7#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
8#include <dt-bindings/clock/qcom,rpmcc.h>
9#include <dt-bindings/soc/qcom,gsbi.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12/ {
13 #address-cells = <1>;
14 #size-cells = <1>;
15 model = "Qualcomm APQ8064";
16 compatible = "qcom,apq8064";
17 interrupt-parent = <&intc>;
18
19 reserved-memory {
20 #address-cells = <1>;
21 #size-cells = <1>;
22 ranges;
23
24 smem_region: smem@80000000 {
25 reg = <0x80000000 0x200000>;
26 no-map;
27 };
28
29 wcnss_mem: wcnss@8f000000 {
30 reg = <0x8f000000 0x700000>;
31 no-map;
32 };
33 };
34
35 cpus {
36 #address-cells = <1>;
37 #size-cells = <0>;
38
39 CPU0: cpu@0 {
40 compatible = "qcom,krait";
41 enable-method = "qcom,kpss-acc-v1";
42 device_type = "cpu";
43 reg = <0>;
44 next-level-cache = <&L2>;
45 qcom,acc = <&acc0>;
46 qcom,saw = <&saw0>;
47 cpu-idle-states = <&CPU_SPC>;
48 };
49
50 CPU1: cpu@1 {
51 compatible = "qcom,krait";
52 enable-method = "qcom,kpss-acc-v1";
53 device_type = "cpu";
54 reg = <1>;
55 next-level-cache = <&L2>;
56 qcom,acc = <&acc1>;
57 qcom,saw = <&saw1>;
58 cpu-idle-states = <&CPU_SPC>;
59 };
60
61 CPU2: cpu@2 {
62 compatible = "qcom,krait";
63 enable-method = "qcom,kpss-acc-v1";
64 device_type = "cpu";
65 reg = <2>;
66 next-level-cache = <&L2>;
67 qcom,acc = <&acc2>;
68 qcom,saw = <&saw2>;
69 cpu-idle-states = <&CPU_SPC>;
70 };
71
72 CPU3: cpu@3 {
73 compatible = "qcom,krait";
74 enable-method = "qcom,kpss-acc-v1";
75 device_type = "cpu";
76 reg = <3>;
77 next-level-cache = <&L2>;
78 qcom,acc = <&acc3>;
79 qcom,saw = <&saw3>;
80 cpu-idle-states = <&CPU_SPC>;
81 };
82
83 L2: l2-cache {
84 compatible = "cache";
85 cache-level = <2>;
86 cache-unified;
87 };
88
89 idle-states {
90 CPU_SPC: spc {
91 compatible = "qcom,idle-state-spc",
92 "arm,idle-state";
93 entry-latency-us = <400>;
94 exit-latency-us = <900>;
95 min-residency-us = <3000>;
96 };
97 };
98 };
99
100 memory@0 {
101 device_type = "memory";
102 reg = <0x0 0x0>;
103 };
104
105 thermal-zones {
106 cpu0-thermal {
107 polling-delay-passive = <250>;
108 polling-delay = <1000>;
109
110 thermal-sensors = <&tsens 7>;
111 coefficients = <1199 0>;
112
113 trips {
114 cpu_alert0: trip0 {
115 temperature = <75000>;
116 hysteresis = <2000>;
117 type = "passive";
118 };
119 cpu_crit0: trip1 {
120 temperature = <110000>;
121 hysteresis = <2000>;
122 type = "critical";
123 };
124 };
125 };
126
127 cpu1-thermal {
128 polling-delay-passive = <250>;
129 polling-delay = <1000>;
130
131 thermal-sensors = <&tsens 8>;
132 coefficients = <1132 0>;
133
134 trips {
135 cpu_alert1: trip0 {
136 temperature = <75000>;
137 hysteresis = <2000>;
138 type = "passive";
139 };
140 cpu_crit1: trip1 {
141 temperature = <110000>;
142 hysteresis = <2000>;
143 type = "critical";
144 };
145 };
146 };
147
148 cpu2-thermal {
149 polling-delay-passive = <250>;
150 polling-delay = <1000>;
151
152 thermal-sensors = <&tsens 9>;
153 coefficients = <1199 0>;
154
155 trips {
156 cpu_alert2: trip0 {
157 temperature = <75000>;
158 hysteresis = <2000>;
159 type = "passive";
160 };
161 cpu_crit2: trip1 {
162 temperature = <110000>;
163 hysteresis = <2000>;
164 type = "critical";
165 };
166 };
167 };
168
169 cpu3-thermal {
170 polling-delay-passive = <250>;
171 polling-delay = <1000>;
172
173 thermal-sensors = <&tsens 10>;
174 coefficients = <1132 0>;
175
176 trips {
177 cpu_alert3: trip0 {
178 temperature = <75000>;
179 hysteresis = <2000>;
180 type = "passive";
181 };
182 cpu_crit3: trip1 {
183 temperature = <110000>;
184 hysteresis = <2000>;
185 type = "critical";
186 };
187 };
188 };
189 };
190
191 cpu-pmu {
192 compatible = "qcom,krait-pmu";
193 interrupts = <1 10 0x304>;
194 };
195
196 clocks {
197 cxo_board: cxo_board {
198 compatible = "fixed-clock";
199 #clock-cells = <0>;
200 clock-frequency = <19200000>;
201 };
202
203 pxo_board: pxo_board {
204 compatible = "fixed-clock";
205 #clock-cells = <0>;
206 clock-frequency = <27000000>;
207 };
208
209 sleep_clk: sleep_clk {
210 compatible = "fixed-clock";
211 #clock-cells = <0>;
212 clock-frequency = <32768>;
213 };
214 };
215
216 sfpb_mutex: hwmutex {
217 compatible = "qcom,sfpb-mutex";
218 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
219 #hwlock-cells = <1>;
220 };
221
222 smem {
223 compatible = "qcom,smem";
224 memory-region = <&smem_region>;
225
226 hwlocks = <&sfpb_mutex 3>;
227 };
228
229 smsm {
230 compatible = "qcom,smsm";
231
232 #address-cells = <1>;
233 #size-cells = <0>;
234
235 qcom,ipc-1 = <&l2cc 8 4>;
236 qcom,ipc-2 = <&l2cc 8 14>;
237 qcom,ipc-3 = <&l2cc 8 23>;
238 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
239
240 apps_smsm: apps@0 {
241 reg = <0>;
242 #qcom,smem-state-cells = <1>;
243 };
244
245 modem_smsm: modem@1 {
246 reg = <1>;
247 interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
248
249 interrupt-controller;
250 #interrupt-cells = <2>;
251 };
252
253 q6_smsm: q6@2 {
254 reg = <2>;
255 interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
256
257 interrupt-controller;
258 #interrupt-cells = <2>;
259 };
260
261 wcnss_smsm: wcnss@3 {
262 reg = <3>;
263 interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
264
265 interrupt-controller;
266 #interrupt-cells = <2>;
267 };
268
269 dsps_smsm: dsps@4 {
270 reg = <4>;
271 interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
272
273 interrupt-controller;
274 #interrupt-cells = <2>;
275 };
276 };
277
278 firmware {
279 scm {
280 compatible = "qcom,scm-apq8064", "qcom,scm";
281
282 clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>;
283 clock-names = "core";
284 };
285 };
286
287 soc: soc {
288 #address-cells = <1>;
289 #size-cells = <1>;
290 ranges;
291 compatible = "simple-bus";
292
293 tlmm_pinmux: pinctrl@800000 {
294 compatible = "qcom,apq8064-pinctrl";
295 reg = <0x800000 0x4000>;
296
297 gpio-controller;
298 gpio-ranges = <&tlmm_pinmux 0 0 90>;
299 #gpio-cells = <2>;
300 interrupt-controller;
301 #interrupt-cells = <2>;
302 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
303
304 pinctrl-names = "default";
305 pinctrl-0 = <&ps_hold>;
306 };
307
308 sfpb_wrapper_mutex: syscon@1200000 {
309 compatible = "syscon";
310 reg = <0x01200000 0x8000>;
311 };
312
313 intc: interrupt-controller@2000000 {
314 compatible = "qcom,msm-qgic2";
315 interrupt-controller;
316 #interrupt-cells = <3>;
317 reg = <0x02000000 0x1000>,
318 <0x02002000 0x1000>;
319 };
320
321 timer@200a000 {
322 compatible = "qcom,kpss-wdt-apq8064", "qcom,kpss-timer",
323 "qcom,msm-timer";
324 interrupts = <1 1 0x301>,
325 <1 2 0x301>,
326 <1 3 0x301>;
327 reg = <0x0200a000 0x100>;
328 clock-frequency = <27000000>;
329 cpu-offset = <0x80000>;
330 };
331
332 acc0: clock-controller@2088000 {
333 compatible = "qcom,kpss-acc-v1";
334 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
335 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
336 clock-names = "pll8_vote", "pxo";
337 clock-output-names = "acpu0_aux";
338 #clock-cells = <0>;
339 };
340
341 acc1: clock-controller@2098000 {
342 compatible = "qcom,kpss-acc-v1";
343 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
344 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
345 clock-names = "pll8_vote", "pxo";
346 clock-output-names = "acpu1_aux";
347 #clock-cells = <0>;
348 };
349
350 acc2: clock-controller@20a8000 {
351 compatible = "qcom,kpss-acc-v1";
352 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
353 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
354 clock-names = "pll8_vote", "pxo";
355 clock-output-names = "acpu2_aux";
356 #clock-cells = <0>;
357 };
358
359 acc3: clock-controller@20b8000 {
360 compatible = "qcom,kpss-acc-v1";
361 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
362 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
363 clock-names = "pll8_vote", "pxo";
364 clock-output-names = "acpu3_aux";
365 #clock-cells = <0>;
366 };
367
368 saw0: power-controller@2089000 {
369 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
370 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
371 regulator;
372 };
373
374 saw1: power-controller@2099000 {
375 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
376 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
377 regulator;
378 };
379
380 saw2: power-controller@20a9000 {
381 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
382 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
383 regulator;
384 };
385
386 saw3: power-controller@20b9000 {
387 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
388 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
389 regulator;
390 };
391
392 sps_sic_non_secure: sps-sic-non-secure@12100000 {
393 compatible = "syscon";
394 reg = <0x12100000 0x10000>;
395 };
396
397 gsbi1: gsbi@12440000 {
398 status = "disabled";
399 compatible = "qcom,gsbi-v1.0.0";
400 cell-index = <1>;
401 reg = <0x12440000 0x100>;
402 clocks = <&gcc GSBI1_H_CLK>;
403 clock-names = "iface";
404 #address-cells = <1>;
405 #size-cells = <1>;
406 ranges;
407
408 syscon-tcsr = <&tcsr>;
409
410 gsbi1_serial: serial@12450000 {
411 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
412 reg = <0x12450000 0x100>,
413 <0x12400000 0x03>;
414 interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
416 clock-names = "core", "iface";
417 status = "disabled";
418 };
419
420 gsbi1_i2c: i2c@12460000 {
421 compatible = "qcom,i2c-qup-v1.1.1";
422 pinctrl-0 = <&i2c1_pins>;
423 pinctrl-1 = <&i2c1_pins_sleep>;
424 pinctrl-names = "default", "sleep";
425 reg = <0x12460000 0x1000>;
426 interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
428 clock-names = "core", "iface";
429 #address-cells = <1>;
430 #size-cells = <0>;
431 status = "disabled";
432 };
433
434 };
435
436 gsbi2: gsbi@12480000 {
437 status = "disabled";
438 compatible = "qcom,gsbi-v1.0.0";
439 cell-index = <2>;
440 reg = <0x12480000 0x100>;
441 clocks = <&gcc GSBI2_H_CLK>;
442 clock-names = "iface";
443 #address-cells = <1>;
444 #size-cells = <1>;
445 ranges;
446
447 syscon-tcsr = <&tcsr>;
448
449 gsbi2_i2c: i2c@124a0000 {
450 compatible = "qcom,i2c-qup-v1.1.1";
451 reg = <0x124a0000 0x1000>;
452 pinctrl-0 = <&i2c2_pins>;
453 pinctrl-1 = <&i2c2_pins_sleep>;
454 pinctrl-names = "default", "sleep";
455 interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
457 clock-names = "core", "iface";
458 #address-cells = <1>;
459 #size-cells = <0>;
460 status = "disabled";
461 };
462 };
463
464 gsbi3: gsbi@16200000 {
465 status = "disabled";
466 compatible = "qcom,gsbi-v1.0.0";
467 cell-index = <3>;
468 reg = <0x16200000 0x100>;
469 clocks = <&gcc GSBI3_H_CLK>;
470 clock-names = "iface";
471 #address-cells = <1>;
472 #size-cells = <1>;
473 ranges;
474 gsbi3_i2c: i2c@16280000 {
475 compatible = "qcom,i2c-qup-v1.1.1";
476 pinctrl-0 = <&i2c3_pins>;
477 pinctrl-1 = <&i2c3_pins_sleep>;
478 pinctrl-names = "default", "sleep";
479 reg = <0x16280000 0x1000>;
480 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&gcc GSBI3_QUP_CLK>,
482 <&gcc GSBI3_H_CLK>;
483 clock-names = "core", "iface";
484 #address-cells = <1>;
485 #size-cells = <0>;
486 status = "disabled";
487 };
488 };
489
490 gsbi4: gsbi@16300000 {
491 status = "disabled";
492 compatible = "qcom,gsbi-v1.0.0";
493 cell-index = <4>;
494 reg = <0x16300000 0x03>;
495 clocks = <&gcc GSBI4_H_CLK>;
496 clock-names = "iface";
497 #address-cells = <1>;
498 #size-cells = <1>;
499 ranges;
500
501 gsbi4_serial: serial@16340000 {
502 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
503 reg = <0x16340000 0x100>,
504 <0x16300000 0x3>;
505 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
506 pinctrl-0 = <&gsbi4_uart_pin_a>;
507 pinctrl-names = "default";
508 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
509 clock-names = "core", "iface";
510 status = "disabled";
511 };
512
513 gsbi4_i2c: i2c@16380000 {
514 compatible = "qcom,i2c-qup-v1.1.1";
515 pinctrl-0 = <&i2c4_pins>;
516 pinctrl-1 = <&i2c4_pins_sleep>;
517 pinctrl-names = "default", "sleep";
518 reg = <0x16380000 0x1000>;
519 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
520 clocks = <&gcc GSBI4_QUP_CLK>,
521 <&gcc GSBI4_H_CLK>;
522 clock-names = "core", "iface";
523 status = "disabled";
524 };
525 };
526
527 gsbi5: gsbi@1a200000 {
528 status = "disabled";
529 compatible = "qcom,gsbi-v1.0.0";
530 cell-index = <5>;
531 reg = <0x1a200000 0x03>;
532 clocks = <&gcc GSBI5_H_CLK>;
533 clock-names = "iface";
534 #address-cells = <1>;
535 #size-cells = <1>;
536 ranges;
537
538 gsbi5_serial: serial@1a240000 {
539 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
540 reg = <0x1a240000 0x100>,
541 <0x1a200000 0x03>;
542 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
544 clock-names = "core", "iface";
545 status = "disabled";
546 };
547
548 gsbi5_spi: spi@1a280000 {
549 compatible = "qcom,spi-qup-v1.1.1";
550 reg = <0x1a280000 0x1000>;
551 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
552 pinctrl-0 = <&spi5_default>;
553 pinctrl-1 = <&spi5_sleep>;
554 pinctrl-names = "default", "sleep";
555 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
556 clock-names = "core", "iface";
557 status = "disabled";
558 #address-cells = <1>;
559 #size-cells = <0>;
560 };
561 };
562
563 gsbi6: gsbi@16500000 {
564 status = "disabled";
565 compatible = "qcom,gsbi-v1.0.0";
566 cell-index = <6>;
567 reg = <0x16500000 0x03>;
568 clocks = <&gcc GSBI6_H_CLK>;
569 clock-names = "iface";
570 #address-cells = <1>;
571 #size-cells = <1>;
572 ranges;
573
574 gsbi6_serial: serial@16540000 {
575 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
576 reg = <0x16540000 0x100>,
577 <0x16500000 0x03>;
578 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
579 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
580 clock-names = "core", "iface";
581 status = "disabled";
582 };
583
584 gsbi6_i2c: i2c@16580000 {
585 compatible = "qcom,i2c-qup-v1.1.1";
586 pinctrl-0 = <&i2c6_pins>;
587 pinctrl-1 = <&i2c6_pins_sleep>;
588 pinctrl-names = "default", "sleep";
589 reg = <0x16580000 0x1000>;
590 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
591 clocks = <&gcc GSBI6_QUP_CLK>,
592 <&gcc GSBI6_H_CLK>;
593 clock-names = "core", "iface";
594 status = "disabled";
595 };
596 };
597
598 gsbi7: gsbi@16600000 {
599 status = "disabled";
600 compatible = "qcom,gsbi-v1.0.0";
601 cell-index = <7>;
602 reg = <0x16600000 0x100>;
603 clocks = <&gcc GSBI7_H_CLK>;
604 clock-names = "iface";
605 #address-cells = <1>;
606 #size-cells = <1>;
607 ranges;
608 syscon-tcsr = <&tcsr>;
609
610 gsbi7_serial: serial@16640000 {
611 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
612 reg = <0x16640000 0x1000>,
613 <0x16600000 0x1000>;
614 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
615 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
616 clock-names = "core", "iface";
617 status = "disabled";
618 };
619
620 gsbi7_i2c: i2c@16680000 {
621 compatible = "qcom,i2c-qup-v1.1.1";
622 pinctrl-0 = <&i2c7_pins>;
623 pinctrl-1 = <&i2c7_pins_sleep>;
624 pinctrl-names = "default", "sleep";
625 reg = <0x16680000 0x1000>;
626 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
627 clocks = <&gcc GSBI7_QUP_CLK>,
628 <&gcc GSBI7_H_CLK>;
629 clock-names = "core", "iface";
630 status = "disabled";
631 };
632 };
633
634 rng@1a500000 {
635 compatible = "qcom,prng";
636 reg = <0x1a500000 0x200>;
637 clocks = <&gcc PRNG_CLK>;
638 clock-names = "core";
639 };
640
641 ssbi2: ssbi@c00000 {
642 compatible = "qcom,ssbi";
643 reg = <0x00c00000 0x1000>;
644 qcom,controller-type = "pmic-arbiter";
645 };
646
647 ssbi: ssbi@500000 {
648 compatible = "qcom,ssbi";
649 reg = <0x00500000 0x1000>;
650 qcom,controller-type = "pmic-arbiter";
651 };
652
653 qfprom: qfprom@700000 {
654 compatible = "qcom,apq8064-qfprom", "qcom,qfprom";
655 reg = <0x00700000 0x1000>;
656 #address-cells = <1>;
657 #size-cells = <1>;
658 ranges;
659 tsens_calib: calib@404 {
660 reg = <0x404 0x10>;
661 };
662 tsens_backup: backup_calib@414 {
663 reg = <0x414 0x10>;
664 };
665 };
666
667 gcc: clock-controller@900000 {
668 compatible = "qcom,gcc-apq8064", "syscon";
669 reg = <0x00900000 0x4000>;
670 #clock-cells = <1>;
671 #power-domain-cells = <1>;
672 #reset-cells = <1>;
673 clocks = <&cxo_board>,
674 <&pxo_board>,
675 <&lcc PLL4>;
676 clock-names = "cxo", "pxo", "pll4";
677
678 tsens: thermal-sensor {
679 compatible = "qcom,msm8960-tsens";
680
681 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
682 nvmem-cell-names = "calib", "calib_backup";
683 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
684 interrupt-names = "uplow";
685
686 #qcom,sensors = <11>;
687 #thermal-sensor-cells = <1>;
688 };
689 };
690
691 lcc: clock-controller@28000000 {
692 compatible = "qcom,lcc-apq8064";
693 reg = <0x28000000 0x1000>;
694 #clock-cells = <1>;
695 #reset-cells = <1>;
696 clocks = <&pxo_board>,
697 <&gcc PLL4_VOTE>,
698 <0>,
699 <0>, <0>,
700 <0>, <0>,
701 <0>;
702 clock-names = "pxo",
703 "pll4_vote",
704 "mi2s_codec_clk",
705 "codec_i2s_mic_codec_clk",
706 "spare_i2s_mic_codec_clk",
707 "codec_i2s_spkr_codec_clk",
708 "spare_i2s_spkr_codec_clk",
709 "pcm_codec_clk";
710 };
711
712 mmcc: clock-controller@4000000 {
713 compatible = "qcom,mmcc-apq8064";
714 reg = <0x4000000 0x1000>;
715 #clock-cells = <1>;
716 #power-domain-cells = <1>;
717 #reset-cells = <1>;
718 clocks = <&pxo_board>,
719 <&gcc PLL3>,
720 <&gcc PLL8_VOTE>,
721 <&dsi0_phy 1>,
722 <&dsi0_phy 0>,
723 <&dsi1_phy 1>,
724 <&dsi1_phy 0>,
725 <&hdmi_phy>;
726 clock-names = "pxo",
727 "pll3",
728 "pll8_vote",
729 "dsi1pll",
730 "dsi1pllbyte",
731 "dsi2pll",
732 "dsi2pllbyte",
733 "hdmipll";
734 };
735
736 l2cc: clock-controller@2011000 {
737 compatible = "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc", "syscon";
738 reg = <0x2011000 0x1000>;
739 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
740 clock-names = "pll8_vote", "pxo";
741 #clock-cells = <0>;
742 };
743
744 rpm: rpm@108000 {
745 compatible = "qcom,rpm-apq8064";
746 reg = <0x108000 0x1000>;
747 qcom,ipc = <&l2cc 0x8 2>;
748
749 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
750 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
751 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
752 interrupt-names = "ack", "err", "wakeup";
753
754 rpmcc: clock-controller {
755 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
756 #clock-cells = <1>;
757 clocks = <&pxo_board>, <&cxo_board>;
758 clock-names = "pxo", "cxo";
759 };
760 };
761
762 usb1: usb@12500000 {
763 compatible = "qcom,ci-hdrc";
764 reg = <0x12500000 0x200>,
765 <0x12500200 0x200>;
766 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
767 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
768 clock-names = "core", "iface";
769 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
770 assigned-clock-rates = <60000000>;
771 resets = <&gcc USB_HS1_RESET>;
772 reset-names = "core";
773 phy_type = "ulpi";
774 ahb-burst-config = <0>;
775 phys = <&usb_hs1_phy>;
776 phy-names = "usb-phy";
777 status = "disabled";
778 #reset-cells = <1>;
779
780 ulpi {
781 usb_hs1_phy: phy {
782 compatible = "qcom,usb-hs-phy-apq8064",
783 "qcom,usb-hs-phy";
784 clocks = <&sleep_clk>, <&cxo_board>;
785 clock-names = "sleep", "ref";
786 resets = <&usb1 0>;
787 reset-names = "por";
788 #phy-cells = <0>;
789 };
790 };
791 };
792
793 usb3: usb@12520000 {
794 compatible = "qcom,ci-hdrc";
795 reg = <0x12520000 0x200>,
796 <0x12520200 0x200>;
797 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
798 clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>;
799 clock-names = "core", "iface";
800 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
801 assigned-clock-rates = <60000000>;
802 resets = <&gcc USB_HS3_RESET>;
803 reset-names = "core";
804 phy_type = "ulpi";
805 ahb-burst-config = <0>;
806 phys = <&usb_hs3_phy>;
807 phy-names = "usb-phy";
808 status = "disabled";
809 #reset-cells = <1>;
810
811 ulpi {
812 usb_hs3_phy: phy {
813 compatible = "qcom,usb-hs-phy-apq8064",
814 "qcom,usb-hs-phy";
815 #phy-cells = <0>;
816 clocks = <&sleep_clk>, <&cxo_board>;
817 clock-names = "sleep", "ref";
818 resets = <&usb3 0>;
819 reset-names = "por";
820 };
821 };
822 };
823
824 usb4: usb@12530000 {
825 compatible = "qcom,ci-hdrc";
826 reg = <0x12530000 0x200>,
827 <0x12530200 0x200>;
828 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
829 clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>;
830 clock-names = "core", "iface";
831 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
832 assigned-clock-rates = <60000000>;
833 resets = <&gcc USB_HS4_RESET>;
834 reset-names = "core";
835 phy_type = "ulpi";
836 ahb-burst-config = <0>;
837 phys = <&usb_hs4_phy>;
838 phy-names = "usb-phy";
839 status = "disabled";
840 #reset-cells = <1>;
841
842 ulpi {
843 usb_hs4_phy: phy {
844 compatible = "qcom,usb-hs-phy-apq8064",
845 "qcom,usb-hs-phy";
846 #phy-cells = <0>;
847 clocks = <&sleep_clk>, <&cxo_board>;
848 clock-names = "sleep", "ref";
849 resets = <&usb4 0>;
850 reset-names = "por";
851 };
852 };
853 };
854
855 sata_phy0: phy@1b400000 {
856 compatible = "qcom,apq8064-sata-phy";
857 status = "disabled";
858 reg = <0x1b400000 0x200>;
859 reg-names = "phy_mem";
860 clocks = <&gcc SATA_PHY_CFG_CLK>;
861 clock-names = "cfg";
862 #phy-cells = <0>;
863 };
864
865 sata0: sata@29000000 {
866 compatible = "qcom,apq8064-ahci", "generic-ahci";
867 status = "disabled";
868 reg = <0x29000000 0x180>;
869 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
870
871 clocks = <&gcc SFAB_SATA_S_H_CLK>,
872 <&gcc SATA_H_CLK>,
873 <&gcc SATA_A_CLK>,
874 <&gcc SATA_RXOOB_CLK>,
875 <&gcc SATA_PMALIVE_CLK>;
876 clock-names = "slave_iface",
877 "iface",
878 "bus",
879 "rxoob",
880 "core_pmalive";
881
882 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
883 <&gcc SATA_PMALIVE_CLK>;
884 assigned-clock-rates = <100000000>, <100000000>;
885
886 phys = <&sata_phy0>;
887 phy-names = "sata-phy";
888 ports-implemented = <0x1>;
889 };
890
891 sdcc3: mmc@12180000 {
892 compatible = "arm,pl18x", "arm,primecell";
893 arm,primecell-periphid = <0x00051180>;
894 status = "disabled";
895 reg = <0x12180000 0x2000>;
896 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
897 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
898 clock-names = "mclk", "apb_pclk";
899 bus-width = <4>;
900 cap-sd-highspeed;
901 cap-mmc-highspeed;
902 max-frequency = <192000000>;
903 no-1-8-v;
904 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
905 dma-names = "tx", "rx";
906 };
907
908 sdcc3bam: dma-controller@12182000 {
909 compatible = "qcom,bam-v1.3.0";
910 reg = <0x12182000 0x8000>;
911 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
912 clocks = <&gcc SDC3_H_CLK>;
913 clock-names = "bam_clk";
914 #dma-cells = <1>;
915 qcom,ee = <0>;
916 };
917
918 sdcc4: mmc@121c0000 {
919 compatible = "arm,pl18x", "arm,primecell";
920 arm,primecell-periphid = <0x00051180>;
921 status = "disabled";
922 reg = <0x121c0000 0x2000>;
923 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
924 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
925 clock-names = "mclk", "apb_pclk";
926 bus-width = <4>;
927 cap-sd-highspeed;
928 cap-mmc-highspeed;
929 max-frequency = <48000000>;
930 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
931 dma-names = "tx", "rx";
932 pinctrl-names = "default";
933 pinctrl-0 = <&sdc4_gpios>;
934 };
935
936 sdcc4bam: dma-controller@121c2000 {
937 compatible = "qcom,bam-v1.3.0";
938 reg = <0x121c2000 0x8000>;
939 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
940 clocks = <&gcc SDC4_H_CLK>;
941 clock-names = "bam_clk";
942 #dma-cells = <1>;
943 qcom,ee = <0>;
944 };
945
946 sdcc1: mmc@12400000 {
947 status = "disabled";
948 compatible = "arm,pl18x", "arm,primecell";
949 pinctrl-names = "default";
950 pinctrl-0 = <&sdcc1_pins>;
951 arm,primecell-periphid = <0x00051180>;
952 reg = <0x12400000 0x2000>;
953 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
954 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
955 clock-names = "mclk", "apb_pclk";
956 bus-width = <8>;
957 max-frequency = <96000000>;
958 non-removable;
959 cap-sd-highspeed;
960 cap-mmc-highspeed;
961 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
962 dma-names = "tx", "rx";
963 };
964
965 sdcc1bam: dma-controller@12402000 {
966 compatible = "qcom,bam-v1.3.0";
967 reg = <0x12402000 0x8000>;
968 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
969 clocks = <&gcc SDC1_H_CLK>;
970 clock-names = "bam_clk";
971 #dma-cells = <1>;
972 qcom,ee = <0>;
973 };
974
975 tcsr: syscon@1a400000 {
976 compatible = "qcom,tcsr-apq8064", "syscon";
977 reg = <0x1a400000 0x100>;
978 };
979
980 gpu: adreno-3xx@4300000 {
981 compatible = "qcom,adreno-320.2", "qcom,adreno";
982 reg = <0x04300000 0x20000>;
983 reg-names = "kgsl_3d0_reg_memory";
984 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
985 interrupt-names = "kgsl_3d0_irq";
986 clock-names =
987 "core",
988 "iface",
989 "mem",
990 "mem_iface";
991 clocks =
992 <&mmcc GFX3D_CLK>,
993 <&mmcc GFX3D_AHB_CLK>,
994 <&mmcc GFX3D_AXI_CLK>,
995 <&mmcc MMSS_IMEM_AHB_CLK>;
996
997 iommus = <&gfx3d 0
998 &gfx3d 1
999 &gfx3d 2
1000 &gfx3d 3
1001 &gfx3d 4
1002 &gfx3d 5
1003 &gfx3d 6
1004 &gfx3d 7
1005 &gfx3d 8
1006 &gfx3d 9
1007 &gfx3d 10
1008 &gfx3d 11
1009 &gfx3d 12
1010 &gfx3d 13
1011 &gfx3d 14
1012 &gfx3d 15
1013 &gfx3d 16
1014 &gfx3d 17
1015 &gfx3d 18
1016 &gfx3d 19
1017 &gfx3d 20
1018 &gfx3d 21
1019 &gfx3d 22
1020 &gfx3d 23
1021 &gfx3d 24
1022 &gfx3d 25
1023 &gfx3d 26
1024 &gfx3d 27
1025 &gfx3d 28
1026 &gfx3d 29
1027 &gfx3d 30
1028 &gfx3d 31
1029 &gfx3d1 0
1030 &gfx3d1 1
1031 &gfx3d1 2
1032 &gfx3d1 3
1033 &gfx3d1 4
1034 &gfx3d1 5
1035 &gfx3d1 6
1036 &gfx3d1 7
1037 &gfx3d1 8
1038 &gfx3d1 9
1039 &gfx3d1 10
1040 &gfx3d1 11
1041 &gfx3d1 12
1042 &gfx3d1 13
1043 &gfx3d1 14
1044 &gfx3d1 15
1045 &gfx3d1 16
1046 &gfx3d1 17
1047 &gfx3d1 18
1048 &gfx3d1 19
1049 &gfx3d1 20
1050 &gfx3d1 21
1051 &gfx3d1 22
1052 &gfx3d1 23
1053 &gfx3d1 24
1054 &gfx3d1 25
1055 &gfx3d1 26
1056 &gfx3d1 27
1057 &gfx3d1 28
1058 &gfx3d1 29
1059 &gfx3d1 30
1060 &gfx3d1 31>;
1061
1062 operating-points-v2 = <&gpu_opp_table>;
1063
1064 gpu_opp_table: opp-table {
1065 compatible = "operating-points-v2";
1066
1067 opp-450000000 {
1068 opp-hz = /bits/ 64 <450000000>;
1069 };
1070
1071 opp-27000000 {
1072 opp-hz = /bits/ 64 <27000000>;
1073 };
1074 };
1075 };
1076
1077 mmss_sfpb: syscon@5700000 {
1078 compatible = "syscon";
1079 reg = <0x5700000 0x70>;
1080 };
1081
1082 dsi0: dsi@4700000 {
1083 compatible = "qcom,apq8064-dsi-ctrl",
1084 "qcom,mdss-dsi-ctrl";
1085 #address-cells = <1>;
1086 #size-cells = <0>;
1087 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1088 reg = <0x04700000 0x200>;
1089 reg-names = "dsi_ctrl";
1090
1091 clocks = <&mmcc DSI_M_AHB_CLK>,
1092 <&mmcc DSI_S_AHB_CLK>,
1093 <&mmcc AMP_AHB_CLK>,
1094 <&mmcc DSI_CLK>,
1095 <&mmcc DSI1_BYTE_CLK>,
1096 <&mmcc DSI_PIXEL_CLK>,
1097 <&mmcc DSI1_ESC_CLK>;
1098 clock-names = "iface", "bus", "core_mmss",
1099 "src", "byte", "pixel",
1100 "core";
1101
1102 assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
1103 <&mmcc DSI1_ESC_SRC>,
1104 <&mmcc DSI_SRC>,
1105 <&mmcc DSI_PIXEL_SRC>;
1106 assigned-clock-parents = <&dsi0_phy 0>,
1107 <&dsi0_phy 0>,
1108 <&dsi0_phy 1>,
1109 <&dsi0_phy 1>;
1110 syscon-sfpb = <&mmss_sfpb>;
1111 phys = <&dsi0_phy>;
1112 status = "disabled";
1113
1114 ports {
1115 #address-cells = <1>;
1116 #size-cells = <0>;
1117
1118 port@0 {
1119 reg = <0>;
1120 dsi0_in: endpoint {
1121 };
1122 };
1123
1124 port@1 {
1125 reg = <1>;
1126 dsi0_out: endpoint {
1127 };
1128 };
1129 };
1130 };
1131
1132
1133 dsi0_phy: phy@4700200 {
1134 compatible = "qcom,dsi-phy-28nm-8960";
1135 #clock-cells = <1>;
1136 #phy-cells = <0>;
1137
1138 reg = <0x04700200 0x100>,
1139 <0x04700300 0x200>,
1140 <0x04700500 0x5c>;
1141 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
1142 clock-names = "iface", "ref";
1143 clocks = <&mmcc DSI_M_AHB_CLK>,
1144 <&pxo_board>;
1145 status = "disabled";
1146 };
1147
1148 dsi1: dsi@5800000 {
1149 compatible = "qcom,mdss-dsi-ctrl";
1150 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1151 reg = <0x05800000 0x200>;
1152 reg-names = "dsi_ctrl";
1153
1154 clocks = <&mmcc DSI2_M_AHB_CLK>,
1155 <&mmcc DSI2_S_AHB_CLK>,
1156 <&mmcc AMP_AHB_CLK>,
1157 <&mmcc DSI2_CLK>,
1158 <&mmcc DSI2_BYTE_CLK>,
1159 <&mmcc DSI2_PIXEL_CLK>,
1160 <&mmcc DSI2_ESC_CLK>;
1161 clock-names = "iface",
1162 "bus",
1163 "core_mmss",
1164 "src",
1165 "byte",
1166 "pixel",
1167 "core";
1168
1169 assigned-clocks = <&mmcc DSI2_BYTE_SRC>,
1170 <&mmcc DSI2_ESC_SRC>,
1171 <&mmcc DSI2_SRC>,
1172 <&mmcc DSI2_PIXEL_SRC>;
1173 assigned-clock-parents = <&dsi1_phy 0>,
1174 <&dsi1_phy 0>,
1175 <&dsi1_phy 1>,
1176 <&dsi1_phy 1>;
1177
1178 syscon-sfpb = <&mmss_sfpb>;
1179 phys = <&dsi1_phy>;
1180
1181 #address-cells = <1>;
1182 #size-cells = <0>;
1183
1184 status = "disabled";
1185
1186 ports {
1187 #address-cells = <1>;
1188 #size-cells = <0>;
1189
1190 port@0 {
1191 reg = <0>;
1192 dsi1_in: endpoint {
1193 };
1194 };
1195
1196 port@1 {
1197 reg = <1>;
1198 dsi1_out: endpoint {
1199 };
1200 };
1201 };
1202 };
1203
1204
1205 dsi1_phy: dsi-phy@5800200 {
1206 compatible = "qcom,dsi-phy-28nm-8960";
1207 reg = <0x05800200 0x100>,
1208 <0x05800300 0x200>,
1209 <0x05800500 0x5c>;
1210 reg-names = "dsi_pll",
1211 "dsi_phy",
1212 "dsi_phy_regulator";
1213 clock-names = "iface",
1214 "ref";
1215 clocks = <&mmcc DSI2_M_AHB_CLK>,
1216 <&pxo_board>;
1217 #clock-cells = <1>;
1218 #phy-cells = <0>;
1219
1220 status = "disabled";
1221 };
1222
1223 mdp_port0: iommu@7500000 {
1224 compatible = "qcom,apq8064-iommu";
1225 #iommu-cells = <1>;
1226 clock-names =
1227 "smmu_pclk",
1228 "iommu_clk";
1229 clocks =
1230 <&mmcc SMMU_AHB_CLK>,
1231 <&mmcc MDP_AXI_CLK>;
1232 reg = <0x07500000 0x100000>;
1233 interrupts =
1234 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
1235 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
1236 qcom,ncb = <2>;
1237 };
1238
1239 mdp_port1: iommu@7600000 {
1240 compatible = "qcom,apq8064-iommu";
1241 #iommu-cells = <1>;
1242 clock-names =
1243 "smmu_pclk",
1244 "iommu_clk";
1245 clocks =
1246 <&mmcc SMMU_AHB_CLK>,
1247 <&mmcc MDP_AXI_CLK>;
1248 reg = <0x07600000 0x100000>;
1249 interrupts =
1250 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1251 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1252 qcom,ncb = <2>;
1253 };
1254
1255 gfx3d: iommu@7c00000 {
1256 compatible = "qcom,apq8064-iommu";
1257 #iommu-cells = <1>;
1258 clock-names =
1259 "smmu_pclk",
1260 "iommu_clk";
1261 clocks =
1262 <&mmcc SMMU_AHB_CLK>,
1263 <&mmcc GFX3D_AXI_CLK>;
1264 reg = <0x07c00000 0x100000>;
1265 interrupts =
1266 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1267 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1268 qcom,ncb = <3>;
1269 };
1270
1271 gfx3d1: iommu@7d00000 {
1272 compatible = "qcom,apq8064-iommu";
1273 #iommu-cells = <1>;
1274 clock-names =
1275 "smmu_pclk",
1276 "iommu_clk";
1277 clocks =
1278 <&mmcc SMMU_AHB_CLK>,
1279 <&mmcc GFX3D_AXI_CLK>;
1280 reg = <0x07d00000 0x100000>;
1281 interrupts =
1282 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
1283 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
1284 qcom,ncb = <3>;
1285 };
1286
1287 pcie: pcie@1b500000 {
1288 compatible = "qcom,pcie-apq8064";
1289 reg = <0x1b500000 0x1000>,
1290 <0x1b502000 0x80>,
1291 <0x1b600000 0x100>,
1292 <0x0ff00000 0x100000>;
1293 reg-names = "dbi", "elbi", "parf", "config";
1294 device_type = "pci";
1295 linux,pci-domain = <0>;
1296 bus-range = <0x00 0xff>;
1297 num-lanes = <1>;
1298 #address-cells = <3>;
1299 #size-cells = <2>;
1300 ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00100000>, /* I/O */
1301 <0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* mem */
1302 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1303 interrupt-names = "msi";
1304 #interrupt-cells = <1>;
1305 interrupt-map-mask = <0 0 0 0x7>;
1306 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1307 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1308 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1309 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1310 clocks = <&gcc PCIE_A_CLK>,
1311 <&gcc PCIE_H_CLK>,
1312 <&gcc PCIE_PHY_REF_CLK>;
1313 clock-names = "core", "iface", "phy";
1314 resets = <&gcc PCIE_ACLK_RESET>,
1315 <&gcc PCIE_HCLK_RESET>,
1316 <&gcc PCIE_POR_RESET>,
1317 <&gcc PCIE_PCI_RESET>,
1318 <&gcc PCIE_PHY_RESET>;
1319 reset-names = "axi", "ahb", "por", "pci", "phy";
1320 status = "disabled";
1321 };
1322
1323 hdmi: hdmi-tx@4a00000 {
1324 compatible = "qcom,hdmi-tx-8960";
1325 pinctrl-names = "default";
1326 pinctrl-0 = <&hdmi_pinctrl>;
1327 reg = <0x04a00000 0x2f0>;
1328 reg-names = "core_physical";
1329 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1330 clocks = <&mmcc HDMI_APP_CLK>,
1331 <&mmcc HDMI_M_AHB_CLK>,
1332 <&mmcc HDMI_S_AHB_CLK>;
1333 clock-names = "core",
1334 "master_iface",
1335 "slave_iface";
1336
1337 phys = <&hdmi_phy>;
1338
1339 status = "disabled";
1340
1341 ports {
1342 #address-cells = <1>;
1343 #size-cells = <0>;
1344
1345 port@0 {
1346 reg = <0>;
1347 hdmi_in: endpoint {
1348 };
1349 };
1350
1351 port@1 {
1352 reg = <1>;
1353 hdmi_out: endpoint {
1354 };
1355 };
1356 };
1357 };
1358
1359 hdmi_phy: phy@4a00400 {
1360 compatible = "qcom,hdmi-phy-8960";
1361 reg = <0x4a00400 0x60>,
1362 <0x4a00500 0x100>;
1363 reg-names = "hdmi_phy",
1364 "hdmi_pll";
1365
1366 clocks = <&mmcc HDMI_S_AHB_CLK>;
1367 clock-names = "slave_iface";
1368 #phy-cells = <0>;
1369 #clock-cells = <0>;
1370
1371 status = "disabled";
1372 };
1373
1374 mdp: display-controller@5100000 {
1375 compatible = "qcom,mdp4";
1376 reg = <0x05100000 0xf0000>;
1377 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1378 clocks = <&mmcc MDP_CLK>,
1379 <&mmcc MDP_AHB_CLK>,
1380 <&mmcc MDP_AXI_CLK>,
1381 <&mmcc MDP_LUT_CLK>,
1382 <&mmcc HDMI_TV_CLK>,
1383 <&mmcc MDP_TV_CLK>;
1384 clock-names = "core_clk",
1385 "iface_clk",
1386 "bus_clk",
1387 "lut_clk",
1388 "hdmi_clk",
1389 "tv_clk";
1390
1391 iommus = <&mdp_port0 0
1392 &mdp_port0 2
1393 &mdp_port1 0
1394 &mdp_port1 2>;
1395
1396 ports {
1397 #address-cells = <1>;
1398 #size-cells = <0>;
1399
1400 port@0 {
1401 reg = <0>;
1402 mdp_lvds_out: endpoint {
1403 };
1404 };
1405
1406 port@1 {
1407 reg = <1>;
1408 mdp_dsi1_out: endpoint {
1409 };
1410 };
1411
1412 port@2 {
1413 reg = <2>;
1414 mdp_dsi2_out: endpoint {
1415 };
1416 };
1417
1418 port@3 {
1419 reg = <3>;
1420 mdp_dtv_out: endpoint {
1421 };
1422 };
1423 };
1424 };
1425
1426 riva: riva-pil@3200800 {
1427 compatible = "qcom,riva-pil";
1428
1429 reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>;
1430 reg-names = "ccu", "dxe", "pmu";
1431
1432 interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
1433 <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>;
1434 interrupt-names = "wdog", "fatal";
1435
1436 memory-region = <&wcnss_mem>;
1437
1438 status = "disabled";
1439
1440 iris {
1441 compatible = "qcom,wcn3660";
1442
1443 clocks = <&cxo_board>;
1444 clock-names = "xo";
1445 };
1446
1447 smd-edge {
1448 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
1449
1450 qcom,ipc = <&l2cc 8 25>;
1451 qcom,smd-edge = <6>;
1452
1453 label = "riva";
1454
1455 wcnss {
1456 compatible = "qcom,wcnss";
1457 qcom,smd-channels = "WCNSS_CTRL";
1458
1459 qcom,mmio = <&riva>;
1460
1461 bluetooth {
1462 compatible = "qcom,wcnss-bt";
1463 };
1464
1465 wifi {
1466 compatible = "qcom,wcnss-wlan";
1467
1468 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1469 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1470 interrupt-names = "tx", "rx";
1471
1472 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1473 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1474 };
1475 };
1476 };
1477 };
1478
1479 etb@1a01000 {
1480 compatible = "arm,coresight-etb10", "arm,primecell";
1481 reg = <0x1a01000 0x1000>;
1482
1483 clocks = <&rpmcc RPM_QDSS_CLK>;
1484 clock-names = "apb_pclk";
1485
1486 in-ports {
1487 port {
1488 etb_in: endpoint {
1489 remote-endpoint = <&replicator_out0>;
1490 };
1491 };
1492 };
1493 };
1494
1495 tpiu@1a03000 {
1496 compatible = "arm,coresight-tpiu", "arm,primecell";
1497 reg = <0x1a03000 0x1000>;
1498
1499 clocks = <&rpmcc RPM_QDSS_CLK>;
1500 clock-names = "apb_pclk";
1501
1502 in-ports {
1503 port {
1504 tpiu_in: endpoint {
1505 remote-endpoint = <&replicator_out1>;
1506 };
1507 };
1508 };
1509 };
1510
1511 replicator {
1512 compatible = "arm,coresight-static-replicator";
1513
1514 clocks = <&rpmcc RPM_QDSS_CLK>;
1515 clock-names = "apb_pclk";
1516
1517 out-ports {
1518 #address-cells = <1>;
1519 #size-cells = <0>;
1520
1521 port@0 {
1522 reg = <0>;
1523 replicator_out0: endpoint {
1524 remote-endpoint = <&etb_in>;
1525 };
1526 };
1527 port@1 {
1528 reg = <1>;
1529 replicator_out1: endpoint {
1530 remote-endpoint = <&tpiu_in>;
1531 };
1532 };
1533 };
1534
1535 in-ports {
1536 port {
1537 replicator_in: endpoint {
1538 remote-endpoint = <&funnel_out>;
1539 };
1540 };
1541 };
1542 };
1543
1544 funnel@1a04000 {
1545 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1546 reg = <0x1a04000 0x1000>;
1547
1548 clocks = <&rpmcc RPM_QDSS_CLK>;
1549 clock-names = "apb_pclk";
1550
1551 in-ports {
1552 #address-cells = <1>;
1553 #size-cells = <0>;
1554
1555 /*
1556 * Not described input ports:
1557 * 2 - connected to STM component
1558 * 3 - not-connected
1559 * 6 - not-connected
1560 * 7 - not-connected
1561 */
1562 port@0 {
1563 reg = <0>;
1564 funnel_in0: endpoint {
1565 remote-endpoint = <&etm0_out>;
1566 };
1567 };
1568 port@1 {
1569 reg = <1>;
1570 funnel_in1: endpoint {
1571 remote-endpoint = <&etm1_out>;
1572 };
1573 };
1574 port@4 {
1575 reg = <4>;
1576 funnel_in4: endpoint {
1577 remote-endpoint = <&etm2_out>;
1578 };
1579 };
1580 port@5 {
1581 reg = <5>;
1582 funnel_in5: endpoint {
1583 remote-endpoint = <&etm3_out>;
1584 };
1585 };
1586 };
1587
1588 out-ports {
1589 port {
1590 funnel_out: endpoint {
1591 remote-endpoint = <&replicator_in>;
1592 };
1593 };
1594 };
1595 };
1596
1597 etm@1a1c000 {
1598 compatible = "arm,coresight-etm3x", "arm,primecell";
1599 reg = <0x1a1c000 0x1000>;
1600
1601 clocks = <&rpmcc RPM_QDSS_CLK>;
1602 clock-names = "apb_pclk";
1603
1604 cpu = <&CPU0>;
1605
1606 out-ports {
1607 port {
1608 etm0_out: endpoint {
1609 remote-endpoint = <&funnel_in0>;
1610 };
1611 };
1612 };
1613 };
1614
1615 etm@1a1d000 {
1616 compatible = "arm,coresight-etm3x", "arm,primecell";
1617 reg = <0x1a1d000 0x1000>;
1618
1619 clocks = <&rpmcc RPM_QDSS_CLK>;
1620 clock-names = "apb_pclk";
1621
1622 cpu = <&CPU1>;
1623
1624 out-ports {
1625 port {
1626 etm1_out: endpoint {
1627 remote-endpoint = <&funnel_in1>;
1628 };
1629 };
1630 };
1631 };
1632
1633 etm@1a1e000 {
1634 compatible = "arm,coresight-etm3x", "arm,primecell";
1635 reg = <0x1a1e000 0x1000>;
1636
1637 clocks = <&rpmcc RPM_QDSS_CLK>;
1638 clock-names = "apb_pclk";
1639
1640 cpu = <&CPU2>;
1641
1642 out-ports {
1643 port {
1644 etm2_out: endpoint {
1645 remote-endpoint = <&funnel_in4>;
1646 };
1647 };
1648 };
1649 };
1650
1651 etm@1a1f000 {
1652 compatible = "arm,coresight-etm3x", "arm,primecell";
1653 reg = <0x1a1f000 0x1000>;
1654
1655 clocks = <&rpmcc RPM_QDSS_CLK>;
1656 clock-names = "apb_pclk";
1657
1658 cpu = <&CPU3>;
1659
1660 out-ports {
1661 port {
1662 etm3_out: endpoint {
1663 remote-endpoint = <&funnel_in5>;
1664 };
1665 };
1666 };
1667 };
1668 };
1669};
1670#include "qcom-apq8064-pins.dtsi"