1// SPDX-License-Identifier: GPL-2.0+
  2//
  3// Copyright 2013 Greg Ungerer <gerg@uclinux.org>
  4// Copyright 2011 Freescale Semiconductor, Inc.
  5// Copyright 2011 Linaro Ltd.
  6
  7/dts-v1/;
  8#include "imx50.dtsi"
  9
 10/ {
 11	model = "Freescale i.MX50 Evaluation Kit";
 12	compatible = "fsl,imx50-evk", "fsl,imx50";
 13
 14	memory@70000000 {
 15		device_type = "memory";
 16		reg = <0x70000000 0x80000000>;
 17	};
 18};
 19
 20&cspi {
 21	pinctrl-names = "default";
 22	pinctrl-0 = <&pinctrl_cspi>;
 23	cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>, <&gpio4 13 GPIO_ACTIVE_LOW>;
 24	status = "okay";
 25
 26	flash: m25p32@1 {
 27		#address-cells = <1>;
 28		#size-cells = <1>;
 29		compatible = "m25p32", "jedec,spi-nor";
 30		spi-max-frequency = <25000000>;
 31		reg = <1>;
 32
 33		partition@0 {
 34			label = "bootloader";
 35			reg = <0x0 0x100000>;
 36			read-only;
 37		};
 38
 39		partition@100000 {
 40			label = "kernel";
 41			reg = <0x100000 0x300000>;
 42		};
 43	};
 44};
 45
 46&fec {
 47	pinctrl-names = "default";
 48	pinctrl-0 = <&pinctrl_fec>;
 49	phy-mode = "rmii";
 50	phy-reset-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
 51	status = "okay";
 52};
 53
 54&iomuxc {
 55	imx50-evk {
 56		pinctrl_cspi: cspigrp {
 57			fsl,pins = <
 58				MX50_PAD_CSPI_SCLK__CSPI_SCLK		0x00
 59				MX50_PAD_CSPI_MISO__CSPI_MISO		0x00
 60				MX50_PAD_CSPI_MOSI__CSPI_MOSI		0x00
 61				MX50_PAD_CSPI_SS0__GPIO4_11		0xc4
 62				MX50_PAD_ECSPI1_MOSI__GPIO4_13		0x84
 63			>;
 64		};
 65
 66		pinctrl_fec: fecgrp {
 67			fsl,pins = <
 68				MX50_PAD_SSI_RXFS__FEC_MDC		0x80
 69				MX50_PAD_SSI_RXC__FEC_MDIO		0x80
 70				MX50_PAD_DISP_D0__FEC_TX_CLK		0x80
 71				MX50_PAD_DISP_D1__FEC_RX_ERR		0x80
 72				MX50_PAD_DISP_D2__FEC_RX_DV		0x80
 73				MX50_PAD_DISP_D3__FEC_RDATA_1		0x80
 74				MX50_PAD_DISP_D4__FEC_RDATA_0		0x80
 75				MX50_PAD_DISP_D5__FEC_TX_EN		0x80
 76				MX50_PAD_DISP_D6__FEC_TDATA_1		0x80
 77				MX50_PAD_DISP_D7__FEC_TDATA_0		0x80
 78			>;
 79		};
 80
 81		pinctrl_uart1: uart1grp {
 82			fsl,pins = <
 83				MX50_PAD_UART1_TXD__UART1_TXD_MUX	0x1e4
 84				MX50_PAD_UART1_RXD__UART1_RXD_MUX	0x1e4
 85				MX50_PAD_UART1_RTS__UART1_RTS		0x1e4
 86				MX50_PAD_UART1_CTS__UART1_CTS		0x1e4
 87			>;
 88		};
 89	};
 90};
 91
 92&uart1 {
 93	pinctrl-names = "default";
 94	pinctrl-0 = <&pinctrl_uart1>;
 95	status = "okay";
 96};
 97
 98&usbh1 {
 99	status = "okay";
100};
101
102&usbotg {
103	status = "okay";
104};