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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree file for Cortina systems Gemini SoC
4 */
5
6#include <dt-bindings/interrupt-controller/irq.h>
7#include <dt-bindings/clock/cortina,gemini-clock.h>
8#include <dt-bindings/reset/cortina,gemini-reset.h>
9#include <dt-bindings/gpio/gpio.h>
10
11/ {
12 soc {
13 #address-cells = <1>;
14 #size-cells = <1>;
15 ranges;
16 compatible = "simple-bus";
17 interrupt-parent = <&intcon>;
18
19 flash: flash@30000000 {
20 compatible = "cortina,gemini-flash", "cfi-flash";
21 syscon = <&syscon>;
22 pinctrl-names = "default";
23 pinctrl-0 = <&pflash_default_pins>;
24 bank-width = <2>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27 status = "disabled";
28 };
29
30 syscon: syscon@40000000 {
31 compatible = "cortina,gemini-syscon",
32 "syscon", "simple-mfd";
33 reg = <0x40000000 0x1000>;
34 #clock-cells = <1>;
35 #reset-cells = <1>;
36
37 syscon-reboot {
38 compatible = "syscon-reboot";
39 regmap = <&syscon>;
40 /* GLOBAL_RESET register */
41 offset = <0x0c>;
42 /* RESET_GLOBAL | RESET_CPU1 */
43 mask = <0xC0000000>;
44 };
45
46 pinctrl {
47 compatible = "cortina,gemini-pinctrl";
48 regmap = <&syscon>;
49 /* Hog the DRAM pins */
50 pinctrl-names = "default";
51 pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
52 <&vcontrol_default_pins>;
53
54 dram_default_pins: pinctrl-dram {
55 mux {
56 function = "dram";
57 groups = "dramgrp";
58 };
59 };
60 rtc_default_pins: pinctrl-rtc {
61 mux {
62 function = "rtc";
63 groups = "rtcgrp";
64 };
65 };
66 power_default_pins: pinctrl-power {
67 mux {
68 function = "power";
69 groups = "powergrp";
70 };
71 };
72 cir_default_pins: pinctrl-cir {
73 mux {
74 function = "cir";
75 groups = "cirgrp";
76 };
77 };
78 system_default_pins: pinctrl-system {
79 mux {
80 function = "system";
81 groups = "systemgrp";
82 };
83 };
84 vcontrol_default_pins: pinctrl-vcontrol {
85 mux {
86 function = "vcontrol";
87 groups = "vcontrolgrp";
88 };
89 };
90 ice_default_pins: pinctrl-ice {
91 mux {
92 function = "ice";
93 groups = "icegrp";
94 };
95 };
96 uart_default_pins: pinctrl-uart {
97 mux {
98 function = "uart";
99 groups = "uartrxtxgrp";
100 };
101 };
102 pflash_default_pins: pinctrl-pflash {
103 mux {
104 function = "pflash";
105 groups = "pflashgrp";
106 };
107 };
108 usb_default_pins: pinctrl-usb {
109 mux {
110 function = "usb";
111 groups = "usbgrp";
112 };
113 };
114 gmii_default_pins: pinctrl-gmii {
115 /*
116 * Only activate GMAC0 by default since
117 * GMAC1 will overlap with 8 GPIO lines
118 * gpio2a, gpio2b. Overlay groups with
119 * "gmii_gmac0_grp", "gmii_gmac1_grp" for
120 * both ethernet interfaces.
121 */
122 mux {
123 function = "gmii";
124 groups = "gmii_gmac0_grp";
125 };
126 };
127 pci_default_pins: pinctrl-pci {
128 mux {
129 function = "pci";
130 groups = "pcigrp";
131 };
132 };
133 sata_default_pins: pinctrl-sata {
134 mux {
135 function = "sata";
136 groups = "satagrp";
137 };
138 };
139 /* Activate both groups of pins for this state */
140 sata_and_ide_pins: pinctrl-sata-ide {
141 mux0 {
142 function = "sata";
143 groups = "satagrp";
144 };
145 mux1 {
146 function = "ide";
147 groups = "idegrp";
148 };
149 };
150 tvc_default_pins: pinctrl-tvc {
151 mux {
152 function = "tvc";
153 groups = "tvcgrp";
154 };
155 };
156 };
157 };
158
159 watchdog@41000000 {
160 compatible = "cortina,gemini-watchdog", "faraday,ftwdt010";
161 reg = <0x41000000 0x1000>;
162 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
163 resets = <&syscon GEMINI_RESET_WDOG>;
164 clocks = <&syscon GEMINI_CLK_APB>;
165 clock-names = "PCLK";
166 };
167
168 uart0: serial@42000000 {
169 compatible = "ns16550a";
170 reg = <0x42000000 0x100>;
171 resets = <&syscon GEMINI_RESET_UART>;
172 clocks = <&syscon GEMINI_CLK_UART>;
173 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
174 pinctrl-names = "default";
175 pinctrl-0 = <&uart_default_pins>;
176 reg-shift = <2>;
177 };
178
179 timer@43000000 {
180 compatible = "faraday,fttmr010";
181 reg = <0x43000000 0x1000>;
182 interrupt-parent = <&intcon>;
183 interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
184 <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */
185 <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */
186 resets = <&syscon GEMINI_RESET_TIMER>;
187 /* APB clock or RTC clock */
188 clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>;
189 clock-names = "PCLK", "EXTCLK";
190 syscon = <&syscon>;
191 };
192
193 rtc@45000000 {
194 compatible = "cortina,gemini-rtc", "faraday,ftrtc010";
195 reg = <0x45000000 0x100>;
196 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
197 resets = <&syscon GEMINI_RESET_RTC>;
198 clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>;
199 clock-names = "PCLK", "EXTCLK";
200 pinctrl-names = "default";
201 pinctrl-0 = <&rtc_default_pins>;
202 };
203
204 sata: sata@46000000 {
205 compatible = "cortina,gemini-sata-bridge";
206 reg = <0x46000000 0x100>;
207 resets = <&syscon GEMINI_RESET_SATA0>,
208 <&syscon GEMINI_RESET_SATA1>;
209 reset-names = "sata0", "sata1";
210 clocks = <&syscon GEMINI_CLK_GATE_SATA0>,
211 <&syscon GEMINI_CLK_GATE_SATA1>;
212 clock-names = "SATA0_PCLK", "SATA1_PCLK";
213 /*
214 * This defines the special "ide" state that needs
215 * to be explicitly enabled to enable the IDE pins,
216 * as these pins are normally used for other things.
217 */
218 pinctrl-names = "default", "ide";
219 pinctrl-0 = <&sata_default_pins>;
220 pinctrl-1 = <&sata_and_ide_pins>;
221 syscon = <&syscon>;
222 status = "disabled";
223 };
224
225 intcon: interrupt-controller@48000000 {
226 compatible = "faraday,ftintc010";
227 reg = <0x48000000 0x1000>;
228 resets = <&syscon GEMINI_RESET_INTCON0>;
229 interrupt-controller;
230 #interrupt-cells = <2>;
231 };
232
233 power-controller@4b000000 {
234 compatible = "cortina,gemini-power-controller";
235 reg = <0x4b000000 0x100>;
236 interrupts = <26 IRQ_TYPE_EDGE_RISING>;
237 pinctrl-names = "default";
238 pinctrl-0 = <&power_default_pins>;
239 };
240
241 gpio0: gpio@4d000000 {
242 compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
243 reg = <0x4d000000 0x100>;
244 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
245 resets = <&syscon GEMINI_RESET_GPIO0>;
246 clocks = <&syscon GEMINI_CLK_APB>;
247 gpio-controller;
248 #gpio-cells = <2>;
249 interrupt-controller;
250 #interrupt-cells = <2>;
251 };
252
253 gpio1: gpio@4e000000 {
254 compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
255 reg = <0x4e000000 0x100>;
256 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
257 resets = <&syscon GEMINI_RESET_GPIO1>;
258 clocks = <&syscon GEMINI_CLK_APB>;
259 gpio-controller;
260 #gpio-cells = <2>;
261 interrupt-controller;
262 #interrupt-cells = <2>;
263 };
264
265 gpio2: gpio@4f000000 {
266 compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
267 reg = <0x4f000000 0x100>;
268 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
269 resets = <&syscon GEMINI_RESET_GPIO2>;
270 clocks = <&syscon GEMINI_CLK_APB>;
271 gpio-controller;
272 #gpio-cells = <2>;
273 interrupt-controller;
274 #interrupt-cells = <2>;
275 };
276
277 pci@50000000 {
278 compatible = "cortina,gemini-pci", "faraday,ftpci100";
279 /*
280 * The first 256 bytes in the IO range is actually used
281 * to configure the host bridge.
282 */
283 reg = <0x50000000 0x100>;
284 resets = <&syscon GEMINI_RESET_PCI>;
285 clocks = <&syscon GEMINI_CLK_GATE_PCI>, <&syscon GEMINI_CLK_PCI>;
286 clock-names = "PCLK", "PCICLK";
287 pinctrl-names = "default";
288 pinctrl-0 = <&pci_default_pins>;
289 device_type = "pci";
290 #address-cells = <3>;
291 #size-cells = <2>;
292 status = "disabled";
293
294 #interrupt-cells = <1>;
295 interrupt-map-mask = <0xf800 0 0 7>;
296 interrupt-map =
297 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
298 <0x4800 0 0 2 &pci_intc 1>,
299 <0x4800 0 0 3 &pci_intc 2>,
300 <0x4800 0 0 4 &pci_intc 3>,
301 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
302 <0x5000 0 0 2 &pci_intc 2>,
303 <0x5000 0 0 3 &pci_intc 3>,
304 <0x5000 0 0 4 &pci_intc 0>,
305 <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
306 <0x5800 0 0 2 &pci_intc 3>,
307 <0x5800 0 0 3 &pci_intc 0>,
308 <0x5800 0 0 4 &pci_intc 1>,
309 <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
310 <0x6000 0 0 2 &pci_intc 0>,
311 <0x6000 0 0 3 &pci_intc 1>,
312 <0x6000 0 0 4 &pci_intc 2>;
313
314 bus-range = <0x00 0xff>;
315 /* PCI ranges mappings */
316 ranges =
317 /* 1MiB I/O space 0x50000000-0x500fffff */
318 <0x01000000 0 0 0x50000000 0 0x00100000>,
319 /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */
320 <0x02000000 0 0x58000000 0x58000000 0 0x08000000>;
321
322 /* DMA ranges */
323 dma-ranges =
324 /* 128MiB at 0x00000000-0x07ffffff */
325 <0x02000000 0 0x00000000 0x00000000 0 0x08000000>,
326 /* 64MiB at 0x00000000-0x03ffffff */
327 <0x02000000 0 0x00000000 0x00000000 0 0x04000000>,
328 /* 64MiB at 0x00000000-0x03ffffff */
329 <0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
330
331 /*
332 * This PCI host bridge variant has a cascaded interrupt
333 * controller embedded in the host bridge.
334 */
335 pci_intc: interrupt-controller {
336 interrupt-parent = <&intcon>;
337 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
338 interrupt-controller;
339 #address-cells = <0>;
340 #interrupt-cells = <1>;
341 };
342 };
343
344 ethernet: ethernet@60000000 {
345 compatible = "cortina,gemini-ethernet";
346 reg = <0x60000000 0x4000>, /* Global registers, queue */
347 <0x60004000 0x2000>, /* V-bit */
348 <0x60006000 0x2000>; /* A-bit */
349 pinctrl-names = "default";
350 pinctrl-0 = <&gmii_default_pins>;
351 status = "disabled";
352 #address-cells = <1>;
353 #size-cells = <1>;
354 ranges;
355
356 gmac0: ethernet-port@0 {
357 compatible = "cortina,gemini-ethernet-port";
358 reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
359 <0x6000a000 0x2000>; /* Port 0 GMAC */
360 interrupt-parent = <&intcon>;
361 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
362 resets = <&syscon GEMINI_RESET_GMAC0>;
363 clocks = <&syscon GEMINI_CLK_GATE_GMAC0>;
364 clock-names = "PCLK";
365 };
366
367 gmac1: ethernet-port@1 {
368 compatible = "cortina,gemini-ethernet-port";
369 reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
370 <0x6000e000 0x2000>; /* Port 1 GMAC */
371 interrupt-parent = <&intcon>;
372 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
373 resets = <&syscon GEMINI_RESET_GMAC1>;
374 clocks = <&syscon GEMINI_CLK_GATE_GMAC1>;
375 clock-names = "PCLK";
376 };
377 };
378
379 crypto: crypto@62000000 {
380 compatible = "cortina,sl3516-crypto";
381 reg = <0x62000000 0x10000>;
382 interrupts = <7 IRQ_TYPE_EDGE_RISING>;
383 resets = <&syscon GEMINI_RESET_SECURITY>;
384 clocks = <&syscon GEMINI_CLK_GATE_SECURITY>;
385 };
386
387 ide0: ide@63000000 {
388 compatible = "cortina,gemini-pata", "faraday,ftide010";
389 reg = <0x63000000 0x1000>;
390 interrupts = <4 IRQ_TYPE_EDGE_RISING>;
391 resets = <&syscon GEMINI_RESET_IDE>;
392 clocks = <&syscon GEMINI_CLK_GATE_IDE>;
393 clock-names = "PCLK";
394 sata = <&sata>;
395 status = "disabled";
396 #address-cells = <1>;
397 #size-cells = <0>;
398 };
399
400 ide1: ide@63400000 {
401 compatible = "cortina,gemini-pata", "faraday,ftide010";
402 reg = <0x63400000 0x1000>;
403 interrupts = <5 IRQ_TYPE_EDGE_RISING>;
404 resets = <&syscon GEMINI_RESET_IDE>;
405 clocks = <&syscon GEMINI_CLK_GATE_IDE>;
406 clock-names = "PCLK";
407 sata = <&sata>;
408 status = "disabled";
409 #address-cells = <1>;
410 #size-cells = <0>;
411 };
412
413 dma-controller@67000000 {
414 compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell";
415 /* Faraday Technology FTDMAC020 variant */
416 arm,primecell-periphid = <0x0003b080>;
417 reg = <0x67000000 0x1000>;
418 interrupts = <9 IRQ_TYPE_EDGE_RISING>;
419 resets = <&syscon GEMINI_RESET_DMAC>;
420 clocks = <&syscon GEMINI_CLK_AHB>;
421 clock-names = "apb_pclk";
422 /* Bus interface AHB1 (AHB0) is totally tilted */
423 lli-bus-interface-ahb2;
424 mem-bus-interface-ahb2;
425 memcpy-burst-size = <256>;
426 memcpy-bus-width = <32>;
427 #dma-cells = <2>;
428 };
429
430 display-controller@6a000000 {
431 compatible = "cortina,gemini-tvc", "faraday,tve200";
432 reg = <0x6a000000 0x1000>;
433 interrupts = <13 IRQ_TYPE_EDGE_RISING>;
434 resets = <&syscon GEMINI_RESET_TVC>;
435 clocks = <&syscon GEMINI_CLK_GATE_TVC>,
436 <&syscon GEMINI_CLK_TVC>;
437 clock-names = "PCLK", "TVE";
438 pinctrl-names = "default";
439 pinctrl-0 = <&tvc_default_pins>;
440 status = "disabled";
441 };
442
443 usb0: usb@68000000 {
444 compatible = "cortina,gemini-usb", "faraday,fotg210";
445 reg = <0x68000000 0x1000>;
446 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
447 resets = <&syscon GEMINI_RESET_USB0>;
448 clocks = <&syscon GEMINI_CLK_GATE_USB0>;
449 clock-names = "PCLK";
450 /*
451 * This will claim pins for USB0 and USB1 at the same
452 * time as they are using some common pins. If you for
453 * some reason have a system using USB1 at 96000000 but
454 * NOT using USB0 at 68000000 you wll have to add the
455 * usb_default_pins to the USB controller at 96000000
456 * in your .dts for the board.
457 */
458 pinctrl-names = "default";
459 pinctrl-0 = <&usb_default_pins>;
460 syscon = <&syscon>;
461 status = "disabled";
462 };
463
464 usb1: usb@69000000 {
465 compatible = "cortina,gemini-usb", "faraday,fotg210";
466 reg = <0x69000000 0x1000>;
467 interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
468 resets = <&syscon GEMINI_RESET_USB1>;
469 clocks = <&syscon GEMINI_CLK_GATE_USB1>;
470 clock-names = "PCLK";
471 syscon = <&syscon>;
472 status = "disabled";
473 };
474 };
475};