1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2/*
  3 * Copyright 2022 Broadcom Ltd.
  4 */
  5
  6#include <dt-bindings/interrupt-controller/arm-gic.h>
  7#include <dt-bindings/interrupt-controller/irq.h>
  8
  9/ {
 10	compatible = "brcm,bcm6756", "brcm,bcmbca";
 11	#address-cells = <1>;
 12	#size-cells = <1>;
 13
 14	interrupt-parent = <&gic>;
 15
 16	cpus {
 17		#address-cells = <1>;
 18		#size-cells = <0>;
 19
 20		CA7_0: cpu@0 {
 21			device_type = "cpu";
 22			compatible = "arm,cortex-a7";
 23			reg = <0x0>;
 24			next-level-cache = <&L2_0>;
 25			enable-method = "psci";
 26		};
 27
 28		CA7_1: cpu@1 {
 29			device_type = "cpu";
 30			compatible = "arm,cortex-a7";
 31			reg = <0x1>;
 32			next-level-cache = <&L2_0>;
 33			enable-method = "psci";
 34		};
 35
 36		CA7_2: cpu@2 {
 37			device_type = "cpu";
 38			compatible = "arm,cortex-a7";
 39			reg = <0x2>;
 40			next-level-cache = <&L2_0>;
 41			enable-method = "psci";
 42		};
 43
 44		CA7_3: cpu@3 {
 45			device_type = "cpu";
 46			compatible = "arm,cortex-a7";
 47			reg = <0x3>;
 48			next-level-cache = <&L2_0>;
 49			enable-method = "psci";
 50		};
 51
 52		L2_0: l2-cache0 {
 53			compatible = "cache";
 54			cache-level = <2>;
 55			cache-unified;
 56		};
 57	};
 58
 59	timer {
 60		compatible = "arm,armv7-timer";
 61		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 62			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 63			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 64			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 65		arm,cpu-registers-not-fw-configured;
 66	};
 67
 68	pmu: pmu {
 69		compatible = "arm,cortex-a7-pmu";
 70		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 71			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 72			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 73			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 74		interrupt-affinity = <&CA7_0>, <&CA7_1>,
 75			<&CA7_2>, <&CA7_3>;
 76	};
 77
 78	clocks: clocks {
 79		periph_clk: periph-clk {
 80			compatible = "fixed-clock";
 81			#clock-cells = <0>;
 82			clock-frequency = <200000000>;
 83		};
 84
 85		uart_clk: uart-clk {
 86			compatible = "fixed-factor-clock";
 87			#clock-cells = <0>;
 88			clocks = <&periph_clk>;
 89			clock-div = <4>;
 90			clock-mult = <1>;
 91		};
 92
 93		hsspi_pll: hsspi-pll {
 94			compatible = "fixed-clock";
 95			#clock-cells = <0>;
 96			clock-frequency = <200000000>;
 97		};
 98	};
 99
100	psci {
101		compatible = "arm,psci-0.2";
102		method = "smc";
103	};
104
105	axi@81000000 {
106		compatible = "simple-bus";
107		#address-cells = <1>;
108		#size-cells = <1>;
109		ranges = <0 0x81000000 0x8000>;
110
111		gic: interrupt-controller@1000 {
112			compatible = "arm,cortex-a7-gic";
113			#interrupt-cells = <3>;
114			interrupt-controller;
115			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
116			reg = <0x1000 0x1000>,
117				<0x2000 0x2000>,
118				<0x4000 0x2000>,
119				<0x6000 0x2000>;
120		};
121	};
122
123	bus@ff800000 {
124		compatible = "simple-bus";
125		#address-cells = <1>;
126		#size-cells = <1>;
127		ranges = <0 0xff800000 0x800000>;
128
129		hsspi: spi@1000 {
130			#address-cells = <1>;
131			#size-cells = <0>;
132			compatible = "brcm,bcm6756-hsspi", "brcm,bcmbca-hsspi-v1.1";
133			reg = <0x1000 0x600>, <0x2610 0x4>;
134			reg-names = "hsspi", "spim-ctrl";
135			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
136			clocks = <&hsspi_pll &hsspi_pll>;
137			clock-names = "hsspi", "pll";
138			num-cs = <8>;
139			status = "disabled";
140		};
141
142		uart0: serial@12000 {
143			compatible = "arm,pl011", "arm,primecell";
144			reg = <0x12000 0x1000>;
145			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
146			clocks = <&uart_clk>, <&uart_clk>;
147			clock-names = "uartclk", "apb_pclk";
148			status = "disabled";
149		};
150	};
151};