1/*
  2 * Broadcom BCM470X / BCM5301X ARM platform code.
  3 * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
  4 * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
  5 *
  6 * Licensed under the GNU/GPL. See COPYING for details.
  7 */
  8
  9#include "bcm-ns.dtsi"
 10
 11/ {
 12	mpcore-bus@19000000 {
 13		a9pll: arm_clk@0 {
 14			#clock-cells = <0>;
 15			compatible = "brcm,nsp-armpll";
 16			clocks = <&osc>;
 17			reg = <0x00000 0x1000>;
 18		};
 19
 20		watchdog@20620 {
 21			compatible = "arm,cortex-a9-twd-wdt";
 22			reg = <0x20620 0x20>;
 23			interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
 24						  IRQ_TYPE_EDGE_RISING)>;
 25			clocks = <&periph_clk>;
 26		};
 27	};
 28
 29	clocks {
 30		#address-cells = <1>;
 31		#size-cells = <1>;
 32		ranges;
 33
 34		osc: oscillator {
 35			#clock-cells = <0>;
 36			compatible = "fixed-clock";
 37			clock-frequency = <25000000>;
 38		};
 39
 40		iprocmed: iprocmed {
 41			#clock-cells = <0>;
 42			compatible = "fixed-factor-clock";
 43			clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
 44			clock-div = <2>;
 45			clock-mult = <1>;
 46		};
 47
 48		iprocslow: iprocslow {
 49			#clock-cells = <0>;
 50			compatible = "fixed-factor-clock";
 51			clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
 52			clock-div = <4>;
 53			clock-mult = <1>;
 54		};
 55
 56		periph_clk: periph_clk {
 57			#clock-cells = <0>;
 58			compatible = "fixed-factor-clock";
 59			clocks = <&a9pll>;
 60			clock-div = <2>;
 61			clock-mult = <1>;
 62		};
 63	};
 64
 65	i2c0: i2c@18009000 {
 66		compatible = "brcm,iproc-i2c";
 67		reg = <0x18009000 0x50>;
 68		interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 69		#address-cells = <1>;
 70		#size-cells = <0>;
 71		clock-frequency = <100000>;
 72		status = "disabled";
 73	};
 74
 75	dmu-bus@1800c000 {
 76		cru-bus@100 {
 77			lcpll0: clock-controller@100 {
 78				#clock-cells = <1>;
 79				compatible = "brcm,nsp-lcpll0";
 80				reg = <0x100 0x14>;
 81				clocks = <&osc>;
 82				clock-output-names = "lcpll0", "pcie_phy",
 83						     "sdio", "ddr_phy";
 84			};
 85
 86			genpll: clock-controller@140 {
 87				#clock-cells = <1>;
 88				compatible = "brcm,nsp-genpll";
 89				reg = <0x140 0x24>;
 90				clocks = <&osc>;
 91				clock-output-names = "genpll", "phy",
 92						     "ethernetclk",
 93						     "usbclk", "iprocfast",
 94						     "sata1", "sata2";
 95			};
 96		};
 97	};
 98
 99	spi@18029200 {
100		compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
101		reg = <0x18029200 0x184>,
102		      <0x18029000 0x124>,
103		      <0x1811b408 0x004>,
104		      <0x180293a0 0x01c>;
105		reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
106		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
107			     <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
108			     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
109			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
110			     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
111			     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
112			     <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
113		interrupt-names = "mspi_done",
114				  "mspi_halted",
115				  "spi_lr_fullness_reached",
116				  "spi_lr_session_aborted",
117				  "spi_lr_impatient",
118				  "spi_lr_session_done",
119				  "spi_lr_overread";
120		clocks = <&iprocmed>;
121		num-cs = <2>;
122		#address-cells = <1>;
123		#size-cells = <0>;
124
125		spi_nor: flash@0 {
126			compatible = "jedec,spi-nor";
127			reg = <0>;
128			spi-max-frequency = <20000000>;
129			status = "disabled";
130
131			partitions {
132				compatible = "brcm,bcm947xx-cfe-partitions";
133			};
134		};
135	};
136};