1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2/*
  3 * Device Tree Include file for Marvell Armada 380 SoC.
  4 *
  5 * Copyright (C) 2014 Marvell
  6 *
  7 * Lior Amsalem <alior@marvell.com>
  8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
  9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 10 */
 11
 12#include "armada-38x.dtsi"
 13
 14/ {
 15	model = "Marvell Armada 380 family SoC";
 16	compatible = "marvell,armada380";
 17
 18	cpus {
 19		#address-cells = <1>;
 20		#size-cells = <0>;
 21		enable-method = "marvell,armada-380-smp";
 22
 23		cpu@0 {
 24			device_type = "cpu";
 25			compatible = "arm,cortex-a9";
 26			reg = <0>;
 27		};
 28	};
 29
 30	soc {
 31		internal-regs {
 32			pinctrl@18000 {
 33				compatible = "marvell,mv88f6810-pinctrl";
 34			};
 35		};
 36
 37		pcie {
 38			compatible = "marvell,armada-370-pcie";
 39			status = "disabled";
 40			device_type = "pci";
 41
 42			#address-cells = <3>;
 43			#size-cells = <2>;
 44
 45			msi-parent = <&mpic>;
 46			bus-range = <0x00 0xff>;
 47
 48			ranges =
 49			       <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
 50				0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
 51				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
 52				0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
 53				0x82000000 0x1 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
 54				0x81000000 0x1 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO  */
 55				0x82000000 0x2 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
 56				0x81000000 0x2 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO  */
 57				0x82000000 0x3 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
 58				0x81000000 0x3 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO  */>;
 59
 60			/* x1 port */
 61			pcie@1,0 {
 62				device_type = "pci";
 63				assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
 64				reg = <0x0800 0 0 0 0>;
 65				#address-cells = <3>;
 66				#size-cells = <2>;
 67				interrupt-names = "intx";
 68				interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 69				#interrupt-cells = <1>;
 70				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
 71					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
 72				bus-range = <0x00 0xff>;
 73				interrupt-map-mask = <0 0 0 7>;
 74				interrupt-map = <0 0 0 1 &pcie1_intc 0>,
 75						<0 0 0 2 &pcie1_intc 1>,
 76						<0 0 0 3 &pcie1_intc 2>,
 77						<0 0 0 4 &pcie1_intc 3>;
 78				marvell,pcie-port = <0>;
 79				marvell,pcie-lane = <0>;
 80				clocks = <&gateclk 8>;
 81				status = "disabled";
 82
 83				pcie1_intc: interrupt-controller {
 84					interrupt-controller;
 85					#interrupt-cells = <1>;
 86				};
 87			};
 88
 89			/* x1 port */
 90			pcie@2,0 {
 91				device_type = "pci";
 92				assigned-addresses = <0x82001000 0 0x40000 0 0x2000>;
 93				reg = <0x1000 0 0 0 0>;
 94				#address-cells = <3>;
 95				#size-cells = <2>;
 96				interrupt-names = "intx";
 97				interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 98				#interrupt-cells = <1>;
 99				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
100					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
101				bus-range = <0x00 0xff>;
102				interrupt-map-mask = <0 0 0 7>;
103				interrupt-map = <0 0 0 1 &pcie2_intc 0>,
104						<0 0 0 2 &pcie2_intc 1>,
105						<0 0 0 3 &pcie2_intc 2>,
106						<0 0 0 4 &pcie2_intc 3>;
107				marvell,pcie-port = <1>;
108				marvell,pcie-lane = <0>;
109				clocks = <&gateclk 5>;
110				status = "disabled";
111
112				pcie2_intc: interrupt-controller {
113					interrupt-controller;
114					#interrupt-cells = <1>;
115				};
116			};
117
118			/* x1 port */
119			pcie@3,0 {
120				device_type = "pci";
121				assigned-addresses = <0x82001800 0 0x44000 0 0x2000>;
122				reg = <0x1800 0 0 0 0>;
123				#address-cells = <3>;
124				#size-cells = <2>;
125				interrupt-names = "intx";
126				interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
127				#interrupt-cells = <1>;
128				ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
129					  0x81000000 0 0 0x81000000 0x3 0 1 0>;
130				bus-range = <0x00 0xff>;
131				interrupt-map-mask = <0 0 0 7>;
132				interrupt-map = <0 0 0 1 &pcie3_intc 0>,
133						<0 0 0 2 &pcie3_intc 1>,
134						<0 0 0 3 &pcie3_intc 2>,
135						<0 0 0 4 &pcie3_intc 3>;
136				marvell,pcie-port = <2>;
137				marvell,pcie-lane = <0>;
138				clocks = <&gateclk 6>;
139				status = "disabled";
140
141				pcie3_intc: interrupt-controller {
142					interrupt-controller;
143					#interrupt-cells = <1>;
144				};
145			};
146		};
147	};
148};