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1/* SPDX-License-Identifier: ISC */
2/* Copyright (C) 2021 MediaTek Inc. */
3
4#define FIRMWARE_MT7622 "mediatek/mt7622pr2h.bin"
5#define FIRMWARE_MT7663 "mediatek/mt7663pr2h.bin"
6#define FIRMWARE_MT7668 "mediatek/mt7668pr2h.bin"
7#define FIRMWARE_MT7961 "mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin"
8
9#define HCI_EV_WMT 0xe4
10#define HCI_WMT_MAX_EVENT_SIZE 64
11
12#define BTMTK_WMT_REG_WRITE 0x1
13#define BTMTK_WMT_REG_READ 0x2
14
15#define MT7921_BTSYS_RST 0x70002610
16#define MT7921_BTSYS_RST_WITH_GPIO BIT(7)
17
18#define MT7921_PINMUX_0 0x70005050
19#define MT7921_PINMUX_1 0x70005054
20
21#define MT7921_DLSTATUS 0x7c053c10
22#define BT_DL_STATE BIT(1)
23
24enum {
25 BTMTK_WMT_PATCH_DWNLD = 0x1,
26 BTMTK_WMT_TEST = 0x2,
27 BTMTK_WMT_WAKEUP = 0x3,
28 BTMTK_WMT_HIF = 0x4,
29 BTMTK_WMT_FUNC_CTRL = 0x6,
30 BTMTK_WMT_RST = 0x7,
31 BTMTK_WMT_REGISTER = 0x8,
32 BTMTK_WMT_SEMAPHORE = 0x17,
33};
34
35enum {
36 BTMTK_WMT_INVALID,
37 BTMTK_WMT_PATCH_UNDONE,
38 BTMTK_WMT_PATCH_PROGRESS,
39 BTMTK_WMT_PATCH_DONE,
40 BTMTK_WMT_ON_UNDONE,
41 BTMTK_WMT_ON_DONE,
42 BTMTK_WMT_ON_PROGRESS,
43};
44
45struct btmtk_wmt_hdr {
46 u8 dir;
47 u8 op;
48 __le16 dlen;
49 u8 flag;
50} __packed;
51
52struct btmtk_hci_wmt_cmd {
53 struct btmtk_wmt_hdr hdr;
54 u8 data[];
55} __packed;
56
57struct btmtk_hci_wmt_evt {
58 struct hci_event_hdr hhdr;
59 struct btmtk_wmt_hdr whdr;
60} __packed;
61
62struct btmtk_hci_wmt_evt_funcc {
63 struct btmtk_hci_wmt_evt hwhdr;
64 __be16 status;
65} __packed;
66
67struct btmtk_hci_wmt_evt_reg {
68 struct btmtk_hci_wmt_evt hwhdr;
69 u8 rsv[2];
70 u8 num;
71 __le32 addr;
72 __le32 val;
73} __packed;
74
75struct btmtk_tci_sleep {
76 u8 mode;
77 __le16 duration;
78 __le16 host_duration;
79 u8 host_wakeup_pin;
80 u8 time_compensation;
81} __packed;
82
83struct btmtk_wakeon {
84 u8 mode;
85 u8 gpo;
86 u8 active_high;
87 __le16 enable_delay;
88 __le16 wakeup_delay;
89} __packed;
90
91struct btmtk_sco {
92 u8 clock_config;
93 u8 transmit_format_config;
94 u8 channel_format_config;
95 u8 channel_select_config;
96} __packed;
97
98struct reg_read_cmd {
99 u8 type;
100 u8 rsv;
101 u8 num;
102 __le32 addr;
103} __packed;
104
105struct reg_write_cmd {
106 u8 type;
107 u8 rsv;
108 u8 num;
109 __le32 addr;
110 __le32 data;
111 __le32 mask;
112} __packed;
113
114struct btmtk_hci_wmt_params {
115 u8 op;
116 u8 flag;
117 u16 dlen;
118 const void *data;
119 u32 *status;
120};
121
122typedef int (*wmt_cmd_sync_func_t)(struct hci_dev *,
123 struct btmtk_hci_wmt_params *);
124
125#if IS_ENABLED(CONFIG_BT_MTK)
126
127int btmtk_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr);
128
129int btmtk_setup_firmware_79xx(struct hci_dev *hdev, const char *fwname,
130 wmt_cmd_sync_func_t wmt_cmd_sync);
131
132int btmtk_setup_firmware(struct hci_dev *hdev, const char *fwname,
133 wmt_cmd_sync_func_t wmt_cmd_sync);
134#else
135
136static inline int btmtk_set_bdaddr(struct hci_dev *hdev,
137 const bdaddr_t *bdaddr)
138{
139 return -EOPNOTSUPP;
140}
141
142static int btmtk_setup_firmware_79xx(struct hci_dev *hdev, const char *fwname,
143 wmt_cmd_sync_func_t wmt_cmd_sync)
144{
145 return -EOPNOTSUPP;
146}
147
148static int btmtk_setup_firmware(struct hci_dev *hdev, const char *fwname,
149 wmt_cmd_sync_func_t wmt_cmd_sync)
150{
151 return -EOPNOTSUPP;
152}
153
154#endif
1/* SPDX-License-Identifier: ISC */
2/* Copyright (C) 2021 MediaTek Inc. */
3
4#define FIRMWARE_MT7622 "mediatek/mt7622pr2h.bin"
5#define FIRMWARE_MT7663 "mediatek/mt7663pr2h.bin"
6#define FIRMWARE_MT7668 "mediatek/mt7668pr2h.bin"
7#define FIRMWARE_MT7961 "mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin"
8#define FIRMWARE_MT7925 "mediatek/mt7925/BT_RAM_CODE_MT7925_1_1_hdr.bin"
9
10#define HCI_EV_WMT 0xe4
11#define HCI_WMT_MAX_EVENT_SIZE 64
12
13#define BTMTK_WMT_REG_WRITE 0x1
14#define BTMTK_WMT_REG_READ 0x2
15
16#define MT7921_BTSYS_RST 0x70002610
17#define MT7921_BTSYS_RST_WITH_GPIO BIT(7)
18
19#define MT7921_PINMUX_0 0x70005050
20#define MT7921_PINMUX_1 0x70005054
21
22#define MT7921_DLSTATUS 0x7c053c10
23#define BT_DL_STATE BIT(1)
24
25#define MTK_COREDUMP_SIZE (1024 * 1000)
26#define MTK_COREDUMP_END "coredump end"
27#define MTK_COREDUMP_END_LEN (sizeof(MTK_COREDUMP_END))
28#define MTK_COREDUMP_NUM 255
29
30enum {
31 BTMTK_WMT_PATCH_DWNLD = 0x1,
32 BTMTK_WMT_TEST = 0x2,
33 BTMTK_WMT_WAKEUP = 0x3,
34 BTMTK_WMT_HIF = 0x4,
35 BTMTK_WMT_FUNC_CTRL = 0x6,
36 BTMTK_WMT_RST = 0x7,
37 BTMTK_WMT_REGISTER = 0x8,
38 BTMTK_WMT_SEMAPHORE = 0x17,
39};
40
41enum {
42 BTMTK_WMT_INVALID,
43 BTMTK_WMT_PATCH_UNDONE,
44 BTMTK_WMT_PATCH_PROGRESS,
45 BTMTK_WMT_PATCH_DONE,
46 BTMTK_WMT_ON_UNDONE,
47 BTMTK_WMT_ON_DONE,
48 BTMTK_WMT_ON_PROGRESS,
49};
50
51struct btmtk_wmt_hdr {
52 u8 dir;
53 u8 op;
54 __le16 dlen;
55 u8 flag;
56} __packed;
57
58struct btmtk_hci_wmt_cmd {
59 struct btmtk_wmt_hdr hdr;
60 u8 data[];
61} __packed;
62
63struct btmtk_hci_wmt_evt {
64 struct hci_event_hdr hhdr;
65 struct btmtk_wmt_hdr whdr;
66} __packed;
67
68struct btmtk_hci_wmt_evt_funcc {
69 struct btmtk_hci_wmt_evt hwhdr;
70 __be16 status;
71} __packed;
72
73struct btmtk_hci_wmt_evt_reg {
74 struct btmtk_hci_wmt_evt hwhdr;
75 u8 rsv[2];
76 u8 num;
77 __le32 addr;
78 __le32 val;
79} __packed;
80
81struct btmtk_tci_sleep {
82 u8 mode;
83 __le16 duration;
84 __le16 host_duration;
85 u8 host_wakeup_pin;
86 u8 time_compensation;
87} __packed;
88
89struct btmtk_wakeon {
90 u8 mode;
91 u8 gpo;
92 u8 active_high;
93 __le16 enable_delay;
94 __le16 wakeup_delay;
95} __packed;
96
97struct btmtk_sco {
98 u8 clock_config;
99 u8 transmit_format_config;
100 u8 channel_format_config;
101 u8 channel_select_config;
102} __packed;
103
104struct reg_read_cmd {
105 u8 type;
106 u8 rsv;
107 u8 num;
108 __le32 addr;
109} __packed;
110
111struct reg_write_cmd {
112 u8 type;
113 u8 rsv;
114 u8 num;
115 __le32 addr;
116 __le32 data;
117 __le32 mask;
118} __packed;
119
120struct btmtk_hci_wmt_params {
121 u8 op;
122 u8 flag;
123 u16 dlen;
124 const void *data;
125 u32 *status;
126};
127
128typedef int (*btmtk_reset_sync_func_t)(struct hci_dev *, void *);
129
130struct btmtk_coredump_info {
131 const char *driver_name;
132 u32 fw_version;
133 u16 cnt;
134 int state;
135};
136
137struct btmediatek_data {
138 u32 dev_id;
139 btmtk_reset_sync_func_t reset_sync;
140 struct btmtk_coredump_info cd_info;
141};
142
143typedef int (*wmt_cmd_sync_func_t)(struct hci_dev *,
144 struct btmtk_hci_wmt_params *);
145
146#if IS_ENABLED(CONFIG_BT_MTK)
147
148int btmtk_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr);
149
150int btmtk_setup_firmware_79xx(struct hci_dev *hdev, const char *fwname,
151 wmt_cmd_sync_func_t wmt_cmd_sync);
152
153int btmtk_setup_firmware(struct hci_dev *hdev, const char *fwname,
154 wmt_cmd_sync_func_t wmt_cmd_sync);
155
156void btmtk_reset_sync(struct hci_dev *hdev);
157
158int btmtk_register_coredump(struct hci_dev *hdev, const char *name,
159 u32 fw_version);
160
161int btmtk_process_coredump(struct hci_dev *hdev, struct sk_buff *skb);
162#else
163
164static inline int btmtk_set_bdaddr(struct hci_dev *hdev,
165 const bdaddr_t *bdaddr)
166{
167 return -EOPNOTSUPP;
168}
169
170static int btmtk_setup_firmware_79xx(struct hci_dev *hdev, const char *fwname,
171 wmt_cmd_sync_func_t wmt_cmd_sync)
172{
173 return -EOPNOTSUPP;
174}
175
176static int btmtk_setup_firmware(struct hci_dev *hdev, const char *fwname,
177 wmt_cmd_sync_func_t wmt_cmd_sync)
178{
179 return -EOPNOTSUPP;
180}
181
182static void btmtk_reset_sync(struct hci_dev *hdev)
183{
184}
185
186static int btmtk_register_coredump(struct hci_dev *hdev, const char *name,
187 u32 fw_version)
188{
189 return -EOPNOTSUPP;
190}
191
192static int btmtk_process_coredump(struct hci_dev *hdev, struct sk_buff *skb)
193{
194 return -EOPNOTSUPP;
195}
196#endif