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1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
3#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/interrupt-controller/irq.h>
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/pinctrl/rockchip.h>
7#include <dt-bindings/clock/rk3228-cru.h>
8#include <dt-bindings/thermal/thermal.h>
9#include <dt-bindings/power/rk3228-power.h>
10
11/ {
12 #address-cells = <1>;
13 #size-cells = <1>;
14
15 interrupt-parent = <&gic>;
16
17 aliases {
18 serial0 = &uart0;
19 serial1 = &uart1;
20 serial2 = &uart2;
21 spi0 = &spi0;
22 };
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 cpu0: cpu@f00 {
29 device_type = "cpu";
30 compatible = "arm,cortex-a7";
31 reg = <0xf00>;
32 resets = <&cru SRST_CORE0>;
33 operating-points-v2 = <&cpu0_opp_table>;
34 #cooling-cells = <2>; /* min followed by max */
35 clock-latency = <40000>;
36 clocks = <&cru ARMCLK>;
37 enable-method = "psci";
38 };
39
40 cpu1: cpu@f01 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a7";
43 reg = <0xf01>;
44 resets = <&cru SRST_CORE1>;
45 operating-points-v2 = <&cpu0_opp_table>;
46 #cooling-cells = <2>; /* min followed by max */
47 enable-method = "psci";
48 };
49
50 cpu2: cpu@f02 {
51 device_type = "cpu";
52 compatible = "arm,cortex-a7";
53 reg = <0xf02>;
54 resets = <&cru SRST_CORE2>;
55 operating-points-v2 = <&cpu0_opp_table>;
56 #cooling-cells = <2>; /* min followed by max */
57 enable-method = "psci";
58 };
59
60 cpu3: cpu@f03 {
61 device_type = "cpu";
62 compatible = "arm,cortex-a7";
63 reg = <0xf03>;
64 resets = <&cru SRST_CORE3>;
65 operating-points-v2 = <&cpu0_opp_table>;
66 #cooling-cells = <2>; /* min followed by max */
67 enable-method = "psci";
68 };
69 };
70
71 cpu0_opp_table: opp-table-0 {
72 compatible = "operating-points-v2";
73 opp-shared;
74
75 opp-408000000 {
76 opp-hz = /bits/ 64 <408000000>;
77 opp-microvolt = <950000>;
78 clock-latency-ns = <40000>;
79 opp-suspend;
80 };
81 opp-600000000 {
82 opp-hz = /bits/ 64 <600000000>;
83 opp-microvolt = <975000>;
84 };
85 opp-816000000 {
86 opp-hz = /bits/ 64 <816000000>;
87 opp-microvolt = <1000000>;
88 };
89 opp-1008000000 {
90 opp-hz = /bits/ 64 <1008000000>;
91 opp-microvolt = <1175000>;
92 };
93 opp-1200000000 {
94 opp-hz = /bits/ 64 <1200000000>;
95 opp-microvolt = <1275000>;
96 };
97 };
98
99 arm-pmu {
100 compatible = "arm,cortex-a7-pmu";
101 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
102 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
105 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
106 };
107
108 psci {
109 compatible = "arm,psci-1.0", "arm,psci-0.2";
110 method = "smc";
111 };
112
113 timer {
114 compatible = "arm,armv7-timer";
115 arm,cpu-registers-not-fw-configured;
116 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
117 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
118 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
119 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
120 clock-frequency = <24000000>;
121 };
122
123 xin24m: oscillator {
124 compatible = "fixed-clock";
125 clock-frequency = <24000000>;
126 clock-output-names = "xin24m";
127 #clock-cells = <0>;
128 };
129
130 display_subsystem: display-subsystem {
131 compatible = "rockchip,display-subsystem";
132 ports = <&vop_out>;
133 };
134
135 i2s1: i2s1@100b0000 {
136 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
137 reg = <0x100b0000 0x4000>;
138 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
139 clock-names = "i2s_clk", "i2s_hclk";
140 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
141 dmas = <&pdma 14>, <&pdma 15>;
142 dma-names = "tx", "rx";
143 pinctrl-names = "default";
144 pinctrl-0 = <&i2s1_bus>;
145 status = "disabled";
146 };
147
148 i2s0: i2s0@100c0000 {
149 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
150 reg = <0x100c0000 0x4000>;
151 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
152 clock-names = "i2s_clk", "i2s_hclk";
153 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
154 dmas = <&pdma 11>, <&pdma 12>;
155 dma-names = "tx", "rx";
156 status = "disabled";
157 };
158
159 spdif: spdif@100d0000 {
160 compatible = "rockchip,rk3228-spdif";
161 reg = <0x100d0000 0x1000>;
162 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
163 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
164 clock-names = "mclk", "hclk";
165 dmas = <&pdma 10>;
166 dma-names = "tx";
167 pinctrl-names = "default";
168 pinctrl-0 = <&spdif_tx>;
169 status = "disabled";
170 };
171
172 i2s2: i2s2@100e0000 {
173 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
174 reg = <0x100e0000 0x4000>;
175 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
176 clock-names = "i2s_clk", "i2s_hclk";
177 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
178 dmas = <&pdma 0>, <&pdma 1>;
179 dma-names = "tx", "rx";
180 status = "disabled";
181 };
182
183 grf: syscon@11000000 {
184 compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd";
185 reg = <0x11000000 0x1000>;
186 #address-cells = <1>;
187 #size-cells = <1>;
188
189 io_domains: io-domains {
190 compatible = "rockchip,rk3228-io-voltage-domain";
191 status = "disabled";
192 };
193
194 power: power-controller {
195 compatible = "rockchip,rk3228-power-controller";
196 #power-domain-cells = <1>;
197 #address-cells = <1>;
198 #size-cells = <0>;
199
200 power-domain@RK3228_PD_VIO {
201 reg = <RK3228_PD_VIO>;
202 clocks = <&cru ACLK_HDCP>,
203 <&cru SCLK_HDCP>,
204 <&cru ACLK_IEP>,
205 <&cru HCLK_IEP>,
206 <&cru ACLK_RGA>,
207 <&cru HCLK_RGA>,
208 <&cru SCLK_RGA>;
209 pm_qos = <&qos_hdcp>,
210 <&qos_iep>,
211 <&qos_rga_r>,
212 <&qos_rga_w>;
213 #power-domain-cells = <0>;
214 };
215
216 power-domain@RK3228_PD_VOP {
217 reg = <RK3228_PD_VOP>;
218 clocks =<&cru ACLK_VOP>,
219 <&cru DCLK_VOP>,
220 <&cru HCLK_VOP>;
221 pm_qos = <&qos_vop>;
222 #power-domain-cells = <0>;
223 };
224
225 power-domain@RK3228_PD_VPU {
226 reg = <RK3228_PD_VPU>;
227 clocks = <&cru ACLK_VPU>,
228 <&cru HCLK_VPU>;
229 pm_qos = <&qos_vpu>;
230 #power-domain-cells = <0>;
231 };
232
233 power-domain@RK3228_PD_RKVDEC {
234 reg = <RK3228_PD_RKVDEC>;
235 clocks = <&cru ACLK_RKVDEC>,
236 <&cru HCLK_RKVDEC>,
237 <&cru SCLK_VDEC_CABAC>,
238 <&cru SCLK_VDEC_CORE>;
239 pm_qos = <&qos_rkvdec_r>,
240 <&qos_rkvdec_w>;
241 #power-domain-cells = <0>;
242 };
243
244 power-domain@RK3228_PD_GPU {
245 reg = <RK3228_PD_GPU>;
246 clocks = <&cru ACLK_GPU>;
247 pm_qos = <&qos_gpu>;
248 #power-domain-cells = <0>;
249 };
250 };
251
252 u2phy0: usb2phy@760 {
253 compatible = "rockchip,rk3228-usb2phy";
254 reg = <0x0760 0x0c>;
255 clocks = <&cru SCLK_OTGPHY0>;
256 clock-names = "phyclk";
257 clock-output-names = "usb480m_phy0";
258 #clock-cells = <0>;
259 status = "disabled";
260
261 u2phy0_otg: otg-port {
262 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
265 interrupt-names = "otg-bvalid", "otg-id",
266 "linestate";
267 #phy-cells = <0>;
268 status = "disabled";
269 };
270
271 u2phy0_host: host-port {
272 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
273 interrupt-names = "linestate";
274 #phy-cells = <0>;
275 status = "disabled";
276 };
277 };
278
279 u2phy1: usb2phy@800 {
280 compatible = "rockchip,rk3228-usb2phy";
281 reg = <0x0800 0x0c>;
282 clocks = <&cru SCLK_OTGPHY1>;
283 clock-names = "phyclk";
284 clock-output-names = "usb480m_phy1";
285 #clock-cells = <0>;
286 status = "disabled";
287
288 u2phy1_otg: otg-port {
289 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
290 interrupt-names = "linestate";
291 #phy-cells = <0>;
292 status = "disabled";
293 };
294
295 u2phy1_host: host-port {
296 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
297 interrupt-names = "linestate";
298 #phy-cells = <0>;
299 status = "disabled";
300 };
301 };
302 };
303
304 uart0: serial@11010000 {
305 compatible = "snps,dw-apb-uart";
306 reg = <0x11010000 0x100>;
307 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
308 clock-frequency = <24000000>;
309 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
310 clock-names = "baudclk", "apb_pclk";
311 pinctrl-names = "default";
312 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
313 reg-shift = <2>;
314 reg-io-width = <4>;
315 status = "disabled";
316 };
317
318 uart1: serial@11020000 {
319 compatible = "snps,dw-apb-uart";
320 reg = <0x11020000 0x100>;
321 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
322 clock-frequency = <24000000>;
323 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
324 clock-names = "baudclk", "apb_pclk";
325 pinctrl-names = "default";
326 pinctrl-0 = <&uart1_xfer>;
327 reg-shift = <2>;
328 reg-io-width = <4>;
329 status = "disabled";
330 };
331
332 uart2: serial@11030000 {
333 compatible = "snps,dw-apb-uart";
334 reg = <0x11030000 0x100>;
335 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
336 clock-frequency = <24000000>;
337 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
338 clock-names = "baudclk", "apb_pclk";
339 pinctrl-names = "default";
340 pinctrl-0 = <&uart2_xfer>;
341 reg-shift = <2>;
342 reg-io-width = <4>;
343 status = "disabled";
344 };
345
346 efuse: efuse@11040000 {
347 compatible = "rockchip,rk3228-efuse";
348 reg = <0x11040000 0x20>;
349 clocks = <&cru PCLK_EFUSE_256>;
350 clock-names = "pclk_efuse";
351 #address-cells = <1>;
352 #size-cells = <1>;
353
354 /* Data cells */
355 efuse_id: id@7 {
356 reg = <0x7 0x10>;
357 };
358 cpu_leakage: cpu_leakage@17 {
359 reg = <0x17 0x1>;
360 };
361 };
362
363 i2c0: i2c@11050000 {
364 compatible = "rockchip,rk3228-i2c";
365 reg = <0x11050000 0x1000>;
366 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
367 #address-cells = <1>;
368 #size-cells = <0>;
369 clock-names = "i2c";
370 clocks = <&cru PCLK_I2C0>;
371 pinctrl-names = "default";
372 pinctrl-0 = <&i2c0_xfer>;
373 status = "disabled";
374 };
375
376 i2c1: i2c@11060000 {
377 compatible = "rockchip,rk3228-i2c";
378 reg = <0x11060000 0x1000>;
379 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
380 #address-cells = <1>;
381 #size-cells = <0>;
382 clock-names = "i2c";
383 clocks = <&cru PCLK_I2C1>;
384 pinctrl-names = "default";
385 pinctrl-0 = <&i2c1_xfer>;
386 status = "disabled";
387 };
388
389 i2c2: i2c@11070000 {
390 compatible = "rockchip,rk3228-i2c";
391 reg = <0x11070000 0x1000>;
392 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
393 #address-cells = <1>;
394 #size-cells = <0>;
395 clock-names = "i2c";
396 clocks = <&cru PCLK_I2C2>;
397 pinctrl-names = "default";
398 pinctrl-0 = <&i2c2_xfer>;
399 status = "disabled";
400 };
401
402 i2c3: i2c@11080000 {
403 compatible = "rockchip,rk3228-i2c";
404 reg = <0x11080000 0x1000>;
405 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
406 #address-cells = <1>;
407 #size-cells = <0>;
408 clock-names = "i2c";
409 clocks = <&cru PCLK_I2C3>;
410 pinctrl-names = "default";
411 pinctrl-0 = <&i2c3_xfer>;
412 status = "disabled";
413 };
414
415 spi0: spi@11090000 {
416 compatible = "rockchip,rk3228-spi";
417 reg = <0x11090000 0x1000>;
418 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
419 #address-cells = <1>;
420 #size-cells = <0>;
421 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
422 clock-names = "spiclk", "apb_pclk";
423 pinctrl-names = "default";
424 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
425 status = "disabled";
426 };
427
428 wdt: watchdog@110a0000 {
429 compatible = "rockchip,rk3228-wdt", "snps,dw-wdt";
430 reg = <0x110a0000 0x100>;
431 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&cru PCLK_CPU>;
433 status = "disabled";
434 };
435
436 pwm0: pwm@110b0000 {
437 compatible = "rockchip,rk3288-pwm";
438 reg = <0x110b0000 0x10>;
439 #pwm-cells = <3>;
440 clocks = <&cru PCLK_PWM>;
441 pinctrl-names = "default";
442 pinctrl-0 = <&pwm0_pin>;
443 status = "disabled";
444 };
445
446 pwm1: pwm@110b0010 {
447 compatible = "rockchip,rk3288-pwm";
448 reg = <0x110b0010 0x10>;
449 #pwm-cells = <3>;
450 clocks = <&cru PCLK_PWM>;
451 pinctrl-names = "default";
452 pinctrl-0 = <&pwm1_pin>;
453 status = "disabled";
454 };
455
456 pwm2: pwm@110b0020 {
457 compatible = "rockchip,rk3288-pwm";
458 reg = <0x110b0020 0x10>;
459 #pwm-cells = <3>;
460 clocks = <&cru PCLK_PWM>;
461 pinctrl-names = "default";
462 pinctrl-0 = <&pwm2_pin>;
463 status = "disabled";
464 };
465
466 pwm3: pwm@110b0030 {
467 compatible = "rockchip,rk3288-pwm";
468 reg = <0x110b0030 0x10>;
469 #pwm-cells = <2>;
470 clocks = <&cru PCLK_PWM>;
471 pinctrl-names = "default";
472 pinctrl-0 = <&pwm3_pin>;
473 status = "disabled";
474 };
475
476 timer: timer@110c0000 {
477 compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
478 reg = <0x110c0000 0x20>;
479 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
480 clocks = <&cru PCLK_TIMER>, <&xin24m>;
481 clock-names = "pclk", "timer";
482 };
483
484 cru: clock-controller@110e0000 {
485 compatible = "rockchip,rk3228-cru";
486 reg = <0x110e0000 0x1000>;
487 clocks = <&xin24m>;
488 clock-names = "xin24m";
489 rockchip,grf = <&grf>;
490 #clock-cells = <1>;
491 #reset-cells = <1>;
492 assigned-clocks =
493 <&cru PLL_GPLL>, <&cru ARMCLK>,
494 <&cru PLL_CPLL>, <&cru ACLK_PERI>,
495 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
496 <&cru ACLK_CPU>, <&cru HCLK_CPU>,
497 <&cru PCLK_CPU>;
498 assigned-clock-rates =
499 <594000000>, <816000000>,
500 <500000000>, <150000000>,
501 <150000000>, <75000000>,
502 <150000000>, <150000000>,
503 <75000000>;
504 };
505
506 pdma: dma-controller@110f0000 {
507 compatible = "arm,pl330", "arm,primecell";
508 reg = <0x110f0000 0x4000>;
509 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
511 #dma-cells = <1>;
512 arm,pl330-periph-burst;
513 clocks = <&cru ACLK_DMAC>;
514 clock-names = "apb_pclk";
515 };
516
517 thermal-zones {
518 cpu_thermal: cpu-thermal {
519 polling-delay-passive = <100>; /* milliseconds */
520 polling-delay = <5000>; /* milliseconds */
521
522 thermal-sensors = <&tsadc 0>;
523
524 trips {
525 cpu_alert0: cpu_alert0 {
526 temperature = <70000>; /* millicelsius */
527 hysteresis = <2000>; /* millicelsius */
528 type = "passive";
529 };
530 cpu_alert1: cpu_alert1 {
531 temperature = <75000>; /* millicelsius */
532 hysteresis = <2000>; /* millicelsius */
533 type = "passive";
534 };
535 cpu_crit: cpu_crit {
536 temperature = <90000>; /* millicelsius */
537 hysteresis = <2000>; /* millicelsius */
538 type = "critical";
539 };
540 };
541
542 cooling-maps {
543 map0 {
544 trip = <&cpu_alert0>;
545 cooling-device =
546 <&cpu0 THERMAL_NO_LIMIT 6>,
547 <&cpu1 THERMAL_NO_LIMIT 6>,
548 <&cpu2 THERMAL_NO_LIMIT 6>,
549 <&cpu3 THERMAL_NO_LIMIT 6>;
550 };
551 map1 {
552 trip = <&cpu_alert1>;
553 cooling-device =
554 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
555 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
556 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
557 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
558 };
559 };
560 };
561 };
562
563 tsadc: tsadc@11150000 {
564 compatible = "rockchip,rk3228-tsadc";
565 reg = <0x11150000 0x100>;
566 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
567 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
568 clock-names = "tsadc", "apb_pclk";
569 assigned-clocks = <&cru SCLK_TSADC>;
570 assigned-clock-rates = <32768>;
571 resets = <&cru SRST_TSADC>;
572 reset-names = "tsadc-apb";
573 pinctrl-names = "init", "default", "sleep";
574 pinctrl-0 = <&otp_pin>;
575 pinctrl-1 = <&otp_out>;
576 pinctrl-2 = <&otp_pin>;
577 #thermal-sensor-cells = <1>;
578 rockchip,hw-tshut-temp = <95000>;
579 status = "disabled";
580 };
581
582 hdmi_phy: hdmi-phy@12030000 {
583 compatible = "rockchip,rk3228-hdmi-phy";
584 reg = <0x12030000 0x10000>;
585 clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>;
586 clock-names = "sysclk", "refoclk", "refpclk";
587 #clock-cells = <0>;
588 clock-output-names = "hdmiphy_phy";
589 #phy-cells = <0>;
590 status = "disabled";
591 };
592
593 gpu: gpu@20000000 {
594 compatible = "rockchip,rk3228-mali", "arm,mali-400";
595 reg = <0x20000000 0x10000>;
596 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
598 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
599 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
600 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
601 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
602 interrupt-names = "gp",
603 "gpmmu",
604 "pp0",
605 "ppmmu0",
606 "pp1",
607 "ppmmu1";
608 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
609 clock-names = "bus", "core";
610 power-domains = <&power RK3228_PD_GPU>;
611 resets = <&cru SRST_GPU_A>;
612 status = "disabled";
613 };
614
615 vpu: video-codec@20020000 {
616 compatible = "rockchip,rk3228-vpu", "rockchip,rk3399-vpu";
617 reg = <0x20020000 0x800>;
618 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
619 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
620 interrupt-names = "vepu", "vdpu";
621 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
622 clock-names = "aclk", "hclk";
623 iommus = <&vpu_mmu>;
624 power-domains = <&power RK3228_PD_VPU>;
625 };
626
627 vpu_mmu: iommu@20020800 {
628 compatible = "rockchip,iommu";
629 reg = <0x20020800 0x100>;
630 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
631 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
632 clock-names = "aclk", "iface";
633 power-domains = <&power RK3228_PD_VPU>;
634 #iommu-cells = <0>;
635 };
636
637 vdec: video-codec@20030000 {
638 compatible = "rockchip,rk3228-vdec", "rockchip,rk3399-vdec";
639 reg = <0x20030000 0x480>;
640 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
641 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
642 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
643 clock-names = "axi", "ahb", "cabac", "core";
644 assigned-clocks = <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
645 assigned-clock-rates = <300000000>, <300000000>;
646 iommus = <&vdec_mmu>;
647 power-domains = <&power RK3228_PD_RKVDEC>;
648 };
649
650 vdec_mmu: iommu@20030480 {
651 compatible = "rockchip,iommu";
652 reg = <0x20030480 0x40>, <0x200304c0 0x40>;
653 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
654 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
655 clock-names = "aclk", "iface";
656 power-domains = <&power RK3228_PD_RKVDEC>;
657 #iommu-cells = <0>;
658 };
659
660 vop: vop@20050000 {
661 compatible = "rockchip,rk3228-vop";
662 reg = <0x20050000 0x1ffc>;
663 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
664 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
665 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
666 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
667 reset-names = "axi", "ahb", "dclk";
668 iommus = <&vop_mmu>;
669 power-domains = <&power RK3228_PD_VOP>;
670 status = "disabled";
671
672 vop_out: port {
673 #address-cells = <1>;
674 #size-cells = <0>;
675
676 vop_out_hdmi: endpoint@0 {
677 reg = <0>;
678 remote-endpoint = <&hdmi_in_vop>;
679 };
680 };
681 };
682
683 vop_mmu: iommu@20053f00 {
684 compatible = "rockchip,iommu";
685 reg = <0x20053f00 0x100>;
686 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
687 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
688 clock-names = "aclk", "iface";
689 power-domains = <&power RK3228_PD_VOP>;
690 #iommu-cells = <0>;
691 status = "disabled";
692 };
693
694 rga: rga@20060000 {
695 compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga";
696 reg = <0x20060000 0x1000>;
697 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
699 clock-names = "aclk", "hclk", "sclk";
700 power-domains = <&power RK3228_PD_VIO>;
701 resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>;
702 reset-names = "core", "axi", "ahb";
703 };
704
705 iep_mmu: iommu@20070800 {
706 compatible = "rockchip,iommu";
707 reg = <0x20070800 0x100>;
708 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
709 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
710 clock-names = "aclk", "iface";
711 power-domains = <&power RK3228_PD_VIO>;
712 #iommu-cells = <0>;
713 status = "disabled";
714 };
715
716 hdmi: hdmi@200a0000 {
717 compatible = "rockchip,rk3228-dw-hdmi";
718 reg = <0x200a0000 0x20000>;
719 reg-io-width = <4>;
720 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
721 assigned-clocks = <&cru SCLK_HDMI_PHY>;
722 assigned-clock-parents = <&hdmi_phy>;
723 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
724 clock-names = "iahb", "isfr", "cec";
725 pinctrl-names = "default";
726 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
727 resets = <&cru SRST_HDMI_P>;
728 reset-names = "hdmi";
729 phys = <&hdmi_phy>;
730 phy-names = "hdmi";
731 rockchip,grf = <&grf>;
732 status = "disabled";
733
734 ports {
735 hdmi_in: port {
736 #address-cells = <1>;
737 #size-cells = <0>;
738 hdmi_in_vop: endpoint@0 {
739 reg = <0>;
740 remote-endpoint = <&vop_out_hdmi>;
741 };
742 };
743 };
744 };
745
746 sdmmc: mmc@30000000 {
747 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
748 reg = <0x30000000 0x4000>;
749 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
750 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
751 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
752 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
753 fifo-depth = <0x100>;
754 pinctrl-names = "default";
755 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
756 status = "disabled";
757 };
758
759 sdio: mmc@30010000 {
760 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
761 reg = <0x30010000 0x4000>;
762 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
763 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
764 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
765 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
766 fifo-depth = <0x100>;
767 pinctrl-names = "default";
768 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
769 status = "disabled";
770 };
771
772 emmc: mmc@30020000 {
773 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
774 reg = <0x30020000 0x4000>;
775 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
776 clock-frequency = <37500000>;
777 max-frequency = <37500000>;
778 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
779 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
780 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
781 bus-width = <8>;
782 rockchip,default-sample-phase = <158>;
783 fifo-depth = <0x100>;
784 pinctrl-names = "default";
785 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
786 resets = <&cru SRST_EMMC>;
787 reset-names = "reset";
788 status = "disabled";
789 };
790
791 usb_otg: usb@30040000 {
792 compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb",
793 "snps,dwc2";
794 reg = <0x30040000 0x40000>;
795 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
796 clocks = <&cru HCLK_OTG>;
797 clock-names = "otg";
798 dr_mode = "otg";
799 g-np-tx-fifo-size = <16>;
800 g-rx-fifo-size = <280>;
801 g-tx-fifo-size = <256 128 128 64 32 16>;
802 phys = <&u2phy0_otg>;
803 phy-names = "usb2-phy";
804 status = "disabled";
805 };
806
807 usb_host0_ehci: usb@30080000 {
808 compatible = "generic-ehci";
809 reg = <0x30080000 0x20000>;
810 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
811 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
812 phys = <&u2phy0_host>;
813 phy-names = "usb";
814 status = "disabled";
815 };
816
817 usb_host0_ohci: usb@300a0000 {
818 compatible = "generic-ohci";
819 reg = <0x300a0000 0x20000>;
820 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
821 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
822 phys = <&u2phy0_host>;
823 phy-names = "usb";
824 status = "disabled";
825 };
826
827 usb_host1_ehci: usb@300c0000 {
828 compatible = "generic-ehci";
829 reg = <0x300c0000 0x20000>;
830 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
831 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
832 phys = <&u2phy1_otg>;
833 phy-names = "usb";
834 status = "disabled";
835 };
836
837 usb_host1_ohci: usb@300e0000 {
838 compatible = "generic-ohci";
839 reg = <0x300e0000 0x20000>;
840 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
841 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
842 phys = <&u2phy1_otg>;
843 phy-names = "usb";
844 status = "disabled";
845 };
846
847 usb_host2_ehci: usb@30100000 {
848 compatible = "generic-ehci";
849 reg = <0x30100000 0x20000>;
850 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
851 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
852 phys = <&u2phy1_host>;
853 phy-names = "usb";
854 status = "disabled";
855 };
856
857 usb_host2_ohci: usb@30120000 {
858 compatible = "generic-ohci";
859 reg = <0x30120000 0x20000>;
860 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
861 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
862 phys = <&u2phy1_host>;
863 phy-names = "usb";
864 status = "disabled";
865 };
866
867 gmac: ethernet@30200000 {
868 compatible = "rockchip,rk3228-gmac";
869 reg = <0x30200000 0x10000>;
870 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
871 interrupt-names = "macirq";
872 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
873 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
874 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
875 <&cru PCLK_GMAC>;
876 clock-names = "stmmaceth", "mac_clk_rx",
877 "mac_clk_tx", "clk_mac_ref",
878 "clk_mac_refout", "aclk_mac",
879 "pclk_mac";
880 resets = <&cru SRST_GMAC>;
881 reset-names = "stmmaceth";
882 rockchip,grf = <&grf>;
883 status = "disabled";
884 };
885
886 qos_iep: qos@31030080 {
887 compatible = "rockchip,rk3228-qos", "syscon";
888 reg = <0x31030080 0x20>;
889 };
890
891 qos_rga_w: qos@31030100 {
892 compatible = "rockchip,rk3228-qos", "syscon";
893 reg = <0x31030100 0x20>;
894 };
895
896 qos_hdcp: qos@31030180 {
897 compatible = "rockchip,rk3228-qos", "syscon";
898 reg = <0x31030180 0x20>;
899 };
900
901 qos_rga_r: qos@31030200 {
902 compatible = "rockchip,rk3228-qos", "syscon";
903 reg = <0x31030200 0x20>;
904 };
905
906 qos_vpu: qos@31040000 {
907 compatible = "rockchip,rk3228-qos", "syscon";
908 reg = <0x31040000 0x20>;
909 };
910
911 qos_gpu: qos@31050000 {
912 compatible = "rockchip,rk3228-qos", "syscon";
913 reg = <0x31050000 0x20>;
914 };
915
916 qos_vop: qos@31060000 {
917 compatible = "rockchip,rk3228-qos", "syscon";
918 reg = <0x31060000 0x20>;
919 };
920
921 qos_rkvdec_r: qos@31070000 {
922 compatible = "rockchip,rk3228-qos", "syscon";
923 reg = <0x31070000 0x20>;
924 };
925
926 qos_rkvdec_w: qos@31070080 {
927 compatible = "rockchip,rk3228-qos", "syscon";
928 reg = <0x31070080 0x20>;
929 };
930
931 gic: interrupt-controller@32010000 {
932 compatible = "arm,gic-400";
933 interrupt-controller;
934 #interrupt-cells = <3>;
935 #address-cells = <0>;
936
937 reg = <0x32011000 0x1000>,
938 <0x32012000 0x2000>,
939 <0x32014000 0x2000>,
940 <0x32016000 0x2000>;
941 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
942 };
943
944 pinctrl: pinctrl {
945 compatible = "rockchip,rk3228-pinctrl";
946 rockchip,grf = <&grf>;
947 #address-cells = <1>;
948 #size-cells = <1>;
949 ranges;
950
951 gpio0: gpio@11110000 {
952 compatible = "rockchip,gpio-bank";
953 reg = <0x11110000 0x100>;
954 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
955 clocks = <&cru PCLK_GPIO0>;
956
957 gpio-controller;
958 #gpio-cells = <2>;
959
960 interrupt-controller;
961 #interrupt-cells = <2>;
962 };
963
964 gpio1: gpio@11120000 {
965 compatible = "rockchip,gpio-bank";
966 reg = <0x11120000 0x100>;
967 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
968 clocks = <&cru PCLK_GPIO1>;
969
970 gpio-controller;
971 #gpio-cells = <2>;
972
973 interrupt-controller;
974 #interrupt-cells = <2>;
975 };
976
977 gpio2: gpio@11130000 {
978 compatible = "rockchip,gpio-bank";
979 reg = <0x11130000 0x100>;
980 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
981 clocks = <&cru PCLK_GPIO2>;
982
983 gpio-controller;
984 #gpio-cells = <2>;
985
986 interrupt-controller;
987 #interrupt-cells = <2>;
988 };
989
990 gpio3: gpio@11140000 {
991 compatible = "rockchip,gpio-bank";
992 reg = <0x11140000 0x100>;
993 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
994 clocks = <&cru PCLK_GPIO3>;
995
996 gpio-controller;
997 #gpio-cells = <2>;
998
999 interrupt-controller;
1000 #interrupt-cells = <2>;
1001 };
1002
1003 pcfg_pull_up: pcfg-pull-up {
1004 bias-pull-up;
1005 };
1006
1007 pcfg_pull_down: pcfg-pull-down {
1008 bias-pull-down;
1009 };
1010
1011 pcfg_pull_none: pcfg-pull-none {
1012 bias-disable;
1013 };
1014
1015 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
1016 drive-strength = <12>;
1017 };
1018
1019 sdmmc {
1020 sdmmc_clk: sdmmc-clk {
1021 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>;
1022 };
1023
1024 sdmmc_cmd: sdmmc-cmd {
1025 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>;
1026 };
1027
1028 sdmmc_bus4: sdmmc-bus4 {
1029 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
1030 <1 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
1031 <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>,
1032 <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>;
1033 };
1034 };
1035
1036 sdio {
1037 sdio_clk: sdio-clk {
1038 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>;
1039 };
1040
1041 sdio_cmd: sdio-cmd {
1042 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>;
1043 };
1044
1045 sdio_bus4: sdio-bus4 {
1046 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>,
1047 <3 RK_PA3 1 &pcfg_pull_none_drv_12ma>,
1048 <3 RK_PA4 1 &pcfg_pull_none_drv_12ma>,
1049 <3 RK_PA5 1 &pcfg_pull_none_drv_12ma>;
1050 };
1051 };
1052
1053 emmc {
1054 emmc_clk: emmc-clk {
1055 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
1056 };
1057
1058 emmc_cmd: emmc-cmd {
1059 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>;
1060 };
1061
1062 emmc_bus8: emmc-bus8 {
1063 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>,
1064 <1 RK_PD1 2 &pcfg_pull_none>,
1065 <1 RK_PD2 2 &pcfg_pull_none>,
1066 <1 RK_PD3 2 &pcfg_pull_none>,
1067 <1 RK_PD4 2 &pcfg_pull_none>,
1068 <1 RK_PD5 2 &pcfg_pull_none>,
1069 <1 RK_PD6 2 &pcfg_pull_none>,
1070 <1 RK_PD7 2 &pcfg_pull_none>;
1071 };
1072 };
1073
1074 gmac {
1075 rgmii_pins: rgmii-pins {
1076 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
1077 <2 RK_PB4 1 &pcfg_pull_none>,
1078 <2 RK_PD1 1 &pcfg_pull_none>,
1079 <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
1080 <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
1081 <2 RK_PC6 1 &pcfg_pull_none_drv_12ma>,
1082 <2 RK_PC7 1 &pcfg_pull_none_drv_12ma>,
1083 <2 RK_PB1 1 &pcfg_pull_none_drv_12ma>,
1084 <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,
1085 <2 RK_PC1 1 &pcfg_pull_none>,
1086 <2 RK_PC0 1 &pcfg_pull_none>,
1087 <2 RK_PC5 2 &pcfg_pull_none>,
1088 <2 RK_PC4 2 &pcfg_pull_none>,
1089 <2 RK_PB3 1 &pcfg_pull_none>,
1090 <2 RK_PB0 1 &pcfg_pull_none>;
1091 };
1092
1093 rmii_pins: rmii-pins {
1094 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
1095 <2 RK_PB4 1 &pcfg_pull_none>,
1096 <2 RK_PD1 1 &pcfg_pull_none>,
1097 <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
1098 <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
1099 <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,
1100 <2 RK_PC1 1 &pcfg_pull_none>,
1101 <2 RK_PC0 1 &pcfg_pull_none>,
1102 <2 RK_PB0 1 &pcfg_pull_none>,
1103 <2 RK_PB7 1 &pcfg_pull_none>;
1104 };
1105
1106 phy_pins: phy-pins {
1107 rockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>,
1108 <2 RK_PB0 2 &pcfg_pull_none>;
1109 };
1110 };
1111
1112 hdmi {
1113 hdmi_hpd: hdmi-hpd {
1114 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>;
1115 };
1116
1117 hdmii2c_xfer: hdmii2c-xfer {
1118 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
1119 <0 RK_PA7 2 &pcfg_pull_none>;
1120 };
1121
1122 hdmi_cec: hdmi-cec {
1123 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
1124 };
1125 };
1126
1127 i2c0 {
1128 i2c0_xfer: i2c0-xfer {
1129 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
1130 <0 RK_PA1 1 &pcfg_pull_none>;
1131 };
1132 };
1133
1134 i2c1 {
1135 i2c1_xfer: i2c1-xfer {
1136 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
1137 <0 RK_PA3 1 &pcfg_pull_none>;
1138 };
1139 };
1140
1141 i2c2 {
1142 i2c2_xfer: i2c2-xfer {
1143 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
1144 <2 RK_PC5 1 &pcfg_pull_none>;
1145 };
1146 };
1147
1148 i2c3 {
1149 i2c3_xfer: i2c3-xfer {
1150 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
1151 <0 RK_PA7 1 &pcfg_pull_none>;
1152 };
1153 };
1154
1155 spi0 {
1156 spi0_clk: spi0-clk {
1157 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>;
1158 };
1159 spi0_cs0: spi0-cs0 {
1160 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>;
1161 };
1162 spi0_tx: spi0-tx {
1163 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
1164 };
1165 spi0_rx: spi0-rx {
1166 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
1167 };
1168 spi0_cs1: spi0-cs1 {
1169 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>;
1170 };
1171 };
1172
1173 spi1 {
1174 spi1_clk: spi1-clk {
1175 rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>;
1176 };
1177 spi1_cs0: spi1-cs0 {
1178 rockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>;
1179 };
1180 spi1_rx: spi1-rx {
1181 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>;
1182 };
1183 spi1_tx: spi1-tx {
1184 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>;
1185 };
1186 spi1_cs1: spi1-cs1 {
1187 rockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>;
1188 };
1189 };
1190
1191 i2s1 {
1192 i2s1_bus: i2s1-bus {
1193 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
1194 <0 RK_PB1 1 &pcfg_pull_none>,
1195 <0 RK_PB3 1 &pcfg_pull_none>,
1196 <0 RK_PB4 1 &pcfg_pull_none>,
1197 <0 RK_PB5 1 &pcfg_pull_none>,
1198 <0 RK_PB6 1 &pcfg_pull_none>,
1199 <1 RK_PA2 2 &pcfg_pull_none>,
1200 <1 RK_PA4 2 &pcfg_pull_none>,
1201 <1 RK_PA5 2 &pcfg_pull_none>;
1202 };
1203 };
1204
1205 pwm0 {
1206 pwm0_pin: pwm0-pin {
1207 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>;
1208 };
1209 };
1210
1211 pwm1 {
1212 pwm1_pin: pwm1-pin {
1213 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1214 };
1215 };
1216
1217 pwm2 {
1218 pwm2_pin: pwm2-pin {
1219 rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>;
1220 };
1221 };
1222
1223 pwm3 {
1224 pwm3_pin: pwm3-pin {
1225 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
1226 };
1227 };
1228
1229 spdif {
1230 spdif_tx: spdif-tx {
1231 rockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>;
1232 };
1233 };
1234
1235 tsadc {
1236 otp_pin: otp-pin {
1237 rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
1238 };
1239
1240 otp_out: otp-out {
1241 rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>;
1242 };
1243 };
1244
1245 uart0 {
1246 uart0_xfer: uart0-xfer {
1247 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>,
1248 <2 RK_PD3 1 &pcfg_pull_none>;
1249 };
1250
1251 uart0_cts: uart0-cts {
1252 rockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>;
1253 };
1254
1255 uart0_rts: uart0-rts {
1256 rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>;
1257 };
1258 };
1259
1260 uart1 {
1261 uart1_xfer: uart1-xfer {
1262 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
1263 <1 RK_PB2 1 &pcfg_pull_none>;
1264 };
1265
1266 uart1_cts: uart1-cts {
1267 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>;
1268 };
1269
1270 uart1_rts: uart1-rts {
1271 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1272 };
1273 };
1274
1275 uart2 {
1276 uart2_xfer: uart2-xfer {
1277 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
1278 <1 RK_PC3 2 &pcfg_pull_none>;
1279 };
1280
1281 uart21_xfer: uart21-xfer {
1282 rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>,
1283 <1 RK_PB1 2 &pcfg_pull_none>;
1284 };
1285
1286 uart2_cts: uart2-cts {
1287 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
1288 };
1289
1290 uart2_rts: uart2-rts {
1291 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;
1292 };
1293 };
1294 };
1295};