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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * it87.c - Part of lm_sensors, Linux kernel modules for hardware
4 * monitoring.
5 *
6 * The IT8705F is an LPC-based Super I/O part that contains UARTs, a
7 * parallel port, an IR port, a MIDI port, a floppy controller, etc., in
8 * addition to an Environment Controller (Enhanced Hardware Monitor and
9 * Fan Controller)
10 *
11 * This driver supports only the Environment Controller in the IT8705F and
12 * similar parts. The other devices are supported by different drivers.
13 *
14 * Supports: IT8603E Super I/O chip w/LPC interface
15 * IT8620E Super I/O chip w/LPC interface
16 * IT8622E Super I/O chip w/LPC interface
17 * IT8623E Super I/O chip w/LPC interface
18 * IT8628E Super I/O chip w/LPC interface
19 * IT8705F Super I/O chip w/LPC interface
20 * IT8712F Super I/O chip w/LPC interface
21 * IT8716F Super I/O chip w/LPC interface
22 * IT8718F Super I/O chip w/LPC interface
23 * IT8720F Super I/O chip w/LPC interface
24 * IT8721F Super I/O chip w/LPC interface
25 * IT8726F Super I/O chip w/LPC interface
26 * IT8728F Super I/O chip w/LPC interface
27 * IT8732F Super I/O chip w/LPC interface
28 * IT8758E Super I/O chip w/LPC interface
29 * IT8771E Super I/O chip w/LPC interface
30 * IT8772E Super I/O chip w/LPC interface
31 * IT8781F Super I/O chip w/LPC interface
32 * IT8782F Super I/O chip w/LPC interface
33 * IT8783E/F Super I/O chip w/LPC interface
34 * IT8786E Super I/O chip w/LPC interface
35 * IT8790E Super I/O chip w/LPC interface
36 * IT8792E Super I/O chip w/LPC interface
37 * Sis950 A clone of the IT8705F
38 *
39 * Copyright (C) 2001 Chris Gauthron
40 * Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
41 */
42
43#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44
45#include <linux/bitops.h>
46#include <linux/module.h>
47#include <linux/init.h>
48#include <linux/slab.h>
49#include <linux/jiffies.h>
50#include <linux/platform_device.h>
51#include <linux/hwmon.h>
52#include <linux/hwmon-sysfs.h>
53#include <linux/hwmon-vid.h>
54#include <linux/err.h>
55#include <linux/mutex.h>
56#include <linux/sysfs.h>
57#include <linux/string.h>
58#include <linux/dmi.h>
59#include <linux/acpi.h>
60#include <linux/io.h>
61
62#define DRVNAME "it87"
63
64enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
65 it8771, it8772, it8781, it8782, it8783, it8786, it8790,
66 it8792, it8603, it8620, it8622, it8628 };
67
68static unsigned short force_id;
69module_param(force_id, ushort, 0);
70MODULE_PARM_DESC(force_id, "Override the detected device ID");
71
72static bool ignore_resource_conflict;
73module_param(ignore_resource_conflict, bool, 0);
74MODULE_PARM_DESC(ignore_resource_conflict, "Ignore ACPI resource conflict");
75
76static struct platform_device *it87_pdev[2];
77
78#define REG_2E 0x2e /* The register to read/write */
79#define REG_4E 0x4e /* Secondary register to read/write */
80
81#define DEV 0x07 /* Register: Logical device select */
82#define PME 0x04 /* The device with the fan registers in it */
83
84/* The device with the IT8718F/IT8720F VID value in it */
85#define GPIO 0x07
86
87#define DEVID 0x20 /* Register: Device ID */
88#define DEVREV 0x22 /* Register: Device Revision */
89
90static inline int superio_inb(int ioreg, int reg)
91{
92 outb(reg, ioreg);
93 return inb(ioreg + 1);
94}
95
96static inline void superio_outb(int ioreg, int reg, int val)
97{
98 outb(reg, ioreg);
99 outb(val, ioreg + 1);
100}
101
102static int superio_inw(int ioreg, int reg)
103{
104 int val;
105
106 outb(reg++, ioreg);
107 val = inb(ioreg + 1) << 8;
108 outb(reg, ioreg);
109 val |= inb(ioreg + 1);
110 return val;
111}
112
113static inline void superio_select(int ioreg, int ldn)
114{
115 outb(DEV, ioreg);
116 outb(ldn, ioreg + 1);
117}
118
119static inline int superio_enter(int ioreg)
120{
121 /*
122 * Try to reserve ioreg and ioreg + 1 for exclusive access.
123 */
124 if (!request_muxed_region(ioreg, 2, DRVNAME))
125 return -EBUSY;
126
127 outb(0x87, ioreg);
128 outb(0x01, ioreg);
129 outb(0x55, ioreg);
130 outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
131 return 0;
132}
133
134static inline void superio_exit(int ioreg)
135{
136 outb(0x02, ioreg);
137 outb(0x02, ioreg + 1);
138 release_region(ioreg, 2);
139}
140
141/* Logical device 4 registers */
142#define IT8712F_DEVID 0x8712
143#define IT8705F_DEVID 0x8705
144#define IT8716F_DEVID 0x8716
145#define IT8718F_DEVID 0x8718
146#define IT8720F_DEVID 0x8720
147#define IT8721F_DEVID 0x8721
148#define IT8726F_DEVID 0x8726
149#define IT8728F_DEVID 0x8728
150#define IT8732F_DEVID 0x8732
151#define IT8792E_DEVID 0x8733
152#define IT8771E_DEVID 0x8771
153#define IT8772E_DEVID 0x8772
154#define IT8781F_DEVID 0x8781
155#define IT8782F_DEVID 0x8782
156#define IT8783E_DEVID 0x8783
157#define IT8786E_DEVID 0x8786
158#define IT8790E_DEVID 0x8790
159#define IT8603E_DEVID 0x8603
160#define IT8620E_DEVID 0x8620
161#define IT8622E_DEVID 0x8622
162#define IT8623E_DEVID 0x8623
163#define IT8628E_DEVID 0x8628
164#define IT87_ACT_REG 0x30
165#define IT87_BASE_REG 0x60
166
167/* Logical device 7 registers (IT8712F and later) */
168#define IT87_SIO_GPIO1_REG 0x25
169#define IT87_SIO_GPIO2_REG 0x26
170#define IT87_SIO_GPIO3_REG 0x27
171#define IT87_SIO_GPIO4_REG 0x28
172#define IT87_SIO_GPIO5_REG 0x29
173#define IT87_SIO_PINX1_REG 0x2a /* Pin selection */
174#define IT87_SIO_PINX2_REG 0x2c /* Pin selection */
175#define IT87_SIO_SPI_REG 0xef /* SPI function pin select */
176#define IT87_SIO_VID_REG 0xfc /* VID value */
177#define IT87_SIO_BEEP_PIN_REG 0xf6 /* Beep pin mapping */
178
179/* Update battery voltage after every reading if true */
180static bool update_vbat;
181
182/* Not all BIOSes properly configure the PWM registers */
183static bool fix_pwm_polarity;
184
185/* Many IT87 constants specified below */
186
187/* Length of ISA address segment */
188#define IT87_EXTENT 8
189
190/* Length of ISA address segment for Environmental Controller */
191#define IT87_EC_EXTENT 2
192
193/* Offset of EC registers from ISA base address */
194#define IT87_EC_OFFSET 5
195
196/* Where are the ISA address/data registers relative to the EC base address */
197#define IT87_ADDR_REG_OFFSET 0
198#define IT87_DATA_REG_OFFSET 1
199
200/*----- The IT87 registers -----*/
201
202#define IT87_REG_CONFIG 0x00
203
204#define IT87_REG_ALARM1 0x01
205#define IT87_REG_ALARM2 0x02
206#define IT87_REG_ALARM3 0x03
207
208/*
209 * The IT8718F and IT8720F have the VID value in a different register, in
210 * Super-I/O configuration space.
211 */
212#define IT87_REG_VID 0x0a
213/*
214 * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
215 * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
216 * mode.
217 */
218#define IT87_REG_FAN_DIV 0x0b
219#define IT87_REG_FAN_16BIT 0x0c
220
221/*
222 * Monitors:
223 * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12)
224 * - up to 6 temp (1 to 6)
225 * - up to 6 fan (1 to 6)
226 */
227
228static const u8 IT87_REG_FAN[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
229static const u8 IT87_REG_FAN_MIN[] = { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
230static const u8 IT87_REG_FANX[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
231static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
232static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59 };
233
234#define IT87_REG_FAN_MAIN_CTRL 0x13
235#define IT87_REG_FAN_CTL 0x14
236static const u8 IT87_REG_PWM[] = { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
237static const u8 IT87_REG_PWM_DUTY[] = { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
238
239static const u8 IT87_REG_VIN[] = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
240 0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
241
242#define IT87_REG_TEMP(nr) (0x29 + (nr))
243
244#define IT87_REG_VIN_MAX(nr) (0x30 + (nr) * 2)
245#define IT87_REG_VIN_MIN(nr) (0x31 + (nr) * 2)
246#define IT87_REG_TEMP_HIGH(nr) (0x40 + (nr) * 2)
247#define IT87_REG_TEMP_LOW(nr) (0x41 + (nr) * 2)
248
249#define IT87_REG_VIN_ENABLE 0x50
250#define IT87_REG_TEMP_ENABLE 0x51
251#define IT87_REG_TEMP_EXTRA 0x55
252#define IT87_REG_BEEP_ENABLE 0x5c
253
254#define IT87_REG_CHIPID 0x58
255
256static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 };
257
258#define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i))
259#define IT87_REG_AUTO_PWM(nr, i) (IT87_REG_AUTO_BASE[nr] + 5 + (i))
260
261#define IT87_REG_TEMP456_ENABLE 0x77
262
263#define NUM_VIN ARRAY_SIZE(IT87_REG_VIN)
264#define NUM_VIN_LIMIT 8
265#define NUM_TEMP 6
266#define NUM_TEMP_OFFSET ARRAY_SIZE(IT87_REG_TEMP_OFFSET)
267#define NUM_TEMP_LIMIT 3
268#define NUM_FAN ARRAY_SIZE(IT87_REG_FAN)
269#define NUM_FAN_DIV 3
270#define NUM_PWM ARRAY_SIZE(IT87_REG_PWM)
271#define NUM_AUTO_PWM ARRAY_SIZE(IT87_REG_PWM)
272
273struct it87_devices {
274 const char *name;
275 const char * const suffix;
276 u32 features;
277 u8 peci_mask;
278 u8 old_peci_mask;
279};
280
281#define FEAT_12MV_ADC BIT(0)
282#define FEAT_NEWER_AUTOPWM BIT(1)
283#define FEAT_OLD_AUTOPWM BIT(2)
284#define FEAT_16BIT_FANS BIT(3)
285#define FEAT_TEMP_OFFSET BIT(4)
286#define FEAT_TEMP_PECI BIT(5)
287#define FEAT_TEMP_OLD_PECI BIT(6)
288#define FEAT_FAN16_CONFIG BIT(7) /* Need to enable 16-bit fans */
289#define FEAT_FIVE_FANS BIT(8) /* Supports five fans */
290#define FEAT_VID BIT(9) /* Set if chip supports VID */
291#define FEAT_IN7_INTERNAL BIT(10) /* Set if in7 is internal */
292#define FEAT_SIX_FANS BIT(11) /* Supports six fans */
293#define FEAT_10_9MV_ADC BIT(12)
294#define FEAT_AVCC3 BIT(13) /* Chip supports in9/AVCC3 */
295#define FEAT_FIVE_PWM BIT(14) /* Chip supports 5 pwm chn */
296#define FEAT_SIX_PWM BIT(15) /* Chip supports 6 pwm chn */
297#define FEAT_PWM_FREQ2 BIT(16) /* Separate pwm freq 2 */
298#define FEAT_SIX_TEMP BIT(17) /* Up to 6 temp sensors */
299#define FEAT_VIN3_5V BIT(18) /* VIN3 connected to +5V */
300
301static const struct it87_devices it87_devices[] = {
302 [it87] = {
303 .name = "it87",
304 .suffix = "F",
305 .features = FEAT_OLD_AUTOPWM, /* may need to overwrite */
306 },
307 [it8712] = {
308 .name = "it8712",
309 .suffix = "F",
310 .features = FEAT_OLD_AUTOPWM | FEAT_VID,
311 /* may need to overwrite */
312 },
313 [it8716] = {
314 .name = "it8716",
315 .suffix = "F",
316 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
317 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2,
318 },
319 [it8718] = {
320 .name = "it8718",
321 .suffix = "F",
322 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
323 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
324 | FEAT_PWM_FREQ2,
325 .old_peci_mask = 0x4,
326 },
327 [it8720] = {
328 .name = "it8720",
329 .suffix = "F",
330 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
331 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
332 | FEAT_PWM_FREQ2,
333 .old_peci_mask = 0x4,
334 },
335 [it8721] = {
336 .name = "it8721",
337 .suffix = "F",
338 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
339 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
340 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
341 | FEAT_PWM_FREQ2,
342 .peci_mask = 0x05,
343 .old_peci_mask = 0x02, /* Actually reports PCH */
344 },
345 [it8728] = {
346 .name = "it8728",
347 .suffix = "F",
348 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
349 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS
350 | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2,
351 .peci_mask = 0x07,
352 },
353 [it8732] = {
354 .name = "it8732",
355 .suffix = "F",
356 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
357 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
358 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL,
359 .peci_mask = 0x07,
360 .old_peci_mask = 0x02, /* Actually reports PCH */
361 },
362 [it8771] = {
363 .name = "it8771",
364 .suffix = "E",
365 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
366 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
367 | FEAT_PWM_FREQ2,
368 /* PECI: guesswork */
369 /* 12mV ADC (OHM) */
370 /* 16 bit fans (OHM) */
371 /* three fans, always 16 bit (guesswork) */
372 .peci_mask = 0x07,
373 },
374 [it8772] = {
375 .name = "it8772",
376 .suffix = "E",
377 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
378 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
379 | FEAT_PWM_FREQ2,
380 /* PECI (coreboot) */
381 /* 12mV ADC (HWSensors4, OHM) */
382 /* 16 bit fans (HWSensors4, OHM) */
383 /* three fans, always 16 bit (datasheet) */
384 .peci_mask = 0x07,
385 },
386 [it8781] = {
387 .name = "it8781",
388 .suffix = "F",
389 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
390 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
391 .old_peci_mask = 0x4,
392 },
393 [it8782] = {
394 .name = "it8782",
395 .suffix = "F",
396 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
397 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
398 .old_peci_mask = 0x4,
399 },
400 [it8783] = {
401 .name = "it8783",
402 .suffix = "E/F",
403 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
404 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
405 .old_peci_mask = 0x4,
406 },
407 [it8786] = {
408 .name = "it8786",
409 .suffix = "E",
410 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
411 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
412 | FEAT_PWM_FREQ2,
413 .peci_mask = 0x07,
414 },
415 [it8790] = {
416 .name = "it8790",
417 .suffix = "E",
418 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
419 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
420 | FEAT_PWM_FREQ2,
421 .peci_mask = 0x07,
422 },
423 [it8792] = {
424 .name = "it8792",
425 .suffix = "E",
426 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
427 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
428 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL,
429 .peci_mask = 0x07,
430 .old_peci_mask = 0x02, /* Actually reports PCH */
431 },
432 [it8603] = {
433 .name = "it8603",
434 .suffix = "E",
435 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
436 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
437 | FEAT_AVCC3 | FEAT_PWM_FREQ2,
438 .peci_mask = 0x07,
439 },
440 [it8620] = {
441 .name = "it8620",
442 .suffix = "E",
443 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
444 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
445 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
446 | FEAT_SIX_TEMP | FEAT_VIN3_5V,
447 .peci_mask = 0x07,
448 },
449 [it8622] = {
450 .name = "it8622",
451 .suffix = "E",
452 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
453 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS
454 | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
455 | FEAT_AVCC3 | FEAT_VIN3_5V,
456 .peci_mask = 0x07,
457 },
458 [it8628] = {
459 .name = "it8628",
460 .suffix = "E",
461 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
462 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
463 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
464 | FEAT_SIX_TEMP | FEAT_VIN3_5V,
465 .peci_mask = 0x07,
466 },
467};
468
469#define has_16bit_fans(data) ((data)->features & FEAT_16BIT_FANS)
470#define has_12mv_adc(data) ((data)->features & FEAT_12MV_ADC)
471#define has_10_9mv_adc(data) ((data)->features & FEAT_10_9MV_ADC)
472#define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
473#define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM)
474#define has_temp_offset(data) ((data)->features & FEAT_TEMP_OFFSET)
475#define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
476 ((data)->peci_mask & BIT(nr)))
477#define has_temp_old_peci(data, nr) \
478 (((data)->features & FEAT_TEMP_OLD_PECI) && \
479 ((data)->old_peci_mask & BIT(nr)))
480#define has_fan16_config(data) ((data)->features & FEAT_FAN16_CONFIG)
481#define has_five_fans(data) ((data)->features & (FEAT_FIVE_FANS | \
482 FEAT_SIX_FANS))
483#define has_vid(data) ((data)->features & FEAT_VID)
484#define has_in7_internal(data) ((data)->features & FEAT_IN7_INTERNAL)
485#define has_six_fans(data) ((data)->features & FEAT_SIX_FANS)
486#define has_avcc3(data) ((data)->features & FEAT_AVCC3)
487#define has_five_pwm(data) ((data)->features & (FEAT_FIVE_PWM \
488 | FEAT_SIX_PWM))
489#define has_six_pwm(data) ((data)->features & FEAT_SIX_PWM)
490#define has_pwm_freq2(data) ((data)->features & FEAT_PWM_FREQ2)
491#define has_six_temp(data) ((data)->features & FEAT_SIX_TEMP)
492#define has_vin3_5v(data) ((data)->features & FEAT_VIN3_5V)
493
494struct it87_sio_data {
495 int sioaddr;
496 enum chips type;
497 /* Values read from Super-I/O config space */
498 u8 revision;
499 u8 vid_value;
500 u8 beep_pin;
501 u8 internal; /* Internal sensors can be labeled */
502 bool need_in7_reroute;
503 /* Features skipped based on config or DMI */
504 u16 skip_in;
505 u8 skip_vid;
506 u8 skip_fan;
507 u8 skip_pwm;
508 u8 skip_temp;
509};
510
511/*
512 * For each registered chip, we need to keep some data in memory.
513 * The structure is dynamically allocated.
514 */
515struct it87_data {
516 const struct attribute_group *groups[7];
517 int sioaddr;
518 enum chips type;
519 u32 features;
520 u8 peci_mask;
521 u8 old_peci_mask;
522
523 unsigned short addr;
524 const char *name;
525 struct mutex update_lock;
526 bool valid; /* true if following fields are valid */
527 unsigned long last_updated; /* In jiffies */
528
529 u16 in_scaled; /* Internal voltage sensors are scaled */
530 u16 in_internal; /* Bitfield, internal sensors (for labels) */
531 u16 has_in; /* Bitfield, voltage sensors enabled */
532 u8 in[NUM_VIN][3]; /* [nr][0]=in, [1]=min, [2]=max */
533 bool need_in7_reroute;
534 u8 has_fan; /* Bitfield, fans enabled */
535 u16 fan[NUM_FAN][2]; /* Register values, [nr][0]=fan, [1]=min */
536 u8 has_temp; /* Bitfield, temp sensors enabled */
537 s8 temp[NUM_TEMP][4]; /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
538 u8 sensor; /* Register value (IT87_REG_TEMP_ENABLE) */
539 u8 extra; /* Register value (IT87_REG_TEMP_EXTRA) */
540 u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
541 bool has_vid; /* True if VID supported */
542 u8 vid; /* Register encoding, combined */
543 u8 vrm;
544 u32 alarms; /* Register encoding, combined */
545 bool has_beep; /* true if beep supported */
546 u8 beeps; /* Register encoding */
547 u8 fan_main_ctrl; /* Register value */
548 u8 fan_ctl; /* Register value */
549
550 /*
551 * The following 3 arrays correspond to the same registers up to
552 * the IT8720F. The meaning of bits 6-0 depends on the value of bit
553 * 7, and we want to preserve settings on mode changes, so we have
554 * to track all values separately.
555 * Starting with the IT8721F, the manual PWM duty cycles are stored
556 * in separate registers (8-bit values), so the separate tracking
557 * is no longer needed, but it is still done to keep the driver
558 * simple.
559 */
560 u8 has_pwm; /* Bitfield, pwm control enabled */
561 u8 pwm_ctrl[NUM_PWM]; /* Register value */
562 u8 pwm_duty[NUM_PWM]; /* Manual PWM value set by user */
563 u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */
564
565 /* Automatic fan speed control registers */
566 u8 auto_pwm[NUM_AUTO_PWM][4]; /* [nr][3] is hard-coded */
567 s8 auto_temp[NUM_AUTO_PWM][5]; /* [nr][0] is point1_temp_hyst */
568};
569
570/* Board specific settings from DMI matching */
571struct it87_dmi_data {
572 u8 skip_pwm; /* pwm channels to skip for this board */
573};
574
575/* Global for results from DMI matching, if needed */
576static struct it87_dmi_data *dmi_data;
577
578static int adc_lsb(const struct it87_data *data, int nr)
579{
580 int lsb;
581
582 if (has_12mv_adc(data))
583 lsb = 120;
584 else if (has_10_9mv_adc(data))
585 lsb = 109;
586 else
587 lsb = 160;
588 if (data->in_scaled & BIT(nr))
589 lsb <<= 1;
590 return lsb;
591}
592
593static u8 in_to_reg(const struct it87_data *data, int nr, long val)
594{
595 val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr));
596 return clamp_val(val, 0, 255);
597}
598
599static int in_from_reg(const struct it87_data *data, int nr, int val)
600{
601 return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10);
602}
603
604static inline u8 FAN_TO_REG(long rpm, int div)
605{
606 if (rpm == 0)
607 return 255;
608 rpm = clamp_val(rpm, 1, 1000000);
609 return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
610}
611
612static inline u16 FAN16_TO_REG(long rpm)
613{
614 if (rpm == 0)
615 return 0xffff;
616 return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
617}
618
619#define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
620 1350000 / ((val) * (div)))
621/* The divider is fixed to 2 in 16-bit mode */
622#define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
623 1350000 / ((val) * 2))
624
625#define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
626 ((val) + 500) / 1000), -128, 127))
627#define TEMP_FROM_REG(val) ((val) * 1000)
628
629static u8 pwm_to_reg(const struct it87_data *data, long val)
630{
631 if (has_newer_autopwm(data))
632 return val;
633 else
634 return val >> 1;
635}
636
637static int pwm_from_reg(const struct it87_data *data, u8 reg)
638{
639 if (has_newer_autopwm(data))
640 return reg;
641 else
642 return (reg & 0x7f) << 1;
643}
644
645static int DIV_TO_REG(int val)
646{
647 int answer = 0;
648
649 while (answer < 7 && (val >>= 1))
650 answer++;
651 return answer;
652}
653
654#define DIV_FROM_REG(val) BIT(val)
655
656/*
657 * PWM base frequencies. The frequency has to be divided by either 128 or 256,
658 * depending on the chip type, to calculate the actual PWM frequency.
659 *
660 * Some of the chip datasheets suggest a base frequency of 51 kHz instead
661 * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
662 * of 200 Hz. Sometimes both PWM frequency select registers are affected,
663 * sometimes just one. It is unknown if this is a datasheet error or real,
664 * so this is ignored for now.
665 */
666static const unsigned int pwm_freq[8] = {
667 48000000,
668 24000000,
669 12000000,
670 8000000,
671 6000000,
672 3000000,
673 1500000,
674 750000,
675};
676
677/*
678 * Must be called with data->update_lock held, except during initialization.
679 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
680 * would slow down the IT87 access and should not be necessary.
681 */
682static int it87_read_value(struct it87_data *data, u8 reg)
683{
684 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
685 return inb_p(data->addr + IT87_DATA_REG_OFFSET);
686}
687
688/*
689 * Must be called with data->update_lock held, except during initialization.
690 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
691 * would slow down the IT87 access and should not be necessary.
692 */
693static void it87_write_value(struct it87_data *data, u8 reg, u8 value)
694{
695 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
696 outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
697}
698
699static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
700{
701 data->pwm_ctrl[nr] = it87_read_value(data, IT87_REG_PWM[nr]);
702 if (has_newer_autopwm(data)) {
703 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
704 data->pwm_duty[nr] = it87_read_value(data,
705 IT87_REG_PWM_DUTY[nr]);
706 } else {
707 if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */
708 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
709 else /* Manual mode */
710 data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f;
711 }
712
713 if (has_old_autopwm(data)) {
714 int i;
715
716 for (i = 0; i < 5 ; i++)
717 data->auto_temp[nr][i] = it87_read_value(data,
718 IT87_REG_AUTO_TEMP(nr, i));
719 for (i = 0; i < 3 ; i++)
720 data->auto_pwm[nr][i] = it87_read_value(data,
721 IT87_REG_AUTO_PWM(nr, i));
722 } else if (has_newer_autopwm(data)) {
723 int i;
724
725 /*
726 * 0: temperature hysteresis (base + 5)
727 * 1: fan off temperature (base + 0)
728 * 2: fan start temperature (base + 1)
729 * 3: fan max temperature (base + 2)
730 */
731 data->auto_temp[nr][0] =
732 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 5));
733
734 for (i = 0; i < 3 ; i++)
735 data->auto_temp[nr][i + 1] =
736 it87_read_value(data,
737 IT87_REG_AUTO_TEMP(nr, i));
738 /*
739 * 0: start pwm value (base + 3)
740 * 1: pwm slope (base + 4, 1/8th pwm)
741 */
742 data->auto_pwm[nr][0] =
743 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 3));
744 data->auto_pwm[nr][1] =
745 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 4));
746 }
747}
748
749static struct it87_data *it87_update_device(struct device *dev)
750{
751 struct it87_data *data = dev_get_drvdata(dev);
752 int i;
753
754 mutex_lock(&data->update_lock);
755
756 if (time_after(jiffies, data->last_updated + HZ + HZ / 2) ||
757 !data->valid) {
758 if (update_vbat) {
759 /*
760 * Cleared after each update, so reenable. Value
761 * returned by this read will be previous value
762 */
763 it87_write_value(data, IT87_REG_CONFIG,
764 it87_read_value(data, IT87_REG_CONFIG) | 0x40);
765 }
766 for (i = 0; i < NUM_VIN; i++) {
767 if (!(data->has_in & BIT(i)))
768 continue;
769
770 data->in[i][0] =
771 it87_read_value(data, IT87_REG_VIN[i]);
772
773 /* VBAT and AVCC don't have limit registers */
774 if (i >= NUM_VIN_LIMIT)
775 continue;
776
777 data->in[i][1] =
778 it87_read_value(data, IT87_REG_VIN_MIN(i));
779 data->in[i][2] =
780 it87_read_value(data, IT87_REG_VIN_MAX(i));
781 }
782
783 for (i = 0; i < NUM_FAN; i++) {
784 /* Skip disabled fans */
785 if (!(data->has_fan & BIT(i)))
786 continue;
787
788 data->fan[i][1] =
789 it87_read_value(data, IT87_REG_FAN_MIN[i]);
790 data->fan[i][0] = it87_read_value(data,
791 IT87_REG_FAN[i]);
792 /* Add high byte if in 16-bit mode */
793 if (has_16bit_fans(data)) {
794 data->fan[i][0] |= it87_read_value(data,
795 IT87_REG_FANX[i]) << 8;
796 data->fan[i][1] |= it87_read_value(data,
797 IT87_REG_FANX_MIN[i]) << 8;
798 }
799 }
800 for (i = 0; i < NUM_TEMP; i++) {
801 if (!(data->has_temp & BIT(i)))
802 continue;
803 data->temp[i][0] =
804 it87_read_value(data, IT87_REG_TEMP(i));
805
806 if (has_temp_offset(data) && i < NUM_TEMP_OFFSET)
807 data->temp[i][3] =
808 it87_read_value(data,
809 IT87_REG_TEMP_OFFSET[i]);
810
811 if (i >= NUM_TEMP_LIMIT)
812 continue;
813
814 data->temp[i][1] =
815 it87_read_value(data, IT87_REG_TEMP_LOW(i));
816 data->temp[i][2] =
817 it87_read_value(data, IT87_REG_TEMP_HIGH(i));
818 }
819
820 /* Newer chips don't have clock dividers */
821 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
822 i = it87_read_value(data, IT87_REG_FAN_DIV);
823 data->fan_div[0] = i & 0x07;
824 data->fan_div[1] = (i >> 3) & 0x07;
825 data->fan_div[2] = (i & 0x40) ? 3 : 1;
826 }
827
828 data->alarms =
829 it87_read_value(data, IT87_REG_ALARM1) |
830 (it87_read_value(data, IT87_REG_ALARM2) << 8) |
831 (it87_read_value(data, IT87_REG_ALARM3) << 16);
832 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
833
834 data->fan_main_ctrl = it87_read_value(data,
835 IT87_REG_FAN_MAIN_CTRL);
836 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL);
837 for (i = 0; i < NUM_PWM; i++) {
838 if (!(data->has_pwm & BIT(i)))
839 continue;
840 it87_update_pwm_ctrl(data, i);
841 }
842
843 data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE);
844 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
845 /*
846 * The IT8705F does not have VID capability.
847 * The IT8718F and later don't use IT87_REG_VID for the
848 * same purpose.
849 */
850 if (data->type == it8712 || data->type == it8716) {
851 data->vid = it87_read_value(data, IT87_REG_VID);
852 /*
853 * The older IT8712F revisions had only 5 VID pins,
854 * but we assume it is always safe to read 6 bits.
855 */
856 data->vid &= 0x3f;
857 }
858 data->last_updated = jiffies;
859 data->valid = true;
860 }
861
862 mutex_unlock(&data->update_lock);
863
864 return data;
865}
866
867static ssize_t show_in(struct device *dev, struct device_attribute *attr,
868 char *buf)
869{
870 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
871 struct it87_data *data = it87_update_device(dev);
872 int index = sattr->index;
873 int nr = sattr->nr;
874
875 return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
876}
877
878static ssize_t set_in(struct device *dev, struct device_attribute *attr,
879 const char *buf, size_t count)
880{
881 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
882 struct it87_data *data = dev_get_drvdata(dev);
883 int index = sattr->index;
884 int nr = sattr->nr;
885 unsigned long val;
886
887 if (kstrtoul(buf, 10, &val) < 0)
888 return -EINVAL;
889
890 mutex_lock(&data->update_lock);
891 data->in[nr][index] = in_to_reg(data, nr, val);
892 it87_write_value(data,
893 index == 1 ? IT87_REG_VIN_MIN(nr)
894 : IT87_REG_VIN_MAX(nr),
895 data->in[nr][index]);
896 mutex_unlock(&data->update_lock);
897 return count;
898}
899
900static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0);
901static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
902 0, 1);
903static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
904 0, 2);
905
906static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0);
907static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
908 1, 1);
909static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
910 1, 2);
911
912static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0);
913static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
914 2, 1);
915static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
916 2, 2);
917
918static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0);
919static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
920 3, 1);
921static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
922 3, 2);
923
924static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0);
925static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
926 4, 1);
927static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
928 4, 2);
929
930static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0);
931static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
932 5, 1);
933static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
934 5, 2);
935
936static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0);
937static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in,
938 6, 1);
939static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in,
940 6, 2);
941
942static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0);
943static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in,
944 7, 1);
945static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in,
946 7, 2);
947
948static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0);
949static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0);
950static SENSOR_DEVICE_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 10, 0);
951static SENSOR_DEVICE_ATTR_2(in11_input, S_IRUGO, show_in, NULL, 11, 0);
952static SENSOR_DEVICE_ATTR_2(in12_input, S_IRUGO, show_in, NULL, 12, 0);
953
954/* Up to 6 temperatures */
955static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
956 char *buf)
957{
958 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
959 int nr = sattr->nr;
960 int index = sattr->index;
961 struct it87_data *data = it87_update_device(dev);
962
963 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
964}
965
966static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
967 const char *buf, size_t count)
968{
969 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
970 int nr = sattr->nr;
971 int index = sattr->index;
972 struct it87_data *data = dev_get_drvdata(dev);
973 long val;
974 u8 reg, regval;
975
976 if (kstrtol(buf, 10, &val) < 0)
977 return -EINVAL;
978
979 mutex_lock(&data->update_lock);
980
981 switch (index) {
982 default:
983 case 1:
984 reg = IT87_REG_TEMP_LOW(nr);
985 break;
986 case 2:
987 reg = IT87_REG_TEMP_HIGH(nr);
988 break;
989 case 3:
990 regval = it87_read_value(data, IT87_REG_BEEP_ENABLE);
991 if (!(regval & 0x80)) {
992 regval |= 0x80;
993 it87_write_value(data, IT87_REG_BEEP_ENABLE, regval);
994 }
995 data->valid = false;
996 reg = IT87_REG_TEMP_OFFSET[nr];
997 break;
998 }
999
1000 data->temp[nr][index] = TEMP_TO_REG(val);
1001 it87_write_value(data, reg, data->temp[nr][index]);
1002 mutex_unlock(&data->update_lock);
1003 return count;
1004}
1005
1006static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0);
1007static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1008 0, 1);
1009static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1010 0, 2);
1011static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp,
1012 set_temp, 0, 3);
1013static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0);
1014static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1015 1, 1);
1016static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1017 1, 2);
1018static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp,
1019 set_temp, 1, 3);
1020static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0);
1021static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1022 2, 1);
1023static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1024 2, 2);
1025static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
1026 set_temp, 2, 3);
1027static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0);
1028static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0);
1029static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0);
1030
1031static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
1032 char *buf)
1033{
1034 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1035 int nr = sensor_attr->index;
1036 struct it87_data *data = it87_update_device(dev);
1037 u8 reg = data->sensor; /* In case value is updated while used */
1038 u8 extra = data->extra;
1039
1040 if ((has_temp_peci(data, nr) && (reg >> 6 == nr + 1)) ||
1041 (has_temp_old_peci(data, nr) && (extra & 0x80)))
1042 return sprintf(buf, "6\n"); /* Intel PECI */
1043 if (reg & (1 << nr))
1044 return sprintf(buf, "3\n"); /* thermal diode */
1045 if (reg & (8 << nr))
1046 return sprintf(buf, "4\n"); /* thermistor */
1047 return sprintf(buf, "0\n"); /* disabled */
1048}
1049
1050static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
1051 const char *buf, size_t count)
1052{
1053 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1054 int nr = sensor_attr->index;
1055
1056 struct it87_data *data = dev_get_drvdata(dev);
1057 long val;
1058 u8 reg, extra;
1059
1060 if (kstrtol(buf, 10, &val) < 0)
1061 return -EINVAL;
1062
1063 reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1064 reg &= ~(1 << nr);
1065 reg &= ~(8 << nr);
1066 if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
1067 reg &= 0x3f;
1068 extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1069 if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
1070 extra &= 0x7f;
1071 if (val == 2) { /* backwards compatibility */
1072 dev_warn(dev,
1073 "Sensor type 2 is deprecated, please use 4 instead\n");
1074 val = 4;
1075 }
1076 /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1077 if (val == 3)
1078 reg |= 1 << nr;
1079 else if (val == 4)
1080 reg |= 8 << nr;
1081 else if (has_temp_peci(data, nr) && val == 6)
1082 reg |= (nr + 1) << 6;
1083 else if (has_temp_old_peci(data, nr) && val == 6)
1084 extra |= 0x80;
1085 else if (val != 0)
1086 return -EINVAL;
1087
1088 mutex_lock(&data->update_lock);
1089 data->sensor = reg;
1090 data->extra = extra;
1091 it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor);
1092 if (has_temp_old_peci(data, nr))
1093 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1094 data->valid = false; /* Force cache refresh */
1095 mutex_unlock(&data->update_lock);
1096 return count;
1097}
1098
1099static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type,
1100 set_temp_type, 0);
1101static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type,
1102 set_temp_type, 1);
1103static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
1104 set_temp_type, 2);
1105
1106/* 6 Fans */
1107
1108static int pwm_mode(const struct it87_data *data, int nr)
1109{
1110 if (data->type != it8603 && nr < 3 && !(data->fan_main_ctrl & BIT(nr)))
1111 return 0; /* Full speed */
1112 if (data->pwm_ctrl[nr] & 0x80)
1113 return 2; /* Automatic mode */
1114 if ((data->type == it8603 || nr >= 3) &&
1115 data->pwm_duty[nr] == pwm_to_reg(data, 0xff))
1116 return 0; /* Full speed */
1117
1118 return 1; /* Manual mode */
1119}
1120
1121static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
1122 char *buf)
1123{
1124 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1125 int nr = sattr->nr;
1126 int index = sattr->index;
1127 int speed;
1128 struct it87_data *data = it87_update_device(dev);
1129
1130 speed = has_16bit_fans(data) ?
1131 FAN16_FROM_REG(data->fan[nr][index]) :
1132 FAN_FROM_REG(data->fan[nr][index],
1133 DIV_FROM_REG(data->fan_div[nr]));
1134 return sprintf(buf, "%d\n", speed);
1135}
1136
1137static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
1138 char *buf)
1139{
1140 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1141 struct it87_data *data = it87_update_device(dev);
1142 int nr = sensor_attr->index;
1143
1144 return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr]));
1145}
1146
1147static ssize_t show_pwm_enable(struct device *dev,
1148 struct device_attribute *attr, char *buf)
1149{
1150 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1151 struct it87_data *data = it87_update_device(dev);
1152 int nr = sensor_attr->index;
1153
1154 return sprintf(buf, "%d\n", pwm_mode(data, nr));
1155}
1156
1157static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1158 char *buf)
1159{
1160 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1161 struct it87_data *data = it87_update_device(dev);
1162 int nr = sensor_attr->index;
1163
1164 return sprintf(buf, "%d\n",
1165 pwm_from_reg(data, data->pwm_duty[nr]));
1166}
1167
1168static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
1169 char *buf)
1170{
1171 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1172 struct it87_data *data = it87_update_device(dev);
1173 int nr = sensor_attr->index;
1174 unsigned int freq;
1175 int index;
1176
1177 if (has_pwm_freq2(data) && nr == 1)
1178 index = (data->extra >> 4) & 0x07;
1179 else
1180 index = (data->fan_ctl >> 4) & 0x07;
1181
1182 freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128);
1183
1184 return sprintf(buf, "%u\n", freq);
1185}
1186
1187static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1188 const char *buf, size_t count)
1189{
1190 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1191 int nr = sattr->nr;
1192 int index = sattr->index;
1193
1194 struct it87_data *data = dev_get_drvdata(dev);
1195 long val;
1196 u8 reg;
1197
1198 if (kstrtol(buf, 10, &val) < 0)
1199 return -EINVAL;
1200
1201 mutex_lock(&data->update_lock);
1202
1203 if (has_16bit_fans(data)) {
1204 data->fan[nr][index] = FAN16_TO_REG(val);
1205 it87_write_value(data, IT87_REG_FAN_MIN[nr],
1206 data->fan[nr][index] & 0xff);
1207 it87_write_value(data, IT87_REG_FANX_MIN[nr],
1208 data->fan[nr][index] >> 8);
1209 } else {
1210 reg = it87_read_value(data, IT87_REG_FAN_DIV);
1211 switch (nr) {
1212 case 0:
1213 data->fan_div[nr] = reg & 0x07;
1214 break;
1215 case 1:
1216 data->fan_div[nr] = (reg >> 3) & 0x07;
1217 break;
1218 case 2:
1219 data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
1220 break;
1221 }
1222 data->fan[nr][index] =
1223 FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
1224 it87_write_value(data, IT87_REG_FAN_MIN[nr],
1225 data->fan[nr][index]);
1226 }
1227
1228 mutex_unlock(&data->update_lock);
1229 return count;
1230}
1231
1232static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
1233 const char *buf, size_t count)
1234{
1235 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1236 struct it87_data *data = dev_get_drvdata(dev);
1237 int nr = sensor_attr->index;
1238 unsigned long val;
1239 int min;
1240 u8 old;
1241
1242 if (kstrtoul(buf, 10, &val) < 0)
1243 return -EINVAL;
1244
1245 mutex_lock(&data->update_lock);
1246 old = it87_read_value(data, IT87_REG_FAN_DIV);
1247
1248 /* Save fan min limit */
1249 min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1250
1251 switch (nr) {
1252 case 0:
1253 case 1:
1254 data->fan_div[nr] = DIV_TO_REG(val);
1255 break;
1256 case 2:
1257 if (val < 8)
1258 data->fan_div[nr] = 1;
1259 else
1260 data->fan_div[nr] = 3;
1261 }
1262 val = old & 0x80;
1263 val |= (data->fan_div[0] & 0x07);
1264 val |= (data->fan_div[1] & 0x07) << 3;
1265 if (data->fan_div[2] == 3)
1266 val |= 0x1 << 6;
1267 it87_write_value(data, IT87_REG_FAN_DIV, val);
1268
1269 /* Restore fan min limit */
1270 data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
1271 it87_write_value(data, IT87_REG_FAN_MIN[nr], data->fan[nr][1]);
1272
1273 mutex_unlock(&data->update_lock);
1274 return count;
1275}
1276
1277/* Returns 0 if OK, -EINVAL otherwise */
1278static int check_trip_points(struct device *dev, int nr)
1279{
1280 const struct it87_data *data = dev_get_drvdata(dev);
1281 int i, err = 0;
1282
1283 if (has_old_autopwm(data)) {
1284 for (i = 0; i < 3; i++) {
1285 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1286 err = -EINVAL;
1287 }
1288 for (i = 0; i < 2; i++) {
1289 if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
1290 err = -EINVAL;
1291 }
1292 } else if (has_newer_autopwm(data)) {
1293 for (i = 1; i < 3; i++) {
1294 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1295 err = -EINVAL;
1296 }
1297 }
1298
1299 if (err) {
1300 dev_err(dev,
1301 "Inconsistent trip points, not switching to automatic mode\n");
1302 dev_err(dev, "Adjust the trip points and try again\n");
1303 }
1304 return err;
1305}
1306
1307static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr,
1308 const char *buf, size_t count)
1309{
1310 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1311 struct it87_data *data = dev_get_drvdata(dev);
1312 int nr = sensor_attr->index;
1313 long val;
1314
1315 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
1316 return -EINVAL;
1317
1318 /* Check trip points before switching to automatic mode */
1319 if (val == 2) {
1320 if (check_trip_points(dev, nr) < 0)
1321 return -EINVAL;
1322 }
1323
1324 mutex_lock(&data->update_lock);
1325
1326 if (val == 0) {
1327 if (nr < 3 && data->type != it8603) {
1328 int tmp;
1329 /* make sure the fan is on when in on/off mode */
1330 tmp = it87_read_value(data, IT87_REG_FAN_CTL);
1331 it87_write_value(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
1332 /* set on/off mode */
1333 data->fan_main_ctrl &= ~BIT(nr);
1334 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1335 data->fan_main_ctrl);
1336 } else {
1337 u8 ctrl;
1338
1339 /* No on/off mode, set maximum pwm value */
1340 data->pwm_duty[nr] = pwm_to_reg(data, 0xff);
1341 it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1342 data->pwm_duty[nr]);
1343 /* and set manual mode */
1344 if (has_newer_autopwm(data)) {
1345 ctrl = (data->pwm_ctrl[nr] & 0x7c) |
1346 data->pwm_temp_map[nr];
1347 } else {
1348 ctrl = data->pwm_duty[nr];
1349 }
1350 data->pwm_ctrl[nr] = ctrl;
1351 it87_write_value(data, IT87_REG_PWM[nr], ctrl);
1352 }
1353 } else {
1354 u8 ctrl;
1355
1356 if (has_newer_autopwm(data)) {
1357 ctrl = (data->pwm_ctrl[nr] & 0x7c) |
1358 data->pwm_temp_map[nr];
1359 if (val != 1)
1360 ctrl |= 0x80;
1361 } else {
1362 ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80);
1363 }
1364 data->pwm_ctrl[nr] = ctrl;
1365 it87_write_value(data, IT87_REG_PWM[nr], ctrl);
1366
1367 if (data->type != it8603 && nr < 3) {
1368 /* set SmartGuardian mode */
1369 data->fan_main_ctrl |= BIT(nr);
1370 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1371 data->fan_main_ctrl);
1372 }
1373 }
1374
1375 mutex_unlock(&data->update_lock);
1376 return count;
1377}
1378
1379static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1380 const char *buf, size_t count)
1381{
1382 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1383 struct it87_data *data = dev_get_drvdata(dev);
1384 int nr = sensor_attr->index;
1385 long val;
1386
1387 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1388 return -EINVAL;
1389
1390 mutex_lock(&data->update_lock);
1391 it87_update_pwm_ctrl(data, nr);
1392 if (has_newer_autopwm(data)) {
1393 /*
1394 * If we are in automatic mode, the PWM duty cycle register
1395 * is read-only so we can't write the value.
1396 */
1397 if (data->pwm_ctrl[nr] & 0x80) {
1398 mutex_unlock(&data->update_lock);
1399 return -EBUSY;
1400 }
1401 data->pwm_duty[nr] = pwm_to_reg(data, val);
1402 it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1403 data->pwm_duty[nr]);
1404 } else {
1405 data->pwm_duty[nr] = pwm_to_reg(data, val);
1406 /*
1407 * If we are in manual mode, write the duty cycle immediately;
1408 * otherwise, just store it for later use.
1409 */
1410 if (!(data->pwm_ctrl[nr] & 0x80)) {
1411 data->pwm_ctrl[nr] = data->pwm_duty[nr];
1412 it87_write_value(data, IT87_REG_PWM[nr],
1413 data->pwm_ctrl[nr]);
1414 }
1415 }
1416 mutex_unlock(&data->update_lock);
1417 return count;
1418}
1419
1420static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr,
1421 const char *buf, size_t count)
1422{
1423 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1424 struct it87_data *data = dev_get_drvdata(dev);
1425 int nr = sensor_attr->index;
1426 unsigned long val;
1427 int i;
1428
1429 if (kstrtoul(buf, 10, &val) < 0)
1430 return -EINVAL;
1431
1432 val = clamp_val(val, 0, 1000000);
1433 val *= has_newer_autopwm(data) ? 256 : 128;
1434
1435 /* Search for the nearest available frequency */
1436 for (i = 0; i < 7; i++) {
1437 if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2)
1438 break;
1439 }
1440
1441 mutex_lock(&data->update_lock);
1442 if (nr == 0) {
1443 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f;
1444 data->fan_ctl |= i << 4;
1445 it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl);
1446 } else {
1447 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x8f;
1448 data->extra |= i << 4;
1449 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1450 }
1451 mutex_unlock(&data->update_lock);
1452
1453 return count;
1454}
1455
1456static ssize_t show_pwm_temp_map(struct device *dev,
1457 struct device_attribute *attr, char *buf)
1458{
1459 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1460 struct it87_data *data = it87_update_device(dev);
1461 int nr = sensor_attr->index;
1462 int map;
1463
1464 map = data->pwm_temp_map[nr];
1465 if (map >= 3)
1466 map = 0; /* Should never happen */
1467 if (nr >= 3) /* pwm channels 3..6 map to temp4..6 */
1468 map += 3;
1469
1470 return sprintf(buf, "%d\n", (int)BIT(map));
1471}
1472
1473static ssize_t set_pwm_temp_map(struct device *dev,
1474 struct device_attribute *attr, const char *buf,
1475 size_t count)
1476{
1477 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1478 struct it87_data *data = dev_get_drvdata(dev);
1479 int nr = sensor_attr->index;
1480 long val;
1481 u8 reg;
1482
1483 if (kstrtol(buf, 10, &val) < 0)
1484 return -EINVAL;
1485
1486 if (nr >= 3)
1487 val -= 3;
1488
1489 switch (val) {
1490 case BIT(0):
1491 reg = 0x00;
1492 break;
1493 case BIT(1):
1494 reg = 0x01;
1495 break;
1496 case BIT(2):
1497 reg = 0x02;
1498 break;
1499 default:
1500 return -EINVAL;
1501 }
1502
1503 mutex_lock(&data->update_lock);
1504 it87_update_pwm_ctrl(data, nr);
1505 data->pwm_temp_map[nr] = reg;
1506 /*
1507 * If we are in automatic mode, write the temp mapping immediately;
1508 * otherwise, just store it for later use.
1509 */
1510 if (data->pwm_ctrl[nr] & 0x80) {
1511 data->pwm_ctrl[nr] = (data->pwm_ctrl[nr] & 0xfc) |
1512 data->pwm_temp_map[nr];
1513 it87_write_value(data, IT87_REG_PWM[nr], data->pwm_ctrl[nr]);
1514 }
1515 mutex_unlock(&data->update_lock);
1516 return count;
1517}
1518
1519static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr,
1520 char *buf)
1521{
1522 struct it87_data *data = it87_update_device(dev);
1523 struct sensor_device_attribute_2 *sensor_attr =
1524 to_sensor_dev_attr_2(attr);
1525 int nr = sensor_attr->nr;
1526 int point = sensor_attr->index;
1527
1528 return sprintf(buf, "%d\n",
1529 pwm_from_reg(data, data->auto_pwm[nr][point]));
1530}
1531
1532static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr,
1533 const char *buf, size_t count)
1534{
1535 struct it87_data *data = dev_get_drvdata(dev);
1536 struct sensor_device_attribute_2 *sensor_attr =
1537 to_sensor_dev_attr_2(attr);
1538 int nr = sensor_attr->nr;
1539 int point = sensor_attr->index;
1540 int regaddr;
1541 long val;
1542
1543 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1544 return -EINVAL;
1545
1546 mutex_lock(&data->update_lock);
1547 data->auto_pwm[nr][point] = pwm_to_reg(data, val);
1548 if (has_newer_autopwm(data))
1549 regaddr = IT87_REG_AUTO_TEMP(nr, 3);
1550 else
1551 regaddr = IT87_REG_AUTO_PWM(nr, point);
1552 it87_write_value(data, regaddr, data->auto_pwm[nr][point]);
1553 mutex_unlock(&data->update_lock);
1554 return count;
1555}
1556
1557static ssize_t show_auto_pwm_slope(struct device *dev,
1558 struct device_attribute *attr, char *buf)
1559{
1560 struct it87_data *data = it87_update_device(dev);
1561 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1562 int nr = sensor_attr->index;
1563
1564 return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f);
1565}
1566
1567static ssize_t set_auto_pwm_slope(struct device *dev,
1568 struct device_attribute *attr,
1569 const char *buf, size_t count)
1570{
1571 struct it87_data *data = dev_get_drvdata(dev);
1572 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1573 int nr = sensor_attr->index;
1574 unsigned long val;
1575
1576 if (kstrtoul(buf, 10, &val) < 0 || val > 127)
1577 return -EINVAL;
1578
1579 mutex_lock(&data->update_lock);
1580 data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val;
1581 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 4),
1582 data->auto_pwm[nr][1]);
1583 mutex_unlock(&data->update_lock);
1584 return count;
1585}
1586
1587static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr,
1588 char *buf)
1589{
1590 struct it87_data *data = it87_update_device(dev);
1591 struct sensor_device_attribute_2 *sensor_attr =
1592 to_sensor_dev_attr_2(attr);
1593 int nr = sensor_attr->nr;
1594 int point = sensor_attr->index;
1595 int reg;
1596
1597 if (has_old_autopwm(data) || point)
1598 reg = data->auto_temp[nr][point];
1599 else
1600 reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f);
1601
1602 return sprintf(buf, "%d\n", TEMP_FROM_REG(reg));
1603}
1604
1605static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr,
1606 const char *buf, size_t count)
1607{
1608 struct it87_data *data = dev_get_drvdata(dev);
1609 struct sensor_device_attribute_2 *sensor_attr =
1610 to_sensor_dev_attr_2(attr);
1611 int nr = sensor_attr->nr;
1612 int point = sensor_attr->index;
1613 long val;
1614 int reg;
1615
1616 if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
1617 return -EINVAL;
1618
1619 mutex_lock(&data->update_lock);
1620 if (has_newer_autopwm(data) && !point) {
1621 reg = data->auto_temp[nr][1] - TEMP_TO_REG(val);
1622 reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0);
1623 data->auto_temp[nr][0] = reg;
1624 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 5), reg);
1625 } else {
1626 reg = TEMP_TO_REG(val);
1627 data->auto_temp[nr][point] = reg;
1628 if (has_newer_autopwm(data))
1629 point--;
1630 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point), reg);
1631 }
1632 mutex_unlock(&data->update_lock);
1633 return count;
1634}
1635
1636static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0);
1637static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1638 0, 1);
1639static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div,
1640 set_fan_div, 0);
1641
1642static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0);
1643static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1644 1, 1);
1645static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div,
1646 set_fan_div, 1);
1647
1648static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0);
1649static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1650 2, 1);
1651static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div,
1652 set_fan_div, 2);
1653
1654static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0);
1655static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1656 3, 1);
1657
1658static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0);
1659static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1660 4, 1);
1661
1662static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0);
1663static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1664 5, 1);
1665
1666static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
1667 show_pwm_enable, set_pwm_enable, 0);
1668static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0);
1669static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq,
1670 set_pwm_freq, 0);
1671static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO,
1672 show_pwm_temp_map, set_pwm_temp_map, 0);
1673static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR,
1674 show_auto_pwm, set_auto_pwm, 0, 0);
1675static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR,
1676 show_auto_pwm, set_auto_pwm, 0, 1);
1677static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR,
1678 show_auto_pwm, set_auto_pwm, 0, 2);
1679static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO,
1680 show_auto_pwm, NULL, 0, 3);
1681static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR,
1682 show_auto_temp, set_auto_temp, 0, 1);
1683static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1684 show_auto_temp, set_auto_temp, 0, 0);
1685static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR,
1686 show_auto_temp, set_auto_temp, 0, 2);
1687static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR,
1688 show_auto_temp, set_auto_temp, 0, 3);
1689static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR,
1690 show_auto_temp, set_auto_temp, 0, 4);
1691static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, S_IRUGO | S_IWUSR,
1692 show_auto_pwm, set_auto_pwm, 0, 0);
1693static SENSOR_DEVICE_ATTR(pwm1_auto_slope, S_IRUGO | S_IWUSR,
1694 show_auto_pwm_slope, set_auto_pwm_slope, 0);
1695
1696static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
1697 show_pwm_enable, set_pwm_enable, 1);
1698static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1);
1699static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1);
1700static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO,
1701 show_pwm_temp_map, set_pwm_temp_map, 1);
1702static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR,
1703 show_auto_pwm, set_auto_pwm, 1, 0);
1704static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR,
1705 show_auto_pwm, set_auto_pwm, 1, 1);
1706static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR,
1707 show_auto_pwm, set_auto_pwm, 1, 2);
1708static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO,
1709 show_auto_pwm, NULL, 1, 3);
1710static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR,
1711 show_auto_temp, set_auto_temp, 1, 1);
1712static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1713 show_auto_temp, set_auto_temp, 1, 0);
1714static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR,
1715 show_auto_temp, set_auto_temp, 1, 2);
1716static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR,
1717 show_auto_temp, set_auto_temp, 1, 3);
1718static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR,
1719 show_auto_temp, set_auto_temp, 1, 4);
1720static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, S_IRUGO | S_IWUSR,
1721 show_auto_pwm, set_auto_pwm, 1, 0);
1722static SENSOR_DEVICE_ATTR(pwm2_auto_slope, S_IRUGO | S_IWUSR,
1723 show_auto_pwm_slope, set_auto_pwm_slope, 1);
1724
1725static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR,
1726 show_pwm_enable, set_pwm_enable, 2);
1727static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2);
1728static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2);
1729static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO,
1730 show_pwm_temp_map, set_pwm_temp_map, 2);
1731static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR,
1732 show_auto_pwm, set_auto_pwm, 2, 0);
1733static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR,
1734 show_auto_pwm, set_auto_pwm, 2, 1);
1735static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR,
1736 show_auto_pwm, set_auto_pwm, 2, 2);
1737static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO,
1738 show_auto_pwm, NULL, 2, 3);
1739static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR,
1740 show_auto_temp, set_auto_temp, 2, 1);
1741static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1742 show_auto_temp, set_auto_temp, 2, 0);
1743static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR,
1744 show_auto_temp, set_auto_temp, 2, 2);
1745static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR,
1746 show_auto_temp, set_auto_temp, 2, 3);
1747static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR,
1748 show_auto_temp, set_auto_temp, 2, 4);
1749static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, S_IRUGO | S_IWUSR,
1750 show_auto_pwm, set_auto_pwm, 2, 0);
1751static SENSOR_DEVICE_ATTR(pwm3_auto_slope, S_IRUGO | S_IWUSR,
1752 show_auto_pwm_slope, set_auto_pwm_slope, 2);
1753
1754static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR,
1755 show_pwm_enable, set_pwm_enable, 3);
1756static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3);
1757static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3);
1758static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO,
1759 show_pwm_temp_map, set_pwm_temp_map, 3);
1760static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, S_IRUGO | S_IWUSR,
1761 show_auto_temp, set_auto_temp, 2, 1);
1762static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1763 show_auto_temp, set_auto_temp, 2, 0);
1764static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, S_IRUGO | S_IWUSR,
1765 show_auto_temp, set_auto_temp, 2, 2);
1766static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, S_IRUGO | S_IWUSR,
1767 show_auto_temp, set_auto_temp, 2, 3);
1768static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, S_IRUGO | S_IWUSR,
1769 show_auto_pwm, set_auto_pwm, 3, 0);
1770static SENSOR_DEVICE_ATTR(pwm4_auto_slope, S_IRUGO | S_IWUSR,
1771 show_auto_pwm_slope, set_auto_pwm_slope, 3);
1772
1773static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR,
1774 show_pwm_enable, set_pwm_enable, 4);
1775static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4);
1776static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4);
1777static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO,
1778 show_pwm_temp_map, set_pwm_temp_map, 4);
1779static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, S_IRUGO | S_IWUSR,
1780 show_auto_temp, set_auto_temp, 2, 1);
1781static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1782 show_auto_temp, set_auto_temp, 2, 0);
1783static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, S_IRUGO | S_IWUSR,
1784 show_auto_temp, set_auto_temp, 2, 2);
1785static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, S_IRUGO | S_IWUSR,
1786 show_auto_temp, set_auto_temp, 2, 3);
1787static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, S_IRUGO | S_IWUSR,
1788 show_auto_pwm, set_auto_pwm, 4, 0);
1789static SENSOR_DEVICE_ATTR(pwm5_auto_slope, S_IRUGO | S_IWUSR,
1790 show_auto_pwm_slope, set_auto_pwm_slope, 4);
1791
1792static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR,
1793 show_pwm_enable, set_pwm_enable, 5);
1794static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5);
1795static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5);
1796static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO,
1797 show_pwm_temp_map, set_pwm_temp_map, 5);
1798static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, S_IRUGO | S_IWUSR,
1799 show_auto_temp, set_auto_temp, 2, 1);
1800static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1801 show_auto_temp, set_auto_temp, 2, 0);
1802static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, S_IRUGO | S_IWUSR,
1803 show_auto_temp, set_auto_temp, 2, 2);
1804static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, S_IRUGO | S_IWUSR,
1805 show_auto_temp, set_auto_temp, 2, 3);
1806static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, S_IRUGO | S_IWUSR,
1807 show_auto_pwm, set_auto_pwm, 5, 0);
1808static SENSOR_DEVICE_ATTR(pwm6_auto_slope, S_IRUGO | S_IWUSR,
1809 show_auto_pwm_slope, set_auto_pwm_slope, 5);
1810
1811/* Alarms */
1812static ssize_t alarms_show(struct device *dev, struct device_attribute *attr,
1813 char *buf)
1814{
1815 struct it87_data *data = it87_update_device(dev);
1816
1817 return sprintf(buf, "%u\n", data->alarms);
1818}
1819static DEVICE_ATTR_RO(alarms);
1820
1821static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
1822 char *buf)
1823{
1824 struct it87_data *data = it87_update_device(dev);
1825 int bitnr = to_sensor_dev_attr(attr)->index;
1826
1827 return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
1828}
1829
1830static ssize_t clear_intrusion(struct device *dev,
1831 struct device_attribute *attr, const char *buf,
1832 size_t count)
1833{
1834 struct it87_data *data = dev_get_drvdata(dev);
1835 int config;
1836 long val;
1837
1838 if (kstrtol(buf, 10, &val) < 0 || val != 0)
1839 return -EINVAL;
1840
1841 mutex_lock(&data->update_lock);
1842 config = it87_read_value(data, IT87_REG_CONFIG);
1843 if (config < 0) {
1844 count = config;
1845 } else {
1846 config |= BIT(5);
1847 it87_write_value(data, IT87_REG_CONFIG, config);
1848 /* Invalidate cache to force re-read */
1849 data->valid = false;
1850 }
1851 mutex_unlock(&data->update_lock);
1852
1853 return count;
1854}
1855
1856static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8);
1857static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9);
1858static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10);
1859static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11);
1860static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12);
1861static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13);
1862static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14);
1863static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15);
1864static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0);
1865static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1);
1866static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2);
1867static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3);
1868static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6);
1869static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7);
1870static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16);
1871static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17);
1872static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18);
1873static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR,
1874 show_alarm, clear_intrusion, 4);
1875
1876static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
1877 char *buf)
1878{
1879 struct it87_data *data = it87_update_device(dev);
1880 int bitnr = to_sensor_dev_attr(attr)->index;
1881
1882 return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
1883}
1884
1885static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
1886 const char *buf, size_t count)
1887{
1888 int bitnr = to_sensor_dev_attr(attr)->index;
1889 struct it87_data *data = dev_get_drvdata(dev);
1890 long val;
1891
1892 if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1))
1893 return -EINVAL;
1894
1895 mutex_lock(&data->update_lock);
1896 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1897 if (val)
1898 data->beeps |= BIT(bitnr);
1899 else
1900 data->beeps &= ~BIT(bitnr);
1901 it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps);
1902 mutex_unlock(&data->update_lock);
1903 return count;
1904}
1905
1906static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
1907 show_beep, set_beep, 1);
1908static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1);
1909static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1);
1910static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1);
1911static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1);
1912static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1);
1913static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1);
1914static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1);
1915/* fanX_beep writability is set later */
1916static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0);
1917static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0);
1918static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0);
1919static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0);
1920static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0);
1921static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0);
1922static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
1923 show_beep, set_beep, 2);
1924static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2);
1925static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2);
1926
1927static ssize_t vrm_show(struct device *dev, struct device_attribute *attr,
1928 char *buf)
1929{
1930 struct it87_data *data = dev_get_drvdata(dev);
1931
1932 return sprintf(buf, "%u\n", data->vrm);
1933}
1934
1935static ssize_t vrm_store(struct device *dev, struct device_attribute *attr,
1936 const char *buf, size_t count)
1937{
1938 struct it87_data *data = dev_get_drvdata(dev);
1939 unsigned long val;
1940
1941 if (kstrtoul(buf, 10, &val) < 0)
1942 return -EINVAL;
1943
1944 data->vrm = val;
1945
1946 return count;
1947}
1948static DEVICE_ATTR_RW(vrm);
1949
1950static ssize_t cpu0_vid_show(struct device *dev,
1951 struct device_attribute *attr, char *buf)
1952{
1953 struct it87_data *data = it87_update_device(dev);
1954
1955 return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm));
1956}
1957static DEVICE_ATTR_RO(cpu0_vid);
1958
1959static ssize_t show_label(struct device *dev, struct device_attribute *attr,
1960 char *buf)
1961{
1962 static const char * const labels[] = {
1963 "+5V",
1964 "5VSB",
1965 "Vbat",
1966 "AVCC",
1967 };
1968 static const char * const labels_it8721[] = {
1969 "+3.3V",
1970 "3VSB",
1971 "Vbat",
1972 "+3.3V",
1973 };
1974 struct it87_data *data = dev_get_drvdata(dev);
1975 int nr = to_sensor_dev_attr(attr)->index;
1976 const char *label;
1977
1978 if (has_vin3_5v(data) && nr == 0)
1979 label = labels[0];
1980 else if (has_12mv_adc(data) || has_10_9mv_adc(data))
1981 label = labels_it8721[nr];
1982 else
1983 label = labels[nr];
1984
1985 return sprintf(buf, "%s\n", label);
1986}
1987static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0);
1988static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1);
1989static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2);
1990/* AVCC3 */
1991static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 3);
1992
1993static umode_t it87_in_is_visible(struct kobject *kobj,
1994 struct attribute *attr, int index)
1995{
1996 struct device *dev = kobj_to_dev(kobj);
1997 struct it87_data *data = dev_get_drvdata(dev);
1998 int i = index / 5; /* voltage index */
1999 int a = index % 5; /* attribute index */
2000
2001 if (index >= 40) { /* in8 and higher only have input attributes */
2002 i = index - 40 + 8;
2003 a = 0;
2004 }
2005
2006 if (!(data->has_in & BIT(i)))
2007 return 0;
2008
2009 if (a == 4 && !data->has_beep)
2010 return 0;
2011
2012 return attr->mode;
2013}
2014
2015static struct attribute *it87_attributes_in[] = {
2016 &sensor_dev_attr_in0_input.dev_attr.attr,
2017 &sensor_dev_attr_in0_min.dev_attr.attr,
2018 &sensor_dev_attr_in0_max.dev_attr.attr,
2019 &sensor_dev_attr_in0_alarm.dev_attr.attr,
2020 &sensor_dev_attr_in0_beep.dev_attr.attr, /* 4 */
2021
2022 &sensor_dev_attr_in1_input.dev_attr.attr,
2023 &sensor_dev_attr_in1_min.dev_attr.attr,
2024 &sensor_dev_attr_in1_max.dev_attr.attr,
2025 &sensor_dev_attr_in1_alarm.dev_attr.attr,
2026 &sensor_dev_attr_in1_beep.dev_attr.attr, /* 9 */
2027
2028 &sensor_dev_attr_in2_input.dev_attr.attr,
2029 &sensor_dev_attr_in2_min.dev_attr.attr,
2030 &sensor_dev_attr_in2_max.dev_attr.attr,
2031 &sensor_dev_attr_in2_alarm.dev_attr.attr,
2032 &sensor_dev_attr_in2_beep.dev_attr.attr, /* 14 */
2033
2034 &sensor_dev_attr_in3_input.dev_attr.attr,
2035 &sensor_dev_attr_in3_min.dev_attr.attr,
2036 &sensor_dev_attr_in3_max.dev_attr.attr,
2037 &sensor_dev_attr_in3_alarm.dev_attr.attr,
2038 &sensor_dev_attr_in3_beep.dev_attr.attr, /* 19 */
2039
2040 &sensor_dev_attr_in4_input.dev_attr.attr,
2041 &sensor_dev_attr_in4_min.dev_attr.attr,
2042 &sensor_dev_attr_in4_max.dev_attr.attr,
2043 &sensor_dev_attr_in4_alarm.dev_attr.attr,
2044 &sensor_dev_attr_in4_beep.dev_attr.attr, /* 24 */
2045
2046 &sensor_dev_attr_in5_input.dev_attr.attr,
2047 &sensor_dev_attr_in5_min.dev_attr.attr,
2048 &sensor_dev_attr_in5_max.dev_attr.attr,
2049 &sensor_dev_attr_in5_alarm.dev_attr.attr,
2050 &sensor_dev_attr_in5_beep.dev_attr.attr, /* 29 */
2051
2052 &sensor_dev_attr_in6_input.dev_attr.attr,
2053 &sensor_dev_attr_in6_min.dev_attr.attr,
2054 &sensor_dev_attr_in6_max.dev_attr.attr,
2055 &sensor_dev_attr_in6_alarm.dev_attr.attr,
2056 &sensor_dev_attr_in6_beep.dev_attr.attr, /* 34 */
2057
2058 &sensor_dev_attr_in7_input.dev_attr.attr,
2059 &sensor_dev_attr_in7_min.dev_attr.attr,
2060 &sensor_dev_attr_in7_max.dev_attr.attr,
2061 &sensor_dev_attr_in7_alarm.dev_attr.attr,
2062 &sensor_dev_attr_in7_beep.dev_attr.attr, /* 39 */
2063
2064 &sensor_dev_attr_in8_input.dev_attr.attr, /* 40 */
2065 &sensor_dev_attr_in9_input.dev_attr.attr,
2066 &sensor_dev_attr_in10_input.dev_attr.attr,
2067 &sensor_dev_attr_in11_input.dev_attr.attr,
2068 &sensor_dev_attr_in12_input.dev_attr.attr,
2069 NULL
2070};
2071
2072static const struct attribute_group it87_group_in = {
2073 .attrs = it87_attributes_in,
2074 .is_visible = it87_in_is_visible,
2075};
2076
2077static umode_t it87_temp_is_visible(struct kobject *kobj,
2078 struct attribute *attr, int index)
2079{
2080 struct device *dev = kobj_to_dev(kobj);
2081 struct it87_data *data = dev_get_drvdata(dev);
2082 int i = index / 7; /* temperature index */
2083 int a = index % 7; /* attribute index */
2084
2085 if (index >= 21) {
2086 i = index - 21 + 3;
2087 a = 0;
2088 }
2089
2090 if (!(data->has_temp & BIT(i)))
2091 return 0;
2092
2093 if (a == 5 && !has_temp_offset(data))
2094 return 0;
2095
2096 if (a == 6 && !data->has_beep)
2097 return 0;
2098
2099 return attr->mode;
2100}
2101
2102static struct attribute *it87_attributes_temp[] = {
2103 &sensor_dev_attr_temp1_input.dev_attr.attr,
2104 &sensor_dev_attr_temp1_max.dev_attr.attr,
2105 &sensor_dev_attr_temp1_min.dev_attr.attr,
2106 &sensor_dev_attr_temp1_type.dev_attr.attr,
2107 &sensor_dev_attr_temp1_alarm.dev_attr.attr,
2108 &sensor_dev_attr_temp1_offset.dev_attr.attr, /* 5 */
2109 &sensor_dev_attr_temp1_beep.dev_attr.attr, /* 6 */
2110
2111 &sensor_dev_attr_temp2_input.dev_attr.attr, /* 7 */
2112 &sensor_dev_attr_temp2_max.dev_attr.attr,
2113 &sensor_dev_attr_temp2_min.dev_attr.attr,
2114 &sensor_dev_attr_temp2_type.dev_attr.attr,
2115 &sensor_dev_attr_temp2_alarm.dev_attr.attr,
2116 &sensor_dev_attr_temp2_offset.dev_attr.attr,
2117 &sensor_dev_attr_temp2_beep.dev_attr.attr,
2118
2119 &sensor_dev_attr_temp3_input.dev_attr.attr, /* 14 */
2120 &sensor_dev_attr_temp3_max.dev_attr.attr,
2121 &sensor_dev_attr_temp3_min.dev_attr.attr,
2122 &sensor_dev_attr_temp3_type.dev_attr.attr,
2123 &sensor_dev_attr_temp3_alarm.dev_attr.attr,
2124 &sensor_dev_attr_temp3_offset.dev_attr.attr,
2125 &sensor_dev_attr_temp3_beep.dev_attr.attr,
2126
2127 &sensor_dev_attr_temp4_input.dev_attr.attr, /* 21 */
2128 &sensor_dev_attr_temp5_input.dev_attr.attr,
2129 &sensor_dev_attr_temp6_input.dev_attr.attr,
2130 NULL
2131};
2132
2133static const struct attribute_group it87_group_temp = {
2134 .attrs = it87_attributes_temp,
2135 .is_visible = it87_temp_is_visible,
2136};
2137
2138static umode_t it87_is_visible(struct kobject *kobj,
2139 struct attribute *attr, int index)
2140{
2141 struct device *dev = kobj_to_dev(kobj);
2142 struct it87_data *data = dev_get_drvdata(dev);
2143
2144 if ((index == 2 || index == 3) && !data->has_vid)
2145 return 0;
2146
2147 if (index > 3 && !(data->in_internal & BIT(index - 4)))
2148 return 0;
2149
2150 return attr->mode;
2151}
2152
2153static struct attribute *it87_attributes[] = {
2154 &dev_attr_alarms.attr,
2155 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
2156 &dev_attr_vrm.attr, /* 2 */
2157 &dev_attr_cpu0_vid.attr, /* 3 */
2158 &sensor_dev_attr_in3_label.dev_attr.attr, /* 4 .. 7 */
2159 &sensor_dev_attr_in7_label.dev_attr.attr,
2160 &sensor_dev_attr_in8_label.dev_attr.attr,
2161 &sensor_dev_attr_in9_label.dev_attr.attr,
2162 NULL
2163};
2164
2165static const struct attribute_group it87_group = {
2166 .attrs = it87_attributes,
2167 .is_visible = it87_is_visible,
2168};
2169
2170static umode_t it87_fan_is_visible(struct kobject *kobj,
2171 struct attribute *attr, int index)
2172{
2173 struct device *dev = kobj_to_dev(kobj);
2174 struct it87_data *data = dev_get_drvdata(dev);
2175 int i = index / 5; /* fan index */
2176 int a = index % 5; /* attribute index */
2177
2178 if (index >= 15) { /* fan 4..6 don't have divisor attributes */
2179 i = (index - 15) / 4 + 3;
2180 a = (index - 15) % 4;
2181 }
2182
2183 if (!(data->has_fan & BIT(i)))
2184 return 0;
2185
2186 if (a == 3) { /* beep */
2187 if (!data->has_beep)
2188 return 0;
2189 /* first fan beep attribute is writable */
2190 if (i == __ffs(data->has_fan))
2191 return attr->mode | S_IWUSR;
2192 }
2193
2194 if (a == 4 && has_16bit_fans(data)) /* divisor */
2195 return 0;
2196
2197 return attr->mode;
2198}
2199
2200static struct attribute *it87_attributes_fan[] = {
2201 &sensor_dev_attr_fan1_input.dev_attr.attr,
2202 &sensor_dev_attr_fan1_min.dev_attr.attr,
2203 &sensor_dev_attr_fan1_alarm.dev_attr.attr,
2204 &sensor_dev_attr_fan1_beep.dev_attr.attr, /* 3 */
2205 &sensor_dev_attr_fan1_div.dev_attr.attr, /* 4 */
2206
2207 &sensor_dev_attr_fan2_input.dev_attr.attr,
2208 &sensor_dev_attr_fan2_min.dev_attr.attr,
2209 &sensor_dev_attr_fan2_alarm.dev_attr.attr,
2210 &sensor_dev_attr_fan2_beep.dev_attr.attr,
2211 &sensor_dev_attr_fan2_div.dev_attr.attr, /* 9 */
2212
2213 &sensor_dev_attr_fan3_input.dev_attr.attr,
2214 &sensor_dev_attr_fan3_min.dev_attr.attr,
2215 &sensor_dev_attr_fan3_alarm.dev_attr.attr,
2216 &sensor_dev_attr_fan3_beep.dev_attr.attr,
2217 &sensor_dev_attr_fan3_div.dev_attr.attr, /* 14 */
2218
2219 &sensor_dev_attr_fan4_input.dev_attr.attr, /* 15 */
2220 &sensor_dev_attr_fan4_min.dev_attr.attr,
2221 &sensor_dev_attr_fan4_alarm.dev_attr.attr,
2222 &sensor_dev_attr_fan4_beep.dev_attr.attr,
2223
2224 &sensor_dev_attr_fan5_input.dev_attr.attr, /* 19 */
2225 &sensor_dev_attr_fan5_min.dev_attr.attr,
2226 &sensor_dev_attr_fan5_alarm.dev_attr.attr,
2227 &sensor_dev_attr_fan5_beep.dev_attr.attr,
2228
2229 &sensor_dev_attr_fan6_input.dev_attr.attr, /* 23 */
2230 &sensor_dev_attr_fan6_min.dev_attr.attr,
2231 &sensor_dev_attr_fan6_alarm.dev_attr.attr,
2232 &sensor_dev_attr_fan6_beep.dev_attr.attr,
2233 NULL
2234};
2235
2236static const struct attribute_group it87_group_fan = {
2237 .attrs = it87_attributes_fan,
2238 .is_visible = it87_fan_is_visible,
2239};
2240
2241static umode_t it87_pwm_is_visible(struct kobject *kobj,
2242 struct attribute *attr, int index)
2243{
2244 struct device *dev = kobj_to_dev(kobj);
2245 struct it87_data *data = dev_get_drvdata(dev);
2246 int i = index / 4; /* pwm index */
2247 int a = index % 4; /* attribute index */
2248
2249 if (!(data->has_pwm & BIT(i)))
2250 return 0;
2251
2252 /* pwmX_auto_channels_temp is only writable if auto pwm is supported */
2253 if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data)))
2254 return attr->mode | S_IWUSR;
2255
2256 /* pwm2_freq is writable if there are two pwm frequency selects */
2257 if (has_pwm_freq2(data) && i == 1 && a == 2)
2258 return attr->mode | S_IWUSR;
2259
2260 return attr->mode;
2261}
2262
2263static struct attribute *it87_attributes_pwm[] = {
2264 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2265 &sensor_dev_attr_pwm1.dev_attr.attr,
2266 &sensor_dev_attr_pwm1_freq.dev_attr.attr,
2267 &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
2268
2269 &sensor_dev_attr_pwm2_enable.dev_attr.attr,
2270 &sensor_dev_attr_pwm2.dev_attr.attr,
2271 &sensor_dev_attr_pwm2_freq.dev_attr.attr,
2272 &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
2273
2274 &sensor_dev_attr_pwm3_enable.dev_attr.attr,
2275 &sensor_dev_attr_pwm3.dev_attr.attr,
2276 &sensor_dev_attr_pwm3_freq.dev_attr.attr,
2277 &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
2278
2279 &sensor_dev_attr_pwm4_enable.dev_attr.attr,
2280 &sensor_dev_attr_pwm4.dev_attr.attr,
2281 &sensor_dev_attr_pwm4_freq.dev_attr.attr,
2282 &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr,
2283
2284 &sensor_dev_attr_pwm5_enable.dev_attr.attr,
2285 &sensor_dev_attr_pwm5.dev_attr.attr,
2286 &sensor_dev_attr_pwm5_freq.dev_attr.attr,
2287 &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr,
2288
2289 &sensor_dev_attr_pwm6_enable.dev_attr.attr,
2290 &sensor_dev_attr_pwm6.dev_attr.attr,
2291 &sensor_dev_attr_pwm6_freq.dev_attr.attr,
2292 &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr,
2293
2294 NULL
2295};
2296
2297static const struct attribute_group it87_group_pwm = {
2298 .attrs = it87_attributes_pwm,
2299 .is_visible = it87_pwm_is_visible,
2300};
2301
2302static umode_t it87_auto_pwm_is_visible(struct kobject *kobj,
2303 struct attribute *attr, int index)
2304{
2305 struct device *dev = kobj_to_dev(kobj);
2306 struct it87_data *data = dev_get_drvdata(dev);
2307 int i = index / 11; /* pwm index */
2308 int a = index % 11; /* attribute index */
2309
2310 if (index >= 33) { /* pwm 4..6 */
2311 i = (index - 33) / 6 + 3;
2312 a = (index - 33) % 6 + 4;
2313 }
2314
2315 if (!(data->has_pwm & BIT(i)))
2316 return 0;
2317
2318 if (has_newer_autopwm(data)) {
2319 if (a < 4) /* no auto point pwm */
2320 return 0;
2321 if (a == 8) /* no auto_point4 */
2322 return 0;
2323 }
2324 if (has_old_autopwm(data)) {
2325 if (a >= 9) /* no pwm_auto_start, pwm_auto_slope */
2326 return 0;
2327 }
2328
2329 return attr->mode;
2330}
2331
2332static struct attribute *it87_attributes_auto_pwm[] = {
2333 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
2334 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
2335 &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
2336 &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
2337 &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
2338 &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
2339 &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
2340 &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
2341 &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
2342 &sensor_dev_attr_pwm1_auto_start.dev_attr.attr,
2343 &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr,
2344
2345 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, /* 11 */
2346 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
2347 &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
2348 &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
2349 &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
2350 &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
2351 &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
2352 &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
2353 &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
2354 &sensor_dev_attr_pwm2_auto_start.dev_attr.attr,
2355 &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr,
2356
2357 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, /* 22 */
2358 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
2359 &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
2360 &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
2361 &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
2362 &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
2363 &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
2364 &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
2365 &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
2366 &sensor_dev_attr_pwm3_auto_start.dev_attr.attr,
2367 &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr,
2368
2369 &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr, /* 33 */
2370 &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr,
2371 &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr,
2372 &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr,
2373 &sensor_dev_attr_pwm4_auto_start.dev_attr.attr,
2374 &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr,
2375
2376 &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr,
2377 &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr,
2378 &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr,
2379 &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr,
2380 &sensor_dev_attr_pwm5_auto_start.dev_attr.attr,
2381 &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr,
2382
2383 &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr,
2384 &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr,
2385 &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr,
2386 &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr,
2387 &sensor_dev_attr_pwm6_auto_start.dev_attr.attr,
2388 &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr,
2389
2390 NULL,
2391};
2392
2393static const struct attribute_group it87_group_auto_pwm = {
2394 .attrs = it87_attributes_auto_pwm,
2395 .is_visible = it87_auto_pwm_is_visible,
2396};
2397
2398/* SuperIO detection - will change isa_address if a chip is found */
2399static int __init it87_find(int sioaddr, unsigned short *address,
2400 struct it87_sio_data *sio_data)
2401{
2402 int err;
2403 u16 chip_type;
2404 const struct it87_devices *config;
2405
2406 err = superio_enter(sioaddr);
2407 if (err)
2408 return err;
2409
2410 err = -ENODEV;
2411 chip_type = superio_inw(sioaddr, DEVID);
2412 /* check first for a valid chip before forcing chip id */
2413 if (chip_type == 0xffff)
2414 goto exit;
2415
2416 if (force_id)
2417 chip_type = force_id;
2418
2419 switch (chip_type) {
2420 case IT8705F_DEVID:
2421 sio_data->type = it87;
2422 break;
2423 case IT8712F_DEVID:
2424 sio_data->type = it8712;
2425 break;
2426 case IT8716F_DEVID:
2427 case IT8726F_DEVID:
2428 sio_data->type = it8716;
2429 break;
2430 case IT8718F_DEVID:
2431 sio_data->type = it8718;
2432 break;
2433 case IT8720F_DEVID:
2434 sio_data->type = it8720;
2435 break;
2436 case IT8721F_DEVID:
2437 sio_data->type = it8721;
2438 break;
2439 case IT8728F_DEVID:
2440 sio_data->type = it8728;
2441 break;
2442 case IT8732F_DEVID:
2443 sio_data->type = it8732;
2444 break;
2445 case IT8792E_DEVID:
2446 sio_data->type = it8792;
2447 break;
2448 case IT8771E_DEVID:
2449 sio_data->type = it8771;
2450 break;
2451 case IT8772E_DEVID:
2452 sio_data->type = it8772;
2453 break;
2454 case IT8781F_DEVID:
2455 sio_data->type = it8781;
2456 break;
2457 case IT8782F_DEVID:
2458 sio_data->type = it8782;
2459 break;
2460 case IT8783E_DEVID:
2461 sio_data->type = it8783;
2462 break;
2463 case IT8786E_DEVID:
2464 sio_data->type = it8786;
2465 break;
2466 case IT8790E_DEVID:
2467 sio_data->type = it8790;
2468 break;
2469 case IT8603E_DEVID:
2470 case IT8623E_DEVID:
2471 sio_data->type = it8603;
2472 break;
2473 case IT8620E_DEVID:
2474 sio_data->type = it8620;
2475 break;
2476 case IT8622E_DEVID:
2477 sio_data->type = it8622;
2478 break;
2479 case IT8628E_DEVID:
2480 sio_data->type = it8628;
2481 break;
2482 case 0xffff: /* No device at all */
2483 goto exit;
2484 default:
2485 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
2486 goto exit;
2487 }
2488
2489 superio_select(sioaddr, PME);
2490 if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) {
2491 pr_info("Device not activated, skipping\n");
2492 goto exit;
2493 }
2494
2495 *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1);
2496 if (*address == 0) {
2497 pr_info("Base address not set, skipping\n");
2498 goto exit;
2499 }
2500
2501 err = 0;
2502 sio_data->sioaddr = sioaddr;
2503 sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
2504 pr_info("Found IT%04x%s chip at 0x%x, revision %d\n", chip_type,
2505 it87_devices[sio_data->type].suffix,
2506 *address, sio_data->revision);
2507
2508 config = &it87_devices[sio_data->type];
2509
2510 /* in7 (VSB or VCCH5V) is always internal on some chips */
2511 if (has_in7_internal(config))
2512 sio_data->internal |= BIT(1);
2513
2514 /* in8 (Vbat) is always internal */
2515 sio_data->internal |= BIT(2);
2516
2517 /* in9 (AVCC3), always internal if supported */
2518 if (has_avcc3(config))
2519 sio_data->internal |= BIT(3); /* in9 is AVCC */
2520 else
2521 sio_data->skip_in |= BIT(9);
2522
2523 if (!has_five_pwm(config))
2524 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5);
2525 else if (!has_six_pwm(config))
2526 sio_data->skip_pwm |= BIT(5);
2527
2528 if (!has_vid(config))
2529 sio_data->skip_vid = 1;
2530
2531 /* Read GPIO config and VID value from LDN 7 (GPIO) */
2532 if (sio_data->type == it87) {
2533 /* The IT8705F has a different LD number for GPIO */
2534 superio_select(sioaddr, 5);
2535 sio_data->beep_pin = superio_inb(sioaddr,
2536 IT87_SIO_BEEP_PIN_REG) & 0x3f;
2537 } else if (sio_data->type == it8783) {
2538 int reg25, reg27, reg2a, reg2c, regef;
2539
2540 superio_select(sioaddr, GPIO);
2541
2542 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
2543 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2544 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
2545 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
2546 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG);
2547
2548 /* Check if fan3 is there or not */
2549 if ((reg27 & BIT(0)) || !(reg2c & BIT(2)))
2550 sio_data->skip_fan |= BIT(2);
2551 if ((reg25 & BIT(4)) ||
2552 (!(reg2a & BIT(1)) && (regef & BIT(0))))
2553 sio_data->skip_pwm |= BIT(2);
2554
2555 /* Check if fan2 is there or not */
2556 if (reg27 & BIT(7))
2557 sio_data->skip_fan |= BIT(1);
2558 if (reg27 & BIT(3))
2559 sio_data->skip_pwm |= BIT(1);
2560
2561 /* VIN5 */
2562 if ((reg27 & BIT(0)) || (reg2c & BIT(2)))
2563 sio_data->skip_in |= BIT(5); /* No VIN5 */
2564
2565 /* VIN6 */
2566 if (reg27 & BIT(1))
2567 sio_data->skip_in |= BIT(6); /* No VIN6 */
2568
2569 /*
2570 * VIN7
2571 * Does not depend on bit 2 of Reg2C, contrary to datasheet.
2572 */
2573 if (reg27 & BIT(2)) {
2574 /*
2575 * The data sheet is a bit unclear regarding the
2576 * internal voltage divider for VCCH5V. It says
2577 * "This bit enables and switches VIN7 (pin 91) to the
2578 * internal voltage divider for VCCH5V".
2579 * This is different to other chips, where the internal
2580 * voltage divider would connect VIN7 to an internal
2581 * voltage source. Maybe that is the case here as well.
2582 *
2583 * Since we don't know for sure, re-route it if that is
2584 * not the case, and ask the user to report if the
2585 * resulting voltage is sane.
2586 */
2587 if (!(reg2c & BIT(1))) {
2588 reg2c |= BIT(1);
2589 superio_outb(sioaddr, IT87_SIO_PINX2_REG,
2590 reg2c);
2591 sio_data->need_in7_reroute = true;
2592 pr_notice("Routing internal VCCH5V to in7.\n");
2593 }
2594 pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
2595 pr_notice("Please report if it displays a reasonable voltage.\n");
2596 }
2597
2598 if (reg2c & BIT(0))
2599 sio_data->internal |= BIT(0);
2600 if (reg2c & BIT(1))
2601 sio_data->internal |= BIT(1);
2602
2603 sio_data->beep_pin = superio_inb(sioaddr,
2604 IT87_SIO_BEEP_PIN_REG) & 0x3f;
2605 } else if (sio_data->type == it8603) {
2606 int reg27, reg29;
2607
2608 superio_select(sioaddr, GPIO);
2609
2610 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2611
2612 /* Check if fan3 is there or not */
2613 if (reg27 & BIT(6))
2614 sio_data->skip_pwm |= BIT(2);
2615 if (reg27 & BIT(7))
2616 sio_data->skip_fan |= BIT(2);
2617
2618 /* Check if fan2 is there or not */
2619 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
2620 if (reg29 & BIT(1))
2621 sio_data->skip_pwm |= BIT(1);
2622 if (reg29 & BIT(2))
2623 sio_data->skip_fan |= BIT(1);
2624
2625 sio_data->skip_in |= BIT(5); /* No VIN5 */
2626 sio_data->skip_in |= BIT(6); /* No VIN6 */
2627
2628 sio_data->beep_pin = superio_inb(sioaddr,
2629 IT87_SIO_BEEP_PIN_REG) & 0x3f;
2630 } else if (sio_data->type == it8620 || sio_data->type == it8628) {
2631 int reg;
2632
2633 superio_select(sioaddr, GPIO);
2634
2635 /* Check for pwm5 */
2636 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
2637 if (reg & BIT(6))
2638 sio_data->skip_pwm |= BIT(4);
2639
2640 /* Check for fan4, fan5 */
2641 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
2642 if (!(reg & BIT(5)))
2643 sio_data->skip_fan |= BIT(3);
2644 if (!(reg & BIT(4)))
2645 sio_data->skip_fan |= BIT(4);
2646
2647 /* Check for pwm3, fan3 */
2648 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2649 if (reg & BIT(6))
2650 sio_data->skip_pwm |= BIT(2);
2651 if (reg & BIT(7))
2652 sio_data->skip_fan |= BIT(2);
2653
2654 /* Check for pwm4 */
2655 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG);
2656 if (reg & BIT(2))
2657 sio_data->skip_pwm |= BIT(3);
2658
2659 /* Check for pwm2, fan2 */
2660 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
2661 if (reg & BIT(1))
2662 sio_data->skip_pwm |= BIT(1);
2663 if (reg & BIT(2))
2664 sio_data->skip_fan |= BIT(1);
2665 /* Check for pwm6, fan6 */
2666 if (!(reg & BIT(7))) {
2667 sio_data->skip_pwm |= BIT(5);
2668 sio_data->skip_fan |= BIT(5);
2669 }
2670
2671 /* Check if AVCC is on VIN3 */
2672 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
2673 if (reg & BIT(0))
2674 sio_data->internal |= BIT(0);
2675 else
2676 sio_data->skip_in |= BIT(9);
2677
2678 sio_data->beep_pin = superio_inb(sioaddr,
2679 IT87_SIO_BEEP_PIN_REG) & 0x3f;
2680 } else if (sio_data->type == it8622) {
2681 int reg;
2682
2683 superio_select(sioaddr, GPIO);
2684
2685 /* Check for pwm4, fan4 */
2686 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
2687 if (reg & BIT(6))
2688 sio_data->skip_fan |= BIT(3);
2689 if (reg & BIT(5))
2690 sio_data->skip_pwm |= BIT(3);
2691
2692 /* Check for pwm3, fan3, pwm5, fan5 */
2693 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2694 if (reg & BIT(6))
2695 sio_data->skip_pwm |= BIT(2);
2696 if (reg & BIT(7))
2697 sio_data->skip_fan |= BIT(2);
2698 if (reg & BIT(3))
2699 sio_data->skip_pwm |= BIT(4);
2700 if (reg & BIT(1))
2701 sio_data->skip_fan |= BIT(4);
2702
2703 /* Check for pwm2, fan2 */
2704 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
2705 if (reg & BIT(1))
2706 sio_data->skip_pwm |= BIT(1);
2707 if (reg & BIT(2))
2708 sio_data->skip_fan |= BIT(1);
2709
2710 /* Check for AVCC */
2711 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
2712 if (!(reg & BIT(0)))
2713 sio_data->skip_in |= BIT(9);
2714
2715 sio_data->beep_pin = superio_inb(sioaddr,
2716 IT87_SIO_BEEP_PIN_REG) & 0x3f;
2717 } else {
2718 int reg;
2719 bool uart6;
2720
2721 superio_select(sioaddr, GPIO);
2722
2723 /* Check for fan4, fan5 */
2724 if (has_five_fans(config)) {
2725 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
2726 switch (sio_data->type) {
2727 case it8718:
2728 if (reg & BIT(5))
2729 sio_data->skip_fan |= BIT(3);
2730 if (reg & BIT(4))
2731 sio_data->skip_fan |= BIT(4);
2732 break;
2733 case it8720:
2734 case it8721:
2735 case it8728:
2736 if (!(reg & BIT(5)))
2737 sio_data->skip_fan |= BIT(3);
2738 if (!(reg & BIT(4)))
2739 sio_data->skip_fan |= BIT(4);
2740 break;
2741 default:
2742 break;
2743 }
2744 }
2745
2746 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2747 if (!sio_data->skip_vid) {
2748 /* We need at least 4 VID pins */
2749 if (reg & 0x0f) {
2750 pr_info("VID is disabled (pins used for GPIO)\n");
2751 sio_data->skip_vid = 1;
2752 }
2753 }
2754
2755 /* Check if fan3 is there or not */
2756 if (reg & BIT(6))
2757 sio_data->skip_pwm |= BIT(2);
2758 if (reg & BIT(7))
2759 sio_data->skip_fan |= BIT(2);
2760
2761 /* Check if fan2 is there or not */
2762 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
2763 if (reg & BIT(1))
2764 sio_data->skip_pwm |= BIT(1);
2765 if (reg & BIT(2))
2766 sio_data->skip_fan |= BIT(1);
2767
2768 if ((sio_data->type == it8718 || sio_data->type == it8720) &&
2769 !(sio_data->skip_vid))
2770 sio_data->vid_value = superio_inb(sioaddr,
2771 IT87_SIO_VID_REG);
2772
2773 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
2774
2775 uart6 = sio_data->type == it8782 && (reg & BIT(2));
2776
2777 /*
2778 * The IT8720F has no VIN7 pin, so VCCH5V should always be
2779 * routed internally to VIN7 with an internal divider.
2780 * Curiously, there still is a configuration bit to control
2781 * this, which means it can be set incorrectly. And even
2782 * more curiously, many boards out there are improperly
2783 * configured, even though the IT8720F datasheet claims
2784 * that the internal routing of VCCH5V to VIN7 is the default
2785 * setting. So we force the internal routing in this case.
2786 *
2787 * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
2788 * If UART6 is enabled, re-route VIN7 to the internal divider
2789 * if that is not already the case.
2790 */
2791 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) {
2792 reg |= BIT(1);
2793 superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg);
2794 sio_data->need_in7_reroute = true;
2795 pr_notice("Routing internal VCCH5V to in7\n");
2796 }
2797 if (reg & BIT(0))
2798 sio_data->internal |= BIT(0);
2799 if (reg & BIT(1))
2800 sio_data->internal |= BIT(1);
2801
2802 /*
2803 * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
2804 * While VIN7 can be routed to the internal voltage divider,
2805 * VIN5 and VIN6 are not available if UART6 is enabled.
2806 *
2807 * Also, temp3 is not available if UART6 is enabled and TEMPIN3
2808 * is the temperature source. Since we can not read the
2809 * temperature source here, skip_temp is preliminary.
2810 */
2811 if (uart6) {
2812 sio_data->skip_in |= BIT(5) | BIT(6);
2813 sio_data->skip_temp |= BIT(2);
2814 }
2815
2816 sio_data->beep_pin = superio_inb(sioaddr,
2817 IT87_SIO_BEEP_PIN_REG) & 0x3f;
2818 }
2819 if (sio_data->beep_pin)
2820 pr_info("Beeping is supported\n");
2821
2822 /* Set values based on DMI matches */
2823 if (dmi_data)
2824 sio_data->skip_pwm |= dmi_data->skip_pwm;
2825
2826exit:
2827 superio_exit(sioaddr);
2828 return err;
2829}
2830
2831/*
2832 * Some chips seem to have default value 0xff for all limit
2833 * registers. For low voltage limits it makes no sense and triggers
2834 * alarms, so change to 0 instead. For high temperature limits, it
2835 * means -1 degree C, which surprisingly doesn't trigger an alarm,
2836 * but is still confusing, so change to 127 degrees C.
2837 */
2838static void it87_check_limit_regs(struct it87_data *data)
2839{
2840 int i, reg;
2841
2842 for (i = 0; i < NUM_VIN_LIMIT; i++) {
2843 reg = it87_read_value(data, IT87_REG_VIN_MIN(i));
2844 if (reg == 0xff)
2845 it87_write_value(data, IT87_REG_VIN_MIN(i), 0);
2846 }
2847 for (i = 0; i < NUM_TEMP_LIMIT; i++) {
2848 reg = it87_read_value(data, IT87_REG_TEMP_HIGH(i));
2849 if (reg == 0xff)
2850 it87_write_value(data, IT87_REG_TEMP_HIGH(i), 127);
2851 }
2852}
2853
2854/* Check if voltage monitors are reset manually or by some reason */
2855static void it87_check_voltage_monitors_reset(struct it87_data *data)
2856{
2857 int reg;
2858
2859 reg = it87_read_value(data, IT87_REG_VIN_ENABLE);
2860 if ((reg & 0xff) == 0) {
2861 /* Enable all voltage monitors */
2862 it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff);
2863 }
2864}
2865
2866/* Check if tachometers are reset manually or by some reason */
2867static void it87_check_tachometers_reset(struct platform_device *pdev)
2868{
2869 struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
2870 struct it87_data *data = platform_get_drvdata(pdev);
2871 u8 mask, fan_main_ctrl;
2872
2873 mask = 0x70 & ~(sio_data->skip_fan << 4);
2874 fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
2875 if ((fan_main_ctrl & mask) == 0) {
2876 /* Enable all fan tachometers */
2877 fan_main_ctrl |= mask;
2878 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
2879 fan_main_ctrl);
2880 }
2881}
2882
2883/* Set tachometers to 16-bit mode if needed */
2884static void it87_check_tachometers_16bit_mode(struct platform_device *pdev)
2885{
2886 struct it87_data *data = platform_get_drvdata(pdev);
2887 int reg;
2888
2889 if (!has_fan16_config(data))
2890 return;
2891
2892 reg = it87_read_value(data, IT87_REG_FAN_16BIT);
2893 if (~reg & 0x07 & data->has_fan) {
2894 dev_dbg(&pdev->dev,
2895 "Setting fan1-3 to 16-bit mode\n");
2896 it87_write_value(data, IT87_REG_FAN_16BIT,
2897 reg | 0x07);
2898 }
2899}
2900
2901static void it87_start_monitoring(struct it87_data *data)
2902{
2903 it87_write_value(data, IT87_REG_CONFIG,
2904 (it87_read_value(data, IT87_REG_CONFIG) & 0x3e)
2905 | (update_vbat ? 0x41 : 0x01));
2906}
2907
2908/* Called when we have found a new IT87. */
2909static void it87_init_device(struct platform_device *pdev)
2910{
2911 struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
2912 struct it87_data *data = platform_get_drvdata(pdev);
2913 int tmp, i;
2914
2915 /*
2916 * For each PWM channel:
2917 * - If it is in automatic mode, setting to manual mode should set
2918 * the fan to full speed by default.
2919 * - If it is in manual mode, we need a mapping to temperature
2920 * channels to use when later setting to automatic mode later.
2921 * Use a 1:1 mapping by default (we are clueless.)
2922 * In both cases, the value can (and should) be changed by the user
2923 * prior to switching to a different mode.
2924 * Note that this is no longer needed for the IT8721F and later, as
2925 * these have separate registers for the temperature mapping and the
2926 * manual duty cycle.
2927 */
2928 for (i = 0; i < NUM_AUTO_PWM; i++) {
2929 data->pwm_temp_map[i] = i;
2930 data->pwm_duty[i] = 0x7f; /* Full speed */
2931 data->auto_pwm[i][3] = 0x7f; /* Full speed, hard-coded */
2932 }
2933
2934 it87_check_limit_regs(data);
2935
2936 /*
2937 * Temperature channels are not forcibly enabled, as they can be
2938 * set to two different sensor types and we can't guess which one
2939 * is correct for a given system. These channels can be enabled at
2940 * run-time through the temp{1-3}_type sysfs accessors if needed.
2941 */
2942
2943 it87_check_voltage_monitors_reset(data);
2944
2945 it87_check_tachometers_reset(pdev);
2946
2947 data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
2948 data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
2949
2950 it87_check_tachometers_16bit_mode(pdev);
2951
2952 /* Check for additional fans */
2953 if (has_five_fans(data)) {
2954 tmp = it87_read_value(data, IT87_REG_FAN_16BIT);
2955
2956 if (tmp & BIT(4))
2957 data->has_fan |= BIT(3); /* fan4 enabled */
2958 if (tmp & BIT(5))
2959 data->has_fan |= BIT(4); /* fan5 enabled */
2960 if (has_six_fans(data) && (tmp & BIT(2)))
2961 data->has_fan |= BIT(5); /* fan6 enabled */
2962 }
2963
2964 /* Fan input pins may be used for alternative functions */
2965 data->has_fan &= ~sio_data->skip_fan;
2966
2967 /* Check if pwm5, pwm6 are enabled */
2968 if (has_six_pwm(data)) {
2969 /* The following code may be IT8620E specific */
2970 tmp = it87_read_value(data, IT87_REG_FAN_DIV);
2971 if ((tmp & 0xc0) == 0xc0)
2972 sio_data->skip_pwm |= BIT(4);
2973 if (!(tmp & BIT(3)))
2974 sio_data->skip_pwm |= BIT(5);
2975 }
2976
2977 it87_start_monitoring(data);
2978}
2979
2980/* Return 1 if and only if the PWM interface is safe to use */
2981static int it87_check_pwm(struct device *dev)
2982{
2983 struct it87_data *data = dev_get_drvdata(dev);
2984 /*
2985 * Some BIOSes fail to correctly configure the IT87 fans. All fans off
2986 * and polarity set to active low is sign that this is the case so we
2987 * disable pwm control to protect the user.
2988 */
2989 int tmp = it87_read_value(data, IT87_REG_FAN_CTL);
2990
2991 if ((tmp & 0x87) == 0) {
2992 if (fix_pwm_polarity) {
2993 /*
2994 * The user asks us to attempt a chip reconfiguration.
2995 * This means switching to active high polarity and
2996 * inverting all fan speed values.
2997 */
2998 int i;
2999 u8 pwm[3];
3000
3001 for (i = 0; i < ARRAY_SIZE(pwm); i++)
3002 pwm[i] = it87_read_value(data,
3003 IT87_REG_PWM[i]);
3004
3005 /*
3006 * If any fan is in automatic pwm mode, the polarity
3007 * might be correct, as suspicious as it seems, so we
3008 * better don't change anything (but still disable the
3009 * PWM interface).
3010 */
3011 if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
3012 dev_info(dev,
3013 "Reconfiguring PWM to active high polarity\n");
3014 it87_write_value(data, IT87_REG_FAN_CTL,
3015 tmp | 0x87);
3016 for (i = 0; i < 3; i++)
3017 it87_write_value(data,
3018 IT87_REG_PWM[i],
3019 0x7f & ~pwm[i]);
3020 return 1;
3021 }
3022
3023 dev_info(dev,
3024 "PWM configuration is too broken to be fixed\n");
3025 }
3026
3027 return 0;
3028 } else if (fix_pwm_polarity) {
3029 dev_info(dev,
3030 "PWM configuration looks sane, won't touch\n");
3031 }
3032
3033 return 1;
3034}
3035
3036static int it87_probe(struct platform_device *pdev)
3037{
3038 struct it87_data *data;
3039 struct resource *res;
3040 struct device *dev = &pdev->dev;
3041 struct it87_sio_data *sio_data = dev_get_platdata(dev);
3042 int enable_pwm_interface;
3043 struct device *hwmon_dev;
3044
3045 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3046 if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT,
3047 DRVNAME)) {
3048 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
3049 (unsigned long)res->start,
3050 (unsigned long)(res->start + IT87_EC_EXTENT - 1));
3051 return -EBUSY;
3052 }
3053
3054 data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL);
3055 if (!data)
3056 return -ENOMEM;
3057
3058 data->addr = res->start;
3059 data->sioaddr = sio_data->sioaddr;
3060 data->type = sio_data->type;
3061 data->features = it87_devices[sio_data->type].features;
3062 data->peci_mask = it87_devices[sio_data->type].peci_mask;
3063 data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
3064 /*
3065 * IT8705F Datasheet 0.4.1, 3h == Version G.
3066 * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
3067 * These are the first revisions with 16-bit tachometer support.
3068 */
3069 switch (data->type) {
3070 case it87:
3071 if (sio_data->revision >= 0x03) {
3072 data->features &= ~FEAT_OLD_AUTOPWM;
3073 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
3074 }
3075 break;
3076 case it8712:
3077 if (sio_data->revision >= 0x08) {
3078 data->features &= ~FEAT_OLD_AUTOPWM;
3079 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
3080 FEAT_FIVE_FANS;
3081 }
3082 break;
3083 default:
3084 break;
3085 }
3086
3087 /* Now, we do the remaining detection. */
3088 if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80) ||
3089 it87_read_value(data, IT87_REG_CHIPID) != 0x90)
3090 return -ENODEV;
3091
3092 platform_set_drvdata(pdev, data);
3093
3094 mutex_init(&data->update_lock);
3095
3096 /* Check PWM configuration */
3097 enable_pwm_interface = it87_check_pwm(dev);
3098 if (!enable_pwm_interface)
3099 dev_info(dev,
3100 "Detected broken BIOS defaults, disabling PWM interface\n");
3101
3102 /* Starting with IT8721F, we handle scaling of internal voltages */
3103 if (has_12mv_adc(data)) {
3104 if (sio_data->internal & BIT(0))
3105 data->in_scaled |= BIT(3); /* in3 is AVCC */
3106 if (sio_data->internal & BIT(1))
3107 data->in_scaled |= BIT(7); /* in7 is VSB */
3108 if (sio_data->internal & BIT(2))
3109 data->in_scaled |= BIT(8); /* in8 is Vbat */
3110 if (sio_data->internal & BIT(3))
3111 data->in_scaled |= BIT(9); /* in9 is AVCC */
3112 } else if (sio_data->type == it8781 || sio_data->type == it8782 ||
3113 sio_data->type == it8783) {
3114 if (sio_data->internal & BIT(0))
3115 data->in_scaled |= BIT(3); /* in3 is VCC5V */
3116 if (sio_data->internal & BIT(1))
3117 data->in_scaled |= BIT(7); /* in7 is VCCH5V */
3118 }
3119
3120 data->has_temp = 0x07;
3121 if (sio_data->skip_temp & BIT(2)) {
3122 if (sio_data->type == it8782 &&
3123 !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80))
3124 data->has_temp &= ~BIT(2);
3125 }
3126
3127 data->in_internal = sio_data->internal;
3128 data->need_in7_reroute = sio_data->need_in7_reroute;
3129 data->has_in = 0x3ff & ~sio_data->skip_in;
3130
3131 if (has_six_temp(data)) {
3132 u8 reg = it87_read_value(data, IT87_REG_TEMP456_ENABLE);
3133
3134 /* Check for additional temperature sensors */
3135 if ((reg & 0x03) >= 0x02)
3136 data->has_temp |= BIT(3);
3137 if (((reg >> 2) & 0x03) >= 0x02)
3138 data->has_temp |= BIT(4);
3139 if (((reg >> 4) & 0x03) >= 0x02)
3140 data->has_temp |= BIT(5);
3141
3142 /* Check for additional voltage sensors */
3143 if ((reg & 0x03) == 0x01)
3144 data->has_in |= BIT(10);
3145 if (((reg >> 2) & 0x03) == 0x01)
3146 data->has_in |= BIT(11);
3147 if (((reg >> 4) & 0x03) == 0x01)
3148 data->has_in |= BIT(12);
3149 }
3150
3151 data->has_beep = !!sio_data->beep_pin;
3152
3153 /* Initialize the IT87 chip */
3154 it87_init_device(pdev);
3155
3156 if (!sio_data->skip_vid) {
3157 data->has_vid = true;
3158 data->vrm = vid_which_vrm();
3159 /* VID reading from Super-I/O config space if available */
3160 data->vid = sio_data->vid_value;
3161 }
3162
3163 /* Prepare for sysfs hooks */
3164 data->groups[0] = &it87_group;
3165 data->groups[1] = &it87_group_in;
3166 data->groups[2] = &it87_group_temp;
3167 data->groups[3] = &it87_group_fan;
3168
3169 if (enable_pwm_interface) {
3170 data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1;
3171 data->has_pwm &= ~sio_data->skip_pwm;
3172
3173 data->groups[4] = &it87_group_pwm;
3174 if (has_old_autopwm(data) || has_newer_autopwm(data))
3175 data->groups[5] = &it87_group_auto_pwm;
3176 }
3177
3178 hwmon_dev = devm_hwmon_device_register_with_groups(dev,
3179 it87_devices[sio_data->type].name,
3180 data, data->groups);
3181 return PTR_ERR_OR_ZERO(hwmon_dev);
3182}
3183
3184static void it87_resume_sio(struct platform_device *pdev)
3185{
3186 struct it87_data *data = dev_get_drvdata(&pdev->dev);
3187 int err;
3188 int reg2c;
3189
3190 if (!data->need_in7_reroute)
3191 return;
3192
3193 err = superio_enter(data->sioaddr);
3194 if (err) {
3195 dev_warn(&pdev->dev,
3196 "Unable to enter Super I/O to reroute in7 (%d)",
3197 err);
3198 return;
3199 }
3200
3201 superio_select(data->sioaddr, GPIO);
3202
3203 reg2c = superio_inb(data->sioaddr, IT87_SIO_PINX2_REG);
3204 if (!(reg2c & BIT(1))) {
3205 dev_dbg(&pdev->dev,
3206 "Routing internal VCCH5V to in7 again");
3207
3208 reg2c |= BIT(1);
3209 superio_outb(data->sioaddr, IT87_SIO_PINX2_REG,
3210 reg2c);
3211 }
3212
3213 superio_exit(data->sioaddr);
3214}
3215
3216static int it87_resume(struct device *dev)
3217{
3218 struct platform_device *pdev = to_platform_device(dev);
3219 struct it87_data *data = dev_get_drvdata(dev);
3220
3221 it87_resume_sio(pdev);
3222
3223 mutex_lock(&data->update_lock);
3224
3225 it87_check_pwm(dev);
3226 it87_check_limit_regs(data);
3227 it87_check_voltage_monitors_reset(data);
3228 it87_check_tachometers_reset(pdev);
3229 it87_check_tachometers_16bit_mode(pdev);
3230
3231 it87_start_monitoring(data);
3232
3233 /* force update */
3234 data->valid = false;
3235
3236 mutex_unlock(&data->update_lock);
3237
3238 it87_update_device(dev);
3239
3240 return 0;
3241}
3242
3243static DEFINE_SIMPLE_DEV_PM_OPS(it87_dev_pm_ops, NULL, it87_resume);
3244
3245static struct platform_driver it87_driver = {
3246 .driver = {
3247 .name = DRVNAME,
3248 .pm = pm_sleep_ptr(&it87_dev_pm_ops),
3249 },
3250 .probe = it87_probe,
3251};
3252
3253static int __init it87_device_add(int index, unsigned short address,
3254 const struct it87_sio_data *sio_data)
3255{
3256 struct platform_device *pdev;
3257 struct resource res = {
3258 .start = address + IT87_EC_OFFSET,
3259 .end = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1,
3260 .name = DRVNAME,
3261 .flags = IORESOURCE_IO,
3262 };
3263 int err;
3264
3265 err = acpi_check_resource_conflict(&res);
3266 if (err) {
3267 if (!ignore_resource_conflict)
3268 return err;
3269 }
3270
3271 pdev = platform_device_alloc(DRVNAME, address);
3272 if (!pdev)
3273 return -ENOMEM;
3274
3275 err = platform_device_add_resources(pdev, &res, 1);
3276 if (err) {
3277 pr_err("Device resource addition failed (%d)\n", err);
3278 goto exit_device_put;
3279 }
3280
3281 err = platform_device_add_data(pdev, sio_data,
3282 sizeof(struct it87_sio_data));
3283 if (err) {
3284 pr_err("Platform data allocation failed\n");
3285 goto exit_device_put;
3286 }
3287
3288 err = platform_device_add(pdev);
3289 if (err) {
3290 pr_err("Device addition failed (%d)\n", err);
3291 goto exit_device_put;
3292 }
3293
3294 it87_pdev[index] = pdev;
3295 return 0;
3296
3297exit_device_put:
3298 platform_device_put(pdev);
3299 return err;
3300}
3301
3302/* callback function for DMI */
3303static int it87_dmi_cb(const struct dmi_system_id *dmi_entry)
3304{
3305 dmi_data = dmi_entry->driver_data;
3306
3307 if (dmi_data && dmi_data->skip_pwm)
3308 pr_info("Disabling pwm2 due to hardware constraints\n");
3309
3310 return 1;
3311}
3312
3313/*
3314 * On the Shuttle SN68PT, FAN_CTL2 is apparently not
3315 * connected to a fan, but to something else. One user
3316 * has reported instant system power-off when changing
3317 * the PWM2 duty cycle, so we disable it.
3318 * I use the board name string as the trigger in case
3319 * the same board is ever used in other systems.
3320 */
3321static struct it87_dmi_data nvidia_fn68pt = {
3322 .skip_pwm = BIT(1),
3323};
3324
3325#define IT87_DMI_MATCH_VND(vendor, name, cb, data) \
3326 { \
3327 .callback = cb, \
3328 .matches = { \
3329 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, vendor), \
3330 DMI_EXACT_MATCH(DMI_BOARD_NAME, name), \
3331 }, \
3332 .driver_data = data, \
3333 }
3334
3335static const struct dmi_system_id it87_dmi_table[] __initconst = {
3336 IT87_DMI_MATCH_VND("nVIDIA", "FN68PT", it87_dmi_cb, &nvidia_fn68pt),
3337 { }
3338
3339};
3340MODULE_DEVICE_TABLE(dmi, it87_dmi_table);
3341
3342static int __init sm_it87_init(void)
3343{
3344 int sioaddr[2] = { REG_2E, REG_4E };
3345 struct it87_sio_data sio_data;
3346 unsigned short isa_address[2];
3347 bool found = false;
3348 int i, err;
3349
3350 err = platform_driver_register(&it87_driver);
3351 if (err)
3352 return err;
3353
3354 dmi_check_system(it87_dmi_table);
3355
3356 for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
3357 memset(&sio_data, 0, sizeof(struct it87_sio_data));
3358 isa_address[i] = 0;
3359 err = it87_find(sioaddr[i], &isa_address[i], &sio_data);
3360 if (err || isa_address[i] == 0)
3361 continue;
3362 /*
3363 * Don't register second chip if its ISA address matches
3364 * the first chip's ISA address.
3365 */
3366 if (i && isa_address[i] == isa_address[0])
3367 break;
3368
3369 err = it87_device_add(i, isa_address[i], &sio_data);
3370 if (err)
3371 goto exit_dev_unregister;
3372
3373 found = true;
3374
3375 /*
3376 * IT8705F may respond on both SIO addresses.
3377 * Stop probing after finding one.
3378 */
3379 if (sio_data.type == it87)
3380 break;
3381 }
3382
3383 if (!found) {
3384 err = -ENODEV;
3385 goto exit_unregister;
3386 }
3387 return 0;
3388
3389exit_dev_unregister:
3390 /* NULL check handled by platform_device_unregister */
3391 platform_device_unregister(it87_pdev[0]);
3392exit_unregister:
3393 platform_driver_unregister(&it87_driver);
3394 return err;
3395}
3396
3397static void __exit sm_it87_exit(void)
3398{
3399 /* NULL check handled by platform_device_unregister */
3400 platform_device_unregister(it87_pdev[1]);
3401 platform_device_unregister(it87_pdev[0]);
3402 platform_driver_unregister(&it87_driver);
3403}
3404
3405MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
3406MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
3407module_param(update_vbat, bool, 0);
3408MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
3409module_param(fix_pwm_polarity, bool, 0);
3410MODULE_PARM_DESC(fix_pwm_polarity,
3411 "Force PWM polarity to active high (DANGEROUS)");
3412MODULE_LICENSE("GPL");
3413
3414module_init(sm_it87_init);
3415module_exit(sm_it87_exit);
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * it87.c - Part of lm_sensors, Linux kernel modules for hardware
4 * monitoring.
5 *
6 * The IT8705F is an LPC-based Super I/O part that contains UARTs, a
7 * parallel port, an IR port, a MIDI port, a floppy controller, etc., in
8 * addition to an Environment Controller (Enhanced Hardware Monitor and
9 * Fan Controller)
10 *
11 * This driver supports only the Environment Controller in the IT8705F and
12 * similar parts. The other devices are supported by different drivers.
13 *
14 * Supports: IT8603E Super I/O chip w/LPC interface
15 * IT8620E Super I/O chip w/LPC interface
16 * IT8622E Super I/O chip w/LPC interface
17 * IT8623E Super I/O chip w/LPC interface
18 * IT8628E Super I/O chip w/LPC interface
19 * IT8705F Super I/O chip w/LPC interface
20 * IT8712F Super I/O chip w/LPC interface
21 * IT8716F Super I/O chip w/LPC interface
22 * IT8718F Super I/O chip w/LPC interface
23 * IT8720F Super I/O chip w/LPC interface
24 * IT8721F Super I/O chip w/LPC interface
25 * IT8726F Super I/O chip w/LPC interface
26 * IT8728F Super I/O chip w/LPC interface
27 * IT8732F Super I/O chip w/LPC interface
28 * IT8758E Super I/O chip w/LPC interface
29 * IT8771E Super I/O chip w/LPC interface
30 * IT8772E Super I/O chip w/LPC interface
31 * IT8781F Super I/O chip w/LPC interface
32 * IT8782F Super I/O chip w/LPC interface
33 * IT8783E/F Super I/O chip w/LPC interface
34 * IT8786E Super I/O chip w/LPC interface
35 * IT8790E Super I/O chip w/LPC interface
36 * IT8792E Super I/O chip w/LPC interface
37 * Sis950 A clone of the IT8705F
38 *
39 * Copyright (C) 2001 Chris Gauthron
40 * Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
41 */
42
43#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44
45#include <linux/bitops.h>
46#include <linux/module.h>
47#include <linux/init.h>
48#include <linux/slab.h>
49#include <linux/jiffies.h>
50#include <linux/platform_device.h>
51#include <linux/hwmon.h>
52#include <linux/hwmon-sysfs.h>
53#include <linux/hwmon-vid.h>
54#include <linux/err.h>
55#include <linux/mutex.h>
56#include <linux/sysfs.h>
57#include <linux/string.h>
58#include <linux/dmi.h>
59#include <linux/acpi.h>
60#include <linux/io.h>
61
62#define DRVNAME "it87"
63
64enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
65 it8771, it8772, it8781, it8782, it8783, it8786, it8790,
66 it8792, it8603, it8620, it8622, it8628 };
67
68static unsigned short force_id;
69module_param(force_id, ushort, 0);
70MODULE_PARM_DESC(force_id, "Override the detected device ID");
71
72static bool ignore_resource_conflict;
73module_param(ignore_resource_conflict, bool, 0);
74MODULE_PARM_DESC(ignore_resource_conflict, "Ignore ACPI resource conflict");
75
76static struct platform_device *it87_pdev[2];
77
78#define REG_2E 0x2e /* The register to read/write */
79#define REG_4E 0x4e /* Secondary register to read/write */
80
81#define DEV 0x07 /* Register: Logical device select */
82#define PME 0x04 /* The device with the fan registers in it */
83
84/* The device with the IT8718F/IT8720F VID value in it */
85#define GPIO 0x07
86
87#define DEVID 0x20 /* Register: Device ID */
88#define DEVREV 0x22 /* Register: Device Revision */
89
90static inline int superio_inb(int ioreg, int reg)
91{
92 outb(reg, ioreg);
93 return inb(ioreg + 1);
94}
95
96static inline void superio_outb(int ioreg, int reg, int val)
97{
98 outb(reg, ioreg);
99 outb(val, ioreg + 1);
100}
101
102static int superio_inw(int ioreg, int reg)
103{
104 int val;
105
106 outb(reg++, ioreg);
107 val = inb(ioreg + 1) << 8;
108 outb(reg, ioreg);
109 val |= inb(ioreg + 1);
110 return val;
111}
112
113static inline void superio_select(int ioreg, int ldn)
114{
115 outb(DEV, ioreg);
116 outb(ldn, ioreg + 1);
117}
118
119static inline int superio_enter(int ioreg)
120{
121 /*
122 * Try to reserve ioreg and ioreg + 1 for exclusive access.
123 */
124 if (!request_muxed_region(ioreg, 2, DRVNAME))
125 return -EBUSY;
126
127 outb(0x87, ioreg);
128 outb(0x01, ioreg);
129 outb(0x55, ioreg);
130 outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
131 return 0;
132}
133
134static inline void superio_exit(int ioreg)
135{
136 outb(0x02, ioreg);
137 outb(0x02, ioreg + 1);
138 release_region(ioreg, 2);
139}
140
141/* Logical device 4 registers */
142#define IT8712F_DEVID 0x8712
143#define IT8705F_DEVID 0x8705
144#define IT8716F_DEVID 0x8716
145#define IT8718F_DEVID 0x8718
146#define IT8720F_DEVID 0x8720
147#define IT8721F_DEVID 0x8721
148#define IT8726F_DEVID 0x8726
149#define IT8728F_DEVID 0x8728
150#define IT8732F_DEVID 0x8732
151#define IT8792E_DEVID 0x8733
152#define IT8771E_DEVID 0x8771
153#define IT8772E_DEVID 0x8772
154#define IT8781F_DEVID 0x8781
155#define IT8782F_DEVID 0x8782
156#define IT8783E_DEVID 0x8783
157#define IT8786E_DEVID 0x8786
158#define IT8790E_DEVID 0x8790
159#define IT8603E_DEVID 0x8603
160#define IT8620E_DEVID 0x8620
161#define IT8622E_DEVID 0x8622
162#define IT8623E_DEVID 0x8623
163#define IT8628E_DEVID 0x8628
164#define IT87_ACT_REG 0x30
165#define IT87_BASE_REG 0x60
166
167/* Logical device 7 registers (IT8712F and later) */
168#define IT87_SIO_GPIO1_REG 0x25
169#define IT87_SIO_GPIO2_REG 0x26
170#define IT87_SIO_GPIO3_REG 0x27
171#define IT87_SIO_GPIO4_REG 0x28
172#define IT87_SIO_GPIO5_REG 0x29
173#define IT87_SIO_PINX1_REG 0x2a /* Pin selection */
174#define IT87_SIO_PINX2_REG 0x2c /* Pin selection */
175#define IT87_SIO_SPI_REG 0xef /* SPI function pin select */
176#define IT87_SIO_VID_REG 0xfc /* VID value */
177#define IT87_SIO_BEEP_PIN_REG 0xf6 /* Beep pin mapping */
178
179/* Update battery voltage after every reading if true */
180static bool update_vbat;
181
182/* Not all BIOSes properly configure the PWM registers */
183static bool fix_pwm_polarity;
184
185/* Many IT87 constants specified below */
186
187/* Length of ISA address segment */
188#define IT87_EXTENT 8
189
190/* Length of ISA address segment for Environmental Controller */
191#define IT87_EC_EXTENT 2
192
193/* Offset of EC registers from ISA base address */
194#define IT87_EC_OFFSET 5
195
196/* Where are the ISA address/data registers relative to the EC base address */
197#define IT87_ADDR_REG_OFFSET 0
198#define IT87_DATA_REG_OFFSET 1
199
200/*----- The IT87 registers -----*/
201
202#define IT87_REG_CONFIG 0x00
203
204#define IT87_REG_ALARM1 0x01
205#define IT87_REG_ALARM2 0x02
206#define IT87_REG_ALARM3 0x03
207
208/*
209 * The IT8718F and IT8720F have the VID value in a different register, in
210 * Super-I/O configuration space.
211 */
212#define IT87_REG_VID 0x0a
213/*
214 * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
215 * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
216 * mode.
217 */
218#define IT87_REG_FAN_DIV 0x0b
219#define IT87_REG_FAN_16BIT 0x0c
220
221/*
222 * Monitors:
223 * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12)
224 * - up to 6 temp (1 to 6)
225 * - up to 6 fan (1 to 6)
226 */
227
228static const u8 IT87_REG_FAN[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
229static const u8 IT87_REG_FAN_MIN[] = { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
230static const u8 IT87_REG_FANX[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
231static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
232static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59 };
233
234#define IT87_REG_FAN_MAIN_CTRL 0x13
235#define IT87_REG_FAN_CTL 0x14
236static const u8 IT87_REG_PWM[] = { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
237static const u8 IT87_REG_PWM_DUTY[] = { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
238
239static const u8 IT87_REG_VIN[] = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
240 0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
241
242#define IT87_REG_TEMP(nr) (0x29 + (nr))
243
244#define IT87_REG_VIN_MAX(nr) (0x30 + (nr) * 2)
245#define IT87_REG_VIN_MIN(nr) (0x31 + (nr) * 2)
246#define IT87_REG_TEMP_HIGH(nr) (0x40 + (nr) * 2)
247#define IT87_REG_TEMP_LOW(nr) (0x41 + (nr) * 2)
248
249#define IT87_REG_VIN_ENABLE 0x50
250#define IT87_REG_TEMP_ENABLE 0x51
251#define IT87_REG_TEMP_EXTRA 0x55
252#define IT87_REG_BEEP_ENABLE 0x5c
253
254#define IT87_REG_CHIPID 0x58
255
256static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 };
257
258#define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i))
259#define IT87_REG_AUTO_PWM(nr, i) (IT87_REG_AUTO_BASE[nr] + 5 + (i))
260
261#define IT87_REG_TEMP456_ENABLE 0x77
262
263#define NUM_VIN ARRAY_SIZE(IT87_REG_VIN)
264#define NUM_VIN_LIMIT 8
265#define NUM_TEMP 6
266#define NUM_TEMP_OFFSET ARRAY_SIZE(IT87_REG_TEMP_OFFSET)
267#define NUM_TEMP_LIMIT 3
268#define NUM_FAN ARRAY_SIZE(IT87_REG_FAN)
269#define NUM_FAN_DIV 3
270#define NUM_PWM ARRAY_SIZE(IT87_REG_PWM)
271#define NUM_AUTO_PWM ARRAY_SIZE(IT87_REG_PWM)
272
273struct it87_devices {
274 const char *name;
275 const char * const suffix;
276 u32 features;
277 u8 peci_mask;
278 u8 old_peci_mask;
279};
280
281#define FEAT_12MV_ADC BIT(0)
282#define FEAT_NEWER_AUTOPWM BIT(1)
283#define FEAT_OLD_AUTOPWM BIT(2)
284#define FEAT_16BIT_FANS BIT(3)
285#define FEAT_TEMP_OFFSET BIT(4)
286#define FEAT_TEMP_PECI BIT(5)
287#define FEAT_TEMP_OLD_PECI BIT(6)
288#define FEAT_FAN16_CONFIG BIT(7) /* Need to enable 16-bit fans */
289#define FEAT_FIVE_FANS BIT(8) /* Supports five fans */
290#define FEAT_VID BIT(9) /* Set if chip supports VID */
291#define FEAT_IN7_INTERNAL BIT(10) /* Set if in7 is internal */
292#define FEAT_SIX_FANS BIT(11) /* Supports six fans */
293#define FEAT_10_9MV_ADC BIT(12)
294#define FEAT_AVCC3 BIT(13) /* Chip supports in9/AVCC3 */
295#define FEAT_FIVE_PWM BIT(14) /* Chip supports 5 pwm chn */
296#define FEAT_SIX_PWM BIT(15) /* Chip supports 6 pwm chn */
297#define FEAT_PWM_FREQ2 BIT(16) /* Separate pwm freq 2 */
298#define FEAT_SIX_TEMP BIT(17) /* Up to 6 temp sensors */
299#define FEAT_VIN3_5V BIT(18) /* VIN3 connected to +5V */
300
301static const struct it87_devices it87_devices[] = {
302 [it87] = {
303 .name = "it87",
304 .suffix = "F",
305 .features = FEAT_OLD_AUTOPWM, /* may need to overwrite */
306 },
307 [it8712] = {
308 .name = "it8712",
309 .suffix = "F",
310 .features = FEAT_OLD_AUTOPWM | FEAT_VID,
311 /* may need to overwrite */
312 },
313 [it8716] = {
314 .name = "it8716",
315 .suffix = "F",
316 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
317 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2,
318 },
319 [it8718] = {
320 .name = "it8718",
321 .suffix = "F",
322 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
323 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
324 | FEAT_PWM_FREQ2,
325 .old_peci_mask = 0x4,
326 },
327 [it8720] = {
328 .name = "it8720",
329 .suffix = "F",
330 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
331 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
332 | FEAT_PWM_FREQ2,
333 .old_peci_mask = 0x4,
334 },
335 [it8721] = {
336 .name = "it8721",
337 .suffix = "F",
338 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
339 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
340 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
341 | FEAT_PWM_FREQ2,
342 .peci_mask = 0x05,
343 .old_peci_mask = 0x02, /* Actually reports PCH */
344 },
345 [it8728] = {
346 .name = "it8728",
347 .suffix = "F",
348 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
349 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS
350 | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2,
351 .peci_mask = 0x07,
352 },
353 [it8732] = {
354 .name = "it8732",
355 .suffix = "F",
356 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
357 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
358 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL,
359 .peci_mask = 0x07,
360 .old_peci_mask = 0x02, /* Actually reports PCH */
361 },
362 [it8771] = {
363 .name = "it8771",
364 .suffix = "E",
365 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
366 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
367 | FEAT_PWM_FREQ2,
368 /* PECI: guesswork */
369 /* 12mV ADC (OHM) */
370 /* 16 bit fans (OHM) */
371 /* three fans, always 16 bit (guesswork) */
372 .peci_mask = 0x07,
373 },
374 [it8772] = {
375 .name = "it8772",
376 .suffix = "E",
377 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
378 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
379 | FEAT_PWM_FREQ2,
380 /* PECI (coreboot) */
381 /* 12mV ADC (HWSensors4, OHM) */
382 /* 16 bit fans (HWSensors4, OHM) */
383 /* three fans, always 16 bit (datasheet) */
384 .peci_mask = 0x07,
385 },
386 [it8781] = {
387 .name = "it8781",
388 .suffix = "F",
389 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
390 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
391 .old_peci_mask = 0x4,
392 },
393 [it8782] = {
394 .name = "it8782",
395 .suffix = "F",
396 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
397 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
398 .old_peci_mask = 0x4,
399 },
400 [it8783] = {
401 .name = "it8783",
402 .suffix = "E/F",
403 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
404 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
405 .old_peci_mask = 0x4,
406 },
407 [it8786] = {
408 .name = "it8786",
409 .suffix = "E",
410 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
411 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
412 | FEAT_PWM_FREQ2,
413 .peci_mask = 0x07,
414 },
415 [it8790] = {
416 .name = "it8790",
417 .suffix = "E",
418 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
419 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
420 | FEAT_PWM_FREQ2,
421 .peci_mask = 0x07,
422 },
423 [it8792] = {
424 .name = "it8792",
425 .suffix = "E",
426 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
427 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
428 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL,
429 .peci_mask = 0x07,
430 .old_peci_mask = 0x02, /* Actually reports PCH */
431 },
432 [it8603] = {
433 .name = "it8603",
434 .suffix = "E",
435 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
436 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
437 | FEAT_AVCC3 | FEAT_PWM_FREQ2,
438 .peci_mask = 0x07,
439 },
440 [it8620] = {
441 .name = "it8620",
442 .suffix = "E",
443 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
444 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
445 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
446 | FEAT_SIX_TEMP | FEAT_VIN3_5V,
447 .peci_mask = 0x07,
448 },
449 [it8622] = {
450 .name = "it8622",
451 .suffix = "E",
452 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
453 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS
454 | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
455 | FEAT_AVCC3 | FEAT_VIN3_5V,
456 .peci_mask = 0x07,
457 },
458 [it8628] = {
459 .name = "it8628",
460 .suffix = "E",
461 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
462 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
463 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
464 | FEAT_SIX_TEMP | FEAT_VIN3_5V,
465 .peci_mask = 0x07,
466 },
467};
468
469#define has_16bit_fans(data) ((data)->features & FEAT_16BIT_FANS)
470#define has_12mv_adc(data) ((data)->features & FEAT_12MV_ADC)
471#define has_10_9mv_adc(data) ((data)->features & FEAT_10_9MV_ADC)
472#define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
473#define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM)
474#define has_temp_offset(data) ((data)->features & FEAT_TEMP_OFFSET)
475#define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
476 ((data)->peci_mask & BIT(nr)))
477#define has_temp_old_peci(data, nr) \
478 (((data)->features & FEAT_TEMP_OLD_PECI) && \
479 ((data)->old_peci_mask & BIT(nr)))
480#define has_fan16_config(data) ((data)->features & FEAT_FAN16_CONFIG)
481#define has_five_fans(data) ((data)->features & (FEAT_FIVE_FANS | \
482 FEAT_SIX_FANS))
483#define has_vid(data) ((data)->features & FEAT_VID)
484#define has_in7_internal(data) ((data)->features & FEAT_IN7_INTERNAL)
485#define has_six_fans(data) ((data)->features & FEAT_SIX_FANS)
486#define has_avcc3(data) ((data)->features & FEAT_AVCC3)
487#define has_five_pwm(data) ((data)->features & (FEAT_FIVE_PWM \
488 | FEAT_SIX_PWM))
489#define has_six_pwm(data) ((data)->features & FEAT_SIX_PWM)
490#define has_pwm_freq2(data) ((data)->features & FEAT_PWM_FREQ2)
491#define has_six_temp(data) ((data)->features & FEAT_SIX_TEMP)
492#define has_vin3_5v(data) ((data)->features & FEAT_VIN3_5V)
493
494struct it87_sio_data {
495 int sioaddr;
496 enum chips type;
497 /* Values read from Super-I/O config space */
498 u8 revision;
499 u8 vid_value;
500 u8 beep_pin;
501 u8 internal; /* Internal sensors can be labeled */
502 bool need_in7_reroute;
503 /* Features skipped based on config or DMI */
504 u16 skip_in;
505 u8 skip_vid;
506 u8 skip_fan;
507 u8 skip_pwm;
508 u8 skip_temp;
509};
510
511/*
512 * For each registered chip, we need to keep some data in memory.
513 * The structure is dynamically allocated.
514 */
515struct it87_data {
516 const struct attribute_group *groups[7];
517 int sioaddr;
518 enum chips type;
519 u32 features;
520 u8 peci_mask;
521 u8 old_peci_mask;
522
523 unsigned short addr;
524 const char *name;
525 struct mutex update_lock;
526 bool valid; /* true if following fields are valid */
527 unsigned long last_updated; /* In jiffies */
528
529 u16 in_scaled; /* Internal voltage sensors are scaled */
530 u16 in_internal; /* Bitfield, internal sensors (for labels) */
531 u16 has_in; /* Bitfield, voltage sensors enabled */
532 u8 in[NUM_VIN][3]; /* [nr][0]=in, [1]=min, [2]=max */
533 bool need_in7_reroute;
534 u8 has_fan; /* Bitfield, fans enabled */
535 u16 fan[NUM_FAN][2]; /* Register values, [nr][0]=fan, [1]=min */
536 u8 has_temp; /* Bitfield, temp sensors enabled */
537 s8 temp[NUM_TEMP][4]; /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
538 u8 sensor; /* Register value (IT87_REG_TEMP_ENABLE) */
539 u8 extra; /* Register value (IT87_REG_TEMP_EXTRA) */
540 u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
541 bool has_vid; /* True if VID supported */
542 u8 vid; /* Register encoding, combined */
543 u8 vrm;
544 u32 alarms; /* Register encoding, combined */
545 bool has_beep; /* true if beep supported */
546 u8 beeps; /* Register encoding */
547 u8 fan_main_ctrl; /* Register value */
548 u8 fan_ctl; /* Register value */
549
550 /*
551 * The following 3 arrays correspond to the same registers up to
552 * the IT8720F. The meaning of bits 6-0 depends on the value of bit
553 * 7, and we want to preserve settings on mode changes, so we have
554 * to track all values separately.
555 * Starting with the IT8721F, the manual PWM duty cycles are stored
556 * in separate registers (8-bit values), so the separate tracking
557 * is no longer needed, but it is still done to keep the driver
558 * simple.
559 */
560 u8 has_pwm; /* Bitfield, pwm control enabled */
561 u8 pwm_ctrl[NUM_PWM]; /* Register value */
562 u8 pwm_duty[NUM_PWM]; /* Manual PWM value set by user */
563 u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */
564
565 /* Automatic fan speed control registers */
566 u8 auto_pwm[NUM_AUTO_PWM][4]; /* [nr][3] is hard-coded */
567 s8 auto_temp[NUM_AUTO_PWM][5]; /* [nr][0] is point1_temp_hyst */
568};
569
570/* Board specific settings from DMI matching */
571struct it87_dmi_data {
572 u8 skip_pwm; /* pwm channels to skip for this board */
573};
574
575/* Global for results from DMI matching, if needed */
576static struct it87_dmi_data *dmi_data;
577
578static int adc_lsb(const struct it87_data *data, int nr)
579{
580 int lsb;
581
582 if (has_12mv_adc(data))
583 lsb = 120;
584 else if (has_10_9mv_adc(data))
585 lsb = 109;
586 else
587 lsb = 160;
588 if (data->in_scaled & BIT(nr))
589 lsb <<= 1;
590 return lsb;
591}
592
593static u8 in_to_reg(const struct it87_data *data, int nr, long val)
594{
595 val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr));
596 return clamp_val(val, 0, 255);
597}
598
599static int in_from_reg(const struct it87_data *data, int nr, int val)
600{
601 return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10);
602}
603
604static inline u8 FAN_TO_REG(long rpm, int div)
605{
606 if (rpm == 0)
607 return 255;
608 rpm = clamp_val(rpm, 1, 1000000);
609 return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
610}
611
612static inline u16 FAN16_TO_REG(long rpm)
613{
614 if (rpm == 0)
615 return 0xffff;
616 return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
617}
618
619#define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
620 1350000 / ((val) * (div)))
621/* The divider is fixed to 2 in 16-bit mode */
622#define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
623 1350000 / ((val) * 2))
624
625#define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
626 ((val) + 500) / 1000), -128, 127))
627#define TEMP_FROM_REG(val) ((val) * 1000)
628
629static u8 pwm_to_reg(const struct it87_data *data, long val)
630{
631 if (has_newer_autopwm(data))
632 return val;
633 else
634 return val >> 1;
635}
636
637static int pwm_from_reg(const struct it87_data *data, u8 reg)
638{
639 if (has_newer_autopwm(data))
640 return reg;
641 else
642 return (reg & 0x7f) << 1;
643}
644
645static int DIV_TO_REG(int val)
646{
647 int answer = 0;
648
649 while (answer < 7 && (val >>= 1))
650 answer++;
651 return answer;
652}
653
654#define DIV_FROM_REG(val) BIT(val)
655
656/*
657 * PWM base frequencies. The frequency has to be divided by either 128 or 256,
658 * depending on the chip type, to calculate the actual PWM frequency.
659 *
660 * Some of the chip datasheets suggest a base frequency of 51 kHz instead
661 * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
662 * of 200 Hz. Sometimes both PWM frequency select registers are affected,
663 * sometimes just one. It is unknown if this is a datasheet error or real,
664 * so this is ignored for now.
665 */
666static const unsigned int pwm_freq[8] = {
667 48000000,
668 24000000,
669 12000000,
670 8000000,
671 6000000,
672 3000000,
673 1500000,
674 750000,
675};
676
677/*
678 * Must be called with data->update_lock held, except during initialization.
679 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
680 * would slow down the IT87 access and should not be necessary.
681 */
682static int it87_read_value(struct it87_data *data, u8 reg)
683{
684 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
685 return inb_p(data->addr + IT87_DATA_REG_OFFSET);
686}
687
688/*
689 * Must be called with data->update_lock held, except during initialization.
690 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
691 * would slow down the IT87 access and should not be necessary.
692 */
693static void it87_write_value(struct it87_data *data, u8 reg, u8 value)
694{
695 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
696 outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
697}
698
699static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
700{
701 data->pwm_ctrl[nr] = it87_read_value(data, IT87_REG_PWM[nr]);
702 if (has_newer_autopwm(data)) {
703 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
704 data->pwm_duty[nr] = it87_read_value(data,
705 IT87_REG_PWM_DUTY[nr]);
706 } else {
707 if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */
708 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
709 else /* Manual mode */
710 data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f;
711 }
712
713 if (has_old_autopwm(data)) {
714 int i;
715
716 for (i = 0; i < 5 ; i++)
717 data->auto_temp[nr][i] = it87_read_value(data,
718 IT87_REG_AUTO_TEMP(nr, i));
719 for (i = 0; i < 3 ; i++)
720 data->auto_pwm[nr][i] = it87_read_value(data,
721 IT87_REG_AUTO_PWM(nr, i));
722 } else if (has_newer_autopwm(data)) {
723 int i;
724
725 /*
726 * 0: temperature hysteresis (base + 5)
727 * 1: fan off temperature (base + 0)
728 * 2: fan start temperature (base + 1)
729 * 3: fan max temperature (base + 2)
730 */
731 data->auto_temp[nr][0] =
732 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 5));
733
734 for (i = 0; i < 3 ; i++)
735 data->auto_temp[nr][i + 1] =
736 it87_read_value(data,
737 IT87_REG_AUTO_TEMP(nr, i));
738 /*
739 * 0: start pwm value (base + 3)
740 * 1: pwm slope (base + 4, 1/8th pwm)
741 */
742 data->auto_pwm[nr][0] =
743 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 3));
744 data->auto_pwm[nr][1] =
745 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 4));
746 }
747}
748
749static struct it87_data *it87_update_device(struct device *dev)
750{
751 struct it87_data *data = dev_get_drvdata(dev);
752 int i;
753
754 mutex_lock(&data->update_lock);
755
756 if (time_after(jiffies, data->last_updated + HZ + HZ / 2) ||
757 !data->valid) {
758 if (update_vbat) {
759 /*
760 * Cleared after each update, so reenable. Value
761 * returned by this read will be previous value
762 */
763 it87_write_value(data, IT87_REG_CONFIG,
764 it87_read_value(data, IT87_REG_CONFIG) | 0x40);
765 }
766 for (i = 0; i < NUM_VIN; i++) {
767 if (!(data->has_in & BIT(i)))
768 continue;
769
770 data->in[i][0] =
771 it87_read_value(data, IT87_REG_VIN[i]);
772
773 /* VBAT and AVCC don't have limit registers */
774 if (i >= NUM_VIN_LIMIT)
775 continue;
776
777 data->in[i][1] =
778 it87_read_value(data, IT87_REG_VIN_MIN(i));
779 data->in[i][2] =
780 it87_read_value(data, IT87_REG_VIN_MAX(i));
781 }
782
783 for (i = 0; i < NUM_FAN; i++) {
784 /* Skip disabled fans */
785 if (!(data->has_fan & BIT(i)))
786 continue;
787
788 data->fan[i][1] =
789 it87_read_value(data, IT87_REG_FAN_MIN[i]);
790 data->fan[i][0] = it87_read_value(data,
791 IT87_REG_FAN[i]);
792 /* Add high byte if in 16-bit mode */
793 if (has_16bit_fans(data)) {
794 data->fan[i][0] |= it87_read_value(data,
795 IT87_REG_FANX[i]) << 8;
796 data->fan[i][1] |= it87_read_value(data,
797 IT87_REG_FANX_MIN[i]) << 8;
798 }
799 }
800 for (i = 0; i < NUM_TEMP; i++) {
801 if (!(data->has_temp & BIT(i)))
802 continue;
803 data->temp[i][0] =
804 it87_read_value(data, IT87_REG_TEMP(i));
805
806 if (has_temp_offset(data) && i < NUM_TEMP_OFFSET)
807 data->temp[i][3] =
808 it87_read_value(data,
809 IT87_REG_TEMP_OFFSET[i]);
810
811 if (i >= NUM_TEMP_LIMIT)
812 continue;
813
814 data->temp[i][1] =
815 it87_read_value(data, IT87_REG_TEMP_LOW(i));
816 data->temp[i][2] =
817 it87_read_value(data, IT87_REG_TEMP_HIGH(i));
818 }
819
820 /* Newer chips don't have clock dividers */
821 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
822 i = it87_read_value(data, IT87_REG_FAN_DIV);
823 data->fan_div[0] = i & 0x07;
824 data->fan_div[1] = (i >> 3) & 0x07;
825 data->fan_div[2] = (i & 0x40) ? 3 : 1;
826 }
827
828 data->alarms =
829 it87_read_value(data, IT87_REG_ALARM1) |
830 (it87_read_value(data, IT87_REG_ALARM2) << 8) |
831 (it87_read_value(data, IT87_REG_ALARM3) << 16);
832 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
833
834 data->fan_main_ctrl = it87_read_value(data,
835 IT87_REG_FAN_MAIN_CTRL);
836 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL);
837 for (i = 0; i < NUM_PWM; i++) {
838 if (!(data->has_pwm & BIT(i)))
839 continue;
840 it87_update_pwm_ctrl(data, i);
841 }
842
843 data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE);
844 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
845 /*
846 * The IT8705F does not have VID capability.
847 * The IT8718F and later don't use IT87_REG_VID for the
848 * same purpose.
849 */
850 if (data->type == it8712 || data->type == it8716) {
851 data->vid = it87_read_value(data, IT87_REG_VID);
852 /*
853 * The older IT8712F revisions had only 5 VID pins,
854 * but we assume it is always safe to read 6 bits.
855 */
856 data->vid &= 0x3f;
857 }
858 data->last_updated = jiffies;
859 data->valid = true;
860 }
861
862 mutex_unlock(&data->update_lock);
863
864 return data;
865}
866
867static ssize_t show_in(struct device *dev, struct device_attribute *attr,
868 char *buf)
869{
870 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
871 struct it87_data *data = it87_update_device(dev);
872 int index = sattr->index;
873 int nr = sattr->nr;
874
875 return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
876}
877
878static ssize_t set_in(struct device *dev, struct device_attribute *attr,
879 const char *buf, size_t count)
880{
881 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
882 struct it87_data *data = dev_get_drvdata(dev);
883 int index = sattr->index;
884 int nr = sattr->nr;
885 unsigned long val;
886
887 if (kstrtoul(buf, 10, &val) < 0)
888 return -EINVAL;
889
890 mutex_lock(&data->update_lock);
891 data->in[nr][index] = in_to_reg(data, nr, val);
892 it87_write_value(data,
893 index == 1 ? IT87_REG_VIN_MIN(nr)
894 : IT87_REG_VIN_MAX(nr),
895 data->in[nr][index]);
896 mutex_unlock(&data->update_lock);
897 return count;
898}
899
900static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0);
901static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
902 0, 1);
903static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
904 0, 2);
905
906static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0);
907static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
908 1, 1);
909static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
910 1, 2);
911
912static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0);
913static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
914 2, 1);
915static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
916 2, 2);
917
918static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0);
919static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
920 3, 1);
921static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
922 3, 2);
923
924static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0);
925static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
926 4, 1);
927static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
928 4, 2);
929
930static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0);
931static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
932 5, 1);
933static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
934 5, 2);
935
936static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0);
937static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in,
938 6, 1);
939static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in,
940 6, 2);
941
942static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0);
943static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in,
944 7, 1);
945static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in,
946 7, 2);
947
948static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0);
949static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0);
950static SENSOR_DEVICE_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 10, 0);
951static SENSOR_DEVICE_ATTR_2(in11_input, S_IRUGO, show_in, NULL, 11, 0);
952static SENSOR_DEVICE_ATTR_2(in12_input, S_IRUGO, show_in, NULL, 12, 0);
953
954/* Up to 6 temperatures */
955static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
956 char *buf)
957{
958 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
959 int nr = sattr->nr;
960 int index = sattr->index;
961 struct it87_data *data = it87_update_device(dev);
962
963 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
964}
965
966static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
967 const char *buf, size_t count)
968{
969 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
970 int nr = sattr->nr;
971 int index = sattr->index;
972 struct it87_data *data = dev_get_drvdata(dev);
973 long val;
974 u8 reg, regval;
975
976 if (kstrtol(buf, 10, &val) < 0)
977 return -EINVAL;
978
979 mutex_lock(&data->update_lock);
980
981 switch (index) {
982 default:
983 case 1:
984 reg = IT87_REG_TEMP_LOW(nr);
985 break;
986 case 2:
987 reg = IT87_REG_TEMP_HIGH(nr);
988 break;
989 case 3:
990 regval = it87_read_value(data, IT87_REG_BEEP_ENABLE);
991 if (!(regval & 0x80)) {
992 regval |= 0x80;
993 it87_write_value(data, IT87_REG_BEEP_ENABLE, regval);
994 }
995 data->valid = false;
996 reg = IT87_REG_TEMP_OFFSET[nr];
997 break;
998 }
999
1000 data->temp[nr][index] = TEMP_TO_REG(val);
1001 it87_write_value(data, reg, data->temp[nr][index]);
1002 mutex_unlock(&data->update_lock);
1003 return count;
1004}
1005
1006static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0);
1007static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1008 0, 1);
1009static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1010 0, 2);
1011static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp,
1012 set_temp, 0, 3);
1013static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0);
1014static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1015 1, 1);
1016static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1017 1, 2);
1018static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp,
1019 set_temp, 1, 3);
1020static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0);
1021static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1022 2, 1);
1023static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1024 2, 2);
1025static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
1026 set_temp, 2, 3);
1027static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0);
1028static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0);
1029static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0);
1030
1031static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
1032 char *buf)
1033{
1034 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1035 int nr = sensor_attr->index;
1036 struct it87_data *data = it87_update_device(dev);
1037 u8 reg = data->sensor; /* In case value is updated while used */
1038 u8 extra = data->extra;
1039
1040 if ((has_temp_peci(data, nr) && (reg >> 6 == nr + 1)) ||
1041 (has_temp_old_peci(data, nr) && (extra & 0x80)))
1042 return sprintf(buf, "6\n"); /* Intel PECI */
1043 if (reg & (1 << nr))
1044 return sprintf(buf, "3\n"); /* thermal diode */
1045 if (reg & (8 << nr))
1046 return sprintf(buf, "4\n"); /* thermistor */
1047 return sprintf(buf, "0\n"); /* disabled */
1048}
1049
1050static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
1051 const char *buf, size_t count)
1052{
1053 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1054 int nr = sensor_attr->index;
1055
1056 struct it87_data *data = dev_get_drvdata(dev);
1057 long val;
1058 u8 reg, extra;
1059
1060 if (kstrtol(buf, 10, &val) < 0)
1061 return -EINVAL;
1062
1063 reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1064 reg &= ~(1 << nr);
1065 reg &= ~(8 << nr);
1066 if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
1067 reg &= 0x3f;
1068 extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1069 if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
1070 extra &= 0x7f;
1071 if (val == 2) { /* backwards compatibility */
1072 dev_warn(dev,
1073 "Sensor type 2 is deprecated, please use 4 instead\n");
1074 val = 4;
1075 }
1076 /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1077 if (val == 3)
1078 reg |= 1 << nr;
1079 else if (val == 4)
1080 reg |= 8 << nr;
1081 else if (has_temp_peci(data, nr) && val == 6)
1082 reg |= (nr + 1) << 6;
1083 else if (has_temp_old_peci(data, nr) && val == 6)
1084 extra |= 0x80;
1085 else if (val != 0)
1086 return -EINVAL;
1087
1088 mutex_lock(&data->update_lock);
1089 data->sensor = reg;
1090 data->extra = extra;
1091 it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor);
1092 if (has_temp_old_peci(data, nr))
1093 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1094 data->valid = false; /* Force cache refresh */
1095 mutex_unlock(&data->update_lock);
1096 return count;
1097}
1098
1099static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type,
1100 set_temp_type, 0);
1101static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type,
1102 set_temp_type, 1);
1103static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
1104 set_temp_type, 2);
1105
1106/* 6 Fans */
1107
1108static int pwm_mode(const struct it87_data *data, int nr)
1109{
1110 if (data->type != it8603 && nr < 3 && !(data->fan_main_ctrl & BIT(nr)))
1111 return 0; /* Full speed */
1112 if (data->pwm_ctrl[nr] & 0x80)
1113 return 2; /* Automatic mode */
1114 if ((data->type == it8603 || nr >= 3) &&
1115 data->pwm_duty[nr] == pwm_to_reg(data, 0xff))
1116 return 0; /* Full speed */
1117
1118 return 1; /* Manual mode */
1119}
1120
1121static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
1122 char *buf)
1123{
1124 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1125 int nr = sattr->nr;
1126 int index = sattr->index;
1127 int speed;
1128 struct it87_data *data = it87_update_device(dev);
1129
1130 speed = has_16bit_fans(data) ?
1131 FAN16_FROM_REG(data->fan[nr][index]) :
1132 FAN_FROM_REG(data->fan[nr][index],
1133 DIV_FROM_REG(data->fan_div[nr]));
1134 return sprintf(buf, "%d\n", speed);
1135}
1136
1137static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
1138 char *buf)
1139{
1140 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1141 struct it87_data *data = it87_update_device(dev);
1142 int nr = sensor_attr->index;
1143
1144 return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr]));
1145}
1146
1147static ssize_t show_pwm_enable(struct device *dev,
1148 struct device_attribute *attr, char *buf)
1149{
1150 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1151 struct it87_data *data = it87_update_device(dev);
1152 int nr = sensor_attr->index;
1153
1154 return sprintf(buf, "%d\n", pwm_mode(data, nr));
1155}
1156
1157static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1158 char *buf)
1159{
1160 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1161 struct it87_data *data = it87_update_device(dev);
1162 int nr = sensor_attr->index;
1163
1164 return sprintf(buf, "%d\n",
1165 pwm_from_reg(data, data->pwm_duty[nr]));
1166}
1167
1168static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
1169 char *buf)
1170{
1171 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1172 struct it87_data *data = it87_update_device(dev);
1173 int nr = sensor_attr->index;
1174 unsigned int freq;
1175 int index;
1176
1177 if (has_pwm_freq2(data) && nr == 1)
1178 index = (data->extra >> 4) & 0x07;
1179 else
1180 index = (data->fan_ctl >> 4) & 0x07;
1181
1182 freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128);
1183
1184 return sprintf(buf, "%u\n", freq);
1185}
1186
1187static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1188 const char *buf, size_t count)
1189{
1190 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1191 int nr = sattr->nr;
1192 int index = sattr->index;
1193
1194 struct it87_data *data = dev_get_drvdata(dev);
1195 long val;
1196 u8 reg;
1197
1198 if (kstrtol(buf, 10, &val) < 0)
1199 return -EINVAL;
1200
1201 mutex_lock(&data->update_lock);
1202
1203 if (has_16bit_fans(data)) {
1204 data->fan[nr][index] = FAN16_TO_REG(val);
1205 it87_write_value(data, IT87_REG_FAN_MIN[nr],
1206 data->fan[nr][index] & 0xff);
1207 it87_write_value(data, IT87_REG_FANX_MIN[nr],
1208 data->fan[nr][index] >> 8);
1209 } else {
1210 reg = it87_read_value(data, IT87_REG_FAN_DIV);
1211 switch (nr) {
1212 case 0:
1213 data->fan_div[nr] = reg & 0x07;
1214 break;
1215 case 1:
1216 data->fan_div[nr] = (reg >> 3) & 0x07;
1217 break;
1218 case 2:
1219 data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
1220 break;
1221 }
1222 data->fan[nr][index] =
1223 FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
1224 it87_write_value(data, IT87_REG_FAN_MIN[nr],
1225 data->fan[nr][index]);
1226 }
1227
1228 mutex_unlock(&data->update_lock);
1229 return count;
1230}
1231
1232static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
1233 const char *buf, size_t count)
1234{
1235 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1236 struct it87_data *data = dev_get_drvdata(dev);
1237 int nr = sensor_attr->index;
1238 unsigned long val;
1239 int min;
1240 u8 old;
1241
1242 if (kstrtoul(buf, 10, &val) < 0)
1243 return -EINVAL;
1244
1245 mutex_lock(&data->update_lock);
1246 old = it87_read_value(data, IT87_REG_FAN_DIV);
1247
1248 /* Save fan min limit */
1249 min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1250
1251 switch (nr) {
1252 case 0:
1253 case 1:
1254 data->fan_div[nr] = DIV_TO_REG(val);
1255 break;
1256 case 2:
1257 if (val < 8)
1258 data->fan_div[nr] = 1;
1259 else
1260 data->fan_div[nr] = 3;
1261 }
1262 val = old & 0x80;
1263 val |= (data->fan_div[0] & 0x07);
1264 val |= (data->fan_div[1] & 0x07) << 3;
1265 if (data->fan_div[2] == 3)
1266 val |= 0x1 << 6;
1267 it87_write_value(data, IT87_REG_FAN_DIV, val);
1268
1269 /* Restore fan min limit */
1270 data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
1271 it87_write_value(data, IT87_REG_FAN_MIN[nr], data->fan[nr][1]);
1272
1273 mutex_unlock(&data->update_lock);
1274 return count;
1275}
1276
1277/* Returns 0 if OK, -EINVAL otherwise */
1278static int check_trip_points(struct device *dev, int nr)
1279{
1280 const struct it87_data *data = dev_get_drvdata(dev);
1281 int i, err = 0;
1282
1283 if (has_old_autopwm(data)) {
1284 for (i = 0; i < 3; i++) {
1285 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1286 err = -EINVAL;
1287 }
1288 for (i = 0; i < 2; i++) {
1289 if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
1290 err = -EINVAL;
1291 }
1292 } else if (has_newer_autopwm(data)) {
1293 for (i = 1; i < 3; i++) {
1294 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1295 err = -EINVAL;
1296 }
1297 }
1298
1299 if (err) {
1300 dev_err(dev,
1301 "Inconsistent trip points, not switching to automatic mode\n");
1302 dev_err(dev, "Adjust the trip points and try again\n");
1303 }
1304 return err;
1305}
1306
1307static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr,
1308 const char *buf, size_t count)
1309{
1310 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1311 struct it87_data *data = dev_get_drvdata(dev);
1312 int nr = sensor_attr->index;
1313 long val;
1314
1315 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
1316 return -EINVAL;
1317
1318 /* Check trip points before switching to automatic mode */
1319 if (val == 2) {
1320 if (check_trip_points(dev, nr) < 0)
1321 return -EINVAL;
1322 }
1323
1324 mutex_lock(&data->update_lock);
1325
1326 if (val == 0) {
1327 if (nr < 3 && data->type != it8603) {
1328 int tmp;
1329 /* make sure the fan is on when in on/off mode */
1330 tmp = it87_read_value(data, IT87_REG_FAN_CTL);
1331 it87_write_value(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
1332 /* set on/off mode */
1333 data->fan_main_ctrl &= ~BIT(nr);
1334 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1335 data->fan_main_ctrl);
1336 } else {
1337 u8 ctrl;
1338
1339 /* No on/off mode, set maximum pwm value */
1340 data->pwm_duty[nr] = pwm_to_reg(data, 0xff);
1341 it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1342 data->pwm_duty[nr]);
1343 /* and set manual mode */
1344 if (has_newer_autopwm(data)) {
1345 ctrl = (data->pwm_ctrl[nr] & 0x7c) |
1346 data->pwm_temp_map[nr];
1347 } else {
1348 ctrl = data->pwm_duty[nr];
1349 }
1350 data->pwm_ctrl[nr] = ctrl;
1351 it87_write_value(data, IT87_REG_PWM[nr], ctrl);
1352 }
1353 } else {
1354 u8 ctrl;
1355
1356 if (has_newer_autopwm(data)) {
1357 ctrl = (data->pwm_ctrl[nr] & 0x7c) |
1358 data->pwm_temp_map[nr];
1359 if (val != 1)
1360 ctrl |= 0x80;
1361 } else {
1362 ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80);
1363 }
1364 data->pwm_ctrl[nr] = ctrl;
1365 it87_write_value(data, IT87_REG_PWM[nr], ctrl);
1366
1367 if (data->type != it8603 && nr < 3) {
1368 /* set SmartGuardian mode */
1369 data->fan_main_ctrl |= BIT(nr);
1370 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1371 data->fan_main_ctrl);
1372 }
1373 }
1374
1375 mutex_unlock(&data->update_lock);
1376 return count;
1377}
1378
1379static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1380 const char *buf, size_t count)
1381{
1382 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1383 struct it87_data *data = dev_get_drvdata(dev);
1384 int nr = sensor_attr->index;
1385 long val;
1386
1387 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1388 return -EINVAL;
1389
1390 mutex_lock(&data->update_lock);
1391 it87_update_pwm_ctrl(data, nr);
1392 if (has_newer_autopwm(data)) {
1393 /*
1394 * If we are in automatic mode, the PWM duty cycle register
1395 * is read-only so we can't write the value.
1396 */
1397 if (data->pwm_ctrl[nr] & 0x80) {
1398 mutex_unlock(&data->update_lock);
1399 return -EBUSY;
1400 }
1401 data->pwm_duty[nr] = pwm_to_reg(data, val);
1402 it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1403 data->pwm_duty[nr]);
1404 } else {
1405 data->pwm_duty[nr] = pwm_to_reg(data, val);
1406 /*
1407 * If we are in manual mode, write the duty cycle immediately;
1408 * otherwise, just store it for later use.
1409 */
1410 if (!(data->pwm_ctrl[nr] & 0x80)) {
1411 data->pwm_ctrl[nr] = data->pwm_duty[nr];
1412 it87_write_value(data, IT87_REG_PWM[nr],
1413 data->pwm_ctrl[nr]);
1414 }
1415 }
1416 mutex_unlock(&data->update_lock);
1417 return count;
1418}
1419
1420static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr,
1421 const char *buf, size_t count)
1422{
1423 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1424 struct it87_data *data = dev_get_drvdata(dev);
1425 int nr = sensor_attr->index;
1426 unsigned long val;
1427 int i;
1428
1429 if (kstrtoul(buf, 10, &val) < 0)
1430 return -EINVAL;
1431
1432 val = clamp_val(val, 0, 1000000);
1433 val *= has_newer_autopwm(data) ? 256 : 128;
1434
1435 /* Search for the nearest available frequency */
1436 for (i = 0; i < 7; i++) {
1437 if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2)
1438 break;
1439 }
1440
1441 mutex_lock(&data->update_lock);
1442 if (nr == 0) {
1443 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f;
1444 data->fan_ctl |= i << 4;
1445 it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl);
1446 } else {
1447 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x8f;
1448 data->extra |= i << 4;
1449 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1450 }
1451 mutex_unlock(&data->update_lock);
1452
1453 return count;
1454}
1455
1456static ssize_t show_pwm_temp_map(struct device *dev,
1457 struct device_attribute *attr, char *buf)
1458{
1459 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1460 struct it87_data *data = it87_update_device(dev);
1461 int nr = sensor_attr->index;
1462 int map;
1463
1464 map = data->pwm_temp_map[nr];
1465 if (map >= 3)
1466 map = 0; /* Should never happen */
1467 if (nr >= 3) /* pwm channels 3..6 map to temp4..6 */
1468 map += 3;
1469
1470 return sprintf(buf, "%d\n", (int)BIT(map));
1471}
1472
1473static ssize_t set_pwm_temp_map(struct device *dev,
1474 struct device_attribute *attr, const char *buf,
1475 size_t count)
1476{
1477 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1478 struct it87_data *data = dev_get_drvdata(dev);
1479 int nr = sensor_attr->index;
1480 long val;
1481 u8 reg;
1482
1483 if (kstrtol(buf, 10, &val) < 0)
1484 return -EINVAL;
1485
1486 if (nr >= 3)
1487 val -= 3;
1488
1489 switch (val) {
1490 case BIT(0):
1491 reg = 0x00;
1492 break;
1493 case BIT(1):
1494 reg = 0x01;
1495 break;
1496 case BIT(2):
1497 reg = 0x02;
1498 break;
1499 default:
1500 return -EINVAL;
1501 }
1502
1503 mutex_lock(&data->update_lock);
1504 it87_update_pwm_ctrl(data, nr);
1505 data->pwm_temp_map[nr] = reg;
1506 /*
1507 * If we are in automatic mode, write the temp mapping immediately;
1508 * otherwise, just store it for later use.
1509 */
1510 if (data->pwm_ctrl[nr] & 0x80) {
1511 data->pwm_ctrl[nr] = (data->pwm_ctrl[nr] & 0xfc) |
1512 data->pwm_temp_map[nr];
1513 it87_write_value(data, IT87_REG_PWM[nr], data->pwm_ctrl[nr]);
1514 }
1515 mutex_unlock(&data->update_lock);
1516 return count;
1517}
1518
1519static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr,
1520 char *buf)
1521{
1522 struct it87_data *data = it87_update_device(dev);
1523 struct sensor_device_attribute_2 *sensor_attr =
1524 to_sensor_dev_attr_2(attr);
1525 int nr = sensor_attr->nr;
1526 int point = sensor_attr->index;
1527
1528 return sprintf(buf, "%d\n",
1529 pwm_from_reg(data, data->auto_pwm[nr][point]));
1530}
1531
1532static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr,
1533 const char *buf, size_t count)
1534{
1535 struct it87_data *data = dev_get_drvdata(dev);
1536 struct sensor_device_attribute_2 *sensor_attr =
1537 to_sensor_dev_attr_2(attr);
1538 int nr = sensor_attr->nr;
1539 int point = sensor_attr->index;
1540 int regaddr;
1541 long val;
1542
1543 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1544 return -EINVAL;
1545
1546 mutex_lock(&data->update_lock);
1547 data->auto_pwm[nr][point] = pwm_to_reg(data, val);
1548 if (has_newer_autopwm(data))
1549 regaddr = IT87_REG_AUTO_TEMP(nr, 3);
1550 else
1551 regaddr = IT87_REG_AUTO_PWM(nr, point);
1552 it87_write_value(data, regaddr, data->auto_pwm[nr][point]);
1553 mutex_unlock(&data->update_lock);
1554 return count;
1555}
1556
1557static ssize_t show_auto_pwm_slope(struct device *dev,
1558 struct device_attribute *attr, char *buf)
1559{
1560 struct it87_data *data = it87_update_device(dev);
1561 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1562 int nr = sensor_attr->index;
1563
1564 return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f);
1565}
1566
1567static ssize_t set_auto_pwm_slope(struct device *dev,
1568 struct device_attribute *attr,
1569 const char *buf, size_t count)
1570{
1571 struct it87_data *data = dev_get_drvdata(dev);
1572 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1573 int nr = sensor_attr->index;
1574 unsigned long val;
1575
1576 if (kstrtoul(buf, 10, &val) < 0 || val > 127)
1577 return -EINVAL;
1578
1579 mutex_lock(&data->update_lock);
1580 data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val;
1581 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 4),
1582 data->auto_pwm[nr][1]);
1583 mutex_unlock(&data->update_lock);
1584 return count;
1585}
1586
1587static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr,
1588 char *buf)
1589{
1590 struct it87_data *data = it87_update_device(dev);
1591 struct sensor_device_attribute_2 *sensor_attr =
1592 to_sensor_dev_attr_2(attr);
1593 int nr = sensor_attr->nr;
1594 int point = sensor_attr->index;
1595 int reg;
1596
1597 if (has_old_autopwm(data) || point)
1598 reg = data->auto_temp[nr][point];
1599 else
1600 reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f);
1601
1602 return sprintf(buf, "%d\n", TEMP_FROM_REG(reg));
1603}
1604
1605static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr,
1606 const char *buf, size_t count)
1607{
1608 struct it87_data *data = dev_get_drvdata(dev);
1609 struct sensor_device_attribute_2 *sensor_attr =
1610 to_sensor_dev_attr_2(attr);
1611 int nr = sensor_attr->nr;
1612 int point = sensor_attr->index;
1613 long val;
1614 int reg;
1615
1616 if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
1617 return -EINVAL;
1618
1619 mutex_lock(&data->update_lock);
1620 if (has_newer_autopwm(data) && !point) {
1621 reg = data->auto_temp[nr][1] - TEMP_TO_REG(val);
1622 reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0);
1623 data->auto_temp[nr][0] = reg;
1624 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 5), reg);
1625 } else {
1626 reg = TEMP_TO_REG(val);
1627 data->auto_temp[nr][point] = reg;
1628 if (has_newer_autopwm(data))
1629 point--;
1630 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point), reg);
1631 }
1632 mutex_unlock(&data->update_lock);
1633 return count;
1634}
1635
1636static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0);
1637static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1638 0, 1);
1639static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div,
1640 set_fan_div, 0);
1641
1642static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0);
1643static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1644 1, 1);
1645static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div,
1646 set_fan_div, 1);
1647
1648static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0);
1649static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1650 2, 1);
1651static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div,
1652 set_fan_div, 2);
1653
1654static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0);
1655static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1656 3, 1);
1657
1658static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0);
1659static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1660 4, 1);
1661
1662static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0);
1663static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1664 5, 1);
1665
1666static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
1667 show_pwm_enable, set_pwm_enable, 0);
1668static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0);
1669static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq,
1670 set_pwm_freq, 0);
1671static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO,
1672 show_pwm_temp_map, set_pwm_temp_map, 0);
1673static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR,
1674 show_auto_pwm, set_auto_pwm, 0, 0);
1675static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR,
1676 show_auto_pwm, set_auto_pwm, 0, 1);
1677static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR,
1678 show_auto_pwm, set_auto_pwm, 0, 2);
1679static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO,
1680 show_auto_pwm, NULL, 0, 3);
1681static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR,
1682 show_auto_temp, set_auto_temp, 0, 1);
1683static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1684 show_auto_temp, set_auto_temp, 0, 0);
1685static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR,
1686 show_auto_temp, set_auto_temp, 0, 2);
1687static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR,
1688 show_auto_temp, set_auto_temp, 0, 3);
1689static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR,
1690 show_auto_temp, set_auto_temp, 0, 4);
1691static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, S_IRUGO | S_IWUSR,
1692 show_auto_pwm, set_auto_pwm, 0, 0);
1693static SENSOR_DEVICE_ATTR(pwm1_auto_slope, S_IRUGO | S_IWUSR,
1694 show_auto_pwm_slope, set_auto_pwm_slope, 0);
1695
1696static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
1697 show_pwm_enable, set_pwm_enable, 1);
1698static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1);
1699static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1);
1700static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO,
1701 show_pwm_temp_map, set_pwm_temp_map, 1);
1702static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR,
1703 show_auto_pwm, set_auto_pwm, 1, 0);
1704static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR,
1705 show_auto_pwm, set_auto_pwm, 1, 1);
1706static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR,
1707 show_auto_pwm, set_auto_pwm, 1, 2);
1708static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO,
1709 show_auto_pwm, NULL, 1, 3);
1710static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR,
1711 show_auto_temp, set_auto_temp, 1, 1);
1712static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1713 show_auto_temp, set_auto_temp, 1, 0);
1714static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR,
1715 show_auto_temp, set_auto_temp, 1, 2);
1716static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR,
1717 show_auto_temp, set_auto_temp, 1, 3);
1718static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR,
1719 show_auto_temp, set_auto_temp, 1, 4);
1720static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, S_IRUGO | S_IWUSR,
1721 show_auto_pwm, set_auto_pwm, 1, 0);
1722static SENSOR_DEVICE_ATTR(pwm2_auto_slope, S_IRUGO | S_IWUSR,
1723 show_auto_pwm_slope, set_auto_pwm_slope, 1);
1724
1725static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR,
1726 show_pwm_enable, set_pwm_enable, 2);
1727static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2);
1728static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2);
1729static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO,
1730 show_pwm_temp_map, set_pwm_temp_map, 2);
1731static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR,
1732 show_auto_pwm, set_auto_pwm, 2, 0);
1733static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR,
1734 show_auto_pwm, set_auto_pwm, 2, 1);
1735static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR,
1736 show_auto_pwm, set_auto_pwm, 2, 2);
1737static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO,
1738 show_auto_pwm, NULL, 2, 3);
1739static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR,
1740 show_auto_temp, set_auto_temp, 2, 1);
1741static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1742 show_auto_temp, set_auto_temp, 2, 0);
1743static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR,
1744 show_auto_temp, set_auto_temp, 2, 2);
1745static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR,
1746 show_auto_temp, set_auto_temp, 2, 3);
1747static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR,
1748 show_auto_temp, set_auto_temp, 2, 4);
1749static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, S_IRUGO | S_IWUSR,
1750 show_auto_pwm, set_auto_pwm, 2, 0);
1751static SENSOR_DEVICE_ATTR(pwm3_auto_slope, S_IRUGO | S_IWUSR,
1752 show_auto_pwm_slope, set_auto_pwm_slope, 2);
1753
1754static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR,
1755 show_pwm_enable, set_pwm_enable, 3);
1756static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3);
1757static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3);
1758static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO,
1759 show_pwm_temp_map, set_pwm_temp_map, 3);
1760static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, S_IRUGO | S_IWUSR,
1761 show_auto_temp, set_auto_temp, 2, 1);
1762static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1763 show_auto_temp, set_auto_temp, 2, 0);
1764static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, S_IRUGO | S_IWUSR,
1765 show_auto_temp, set_auto_temp, 2, 2);
1766static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, S_IRUGO | S_IWUSR,
1767 show_auto_temp, set_auto_temp, 2, 3);
1768static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, S_IRUGO | S_IWUSR,
1769 show_auto_pwm, set_auto_pwm, 3, 0);
1770static SENSOR_DEVICE_ATTR(pwm4_auto_slope, S_IRUGO | S_IWUSR,
1771 show_auto_pwm_slope, set_auto_pwm_slope, 3);
1772
1773static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR,
1774 show_pwm_enable, set_pwm_enable, 4);
1775static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4);
1776static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4);
1777static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO,
1778 show_pwm_temp_map, set_pwm_temp_map, 4);
1779static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, S_IRUGO | S_IWUSR,
1780 show_auto_temp, set_auto_temp, 2, 1);
1781static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1782 show_auto_temp, set_auto_temp, 2, 0);
1783static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, S_IRUGO | S_IWUSR,
1784 show_auto_temp, set_auto_temp, 2, 2);
1785static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, S_IRUGO | S_IWUSR,
1786 show_auto_temp, set_auto_temp, 2, 3);
1787static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, S_IRUGO | S_IWUSR,
1788 show_auto_pwm, set_auto_pwm, 4, 0);
1789static SENSOR_DEVICE_ATTR(pwm5_auto_slope, S_IRUGO | S_IWUSR,
1790 show_auto_pwm_slope, set_auto_pwm_slope, 4);
1791
1792static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR,
1793 show_pwm_enable, set_pwm_enable, 5);
1794static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5);
1795static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5);
1796static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO,
1797 show_pwm_temp_map, set_pwm_temp_map, 5);
1798static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, S_IRUGO | S_IWUSR,
1799 show_auto_temp, set_auto_temp, 2, 1);
1800static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1801 show_auto_temp, set_auto_temp, 2, 0);
1802static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, S_IRUGO | S_IWUSR,
1803 show_auto_temp, set_auto_temp, 2, 2);
1804static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, S_IRUGO | S_IWUSR,
1805 show_auto_temp, set_auto_temp, 2, 3);
1806static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, S_IRUGO | S_IWUSR,
1807 show_auto_pwm, set_auto_pwm, 5, 0);
1808static SENSOR_DEVICE_ATTR(pwm6_auto_slope, S_IRUGO | S_IWUSR,
1809 show_auto_pwm_slope, set_auto_pwm_slope, 5);
1810
1811/* Alarms */
1812static ssize_t alarms_show(struct device *dev, struct device_attribute *attr,
1813 char *buf)
1814{
1815 struct it87_data *data = it87_update_device(dev);
1816
1817 return sprintf(buf, "%u\n", data->alarms);
1818}
1819static DEVICE_ATTR_RO(alarms);
1820
1821static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
1822 char *buf)
1823{
1824 struct it87_data *data = it87_update_device(dev);
1825 int bitnr = to_sensor_dev_attr(attr)->index;
1826
1827 return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
1828}
1829
1830static ssize_t clear_intrusion(struct device *dev,
1831 struct device_attribute *attr, const char *buf,
1832 size_t count)
1833{
1834 struct it87_data *data = dev_get_drvdata(dev);
1835 int config;
1836 long val;
1837
1838 if (kstrtol(buf, 10, &val) < 0 || val != 0)
1839 return -EINVAL;
1840
1841 mutex_lock(&data->update_lock);
1842 config = it87_read_value(data, IT87_REG_CONFIG);
1843 if (config < 0) {
1844 count = config;
1845 } else {
1846 config |= BIT(5);
1847 it87_write_value(data, IT87_REG_CONFIG, config);
1848 /* Invalidate cache to force re-read */
1849 data->valid = false;
1850 }
1851 mutex_unlock(&data->update_lock);
1852
1853 return count;
1854}
1855
1856static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8);
1857static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9);
1858static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10);
1859static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11);
1860static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12);
1861static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13);
1862static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14);
1863static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15);
1864static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0);
1865static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1);
1866static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2);
1867static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3);
1868static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6);
1869static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7);
1870static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16);
1871static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17);
1872static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18);
1873static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR,
1874 show_alarm, clear_intrusion, 4);
1875
1876static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
1877 char *buf)
1878{
1879 struct it87_data *data = it87_update_device(dev);
1880 int bitnr = to_sensor_dev_attr(attr)->index;
1881
1882 return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
1883}
1884
1885static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
1886 const char *buf, size_t count)
1887{
1888 int bitnr = to_sensor_dev_attr(attr)->index;
1889 struct it87_data *data = dev_get_drvdata(dev);
1890 long val;
1891
1892 if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1))
1893 return -EINVAL;
1894
1895 mutex_lock(&data->update_lock);
1896 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1897 if (val)
1898 data->beeps |= BIT(bitnr);
1899 else
1900 data->beeps &= ~BIT(bitnr);
1901 it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps);
1902 mutex_unlock(&data->update_lock);
1903 return count;
1904}
1905
1906static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
1907 show_beep, set_beep, 1);
1908static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1);
1909static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1);
1910static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1);
1911static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1);
1912static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1);
1913static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1);
1914static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1);
1915/* fanX_beep writability is set later */
1916static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0);
1917static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0);
1918static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0);
1919static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0);
1920static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0);
1921static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0);
1922static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
1923 show_beep, set_beep, 2);
1924static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2);
1925static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2);
1926
1927static ssize_t vrm_show(struct device *dev, struct device_attribute *attr,
1928 char *buf)
1929{
1930 struct it87_data *data = dev_get_drvdata(dev);
1931
1932 return sprintf(buf, "%u\n", data->vrm);
1933}
1934
1935static ssize_t vrm_store(struct device *dev, struct device_attribute *attr,
1936 const char *buf, size_t count)
1937{
1938 struct it87_data *data = dev_get_drvdata(dev);
1939 unsigned long val;
1940
1941 if (kstrtoul(buf, 10, &val) < 0)
1942 return -EINVAL;
1943
1944 data->vrm = val;
1945
1946 return count;
1947}
1948static DEVICE_ATTR_RW(vrm);
1949
1950static ssize_t cpu0_vid_show(struct device *dev,
1951 struct device_attribute *attr, char *buf)
1952{
1953 struct it87_data *data = it87_update_device(dev);
1954
1955 return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm));
1956}
1957static DEVICE_ATTR_RO(cpu0_vid);
1958
1959static ssize_t show_label(struct device *dev, struct device_attribute *attr,
1960 char *buf)
1961{
1962 static const char * const labels[] = {
1963 "+5V",
1964 "5VSB",
1965 "Vbat",
1966 "AVCC",
1967 };
1968 static const char * const labels_it8721[] = {
1969 "+3.3V",
1970 "3VSB",
1971 "Vbat",
1972 "+3.3V",
1973 };
1974 struct it87_data *data = dev_get_drvdata(dev);
1975 int nr = to_sensor_dev_attr(attr)->index;
1976 const char *label;
1977
1978 if (has_vin3_5v(data) && nr == 0)
1979 label = labels[0];
1980 else if (has_12mv_adc(data) || has_10_9mv_adc(data))
1981 label = labels_it8721[nr];
1982 else
1983 label = labels[nr];
1984
1985 return sprintf(buf, "%s\n", label);
1986}
1987static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0);
1988static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1);
1989static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2);
1990/* AVCC3 */
1991static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 3);
1992
1993static umode_t it87_in_is_visible(struct kobject *kobj,
1994 struct attribute *attr, int index)
1995{
1996 struct device *dev = kobj_to_dev(kobj);
1997 struct it87_data *data = dev_get_drvdata(dev);
1998 int i = index / 5; /* voltage index */
1999 int a = index % 5; /* attribute index */
2000
2001 if (index >= 40) { /* in8 and higher only have input attributes */
2002 i = index - 40 + 8;
2003 a = 0;
2004 }
2005
2006 if (!(data->has_in & BIT(i)))
2007 return 0;
2008
2009 if (a == 4 && !data->has_beep)
2010 return 0;
2011
2012 return attr->mode;
2013}
2014
2015static struct attribute *it87_attributes_in[] = {
2016 &sensor_dev_attr_in0_input.dev_attr.attr,
2017 &sensor_dev_attr_in0_min.dev_attr.attr,
2018 &sensor_dev_attr_in0_max.dev_attr.attr,
2019 &sensor_dev_attr_in0_alarm.dev_attr.attr,
2020 &sensor_dev_attr_in0_beep.dev_attr.attr, /* 4 */
2021
2022 &sensor_dev_attr_in1_input.dev_attr.attr,
2023 &sensor_dev_attr_in1_min.dev_attr.attr,
2024 &sensor_dev_attr_in1_max.dev_attr.attr,
2025 &sensor_dev_attr_in1_alarm.dev_attr.attr,
2026 &sensor_dev_attr_in1_beep.dev_attr.attr, /* 9 */
2027
2028 &sensor_dev_attr_in2_input.dev_attr.attr,
2029 &sensor_dev_attr_in2_min.dev_attr.attr,
2030 &sensor_dev_attr_in2_max.dev_attr.attr,
2031 &sensor_dev_attr_in2_alarm.dev_attr.attr,
2032 &sensor_dev_attr_in2_beep.dev_attr.attr, /* 14 */
2033
2034 &sensor_dev_attr_in3_input.dev_attr.attr,
2035 &sensor_dev_attr_in3_min.dev_attr.attr,
2036 &sensor_dev_attr_in3_max.dev_attr.attr,
2037 &sensor_dev_attr_in3_alarm.dev_attr.attr,
2038 &sensor_dev_attr_in3_beep.dev_attr.attr, /* 19 */
2039
2040 &sensor_dev_attr_in4_input.dev_attr.attr,
2041 &sensor_dev_attr_in4_min.dev_attr.attr,
2042 &sensor_dev_attr_in4_max.dev_attr.attr,
2043 &sensor_dev_attr_in4_alarm.dev_attr.attr,
2044 &sensor_dev_attr_in4_beep.dev_attr.attr, /* 24 */
2045
2046 &sensor_dev_attr_in5_input.dev_attr.attr,
2047 &sensor_dev_attr_in5_min.dev_attr.attr,
2048 &sensor_dev_attr_in5_max.dev_attr.attr,
2049 &sensor_dev_attr_in5_alarm.dev_attr.attr,
2050 &sensor_dev_attr_in5_beep.dev_attr.attr, /* 29 */
2051
2052 &sensor_dev_attr_in6_input.dev_attr.attr,
2053 &sensor_dev_attr_in6_min.dev_attr.attr,
2054 &sensor_dev_attr_in6_max.dev_attr.attr,
2055 &sensor_dev_attr_in6_alarm.dev_attr.attr,
2056 &sensor_dev_attr_in6_beep.dev_attr.attr, /* 34 */
2057
2058 &sensor_dev_attr_in7_input.dev_attr.attr,
2059 &sensor_dev_attr_in7_min.dev_attr.attr,
2060 &sensor_dev_attr_in7_max.dev_attr.attr,
2061 &sensor_dev_attr_in7_alarm.dev_attr.attr,
2062 &sensor_dev_attr_in7_beep.dev_attr.attr, /* 39 */
2063
2064 &sensor_dev_attr_in8_input.dev_attr.attr, /* 40 */
2065 &sensor_dev_attr_in9_input.dev_attr.attr,
2066 &sensor_dev_attr_in10_input.dev_attr.attr,
2067 &sensor_dev_attr_in11_input.dev_attr.attr,
2068 &sensor_dev_attr_in12_input.dev_attr.attr,
2069 NULL
2070};
2071
2072static const struct attribute_group it87_group_in = {
2073 .attrs = it87_attributes_in,
2074 .is_visible = it87_in_is_visible,
2075};
2076
2077static umode_t it87_temp_is_visible(struct kobject *kobj,
2078 struct attribute *attr, int index)
2079{
2080 struct device *dev = kobj_to_dev(kobj);
2081 struct it87_data *data = dev_get_drvdata(dev);
2082 int i = index / 7; /* temperature index */
2083 int a = index % 7; /* attribute index */
2084
2085 if (index >= 21) {
2086 i = index - 21 + 3;
2087 a = 0;
2088 }
2089
2090 if (!(data->has_temp & BIT(i)))
2091 return 0;
2092
2093 if (a == 5 && !has_temp_offset(data))
2094 return 0;
2095
2096 if (a == 6 && !data->has_beep)
2097 return 0;
2098
2099 return attr->mode;
2100}
2101
2102static struct attribute *it87_attributes_temp[] = {
2103 &sensor_dev_attr_temp1_input.dev_attr.attr,
2104 &sensor_dev_attr_temp1_max.dev_attr.attr,
2105 &sensor_dev_attr_temp1_min.dev_attr.attr,
2106 &sensor_dev_attr_temp1_type.dev_attr.attr,
2107 &sensor_dev_attr_temp1_alarm.dev_attr.attr,
2108 &sensor_dev_attr_temp1_offset.dev_attr.attr, /* 5 */
2109 &sensor_dev_attr_temp1_beep.dev_attr.attr, /* 6 */
2110
2111 &sensor_dev_attr_temp2_input.dev_attr.attr, /* 7 */
2112 &sensor_dev_attr_temp2_max.dev_attr.attr,
2113 &sensor_dev_attr_temp2_min.dev_attr.attr,
2114 &sensor_dev_attr_temp2_type.dev_attr.attr,
2115 &sensor_dev_attr_temp2_alarm.dev_attr.attr,
2116 &sensor_dev_attr_temp2_offset.dev_attr.attr,
2117 &sensor_dev_attr_temp2_beep.dev_attr.attr,
2118
2119 &sensor_dev_attr_temp3_input.dev_attr.attr, /* 14 */
2120 &sensor_dev_attr_temp3_max.dev_attr.attr,
2121 &sensor_dev_attr_temp3_min.dev_attr.attr,
2122 &sensor_dev_attr_temp3_type.dev_attr.attr,
2123 &sensor_dev_attr_temp3_alarm.dev_attr.attr,
2124 &sensor_dev_attr_temp3_offset.dev_attr.attr,
2125 &sensor_dev_attr_temp3_beep.dev_attr.attr,
2126
2127 &sensor_dev_attr_temp4_input.dev_attr.attr, /* 21 */
2128 &sensor_dev_attr_temp5_input.dev_attr.attr,
2129 &sensor_dev_attr_temp6_input.dev_attr.attr,
2130 NULL
2131};
2132
2133static const struct attribute_group it87_group_temp = {
2134 .attrs = it87_attributes_temp,
2135 .is_visible = it87_temp_is_visible,
2136};
2137
2138static umode_t it87_is_visible(struct kobject *kobj,
2139 struct attribute *attr, int index)
2140{
2141 struct device *dev = kobj_to_dev(kobj);
2142 struct it87_data *data = dev_get_drvdata(dev);
2143
2144 if ((index == 2 || index == 3) && !data->has_vid)
2145 return 0;
2146
2147 if (index > 3 && !(data->in_internal & BIT(index - 4)))
2148 return 0;
2149
2150 return attr->mode;
2151}
2152
2153static struct attribute *it87_attributes[] = {
2154 &dev_attr_alarms.attr,
2155 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
2156 &dev_attr_vrm.attr, /* 2 */
2157 &dev_attr_cpu0_vid.attr, /* 3 */
2158 &sensor_dev_attr_in3_label.dev_attr.attr, /* 4 .. 7 */
2159 &sensor_dev_attr_in7_label.dev_attr.attr,
2160 &sensor_dev_attr_in8_label.dev_attr.attr,
2161 &sensor_dev_attr_in9_label.dev_attr.attr,
2162 NULL
2163};
2164
2165static const struct attribute_group it87_group = {
2166 .attrs = it87_attributes,
2167 .is_visible = it87_is_visible,
2168};
2169
2170static umode_t it87_fan_is_visible(struct kobject *kobj,
2171 struct attribute *attr, int index)
2172{
2173 struct device *dev = kobj_to_dev(kobj);
2174 struct it87_data *data = dev_get_drvdata(dev);
2175 int i = index / 5; /* fan index */
2176 int a = index % 5; /* attribute index */
2177
2178 if (index >= 15) { /* fan 4..6 don't have divisor attributes */
2179 i = (index - 15) / 4 + 3;
2180 a = (index - 15) % 4;
2181 }
2182
2183 if (!(data->has_fan & BIT(i)))
2184 return 0;
2185
2186 if (a == 3) { /* beep */
2187 if (!data->has_beep)
2188 return 0;
2189 /* first fan beep attribute is writable */
2190 if (i == __ffs(data->has_fan))
2191 return attr->mode | S_IWUSR;
2192 }
2193
2194 if (a == 4 && has_16bit_fans(data)) /* divisor */
2195 return 0;
2196
2197 return attr->mode;
2198}
2199
2200static struct attribute *it87_attributes_fan[] = {
2201 &sensor_dev_attr_fan1_input.dev_attr.attr,
2202 &sensor_dev_attr_fan1_min.dev_attr.attr,
2203 &sensor_dev_attr_fan1_alarm.dev_attr.attr,
2204 &sensor_dev_attr_fan1_beep.dev_attr.attr, /* 3 */
2205 &sensor_dev_attr_fan1_div.dev_attr.attr, /* 4 */
2206
2207 &sensor_dev_attr_fan2_input.dev_attr.attr,
2208 &sensor_dev_attr_fan2_min.dev_attr.attr,
2209 &sensor_dev_attr_fan2_alarm.dev_attr.attr,
2210 &sensor_dev_attr_fan2_beep.dev_attr.attr,
2211 &sensor_dev_attr_fan2_div.dev_attr.attr, /* 9 */
2212
2213 &sensor_dev_attr_fan3_input.dev_attr.attr,
2214 &sensor_dev_attr_fan3_min.dev_attr.attr,
2215 &sensor_dev_attr_fan3_alarm.dev_attr.attr,
2216 &sensor_dev_attr_fan3_beep.dev_attr.attr,
2217 &sensor_dev_attr_fan3_div.dev_attr.attr, /* 14 */
2218
2219 &sensor_dev_attr_fan4_input.dev_attr.attr, /* 15 */
2220 &sensor_dev_attr_fan4_min.dev_attr.attr,
2221 &sensor_dev_attr_fan4_alarm.dev_attr.attr,
2222 &sensor_dev_attr_fan4_beep.dev_attr.attr,
2223
2224 &sensor_dev_attr_fan5_input.dev_attr.attr, /* 19 */
2225 &sensor_dev_attr_fan5_min.dev_attr.attr,
2226 &sensor_dev_attr_fan5_alarm.dev_attr.attr,
2227 &sensor_dev_attr_fan5_beep.dev_attr.attr,
2228
2229 &sensor_dev_attr_fan6_input.dev_attr.attr, /* 23 */
2230 &sensor_dev_attr_fan6_min.dev_attr.attr,
2231 &sensor_dev_attr_fan6_alarm.dev_attr.attr,
2232 &sensor_dev_attr_fan6_beep.dev_attr.attr,
2233 NULL
2234};
2235
2236static const struct attribute_group it87_group_fan = {
2237 .attrs = it87_attributes_fan,
2238 .is_visible = it87_fan_is_visible,
2239};
2240
2241static umode_t it87_pwm_is_visible(struct kobject *kobj,
2242 struct attribute *attr, int index)
2243{
2244 struct device *dev = kobj_to_dev(kobj);
2245 struct it87_data *data = dev_get_drvdata(dev);
2246 int i = index / 4; /* pwm index */
2247 int a = index % 4; /* attribute index */
2248
2249 if (!(data->has_pwm & BIT(i)))
2250 return 0;
2251
2252 /* pwmX_auto_channels_temp is only writable if auto pwm is supported */
2253 if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data)))
2254 return attr->mode | S_IWUSR;
2255
2256 /* pwm2_freq is writable if there are two pwm frequency selects */
2257 if (has_pwm_freq2(data) && i == 1 && a == 2)
2258 return attr->mode | S_IWUSR;
2259
2260 return attr->mode;
2261}
2262
2263static struct attribute *it87_attributes_pwm[] = {
2264 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2265 &sensor_dev_attr_pwm1.dev_attr.attr,
2266 &sensor_dev_attr_pwm1_freq.dev_attr.attr,
2267 &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
2268
2269 &sensor_dev_attr_pwm2_enable.dev_attr.attr,
2270 &sensor_dev_attr_pwm2.dev_attr.attr,
2271 &sensor_dev_attr_pwm2_freq.dev_attr.attr,
2272 &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
2273
2274 &sensor_dev_attr_pwm3_enable.dev_attr.attr,
2275 &sensor_dev_attr_pwm3.dev_attr.attr,
2276 &sensor_dev_attr_pwm3_freq.dev_attr.attr,
2277 &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
2278
2279 &sensor_dev_attr_pwm4_enable.dev_attr.attr,
2280 &sensor_dev_attr_pwm4.dev_attr.attr,
2281 &sensor_dev_attr_pwm4_freq.dev_attr.attr,
2282 &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr,
2283
2284 &sensor_dev_attr_pwm5_enable.dev_attr.attr,
2285 &sensor_dev_attr_pwm5.dev_attr.attr,
2286 &sensor_dev_attr_pwm5_freq.dev_attr.attr,
2287 &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr,
2288
2289 &sensor_dev_attr_pwm6_enable.dev_attr.attr,
2290 &sensor_dev_attr_pwm6.dev_attr.attr,
2291 &sensor_dev_attr_pwm6_freq.dev_attr.attr,
2292 &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr,
2293
2294 NULL
2295};
2296
2297static const struct attribute_group it87_group_pwm = {
2298 .attrs = it87_attributes_pwm,
2299 .is_visible = it87_pwm_is_visible,
2300};
2301
2302static umode_t it87_auto_pwm_is_visible(struct kobject *kobj,
2303 struct attribute *attr, int index)
2304{
2305 struct device *dev = kobj_to_dev(kobj);
2306 struct it87_data *data = dev_get_drvdata(dev);
2307 int i = index / 11; /* pwm index */
2308 int a = index % 11; /* attribute index */
2309
2310 if (index >= 33) { /* pwm 4..6 */
2311 i = (index - 33) / 6 + 3;
2312 a = (index - 33) % 6 + 4;
2313 }
2314
2315 if (!(data->has_pwm & BIT(i)))
2316 return 0;
2317
2318 if (has_newer_autopwm(data)) {
2319 if (a < 4) /* no auto point pwm */
2320 return 0;
2321 if (a == 8) /* no auto_point4 */
2322 return 0;
2323 }
2324 if (has_old_autopwm(data)) {
2325 if (a >= 9) /* no pwm_auto_start, pwm_auto_slope */
2326 return 0;
2327 }
2328
2329 return attr->mode;
2330}
2331
2332static struct attribute *it87_attributes_auto_pwm[] = {
2333 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
2334 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
2335 &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
2336 &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
2337 &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
2338 &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
2339 &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
2340 &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
2341 &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
2342 &sensor_dev_attr_pwm1_auto_start.dev_attr.attr,
2343 &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr,
2344
2345 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, /* 11 */
2346 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
2347 &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
2348 &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
2349 &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
2350 &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
2351 &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
2352 &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
2353 &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
2354 &sensor_dev_attr_pwm2_auto_start.dev_attr.attr,
2355 &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr,
2356
2357 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, /* 22 */
2358 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
2359 &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
2360 &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
2361 &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
2362 &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
2363 &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
2364 &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
2365 &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
2366 &sensor_dev_attr_pwm3_auto_start.dev_attr.attr,
2367 &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr,
2368
2369 &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr, /* 33 */
2370 &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr,
2371 &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr,
2372 &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr,
2373 &sensor_dev_attr_pwm4_auto_start.dev_attr.attr,
2374 &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr,
2375
2376 &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr,
2377 &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr,
2378 &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr,
2379 &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr,
2380 &sensor_dev_attr_pwm5_auto_start.dev_attr.attr,
2381 &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr,
2382
2383 &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr,
2384 &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr,
2385 &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr,
2386 &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr,
2387 &sensor_dev_attr_pwm6_auto_start.dev_attr.attr,
2388 &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr,
2389
2390 NULL,
2391};
2392
2393static const struct attribute_group it87_group_auto_pwm = {
2394 .attrs = it87_attributes_auto_pwm,
2395 .is_visible = it87_auto_pwm_is_visible,
2396};
2397
2398/* SuperIO detection - will change isa_address if a chip is found */
2399static int __init it87_find(int sioaddr, unsigned short *address,
2400 struct it87_sio_data *sio_data)
2401{
2402 int err;
2403 u16 chip_type;
2404 const struct it87_devices *config;
2405
2406 err = superio_enter(sioaddr);
2407 if (err)
2408 return err;
2409
2410 err = -ENODEV;
2411 chip_type = superio_inw(sioaddr, DEVID);
2412 /* check first for a valid chip before forcing chip id */
2413 if (chip_type == 0xffff)
2414 goto exit;
2415
2416 if (force_id)
2417 chip_type = force_id;
2418
2419 switch (chip_type) {
2420 case IT8705F_DEVID:
2421 sio_data->type = it87;
2422 break;
2423 case IT8712F_DEVID:
2424 sio_data->type = it8712;
2425 break;
2426 case IT8716F_DEVID:
2427 case IT8726F_DEVID:
2428 sio_data->type = it8716;
2429 break;
2430 case IT8718F_DEVID:
2431 sio_data->type = it8718;
2432 break;
2433 case IT8720F_DEVID:
2434 sio_data->type = it8720;
2435 break;
2436 case IT8721F_DEVID:
2437 sio_data->type = it8721;
2438 break;
2439 case IT8728F_DEVID:
2440 sio_data->type = it8728;
2441 break;
2442 case IT8732F_DEVID:
2443 sio_data->type = it8732;
2444 break;
2445 case IT8792E_DEVID:
2446 sio_data->type = it8792;
2447 break;
2448 case IT8771E_DEVID:
2449 sio_data->type = it8771;
2450 break;
2451 case IT8772E_DEVID:
2452 sio_data->type = it8772;
2453 break;
2454 case IT8781F_DEVID:
2455 sio_data->type = it8781;
2456 break;
2457 case IT8782F_DEVID:
2458 sio_data->type = it8782;
2459 break;
2460 case IT8783E_DEVID:
2461 sio_data->type = it8783;
2462 break;
2463 case IT8786E_DEVID:
2464 sio_data->type = it8786;
2465 break;
2466 case IT8790E_DEVID:
2467 sio_data->type = it8790;
2468 break;
2469 case IT8603E_DEVID:
2470 case IT8623E_DEVID:
2471 sio_data->type = it8603;
2472 break;
2473 case IT8620E_DEVID:
2474 sio_data->type = it8620;
2475 break;
2476 case IT8622E_DEVID:
2477 sio_data->type = it8622;
2478 break;
2479 case IT8628E_DEVID:
2480 sio_data->type = it8628;
2481 break;
2482 case 0xffff: /* No device at all */
2483 goto exit;
2484 default:
2485 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
2486 goto exit;
2487 }
2488
2489 superio_select(sioaddr, PME);
2490 if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) {
2491 pr_info("Device not activated, skipping\n");
2492 goto exit;
2493 }
2494
2495 *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1);
2496 if (*address == 0) {
2497 pr_info("Base address not set, skipping\n");
2498 goto exit;
2499 }
2500
2501 err = 0;
2502 sio_data->sioaddr = sioaddr;
2503 sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
2504 pr_info("Found IT%04x%s chip at 0x%x, revision %d\n", chip_type,
2505 it87_devices[sio_data->type].suffix,
2506 *address, sio_data->revision);
2507
2508 config = &it87_devices[sio_data->type];
2509
2510 /* in7 (VSB or VCCH5V) is always internal on some chips */
2511 if (has_in7_internal(config))
2512 sio_data->internal |= BIT(1);
2513
2514 /* in8 (Vbat) is always internal */
2515 sio_data->internal |= BIT(2);
2516
2517 /* in9 (AVCC3), always internal if supported */
2518 if (has_avcc3(config))
2519 sio_data->internal |= BIT(3); /* in9 is AVCC */
2520 else
2521 sio_data->skip_in |= BIT(9);
2522
2523 if (!has_five_pwm(config))
2524 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5);
2525 else if (!has_six_pwm(config))
2526 sio_data->skip_pwm |= BIT(5);
2527
2528 if (!has_vid(config))
2529 sio_data->skip_vid = 1;
2530
2531 /* Read GPIO config and VID value from LDN 7 (GPIO) */
2532 if (sio_data->type == it87) {
2533 /* The IT8705F has a different LD number for GPIO */
2534 superio_select(sioaddr, 5);
2535 sio_data->beep_pin = superio_inb(sioaddr,
2536 IT87_SIO_BEEP_PIN_REG) & 0x3f;
2537 } else if (sio_data->type == it8783) {
2538 int reg25, reg27, reg2a, reg2c, regef;
2539
2540 superio_select(sioaddr, GPIO);
2541
2542 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
2543 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2544 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
2545 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
2546 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG);
2547
2548 /* Check if fan3 is there or not */
2549 if ((reg27 & BIT(0)) || !(reg2c & BIT(2)))
2550 sio_data->skip_fan |= BIT(2);
2551 if ((reg25 & BIT(4)) ||
2552 (!(reg2a & BIT(1)) && (regef & BIT(0))))
2553 sio_data->skip_pwm |= BIT(2);
2554
2555 /* Check if fan2 is there or not */
2556 if (reg27 & BIT(7))
2557 sio_data->skip_fan |= BIT(1);
2558 if (reg27 & BIT(3))
2559 sio_data->skip_pwm |= BIT(1);
2560
2561 /* VIN5 */
2562 if ((reg27 & BIT(0)) || (reg2c & BIT(2)))
2563 sio_data->skip_in |= BIT(5); /* No VIN5 */
2564
2565 /* VIN6 */
2566 if (reg27 & BIT(1))
2567 sio_data->skip_in |= BIT(6); /* No VIN6 */
2568
2569 /*
2570 * VIN7
2571 * Does not depend on bit 2 of Reg2C, contrary to datasheet.
2572 */
2573 if (reg27 & BIT(2)) {
2574 /*
2575 * The data sheet is a bit unclear regarding the
2576 * internal voltage divider for VCCH5V. It says
2577 * "This bit enables and switches VIN7 (pin 91) to the
2578 * internal voltage divider for VCCH5V".
2579 * This is different to other chips, where the internal
2580 * voltage divider would connect VIN7 to an internal
2581 * voltage source. Maybe that is the case here as well.
2582 *
2583 * Since we don't know for sure, re-route it if that is
2584 * not the case, and ask the user to report if the
2585 * resulting voltage is sane.
2586 */
2587 if (!(reg2c & BIT(1))) {
2588 reg2c |= BIT(1);
2589 superio_outb(sioaddr, IT87_SIO_PINX2_REG,
2590 reg2c);
2591 sio_data->need_in7_reroute = true;
2592 pr_notice("Routing internal VCCH5V to in7.\n");
2593 }
2594 pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
2595 pr_notice("Please report if it displays a reasonable voltage.\n");
2596 }
2597
2598 if (reg2c & BIT(0))
2599 sio_data->internal |= BIT(0);
2600 if (reg2c & BIT(1))
2601 sio_data->internal |= BIT(1);
2602
2603 sio_data->beep_pin = superio_inb(sioaddr,
2604 IT87_SIO_BEEP_PIN_REG) & 0x3f;
2605 } else if (sio_data->type == it8603) {
2606 int reg27, reg29;
2607
2608 superio_select(sioaddr, GPIO);
2609
2610 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2611
2612 /* Check if fan3 is there or not */
2613 if (reg27 & BIT(6))
2614 sio_data->skip_pwm |= BIT(2);
2615 if (reg27 & BIT(7))
2616 sio_data->skip_fan |= BIT(2);
2617
2618 /* Check if fan2 is there or not */
2619 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
2620 if (reg29 & BIT(1))
2621 sio_data->skip_pwm |= BIT(1);
2622 if (reg29 & BIT(2))
2623 sio_data->skip_fan |= BIT(1);
2624
2625 sio_data->skip_in |= BIT(5); /* No VIN5 */
2626 sio_data->skip_in |= BIT(6); /* No VIN6 */
2627
2628 sio_data->beep_pin = superio_inb(sioaddr,
2629 IT87_SIO_BEEP_PIN_REG) & 0x3f;
2630 } else if (sio_data->type == it8620 || sio_data->type == it8628) {
2631 int reg;
2632
2633 superio_select(sioaddr, GPIO);
2634
2635 /* Check for pwm5 */
2636 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
2637 if (reg & BIT(6))
2638 sio_data->skip_pwm |= BIT(4);
2639
2640 /* Check for fan4, fan5 */
2641 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
2642 if (!(reg & BIT(5)))
2643 sio_data->skip_fan |= BIT(3);
2644 if (!(reg & BIT(4)))
2645 sio_data->skip_fan |= BIT(4);
2646
2647 /* Check for pwm3, fan3 */
2648 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2649 if (reg & BIT(6))
2650 sio_data->skip_pwm |= BIT(2);
2651 if (reg & BIT(7))
2652 sio_data->skip_fan |= BIT(2);
2653
2654 /* Check for pwm4 */
2655 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG);
2656 if (reg & BIT(2))
2657 sio_data->skip_pwm |= BIT(3);
2658
2659 /* Check for pwm2, fan2 */
2660 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
2661 if (reg & BIT(1))
2662 sio_data->skip_pwm |= BIT(1);
2663 if (reg & BIT(2))
2664 sio_data->skip_fan |= BIT(1);
2665 /* Check for pwm6, fan6 */
2666 if (!(reg & BIT(7))) {
2667 sio_data->skip_pwm |= BIT(5);
2668 sio_data->skip_fan |= BIT(5);
2669 }
2670
2671 /* Check if AVCC is on VIN3 */
2672 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
2673 if (reg & BIT(0))
2674 sio_data->internal |= BIT(0);
2675 else
2676 sio_data->skip_in |= BIT(9);
2677
2678 sio_data->beep_pin = superio_inb(sioaddr,
2679 IT87_SIO_BEEP_PIN_REG) & 0x3f;
2680 } else if (sio_data->type == it8622) {
2681 int reg;
2682
2683 superio_select(sioaddr, GPIO);
2684
2685 /* Check for pwm4, fan4 */
2686 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
2687 if (reg & BIT(6))
2688 sio_data->skip_fan |= BIT(3);
2689 if (reg & BIT(5))
2690 sio_data->skip_pwm |= BIT(3);
2691
2692 /* Check for pwm3, fan3, pwm5, fan5 */
2693 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2694 if (reg & BIT(6))
2695 sio_data->skip_pwm |= BIT(2);
2696 if (reg & BIT(7))
2697 sio_data->skip_fan |= BIT(2);
2698 if (reg & BIT(3))
2699 sio_data->skip_pwm |= BIT(4);
2700 if (reg & BIT(1))
2701 sio_data->skip_fan |= BIT(4);
2702
2703 /* Check for pwm2, fan2 */
2704 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
2705 if (reg & BIT(1))
2706 sio_data->skip_pwm |= BIT(1);
2707 if (reg & BIT(2))
2708 sio_data->skip_fan |= BIT(1);
2709
2710 /* Check for AVCC */
2711 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
2712 if (!(reg & BIT(0)))
2713 sio_data->skip_in |= BIT(9);
2714
2715 sio_data->beep_pin = superio_inb(sioaddr,
2716 IT87_SIO_BEEP_PIN_REG) & 0x3f;
2717 } else {
2718 int reg;
2719 bool uart6;
2720
2721 superio_select(sioaddr, GPIO);
2722
2723 /* Check for fan4, fan5 */
2724 if (has_five_fans(config)) {
2725 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
2726 switch (sio_data->type) {
2727 case it8718:
2728 if (reg & BIT(5))
2729 sio_data->skip_fan |= BIT(3);
2730 if (reg & BIT(4))
2731 sio_data->skip_fan |= BIT(4);
2732 break;
2733 case it8720:
2734 case it8721:
2735 case it8728:
2736 if (!(reg & BIT(5)))
2737 sio_data->skip_fan |= BIT(3);
2738 if (!(reg & BIT(4)))
2739 sio_data->skip_fan |= BIT(4);
2740 break;
2741 default:
2742 break;
2743 }
2744 }
2745
2746 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2747 if (!sio_data->skip_vid) {
2748 /* We need at least 4 VID pins */
2749 if (reg & 0x0f) {
2750 pr_info("VID is disabled (pins used for GPIO)\n");
2751 sio_data->skip_vid = 1;
2752 }
2753 }
2754
2755 /* Check if fan3 is there or not */
2756 if (reg & BIT(6))
2757 sio_data->skip_pwm |= BIT(2);
2758 if (reg & BIT(7))
2759 sio_data->skip_fan |= BIT(2);
2760
2761 /* Check if fan2 is there or not */
2762 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
2763 if (reg & BIT(1))
2764 sio_data->skip_pwm |= BIT(1);
2765 if (reg & BIT(2))
2766 sio_data->skip_fan |= BIT(1);
2767
2768 if ((sio_data->type == it8718 || sio_data->type == it8720) &&
2769 !(sio_data->skip_vid))
2770 sio_data->vid_value = superio_inb(sioaddr,
2771 IT87_SIO_VID_REG);
2772
2773 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
2774
2775 uart6 = sio_data->type == it8782 && (reg & BIT(2));
2776
2777 /*
2778 * The IT8720F has no VIN7 pin, so VCCH5V should always be
2779 * routed internally to VIN7 with an internal divider.
2780 * Curiously, there still is a configuration bit to control
2781 * this, which means it can be set incorrectly. And even
2782 * more curiously, many boards out there are improperly
2783 * configured, even though the IT8720F datasheet claims
2784 * that the internal routing of VCCH5V to VIN7 is the default
2785 * setting. So we force the internal routing in this case.
2786 *
2787 * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
2788 * If UART6 is enabled, re-route VIN7 to the internal divider
2789 * if that is not already the case.
2790 */
2791 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) {
2792 reg |= BIT(1);
2793 superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg);
2794 sio_data->need_in7_reroute = true;
2795 pr_notice("Routing internal VCCH5V to in7\n");
2796 }
2797 if (reg & BIT(0))
2798 sio_data->internal |= BIT(0);
2799 if (reg & BIT(1))
2800 sio_data->internal |= BIT(1);
2801
2802 /*
2803 * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
2804 * While VIN7 can be routed to the internal voltage divider,
2805 * VIN5 and VIN6 are not available if UART6 is enabled.
2806 *
2807 * Also, temp3 is not available if UART6 is enabled and TEMPIN3
2808 * is the temperature source. Since we can not read the
2809 * temperature source here, skip_temp is preliminary.
2810 */
2811 if (uart6) {
2812 sio_data->skip_in |= BIT(5) | BIT(6);
2813 sio_data->skip_temp |= BIT(2);
2814 }
2815
2816 sio_data->beep_pin = superio_inb(sioaddr,
2817 IT87_SIO_BEEP_PIN_REG) & 0x3f;
2818 }
2819 if (sio_data->beep_pin)
2820 pr_info("Beeping is supported\n");
2821
2822 /* Set values based on DMI matches */
2823 if (dmi_data)
2824 sio_data->skip_pwm |= dmi_data->skip_pwm;
2825
2826exit:
2827 superio_exit(sioaddr);
2828 return err;
2829}
2830
2831/*
2832 * Some chips seem to have default value 0xff for all limit
2833 * registers. For low voltage limits it makes no sense and triggers
2834 * alarms, so change to 0 instead. For high temperature limits, it
2835 * means -1 degree C, which surprisingly doesn't trigger an alarm,
2836 * but is still confusing, so change to 127 degrees C.
2837 */
2838static void it87_check_limit_regs(struct it87_data *data)
2839{
2840 int i, reg;
2841
2842 for (i = 0; i < NUM_VIN_LIMIT; i++) {
2843 reg = it87_read_value(data, IT87_REG_VIN_MIN(i));
2844 if (reg == 0xff)
2845 it87_write_value(data, IT87_REG_VIN_MIN(i), 0);
2846 }
2847 for (i = 0; i < NUM_TEMP_LIMIT; i++) {
2848 reg = it87_read_value(data, IT87_REG_TEMP_HIGH(i));
2849 if (reg == 0xff)
2850 it87_write_value(data, IT87_REG_TEMP_HIGH(i), 127);
2851 }
2852}
2853
2854/* Check if voltage monitors are reset manually or by some reason */
2855static void it87_check_voltage_monitors_reset(struct it87_data *data)
2856{
2857 int reg;
2858
2859 reg = it87_read_value(data, IT87_REG_VIN_ENABLE);
2860 if ((reg & 0xff) == 0) {
2861 /* Enable all voltage monitors */
2862 it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff);
2863 }
2864}
2865
2866/* Check if tachometers are reset manually or by some reason */
2867static void it87_check_tachometers_reset(struct platform_device *pdev)
2868{
2869 struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
2870 struct it87_data *data = platform_get_drvdata(pdev);
2871 u8 mask, fan_main_ctrl;
2872
2873 mask = 0x70 & ~(sio_data->skip_fan << 4);
2874 fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
2875 if ((fan_main_ctrl & mask) == 0) {
2876 /* Enable all fan tachometers */
2877 fan_main_ctrl |= mask;
2878 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
2879 fan_main_ctrl);
2880 }
2881}
2882
2883/* Set tachometers to 16-bit mode if needed */
2884static void it87_check_tachometers_16bit_mode(struct platform_device *pdev)
2885{
2886 struct it87_data *data = platform_get_drvdata(pdev);
2887 int reg;
2888
2889 if (!has_fan16_config(data))
2890 return;
2891
2892 reg = it87_read_value(data, IT87_REG_FAN_16BIT);
2893 if (~reg & 0x07 & data->has_fan) {
2894 dev_dbg(&pdev->dev,
2895 "Setting fan1-3 to 16-bit mode\n");
2896 it87_write_value(data, IT87_REG_FAN_16BIT,
2897 reg | 0x07);
2898 }
2899}
2900
2901static void it87_start_monitoring(struct it87_data *data)
2902{
2903 it87_write_value(data, IT87_REG_CONFIG,
2904 (it87_read_value(data, IT87_REG_CONFIG) & 0x3e)
2905 | (update_vbat ? 0x41 : 0x01));
2906}
2907
2908/* Called when we have found a new IT87. */
2909static void it87_init_device(struct platform_device *pdev)
2910{
2911 struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
2912 struct it87_data *data = platform_get_drvdata(pdev);
2913 int tmp, i;
2914
2915 /*
2916 * For each PWM channel:
2917 * - If it is in automatic mode, setting to manual mode should set
2918 * the fan to full speed by default.
2919 * - If it is in manual mode, we need a mapping to temperature
2920 * channels to use when later setting to automatic mode later.
2921 * Use a 1:1 mapping by default (we are clueless.)
2922 * In both cases, the value can (and should) be changed by the user
2923 * prior to switching to a different mode.
2924 * Note that this is no longer needed for the IT8721F and later, as
2925 * these have separate registers for the temperature mapping and the
2926 * manual duty cycle.
2927 */
2928 for (i = 0; i < NUM_AUTO_PWM; i++) {
2929 data->pwm_temp_map[i] = i;
2930 data->pwm_duty[i] = 0x7f; /* Full speed */
2931 data->auto_pwm[i][3] = 0x7f; /* Full speed, hard-coded */
2932 }
2933
2934 it87_check_limit_regs(data);
2935
2936 /*
2937 * Temperature channels are not forcibly enabled, as they can be
2938 * set to two different sensor types and we can't guess which one
2939 * is correct for a given system. These channels can be enabled at
2940 * run-time through the temp{1-3}_type sysfs accessors if needed.
2941 */
2942
2943 it87_check_voltage_monitors_reset(data);
2944
2945 it87_check_tachometers_reset(pdev);
2946
2947 data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
2948 data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
2949
2950 it87_check_tachometers_16bit_mode(pdev);
2951
2952 /* Check for additional fans */
2953 if (has_five_fans(data)) {
2954 tmp = it87_read_value(data, IT87_REG_FAN_16BIT);
2955
2956 if (tmp & BIT(4))
2957 data->has_fan |= BIT(3); /* fan4 enabled */
2958 if (tmp & BIT(5))
2959 data->has_fan |= BIT(4); /* fan5 enabled */
2960 if (has_six_fans(data) && (tmp & BIT(2)))
2961 data->has_fan |= BIT(5); /* fan6 enabled */
2962 }
2963
2964 /* Fan input pins may be used for alternative functions */
2965 data->has_fan &= ~sio_data->skip_fan;
2966
2967 /* Check if pwm5, pwm6 are enabled */
2968 if (has_six_pwm(data)) {
2969 /* The following code may be IT8620E specific */
2970 tmp = it87_read_value(data, IT87_REG_FAN_DIV);
2971 if ((tmp & 0xc0) == 0xc0)
2972 sio_data->skip_pwm |= BIT(4);
2973 if (!(tmp & BIT(3)))
2974 sio_data->skip_pwm |= BIT(5);
2975 }
2976
2977 it87_start_monitoring(data);
2978}
2979
2980/* Return 1 if and only if the PWM interface is safe to use */
2981static int it87_check_pwm(struct device *dev)
2982{
2983 struct it87_data *data = dev_get_drvdata(dev);
2984 /*
2985 * Some BIOSes fail to correctly configure the IT87 fans. All fans off
2986 * and polarity set to active low is sign that this is the case so we
2987 * disable pwm control to protect the user.
2988 */
2989 int tmp = it87_read_value(data, IT87_REG_FAN_CTL);
2990
2991 if ((tmp & 0x87) == 0) {
2992 if (fix_pwm_polarity) {
2993 /*
2994 * The user asks us to attempt a chip reconfiguration.
2995 * This means switching to active high polarity and
2996 * inverting all fan speed values.
2997 */
2998 int i;
2999 u8 pwm[3];
3000
3001 for (i = 0; i < ARRAY_SIZE(pwm); i++)
3002 pwm[i] = it87_read_value(data,
3003 IT87_REG_PWM[i]);
3004
3005 /*
3006 * If any fan is in automatic pwm mode, the polarity
3007 * might be correct, as suspicious as it seems, so we
3008 * better don't change anything (but still disable the
3009 * PWM interface).
3010 */
3011 if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
3012 dev_info(dev,
3013 "Reconfiguring PWM to active high polarity\n");
3014 it87_write_value(data, IT87_REG_FAN_CTL,
3015 tmp | 0x87);
3016 for (i = 0; i < 3; i++)
3017 it87_write_value(data,
3018 IT87_REG_PWM[i],
3019 0x7f & ~pwm[i]);
3020 return 1;
3021 }
3022
3023 dev_info(dev,
3024 "PWM configuration is too broken to be fixed\n");
3025 }
3026
3027 return 0;
3028 } else if (fix_pwm_polarity) {
3029 dev_info(dev,
3030 "PWM configuration looks sane, won't touch\n");
3031 }
3032
3033 return 1;
3034}
3035
3036static int it87_probe(struct platform_device *pdev)
3037{
3038 struct it87_data *data;
3039 struct resource *res;
3040 struct device *dev = &pdev->dev;
3041 struct it87_sio_data *sio_data = dev_get_platdata(dev);
3042 int enable_pwm_interface;
3043 struct device *hwmon_dev;
3044
3045 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3046 if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT,
3047 DRVNAME)) {
3048 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
3049 (unsigned long)res->start,
3050 (unsigned long)(res->start + IT87_EC_EXTENT - 1));
3051 return -EBUSY;
3052 }
3053
3054 data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL);
3055 if (!data)
3056 return -ENOMEM;
3057
3058 data->addr = res->start;
3059 data->sioaddr = sio_data->sioaddr;
3060 data->type = sio_data->type;
3061 data->features = it87_devices[sio_data->type].features;
3062 data->peci_mask = it87_devices[sio_data->type].peci_mask;
3063 data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
3064 /*
3065 * IT8705F Datasheet 0.4.1, 3h == Version G.
3066 * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
3067 * These are the first revisions with 16-bit tachometer support.
3068 */
3069 switch (data->type) {
3070 case it87:
3071 if (sio_data->revision >= 0x03) {
3072 data->features &= ~FEAT_OLD_AUTOPWM;
3073 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
3074 }
3075 break;
3076 case it8712:
3077 if (sio_data->revision >= 0x08) {
3078 data->features &= ~FEAT_OLD_AUTOPWM;
3079 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
3080 FEAT_FIVE_FANS;
3081 }
3082 break;
3083 default:
3084 break;
3085 }
3086
3087 /* Now, we do the remaining detection. */
3088 if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80) ||
3089 it87_read_value(data, IT87_REG_CHIPID) != 0x90)
3090 return -ENODEV;
3091
3092 platform_set_drvdata(pdev, data);
3093
3094 mutex_init(&data->update_lock);
3095
3096 /* Check PWM configuration */
3097 enable_pwm_interface = it87_check_pwm(dev);
3098 if (!enable_pwm_interface)
3099 dev_info(dev,
3100 "Detected broken BIOS defaults, disabling PWM interface\n");
3101
3102 /* Starting with IT8721F, we handle scaling of internal voltages */
3103 if (has_12mv_adc(data)) {
3104 if (sio_data->internal & BIT(0))
3105 data->in_scaled |= BIT(3); /* in3 is AVCC */
3106 if (sio_data->internal & BIT(1))
3107 data->in_scaled |= BIT(7); /* in7 is VSB */
3108 if (sio_data->internal & BIT(2))
3109 data->in_scaled |= BIT(8); /* in8 is Vbat */
3110 if (sio_data->internal & BIT(3))
3111 data->in_scaled |= BIT(9); /* in9 is AVCC */
3112 } else if (sio_data->type == it8781 || sio_data->type == it8782 ||
3113 sio_data->type == it8783) {
3114 if (sio_data->internal & BIT(0))
3115 data->in_scaled |= BIT(3); /* in3 is VCC5V */
3116 if (sio_data->internal & BIT(1))
3117 data->in_scaled |= BIT(7); /* in7 is VCCH5V */
3118 }
3119
3120 data->has_temp = 0x07;
3121 if (sio_data->skip_temp & BIT(2)) {
3122 if (sio_data->type == it8782 &&
3123 !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80))
3124 data->has_temp &= ~BIT(2);
3125 }
3126
3127 data->in_internal = sio_data->internal;
3128 data->need_in7_reroute = sio_data->need_in7_reroute;
3129 data->has_in = 0x3ff & ~sio_data->skip_in;
3130
3131 if (has_six_temp(data)) {
3132 u8 reg = it87_read_value(data, IT87_REG_TEMP456_ENABLE);
3133
3134 /* Check for additional temperature sensors */
3135 if ((reg & 0x03) >= 0x02)
3136 data->has_temp |= BIT(3);
3137 if (((reg >> 2) & 0x03) >= 0x02)
3138 data->has_temp |= BIT(4);
3139 if (((reg >> 4) & 0x03) >= 0x02)
3140 data->has_temp |= BIT(5);
3141
3142 /* Check for additional voltage sensors */
3143 if ((reg & 0x03) == 0x01)
3144 data->has_in |= BIT(10);
3145 if (((reg >> 2) & 0x03) == 0x01)
3146 data->has_in |= BIT(11);
3147 if (((reg >> 4) & 0x03) == 0x01)
3148 data->has_in |= BIT(12);
3149 }
3150
3151 data->has_beep = !!sio_data->beep_pin;
3152
3153 /* Initialize the IT87 chip */
3154 it87_init_device(pdev);
3155
3156 if (!sio_data->skip_vid) {
3157 data->has_vid = true;
3158 data->vrm = vid_which_vrm();
3159 /* VID reading from Super-I/O config space if available */
3160 data->vid = sio_data->vid_value;
3161 }
3162
3163 /* Prepare for sysfs hooks */
3164 data->groups[0] = &it87_group;
3165 data->groups[1] = &it87_group_in;
3166 data->groups[2] = &it87_group_temp;
3167 data->groups[3] = &it87_group_fan;
3168
3169 if (enable_pwm_interface) {
3170 data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1;
3171 data->has_pwm &= ~sio_data->skip_pwm;
3172
3173 data->groups[4] = &it87_group_pwm;
3174 if (has_old_autopwm(data) || has_newer_autopwm(data))
3175 data->groups[5] = &it87_group_auto_pwm;
3176 }
3177
3178 hwmon_dev = devm_hwmon_device_register_with_groups(dev,
3179 it87_devices[sio_data->type].name,
3180 data, data->groups);
3181 return PTR_ERR_OR_ZERO(hwmon_dev);
3182}
3183
3184static void it87_resume_sio(struct platform_device *pdev)
3185{
3186 struct it87_data *data = dev_get_drvdata(&pdev->dev);
3187 int err;
3188 int reg2c;
3189
3190 if (!data->need_in7_reroute)
3191 return;
3192
3193 err = superio_enter(data->sioaddr);
3194 if (err) {
3195 dev_warn(&pdev->dev,
3196 "Unable to enter Super I/O to reroute in7 (%d)",
3197 err);
3198 return;
3199 }
3200
3201 superio_select(data->sioaddr, GPIO);
3202
3203 reg2c = superio_inb(data->sioaddr, IT87_SIO_PINX2_REG);
3204 if (!(reg2c & BIT(1))) {
3205 dev_dbg(&pdev->dev,
3206 "Routing internal VCCH5V to in7 again");
3207
3208 reg2c |= BIT(1);
3209 superio_outb(data->sioaddr, IT87_SIO_PINX2_REG,
3210 reg2c);
3211 }
3212
3213 superio_exit(data->sioaddr);
3214}
3215
3216static int it87_resume(struct device *dev)
3217{
3218 struct platform_device *pdev = to_platform_device(dev);
3219 struct it87_data *data = dev_get_drvdata(dev);
3220
3221 it87_resume_sio(pdev);
3222
3223 mutex_lock(&data->update_lock);
3224
3225 it87_check_pwm(dev);
3226 it87_check_limit_regs(data);
3227 it87_check_voltage_monitors_reset(data);
3228 it87_check_tachometers_reset(pdev);
3229 it87_check_tachometers_16bit_mode(pdev);
3230
3231 it87_start_monitoring(data);
3232
3233 /* force update */
3234 data->valid = false;
3235
3236 mutex_unlock(&data->update_lock);
3237
3238 it87_update_device(dev);
3239
3240 return 0;
3241}
3242
3243static DEFINE_SIMPLE_DEV_PM_OPS(it87_dev_pm_ops, NULL, it87_resume);
3244
3245static struct platform_driver it87_driver = {
3246 .driver = {
3247 .name = DRVNAME,
3248 .pm = pm_sleep_ptr(&it87_dev_pm_ops),
3249 },
3250 .probe = it87_probe,
3251};
3252
3253static int __init it87_device_add(int index, unsigned short address,
3254 const struct it87_sio_data *sio_data)
3255{
3256 struct platform_device *pdev;
3257 struct resource res = {
3258 .start = address + IT87_EC_OFFSET,
3259 .end = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1,
3260 .name = DRVNAME,
3261 .flags = IORESOURCE_IO,
3262 };
3263 int err;
3264
3265 err = acpi_check_resource_conflict(&res);
3266 if (err) {
3267 if (!ignore_resource_conflict)
3268 return err;
3269 }
3270
3271 pdev = platform_device_alloc(DRVNAME, address);
3272 if (!pdev)
3273 return -ENOMEM;
3274
3275 err = platform_device_add_resources(pdev, &res, 1);
3276 if (err) {
3277 pr_err("Device resource addition failed (%d)\n", err);
3278 goto exit_device_put;
3279 }
3280
3281 err = platform_device_add_data(pdev, sio_data,
3282 sizeof(struct it87_sio_data));
3283 if (err) {
3284 pr_err("Platform data allocation failed\n");
3285 goto exit_device_put;
3286 }
3287
3288 err = platform_device_add(pdev);
3289 if (err) {
3290 pr_err("Device addition failed (%d)\n", err);
3291 goto exit_device_put;
3292 }
3293
3294 it87_pdev[index] = pdev;
3295 return 0;
3296
3297exit_device_put:
3298 platform_device_put(pdev);
3299 return err;
3300}
3301
3302/* callback function for DMI */
3303static int it87_dmi_cb(const struct dmi_system_id *dmi_entry)
3304{
3305 dmi_data = dmi_entry->driver_data;
3306
3307 if (dmi_data && dmi_data->skip_pwm)
3308 pr_info("Disabling pwm2 due to hardware constraints\n");
3309
3310 return 1;
3311}
3312
3313/*
3314 * On the Shuttle SN68PT, FAN_CTL2 is apparently not
3315 * connected to a fan, but to something else. One user
3316 * has reported instant system power-off when changing
3317 * the PWM2 duty cycle, so we disable it.
3318 * I use the board name string as the trigger in case
3319 * the same board is ever used in other systems.
3320 */
3321static struct it87_dmi_data nvidia_fn68pt = {
3322 .skip_pwm = BIT(1),
3323};
3324
3325#define IT87_DMI_MATCH_VND(vendor, name, cb, data) \
3326 { \
3327 .callback = cb, \
3328 .matches = { \
3329 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, vendor), \
3330 DMI_EXACT_MATCH(DMI_BOARD_NAME, name), \
3331 }, \
3332 .driver_data = data, \
3333 }
3334
3335static const struct dmi_system_id it87_dmi_table[] __initconst = {
3336 IT87_DMI_MATCH_VND("nVIDIA", "FN68PT", it87_dmi_cb, &nvidia_fn68pt),
3337 { }
3338
3339};
3340MODULE_DEVICE_TABLE(dmi, it87_dmi_table);
3341
3342static int __init sm_it87_init(void)
3343{
3344 int sioaddr[2] = { REG_2E, REG_4E };
3345 struct it87_sio_data sio_data;
3346 unsigned short isa_address[2];
3347 bool found = false;
3348 int i, err;
3349
3350 err = platform_driver_register(&it87_driver);
3351 if (err)
3352 return err;
3353
3354 dmi_check_system(it87_dmi_table);
3355
3356 for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
3357 memset(&sio_data, 0, sizeof(struct it87_sio_data));
3358 isa_address[i] = 0;
3359 err = it87_find(sioaddr[i], &isa_address[i], &sio_data);
3360 if (err || isa_address[i] == 0)
3361 continue;
3362 /*
3363 * Don't register second chip if its ISA address matches
3364 * the first chip's ISA address.
3365 */
3366 if (i && isa_address[i] == isa_address[0])
3367 break;
3368
3369 err = it87_device_add(i, isa_address[i], &sio_data);
3370 if (err)
3371 goto exit_dev_unregister;
3372
3373 found = true;
3374
3375 /*
3376 * IT8705F may respond on both SIO addresses.
3377 * Stop probing after finding one.
3378 */
3379 if (sio_data.type == it87)
3380 break;
3381 }
3382
3383 if (!found) {
3384 err = -ENODEV;
3385 goto exit_unregister;
3386 }
3387 return 0;
3388
3389exit_dev_unregister:
3390 /* NULL check handled by platform_device_unregister */
3391 platform_device_unregister(it87_pdev[0]);
3392exit_unregister:
3393 platform_driver_unregister(&it87_driver);
3394 return err;
3395}
3396
3397static void __exit sm_it87_exit(void)
3398{
3399 /* NULL check handled by platform_device_unregister */
3400 platform_device_unregister(it87_pdev[1]);
3401 platform_device_unregister(it87_pdev[0]);
3402 platform_driver_unregister(&it87_driver);
3403}
3404
3405MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
3406MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
3407module_param(update_vbat, bool, 0);
3408MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
3409module_param(fix_pwm_polarity, bool, 0);
3410MODULE_PARM_DESC(fix_pwm_polarity,
3411 "Force PWM polarity to active high (DANGEROUS)");
3412MODULE_LICENSE("GPL");
3413
3414module_init(sm_it87_init);
3415module_exit(sm_it87_exit);