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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4 */
5
6
7#ifndef _MXS_SAIF_H
8#define _MXS_SAIF_H
9
10#define SAIF_CTRL 0x0
11#define SAIF_STAT 0x10
12#define SAIF_DATA 0x20
13#define SAIF_VERSION 0X30
14
15/* SAIF_CTRL */
16#define BM_SAIF_CTRL_SFTRST 0x80000000
17#define BM_SAIF_CTRL_CLKGATE 0x40000000
18#define BP_SAIF_CTRL_BITCLK_MULT_RATE 27
19#define BM_SAIF_CTRL_BITCLK_MULT_RATE 0x38000000
20#define BF_SAIF_CTRL_BITCLK_MULT_RATE(v) \
21 (((v) << 27) & BM_SAIF_CTRL_BITCLK_MULT_RATE)
22#define BM_SAIF_CTRL_BITCLK_BASE_RATE 0x04000000
23#define BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN 0x02000000
24#define BM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN 0x01000000
25#define BP_SAIF_CTRL_RSRVD2 21
26#define BM_SAIF_CTRL_RSRVD2 0x00E00000
27
28#define BP_SAIF_CTRL_DMAWAIT_COUNT 16
29#define BM_SAIF_CTRL_DMAWAIT_COUNT 0x001F0000
30#define BF_SAIF_CTRL_DMAWAIT_COUNT(v) \
31 (((v) << 16) & BM_SAIF_CTRL_DMAWAIT_COUNT)
32#define BP_SAIF_CTRL_CHANNEL_NUM_SELECT 14
33#define BM_SAIF_CTRL_CHANNEL_NUM_SELECT 0x0000C000
34#define BF_SAIF_CTRL_CHANNEL_NUM_SELECT(v) \
35 (((v) << 14) & BM_SAIF_CTRL_CHANNEL_NUM_SELECT)
36#define BM_SAIF_CTRL_LRCLK_PULSE 0x00002000
37#define BM_SAIF_CTRL_BIT_ORDER 0x00001000
38#define BM_SAIF_CTRL_DELAY 0x00000800
39#define BM_SAIF_CTRL_JUSTIFY 0x00000400
40#define BM_SAIF_CTRL_LRCLK_POLARITY 0x00000200
41#define BM_SAIF_CTRL_BITCLK_EDGE 0x00000100
42#define BP_SAIF_CTRL_WORD_LENGTH 4
43#define BM_SAIF_CTRL_WORD_LENGTH 0x000000F0
44#define BF_SAIF_CTRL_WORD_LENGTH(v) \
45 (((v) << 4) & BM_SAIF_CTRL_WORD_LENGTH)
46#define BM_SAIF_CTRL_BITCLK_48XFS_ENABLE 0x00000008
47#define BM_SAIF_CTRL_SLAVE_MODE 0x00000004
48#define BM_SAIF_CTRL_READ_MODE 0x00000002
49#define BM_SAIF_CTRL_RUN 0x00000001
50
51/* SAIF_STAT */
52#define BM_SAIF_STAT_PRESENT 0x80000000
53#define BP_SAIF_STAT_RSRVD2 17
54#define BM_SAIF_STAT_RSRVD2 0x7FFE0000
55#define BF_SAIF_STAT_RSRVD2(v) \
56 (((v) << 17) & BM_SAIF_STAT_RSRVD2)
57#define BM_SAIF_STAT_DMA_PREQ 0x00010000
58#define BP_SAIF_STAT_RSRVD1 7
59#define BM_SAIF_STAT_RSRVD1 0x0000FF80
60#define BF_SAIF_STAT_RSRVD1(v) \
61 (((v) << 7) & BM_SAIF_STAT_RSRVD1)
62
63#define BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ 0x00000040
64#define BM_SAIF_STAT_FIFO_OVERFLOW_IRQ 0x00000020
65#define BM_SAIF_STAT_FIFO_SERVICE_IRQ 0x00000010
66#define BP_SAIF_STAT_RSRVD0 1
67#define BM_SAIF_STAT_RSRVD0 0x0000000E
68#define BF_SAIF_STAT_RSRVD0(v) \
69 (((v) << 1) & BM_SAIF_STAT_RSRVD0)
70#define BM_SAIF_STAT_BUSY 0x00000001
71
72/* SAFI_DATA */
73#define BP_SAIF_DATA_PCM_RIGHT 16
74#define BM_SAIF_DATA_PCM_RIGHT 0xFFFF0000
75#define BF_SAIF_DATA_PCM_RIGHT(v) \
76 (((v) << 16) & BM_SAIF_DATA_PCM_RIGHT)
77#define BP_SAIF_DATA_PCM_LEFT 0
78#define BM_SAIF_DATA_PCM_LEFT 0x0000FFFF
79#define BF_SAIF_DATA_PCM_LEFT(v) \
80 (((v) << 0) & BM_SAIF_DATA_PCM_LEFT)
81
82/* SAIF_VERSION */
83#define BP_SAIF_VERSION_MAJOR 24
84#define BM_SAIF_VERSION_MAJOR 0xFF000000
85#define BF_SAIF_VERSION_MAJOR(v) \
86 (((v) << 24) & BM_SAIF_VERSION_MAJOR)
87#define BP_SAIF_VERSION_MINOR 16
88#define BM_SAIF_VERSION_MINOR 0x00FF0000
89#define BF_SAIF_VERSION_MINOR(v) \
90 (((v) << 16) & BM_SAIF_VERSION_MINOR)
91#define BP_SAIF_VERSION_STEP 0
92#define BM_SAIF_VERSION_STEP 0x0000FFFF
93#define BF_SAIF_VERSION_STEP(v) \
94 (((v) << 0) & BM_SAIF_VERSION_STEP)
95
96#define MXS_SAIF_MCLK 0
97
98#include "mxs-pcm.h"
99
100struct mxs_saif {
101 struct device *dev;
102 struct clk *clk;
103 unsigned int mclk;
104 unsigned int mclk_in_use;
105 void __iomem *base;
106 unsigned int id;
107 unsigned int master_id;
108 unsigned int cur_rate;
109 unsigned int ongoing;
110
111 u32 fifo_underrun;
112 u32 fifo_overrun;
113
114 enum {
115 MXS_SAIF_STATE_STOPPED,
116 MXS_SAIF_STATE_RUNNING,
117 } state;
118};
119
120extern int mxs_saif_put_mclk(unsigned int saif_id);
121extern int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk,
122 unsigned int rate);
123#endif
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4 */
5
6
7#ifndef _MXS_SAIF_H
8#define _MXS_SAIF_H
9
10#define SAIF_CTRL 0x0
11#define SAIF_STAT 0x10
12#define SAIF_DATA 0x20
13#define SAIF_VERSION 0X30
14
15/* SAIF_CTRL */
16#define BM_SAIF_CTRL_SFTRST 0x80000000
17#define BM_SAIF_CTRL_CLKGATE 0x40000000
18#define BP_SAIF_CTRL_BITCLK_MULT_RATE 27
19#define BM_SAIF_CTRL_BITCLK_MULT_RATE 0x38000000
20#define BF_SAIF_CTRL_BITCLK_MULT_RATE(v) \
21 (((v) << 27) & BM_SAIF_CTRL_BITCLK_MULT_RATE)
22#define BM_SAIF_CTRL_BITCLK_BASE_RATE 0x04000000
23#define BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN 0x02000000
24#define BM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN 0x01000000
25#define BP_SAIF_CTRL_RSRVD2 21
26#define BM_SAIF_CTRL_RSRVD2 0x00E00000
27
28#define BP_SAIF_CTRL_DMAWAIT_COUNT 16
29#define BM_SAIF_CTRL_DMAWAIT_COUNT 0x001F0000
30#define BF_SAIF_CTRL_DMAWAIT_COUNT(v) \
31 (((v) << 16) & BM_SAIF_CTRL_DMAWAIT_COUNT)
32#define BP_SAIF_CTRL_CHANNEL_NUM_SELECT 14
33#define BM_SAIF_CTRL_CHANNEL_NUM_SELECT 0x0000C000
34#define BF_SAIF_CTRL_CHANNEL_NUM_SELECT(v) \
35 (((v) << 14) & BM_SAIF_CTRL_CHANNEL_NUM_SELECT)
36#define BM_SAIF_CTRL_LRCLK_PULSE 0x00002000
37#define BM_SAIF_CTRL_BIT_ORDER 0x00001000
38#define BM_SAIF_CTRL_DELAY 0x00000800
39#define BM_SAIF_CTRL_JUSTIFY 0x00000400
40#define BM_SAIF_CTRL_LRCLK_POLARITY 0x00000200
41#define BM_SAIF_CTRL_BITCLK_EDGE 0x00000100
42#define BP_SAIF_CTRL_WORD_LENGTH 4
43#define BM_SAIF_CTRL_WORD_LENGTH 0x000000F0
44#define BF_SAIF_CTRL_WORD_LENGTH(v) \
45 (((v) << 4) & BM_SAIF_CTRL_WORD_LENGTH)
46#define BM_SAIF_CTRL_BITCLK_48XFS_ENABLE 0x00000008
47#define BM_SAIF_CTRL_SLAVE_MODE 0x00000004
48#define BM_SAIF_CTRL_READ_MODE 0x00000002
49#define BM_SAIF_CTRL_RUN 0x00000001
50
51/* SAIF_STAT */
52#define BM_SAIF_STAT_PRESENT 0x80000000
53#define BP_SAIF_STAT_RSRVD2 17
54#define BM_SAIF_STAT_RSRVD2 0x7FFE0000
55#define BF_SAIF_STAT_RSRVD2(v) \
56 (((v) << 17) & BM_SAIF_STAT_RSRVD2)
57#define BM_SAIF_STAT_DMA_PREQ 0x00010000
58#define BP_SAIF_STAT_RSRVD1 7
59#define BM_SAIF_STAT_RSRVD1 0x0000FF80
60#define BF_SAIF_STAT_RSRVD1(v) \
61 (((v) << 7) & BM_SAIF_STAT_RSRVD1)
62
63#define BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ 0x00000040
64#define BM_SAIF_STAT_FIFO_OVERFLOW_IRQ 0x00000020
65#define BM_SAIF_STAT_FIFO_SERVICE_IRQ 0x00000010
66#define BP_SAIF_STAT_RSRVD0 1
67#define BM_SAIF_STAT_RSRVD0 0x0000000E
68#define BF_SAIF_STAT_RSRVD0(v) \
69 (((v) << 1) & BM_SAIF_STAT_RSRVD0)
70#define BM_SAIF_STAT_BUSY 0x00000001
71
72/* SAFI_DATA */
73#define BP_SAIF_DATA_PCM_RIGHT 16
74#define BM_SAIF_DATA_PCM_RIGHT 0xFFFF0000
75#define BF_SAIF_DATA_PCM_RIGHT(v) \
76 (((v) << 16) & BM_SAIF_DATA_PCM_RIGHT)
77#define BP_SAIF_DATA_PCM_LEFT 0
78#define BM_SAIF_DATA_PCM_LEFT 0x0000FFFF
79#define BF_SAIF_DATA_PCM_LEFT(v) \
80 (((v) << 0) & BM_SAIF_DATA_PCM_LEFT)
81
82/* SAIF_VERSION */
83#define BP_SAIF_VERSION_MAJOR 24
84#define BM_SAIF_VERSION_MAJOR 0xFF000000
85#define BF_SAIF_VERSION_MAJOR(v) \
86 (((v) << 24) & BM_SAIF_VERSION_MAJOR)
87#define BP_SAIF_VERSION_MINOR 16
88#define BM_SAIF_VERSION_MINOR 0x00FF0000
89#define BF_SAIF_VERSION_MINOR(v) \
90 (((v) << 16) & BM_SAIF_VERSION_MINOR)
91#define BP_SAIF_VERSION_STEP 0
92#define BM_SAIF_VERSION_STEP 0x0000FFFF
93#define BF_SAIF_VERSION_STEP(v) \
94 (((v) << 0) & BM_SAIF_VERSION_STEP)
95
96#define MXS_SAIF_MCLK 0
97
98#include "mxs-pcm.h"
99
100struct mxs_saif {
101 struct device *dev;
102 struct clk *clk;
103 unsigned int mclk;
104 unsigned int mclk_in_use;
105 void __iomem *base;
106 unsigned int id;
107 unsigned int master_id;
108 unsigned int cur_rate;
109 unsigned int ongoing;
110
111 u32 fifo_underrun;
112 u32 fifo_overrun;
113
114 enum {
115 MXS_SAIF_STATE_STOPPED,
116 MXS_SAIF_STATE_RUNNING,
117 } state;
118};
119
120extern int mxs_saif_put_mclk(unsigned int saif_id);
121extern int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk,
122 unsigned int rate);
123#endif