1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
   4 *
   5 * Copyright (C) 2004 Texas Instruments, Inc.
   6 * Copyright (C) 2004-2005 David Brownell
   7 *
   8 * OMAP2 & DMA support by Kyungmin Park <kyungmin.park@samsung.com>
   9 */
  10
  11#undef	DEBUG
  12#undef	VERBOSE
  13
  14#include <linux/module.h>
  15#include <linux/kernel.h>
  16#include <linux/ioport.h>
  17#include <linux/types.h>
  18#include <linux/errno.h>
  19#include <linux/delay.h>
  20#include <linux/slab.h>
  21#include <linux/timer.h>
  22#include <linux/list.h>
  23#include <linux/interrupt.h>
  24#include <linux/proc_fs.h>
  25#include <linux/mm.h>
  26#include <linux/moduleparam.h>
  27#include <linux/platform_device.h>
  28#include <linux/usb/ch9.h>
  29#include <linux/usb/gadget.h>
  30#include <linux/usb/otg.h>
  31#include <linux/dma-mapping.h>
  32#include <linux/clk.h>
  33#include <linux/err.h>
  34#include <linux/prefetch.h>
  35#include <linux/io.h>
  36
  37#include <asm/byteorder.h>
  38#include <asm/irq.h>
  39#include <asm/unaligned.h>
  40#include <asm/mach-types.h>
  41
  42#include <linux/omap-dma.h>
  43#include <linux/platform_data/usb-omap1.h>
  44
  45#include <linux/soc/ti/omap1-usb.h>
  46#include <linux/soc/ti/omap1-soc.h>
  47#include <linux/soc/ti/omap1-io.h>
  48
  49#include "omap_udc.h"
  50
  51#undef	USB_TRACE
  52
  53/* bulk DMA seems to be behaving for both IN and OUT */
  54#define	USE_DMA
  55
  56/* ISO too */
  57#define	USE_ISO
  58
  59#define	DRIVER_DESC	"OMAP UDC driver"
  60#define	DRIVER_VERSION	"4 October 2004"
  61
  62#define OMAP_DMA_USB_W2FC_TX0		29
  63#define OMAP_DMA_USB_W2FC_RX0		26
  64
  65/*
  66 * The OMAP UDC needs _very_ early endpoint setup:  before enabling the
  67 * D+ pullup to allow enumeration.  That's too early for the gadget
  68 * framework to use from usb_endpoint_enable(), which happens after
  69 * enumeration as part of activating an interface.  (But if we add an
  70 * optional new "UDC not yet running" state to the gadget driver model,
  71 * even just during driver binding, the endpoint autoconfig logic is the
  72 * natural spot to manufacture new endpoints.)
  73 *
  74 * So instead of using endpoint enable calls to control the hardware setup,
  75 * this driver defines a "fifo mode" parameter.  It's used during driver
  76 * initialization to choose among a set of pre-defined endpoint configs.
  77 * See omap_udc_setup() for available modes, or to add others.  That code
  78 * lives in an init section, so use this driver as a module if you need
  79 * to change the fifo mode after the kernel boots.
  80 *
  81 * Gadget drivers normally ignore endpoints they don't care about, and
  82 * won't include them in configuration descriptors.  That means only
  83 * misbehaving hosts would even notice they exist.
  84 */
  85#ifdef	USE_ISO
  86static unsigned fifo_mode = 3;
  87#else
  88static unsigned fifo_mode;
  89#endif
  90
  91/* "modprobe omap_udc fifo_mode=42", or else as a kernel
  92 * boot parameter "omap_udc:fifo_mode=42"
  93 */
  94module_param(fifo_mode, uint, 0);
  95MODULE_PARM_DESC(fifo_mode, "endpoint configuration");
  96
  97#ifdef	USE_DMA
  98static bool use_dma = 1;
  99
 100/* "modprobe omap_udc use_dma=y", or else as a kernel
 101 * boot parameter "omap_udc:use_dma=y"
 102 */
 103module_param(use_dma, bool, 0);
 104MODULE_PARM_DESC(use_dma, "enable/disable DMA");
 105#else	/* !USE_DMA */
 106
 107/* save a bit of code */
 108#define	use_dma		0
 109#endif	/* !USE_DMA */
 110
 111
 112static const char driver_name[] = "omap_udc";
 113static const char driver_desc[] = DRIVER_DESC;
 114
 115/*-------------------------------------------------------------------------*/
 116
 117/* there's a notion of "current endpoint" for modifying endpoint
 118 * state, and PIO access to its FIFO.
 119 */
 120
 121static void use_ep(struct omap_ep *ep, u16 select)
 122{
 123	u16	num = ep->bEndpointAddress & 0x0f;
 124
 125	if (ep->bEndpointAddress & USB_DIR_IN)
 126		num |= UDC_EP_DIR;
 127	omap_writew(num | select, UDC_EP_NUM);
 128	/* when select, MUST deselect later !! */
 129}
 130
 131static inline void deselect_ep(void)
 132{
 133	u16 w;
 134
 135	w = omap_readw(UDC_EP_NUM);
 136	w &= ~UDC_EP_SEL;
 137	omap_writew(w, UDC_EP_NUM);
 138	/* 6 wait states before TX will happen */
 139}
 140
 141static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
 142
 143/*-------------------------------------------------------------------------*/
 144
 145static int omap_ep_enable(struct usb_ep *_ep,
 146		const struct usb_endpoint_descriptor *desc)
 147{
 148	struct omap_ep	*ep = container_of(_ep, struct omap_ep, ep);
 149	struct omap_udc	*udc;
 150	unsigned long	flags;
 151	u16		maxp;
 152
 153	/* catch various bogus parameters */
 154	if (!_ep || !desc
 155			|| desc->bDescriptorType != USB_DT_ENDPOINT
 156			|| ep->bEndpointAddress != desc->bEndpointAddress
 157			|| ep->maxpacket < usb_endpoint_maxp(desc)) {
 158		DBG("%s, bad ep or descriptor\n", __func__);
 159		return -EINVAL;
 160	}
 161	maxp = usb_endpoint_maxp(desc);
 162	if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
 163				&& maxp != ep->maxpacket)
 164			|| usb_endpoint_maxp(desc) > ep->maxpacket
 165			|| !desc->wMaxPacketSize) {
 166		DBG("%s, bad %s maxpacket\n", __func__, _ep->name);
 167		return -ERANGE;
 168	}
 169
 170#ifdef	USE_ISO
 171	if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
 172				&& desc->bInterval != 1)) {
 173		/* hardware wants period = 1; USB allows 2^(Interval-1) */
 174		DBG("%s, unsupported ISO period %dms\n", _ep->name,
 175				1 << (desc->bInterval - 1));
 176		return -EDOM;
 177	}
 178#else
 179	if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 180		DBG("%s, ISO nyet\n", _ep->name);
 181		return -EDOM;
 182	}
 183#endif
 184
 185	/* xfer types must match, except that interrupt ~= bulk */
 186	if (ep->bmAttributes != desc->bmAttributes
 187			&& ep->bmAttributes != USB_ENDPOINT_XFER_BULK
 188			&& desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
 189		DBG("%s, %s type mismatch\n", __func__, _ep->name);
 190		return -EINVAL;
 191	}
 192
 193	udc = ep->udc;
 194	if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
 195		DBG("%s, bogus device state\n", __func__);
 196		return -ESHUTDOWN;
 197	}
 198
 199	spin_lock_irqsave(&udc->lock, flags);
 200
 201	ep->ep.desc = desc;
 202	ep->irqs = 0;
 203	ep->stopped = 0;
 204	ep->ep.maxpacket = maxp;
 205
 206	/* set endpoint to initial state */
 207	ep->dma_channel = 0;
 208	ep->has_dma = 0;
 209	ep->lch = -1;
 210	use_ep(ep, UDC_EP_SEL);
 211	omap_writew(udc->clr_halt, UDC_CTRL);
 212	ep->ackwait = 0;
 213	deselect_ep();
 214
 215	if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
 216		list_add(&ep->iso, &udc->iso);
 217
 218	/* maybe assign a DMA channel to this endpoint */
 219	if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
 220		/* FIXME ISO can dma, but prefers first channel */
 221		dma_channel_claim(ep, 0);
 222
 223	/* PIO OUT may RX packets */
 224	if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
 225			&& !ep->has_dma
 226			&& !(ep->bEndpointAddress & USB_DIR_IN)) {
 227		omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 228		ep->ackwait = 1 + ep->double_buf;
 229	}
 230
 231	spin_unlock_irqrestore(&udc->lock, flags);
 232	VDBG("%s enabled\n", _ep->name);
 233	return 0;
 234}
 235
 236static void nuke(struct omap_ep *, int status);
 237
 238static int omap_ep_disable(struct usb_ep *_ep)
 239{
 240	struct omap_ep	*ep = container_of(_ep, struct omap_ep, ep);
 241	unsigned long	flags;
 242
 243	if (!_ep || !ep->ep.desc) {
 244		DBG("%s, %s not enabled\n", __func__,
 245			_ep ? ep->ep.name : NULL);
 246		return -EINVAL;
 247	}
 248
 249	spin_lock_irqsave(&ep->udc->lock, flags);
 250	ep->ep.desc = NULL;
 251	nuke(ep, -ESHUTDOWN);
 252	ep->ep.maxpacket = ep->maxpacket;
 253	ep->has_dma = 0;
 254	omap_writew(UDC_SET_HALT, UDC_CTRL);
 255	list_del_init(&ep->iso);
 256	del_timer(&ep->timer);
 257
 258	spin_unlock_irqrestore(&ep->udc->lock, flags);
 259
 260	VDBG("%s disabled\n", _ep->name);
 261	return 0;
 262}
 263
 264/*-------------------------------------------------------------------------*/
 265
 266static struct usb_request *
 267omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
 268{
 269	struct omap_req	*req;
 270
 271	req = kzalloc(sizeof(*req), gfp_flags);
 272	if (!req)
 273		return NULL;
 274
 275	INIT_LIST_HEAD(&req->queue);
 276
 277	return &req->req;
 278}
 279
 280static void
 281omap_free_request(struct usb_ep *ep, struct usb_request *_req)
 282{
 283	struct omap_req	*req = container_of(_req, struct omap_req, req);
 284
 285	kfree(req);
 286}
 287
 288/*-------------------------------------------------------------------------*/
 289
 290static void
 291done(struct omap_ep *ep, struct omap_req *req, int status)
 292{
 293	struct omap_udc		*udc = ep->udc;
 294	unsigned		stopped = ep->stopped;
 295
 296	list_del_init(&req->queue);
 297
 298	if (req->req.status == -EINPROGRESS)
 299		req->req.status = status;
 300	else
 301		status = req->req.status;
 302
 303	if (use_dma && ep->has_dma)
 304		usb_gadget_unmap_request(&udc->gadget, &req->req,
 305				(ep->bEndpointAddress & USB_DIR_IN));
 306
 307#ifndef	USB_TRACE
 308	if (status && status != -ESHUTDOWN)
 309#endif
 310		VDBG("complete %s req %p stat %d len %u/%u\n",
 311			ep->ep.name, &req->req, status,
 312			req->req.actual, req->req.length);
 313
 314	/* don't modify queue heads during completion callback */
 315	ep->stopped = 1;
 316	spin_unlock(&ep->udc->lock);
 317	usb_gadget_giveback_request(&ep->ep, &req->req);
 318	spin_lock(&ep->udc->lock);
 319	ep->stopped = stopped;
 320}
 321
 322/*-------------------------------------------------------------------------*/
 323
 324#define UDC_FIFO_FULL		(UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
 325#define UDC_FIFO_UNWRITABLE	(UDC_EP_HALTED | UDC_FIFO_FULL)
 326
 327#define FIFO_EMPTY	(UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
 328#define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
 329
 330static inline int
 331write_packet(u8 *buf, struct omap_req *req, unsigned max)
 332{
 333	unsigned	len;
 334	u16		*wp;
 335
 336	len = min(req->req.length - req->req.actual, max);
 337	req->req.actual += len;
 338
 339	max = len;
 340	if (likely((((int)buf) & 1) == 0)) {
 341		wp = (u16 *)buf;
 342		while (max >= 2) {
 343			omap_writew(*wp++, UDC_DATA);
 344			max -= 2;
 345		}
 346		buf = (u8 *)wp;
 347	}
 348	while (max--)
 349		omap_writeb(*buf++, UDC_DATA);
 350	return len;
 351}
 352
 353/* FIXME change r/w fifo calling convention */
 354
 355
 356/* return:  0 = still running, 1 = completed, negative = errno */
 357static int write_fifo(struct omap_ep *ep, struct omap_req *req)
 358{
 359	u8		*buf;
 360	unsigned	count;
 361	int		is_last;
 362	u16		ep_stat;
 363
 364	buf = req->req.buf + req->req.actual;
 365	prefetch(buf);
 366
 367	/* PIO-IN isn't double buffered except for iso */
 368	ep_stat = omap_readw(UDC_STAT_FLG);
 369	if (ep_stat & UDC_FIFO_UNWRITABLE)
 370		return 0;
 371
 372	count = ep->ep.maxpacket;
 373	count = write_packet(buf, req, count);
 374	omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 375	ep->ackwait = 1;
 376
 377	/* last packet is often short (sometimes a zlp) */
 378	if (count != ep->ep.maxpacket)
 379		is_last = 1;
 380	else if (req->req.length == req->req.actual
 381			&& !req->req.zero)
 382		is_last = 1;
 383	else
 384		is_last = 0;
 385
 386	/* NOTE:  requests complete when all IN data is in a
 387	 * FIFO (or sometimes later, if a zlp was needed).
 388	 * Use usb_ep_fifo_status() where needed.
 389	 */
 390	if (is_last)
 391		done(ep, req, 0);
 392	return is_last;
 393}
 394
 395static inline int
 396read_packet(u8 *buf, struct omap_req *req, unsigned avail)
 397{
 398	unsigned	len;
 399	u16		*wp;
 400
 401	len = min(req->req.length - req->req.actual, avail);
 402	req->req.actual += len;
 403	avail = len;
 404
 405	if (likely((((int)buf) & 1) == 0)) {
 406		wp = (u16 *)buf;
 407		while (avail >= 2) {
 408			*wp++ = omap_readw(UDC_DATA);
 409			avail -= 2;
 410		}
 411		buf = (u8 *)wp;
 412	}
 413	while (avail--)
 414		*buf++ = omap_readb(UDC_DATA);
 415	return len;
 416}
 417
 418/* return:  0 = still running, 1 = queue empty, negative = errno */
 419static int read_fifo(struct omap_ep *ep, struct omap_req *req)
 420{
 421	u8		*buf;
 422	unsigned	count, avail;
 423	int		is_last;
 424
 425	buf = req->req.buf + req->req.actual;
 426	prefetchw(buf);
 427
 428	for (;;) {
 429		u16	ep_stat = omap_readw(UDC_STAT_FLG);
 430
 431		is_last = 0;
 432		if (ep_stat & FIFO_EMPTY) {
 433			if (!ep->double_buf)
 434				break;
 435			ep->fnf = 1;
 436		}
 437		if (ep_stat & UDC_EP_HALTED)
 438			break;
 439
 440		if (ep_stat & UDC_FIFO_FULL)
 441			avail = ep->ep.maxpacket;
 442		else  {
 443			avail = omap_readw(UDC_RXFSTAT);
 444			ep->fnf = ep->double_buf;
 445		}
 446		count = read_packet(buf, req, avail);
 447
 448		/* partial packet reads may not be errors */
 449		if (count < ep->ep.maxpacket) {
 450			is_last = 1;
 451			/* overflowed this request?  flush extra data */
 452			if (count != avail) {
 453				req->req.status = -EOVERFLOW;
 454				avail -= count;
 455				while (avail--)
 456					omap_readw(UDC_DATA);
 457			}
 458		} else if (req->req.length == req->req.actual)
 459			is_last = 1;
 460		else
 461			is_last = 0;
 462
 463		if (!ep->bEndpointAddress)
 464			break;
 465		if (is_last)
 466			done(ep, req, 0);
 467		break;
 468	}
 469	return is_last;
 470}
 471
 472/*-------------------------------------------------------------------------*/
 473
 474static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
 475{
 476	dma_addr_t	end;
 477
 478	/* IN-DMA needs this on fault/cancel paths, so 15xx misreports
 479	 * the last transfer's bytecount by more than a FIFO's worth.
 480	 */
 481	if (cpu_is_omap15xx())
 482		return 0;
 483
 484	end = omap_get_dma_src_pos(ep->lch);
 485	if (end == ep->dma_counter)
 486		return 0;
 487
 488	end |= start & (0xffff << 16);
 489	if (end < start)
 490		end += 0x10000;
 491	return end - start;
 492}
 493
 494static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
 495{
 496	dma_addr_t	end;
 497
 498	end = omap_get_dma_dst_pos(ep->lch);
 499	if (end == ep->dma_counter)
 500		return 0;
 501
 502	end |= start & (0xffff << 16);
 503	if (cpu_is_omap15xx())
 504		end++;
 505	if (end < start)
 506		end += 0x10000;
 507	return end - start;
 508}
 509
 510
 511/* Each USB transfer request using DMA maps to one or more DMA transfers.
 512 * When DMA completion isn't request completion, the UDC continues with
 513 * the next DMA transfer for that USB transfer.
 514 */
 515
 516static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
 517{
 518	u16		txdma_ctrl, w;
 519	unsigned	length = req->req.length - req->req.actual;
 520	const int	sync_mode = cpu_is_omap15xx()
 521				? OMAP_DMA_SYNC_FRAME
 522				: OMAP_DMA_SYNC_ELEMENT;
 523	int		dma_trigger = 0;
 524
 525	/* measure length in either bytes or packets */
 526	if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
 527			|| (cpu_is_omap15xx() && length < ep->maxpacket)) {
 528		txdma_ctrl = UDC_TXN_EOT | length;
 529		omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
 530				length, 1, sync_mode, dma_trigger, 0);
 531	} else {
 532		length = min(length / ep->maxpacket,
 533				(unsigned) UDC_TXN_TSC + 1);
 534		txdma_ctrl = length;
 535		omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 536				ep->ep.maxpacket >> 1, length, sync_mode,
 537				dma_trigger, 0);
 538		length *= ep->maxpacket;
 539	}
 540	omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 541		OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 542		0, 0);
 543
 544	omap_start_dma(ep->lch);
 545	ep->dma_counter = omap_get_dma_src_pos(ep->lch);
 546	w = omap_readw(UDC_DMA_IRQ_EN);
 547	w |= UDC_TX_DONE_IE(ep->dma_channel);
 548	omap_writew(w, UDC_DMA_IRQ_EN);
 549	omap_writew(UDC_TXN_START | txdma_ctrl, UDC_TXDMA(ep->dma_channel));
 550	req->dma_bytes = length;
 551}
 552
 553static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
 554{
 555	u16 w;
 556
 557	if (status == 0) {
 558		req->req.actual += req->dma_bytes;
 559
 560		/* return if this request needs to send data or zlp */
 561		if (req->req.actual < req->req.length)
 562			return;
 563		if (req->req.zero
 564				&& req->dma_bytes != 0
 565				&& (req->req.actual % ep->maxpacket) == 0)
 566			return;
 567	} else
 568		req->req.actual += dma_src_len(ep, req->req.dma
 569							+ req->req.actual);
 570
 571	/* tx completion */
 572	omap_stop_dma(ep->lch);
 573	w = omap_readw(UDC_DMA_IRQ_EN);
 574	w &= ~UDC_TX_DONE_IE(ep->dma_channel);
 575	omap_writew(w, UDC_DMA_IRQ_EN);
 576	done(ep, req, status);
 577}
 578
 579static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
 580{
 581	unsigned packets = req->req.length - req->req.actual;
 582	int dma_trigger = 0;
 583	u16 w;
 584
 585	/* set up this DMA transfer, enable the fifo, start */
 586	packets /= ep->ep.maxpacket;
 587	packets = min(packets, (unsigned)UDC_RXN_TC + 1);
 588	req->dma_bytes = packets * ep->ep.maxpacket;
 589	omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 590			ep->ep.maxpacket >> 1, packets,
 591			OMAP_DMA_SYNC_ELEMENT,
 592			dma_trigger, 0);
 593	omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 594		OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 595		0, 0);
 596	ep->dma_counter = omap_get_dma_dst_pos(ep->lch);
 597
 598	omap_writew(UDC_RXN_STOP | (packets - 1), UDC_RXDMA(ep->dma_channel));
 599	w = omap_readw(UDC_DMA_IRQ_EN);
 600	w |= UDC_RX_EOT_IE(ep->dma_channel);
 601	omap_writew(w, UDC_DMA_IRQ_EN);
 602	omap_writew(ep->bEndpointAddress & 0xf, UDC_EP_NUM);
 603	omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 604
 605	omap_start_dma(ep->lch);
 606}
 607
 608static void
 609finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
 610{
 611	u16	count, w;
 612
 613	if (status == 0)
 614		ep->dma_counter = (u16) (req->req.dma + req->req.actual);
 615	count = dma_dest_len(ep, req->req.dma + req->req.actual);
 616	count += req->req.actual;
 617	if (one)
 618		count--;
 619	if (count <= req->req.length)
 620		req->req.actual = count;
 621
 622	if (count != req->dma_bytes || status)
 623		omap_stop_dma(ep->lch);
 624
 625	/* if this wasn't short, request may need another transfer */
 626	else if (req->req.actual < req->req.length)
 627		return;
 628
 629	/* rx completion */
 630	w = omap_readw(UDC_DMA_IRQ_EN);
 631	w &= ~UDC_RX_EOT_IE(ep->dma_channel);
 632	omap_writew(w, UDC_DMA_IRQ_EN);
 633	done(ep, req, status);
 634}
 635
 636static void dma_irq(struct omap_udc *udc, u16 irq_src)
 637{
 638	u16		dman_stat = omap_readw(UDC_DMAN_STAT);
 639	struct omap_ep	*ep;
 640	struct omap_req	*req;
 641
 642	/* IN dma: tx to host */
 643	if (irq_src & UDC_TXN_DONE) {
 644		ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
 645		ep->irqs++;
 646		/* can see TXN_DONE after dma abort */
 647		if (!list_empty(&ep->queue)) {
 648			req = container_of(ep->queue.next,
 649						struct omap_req, queue);
 650			finish_in_dma(ep, req, 0);
 651		}
 652		omap_writew(UDC_TXN_DONE, UDC_IRQ_SRC);
 653
 654		if (!list_empty(&ep->queue)) {
 655			req = container_of(ep->queue.next,
 656					struct omap_req, queue);
 657			next_in_dma(ep, req);
 658		}
 659	}
 660
 661	/* OUT dma: rx from host */
 662	if (irq_src & UDC_RXN_EOT) {
 663		ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 664		ep->irqs++;
 665		/* can see RXN_EOT after dma abort */
 666		if (!list_empty(&ep->queue)) {
 667			req = container_of(ep->queue.next,
 668					struct omap_req, queue);
 669			finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
 670		}
 671		omap_writew(UDC_RXN_EOT, UDC_IRQ_SRC);
 672
 673		if (!list_empty(&ep->queue)) {
 674			req = container_of(ep->queue.next,
 675					struct omap_req, queue);
 676			next_out_dma(ep, req);
 677		}
 678	}
 679
 680	if (irq_src & UDC_RXN_CNT) {
 681		ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 682		ep->irqs++;
 683		/* omap15xx does this unasked... */
 684		VDBG("%s, RX_CNT irq?\n", ep->ep.name);
 685		omap_writew(UDC_RXN_CNT, UDC_IRQ_SRC);
 686	}
 687}
 688
 689static void dma_error(int lch, u16 ch_status, void *data)
 690{
 691	struct omap_ep	*ep = data;
 692
 693	/* if ch_status & OMAP_DMA_DROP_IRQ ... */
 694	/* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
 695	ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
 696
 697	/* complete current transfer ... */
 698}
 699
 700static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
 701{
 702	u16	reg;
 703	int	status, restart, is_in;
 704	int	dma_channel;
 705
 706	is_in = ep->bEndpointAddress & USB_DIR_IN;
 707	if (is_in)
 708		reg = omap_readw(UDC_TXDMA_CFG);
 709	else
 710		reg = omap_readw(UDC_RXDMA_CFG);
 711	reg |= UDC_DMA_REQ;		/* "pulse" activated */
 712
 713	ep->dma_channel = 0;
 714	ep->lch = -1;
 715	if (channel == 0 || channel > 3) {
 716		if ((reg & 0x0f00) == 0)
 717			channel = 3;
 718		else if ((reg & 0x00f0) == 0)
 719			channel = 2;
 720		else if ((reg & 0x000f) == 0)	/* preferred for ISO */
 721			channel = 1;
 722		else {
 723			status = -EMLINK;
 724			goto just_restart;
 725		}
 726	}
 727	reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
 728	ep->dma_channel = channel;
 729
 730	if (is_in) {
 731		dma_channel = OMAP_DMA_USB_W2FC_TX0 - 1 + channel;
 732		status = omap_request_dma(dma_channel,
 733			ep->ep.name, dma_error, ep, &ep->lch);
 734		if (status == 0) {
 735			omap_writew(reg, UDC_TXDMA_CFG);
 736			/* EMIFF or SDRC */
 737			omap_set_dma_src_burst_mode(ep->lch,
 738						OMAP_DMA_DATA_BURST_4);
 739			omap_set_dma_src_data_pack(ep->lch, 1);
 740			/* TIPB */
 741			omap_set_dma_dest_params(ep->lch,
 742				OMAP_DMA_PORT_TIPB,
 743				OMAP_DMA_AMODE_CONSTANT,
 744				UDC_DATA_DMA,
 745				0, 0);
 746		}
 747	} else {
 748		dma_channel = OMAP_DMA_USB_W2FC_RX0 - 1 + channel;
 749		status = omap_request_dma(dma_channel,
 750			ep->ep.name, dma_error, ep, &ep->lch);
 751		if (status == 0) {
 752			omap_writew(reg, UDC_RXDMA_CFG);
 753			/* TIPB */
 754			omap_set_dma_src_params(ep->lch,
 755				OMAP_DMA_PORT_TIPB,
 756				OMAP_DMA_AMODE_CONSTANT,
 757				UDC_DATA_DMA,
 758				0, 0);
 759			/* EMIFF or SDRC */
 760			omap_set_dma_dest_burst_mode(ep->lch,
 761						OMAP_DMA_DATA_BURST_4);
 762			omap_set_dma_dest_data_pack(ep->lch, 1);
 763		}
 764	}
 765	if (status)
 766		ep->dma_channel = 0;
 767	else {
 768		ep->has_dma = 1;
 769		omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
 770
 771		/* channel type P: hw synch (fifo) */
 772		if (!cpu_is_omap15xx())
 773			omap_set_dma_channel_mode(ep->lch, OMAP_DMA_LCH_P);
 774	}
 775
 776just_restart:
 777	/* restart any queue, even if the claim failed  */
 778	restart = !ep->stopped && !list_empty(&ep->queue);
 779
 780	if (status)
 781		DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
 782			restart ? " (restart)" : "");
 783	else
 784		DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
 785			is_in ? 't' : 'r',
 786			ep->dma_channel - 1, ep->lch,
 787			restart ? " (restart)" : "");
 788
 789	if (restart) {
 790		struct omap_req	*req;
 791		req = container_of(ep->queue.next, struct omap_req, queue);
 792		if (ep->has_dma)
 793			(is_in ? next_in_dma : next_out_dma)(ep, req);
 794		else {
 795			use_ep(ep, UDC_EP_SEL);
 796			(is_in ? write_fifo : read_fifo)(ep, req);
 797			deselect_ep();
 798			if (!is_in) {
 799				omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 800				ep->ackwait = 1 + ep->double_buf;
 801			}
 802			/* IN: 6 wait states before it'll tx */
 803		}
 804	}
 805}
 806
 807static void dma_channel_release(struct omap_ep *ep)
 808{
 809	int		shift = 4 * (ep->dma_channel - 1);
 810	u16		mask = 0x0f << shift;
 811	struct omap_req	*req;
 812	int		active;
 813
 814	/* abort any active usb transfer request */
 815	if (!list_empty(&ep->queue))
 816		req = container_of(ep->queue.next, struct omap_req, queue);
 817	else
 818		req = NULL;
 819
 820	active = omap_get_dma_active_status(ep->lch);
 821
 822	DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
 823			active ? "active" : "idle",
 824			(ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
 825			ep->dma_channel - 1, req);
 826
 827	/* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
 828	 * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
 829	 */
 830
 831	/* wait till current packet DMA finishes, and fifo empties */
 832	if (ep->bEndpointAddress & USB_DIR_IN) {
 833		omap_writew((omap_readw(UDC_TXDMA_CFG) & ~mask) | UDC_DMA_REQ,
 834					UDC_TXDMA_CFG);
 835
 836		if (req) {
 837			finish_in_dma(ep, req, -ECONNRESET);
 838
 839			/* clear FIFO; hosts probably won't empty it */
 840			use_ep(ep, UDC_EP_SEL);
 841			omap_writew(UDC_CLR_EP, UDC_CTRL);
 842			deselect_ep();
 843		}
 844		while (omap_readw(UDC_TXDMA_CFG) & mask)
 845			udelay(10);
 846	} else {
 847		omap_writew((omap_readw(UDC_RXDMA_CFG) & ~mask) | UDC_DMA_REQ,
 848					UDC_RXDMA_CFG);
 849
 850		/* dma empties the fifo */
 851		while (omap_readw(UDC_RXDMA_CFG) & mask)
 852			udelay(10);
 853		if (req)
 854			finish_out_dma(ep, req, -ECONNRESET, 0);
 855	}
 856	omap_free_dma(ep->lch);
 857	ep->dma_channel = 0;
 858	ep->lch = -1;
 859	/* has_dma still set, till endpoint is fully quiesced */
 860}
 861
 862
 863/*-------------------------------------------------------------------------*/
 864
 865static int
 866omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 867{
 868	struct omap_ep	*ep = container_of(_ep, struct omap_ep, ep);
 869	struct omap_req	*req = container_of(_req, struct omap_req, req);
 870	struct omap_udc	*udc;
 871	unsigned long	flags;
 872	int		is_iso = 0;
 873
 874	/* catch various bogus parameters */
 875	if (!_req || !req->req.complete || !req->req.buf
 876			|| !list_empty(&req->queue)) {
 877		DBG("%s, bad params\n", __func__);
 878		return -EINVAL;
 879	}
 880	if (!_ep || (!ep->ep.desc && ep->bEndpointAddress)) {
 881		DBG("%s, bad ep\n", __func__);
 882		return -EINVAL;
 883	}
 884	if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 885		if (req->req.length > ep->ep.maxpacket)
 886			return -EMSGSIZE;
 887		is_iso = 1;
 888	}
 889
 890	/* this isn't bogus, but OMAP DMA isn't the only hardware to
 891	 * have a hard time with partial packet reads...  reject it.
 892	 */
 893	if (use_dma
 894			&& ep->has_dma
 895			&& ep->bEndpointAddress != 0
 896			&& (ep->bEndpointAddress & USB_DIR_IN) == 0
 897			&& (req->req.length % ep->ep.maxpacket) != 0) {
 898		DBG("%s, no partial packet OUT reads\n", __func__);
 899		return -EMSGSIZE;
 900	}
 901
 902	udc = ep->udc;
 903	if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 904		return -ESHUTDOWN;
 905
 906	if (use_dma && ep->has_dma)
 907		usb_gadget_map_request(&udc->gadget, &req->req,
 908				(ep->bEndpointAddress & USB_DIR_IN));
 909
 910	VDBG("%s queue req %p, len %d buf %p\n",
 911		ep->ep.name, _req, _req->length, _req->buf);
 912
 913	spin_lock_irqsave(&udc->lock, flags);
 914
 915	req->req.status = -EINPROGRESS;
 916	req->req.actual = 0;
 917
 918	/* maybe kickstart non-iso i/o queues */
 919	if (is_iso) {
 920		u16 w;
 921
 922		w = omap_readw(UDC_IRQ_EN);
 923		w |= UDC_SOF_IE;
 924		omap_writew(w, UDC_IRQ_EN);
 925	} else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
 926		int	is_in;
 927
 928		if (ep->bEndpointAddress == 0) {
 929			if (!udc->ep0_pending || !list_empty(&ep->queue)) {
 930				spin_unlock_irqrestore(&udc->lock, flags);
 931				return -EL2HLT;
 932			}
 933
 934			/* empty DATA stage? */
 935			is_in = udc->ep0_in;
 936			if (!req->req.length) {
 937
 938				/* chip became CONFIGURED or ADDRESSED
 939				 * earlier; drivers may already have queued
 940				 * requests to non-control endpoints
 941				 */
 942				if (udc->ep0_set_config) {
 943					u16	irq_en = omap_readw(UDC_IRQ_EN);
 944
 945					irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
 946					if (!udc->ep0_reset_config)
 947						irq_en |= UDC_EPN_RX_IE
 948							| UDC_EPN_TX_IE;
 949					omap_writew(irq_en, UDC_IRQ_EN);
 950				}
 951
 952				/* STATUS for zero length DATA stages is
 953				 * always an IN ... even for IN transfers,
 954				 * a weird case which seem to stall OMAP.
 955				 */
 956				omap_writew(UDC_EP_SEL | UDC_EP_DIR,
 957						UDC_EP_NUM);
 958				omap_writew(UDC_CLR_EP, UDC_CTRL);
 959				omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 960				omap_writew(UDC_EP_DIR, UDC_EP_NUM);
 961
 962				/* cleanup */
 963				udc->ep0_pending = 0;
 964				done(ep, req, 0);
 965				req = NULL;
 966
 967			/* non-empty DATA stage */
 968			} else if (is_in) {
 969				omap_writew(UDC_EP_SEL | UDC_EP_DIR,
 970						UDC_EP_NUM);
 971			} else {
 972				if (udc->ep0_setup)
 973					goto irq_wait;
 974				omap_writew(UDC_EP_SEL, UDC_EP_NUM);
 975			}
 976		} else {
 977			is_in = ep->bEndpointAddress & USB_DIR_IN;
 978			if (!ep->has_dma)
 979				use_ep(ep, UDC_EP_SEL);
 980			/* if ISO: SOF IRQs must be enabled/disabled! */
 981		}
 982
 983		if (ep->has_dma)
 984			(is_in ? next_in_dma : next_out_dma)(ep, req);
 985		else if (req) {
 986			if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
 987				req = NULL;
 988			deselect_ep();
 989			if (!is_in) {
 990				omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 991				ep->ackwait = 1 + ep->double_buf;
 992			}
 993			/* IN: 6 wait states before it'll tx */
 994		}
 995	}
 996
 997irq_wait:
 998	/* irq handler advances the queue */
 999	if (req != NULL)
1000		list_add_tail(&req->queue, &ep->queue);
1001	spin_unlock_irqrestore(&udc->lock, flags);
1002
1003	return 0;
1004}
1005
1006static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1007{
1008	struct omap_ep	*ep = container_of(_ep, struct omap_ep, ep);
1009	struct omap_req	*req = NULL, *iter;
1010	unsigned long	flags;
1011
1012	if (!_ep || !_req)
1013		return -EINVAL;
1014
1015	spin_lock_irqsave(&ep->udc->lock, flags);
1016
1017	/* make sure it's actually queued on this endpoint */
1018	list_for_each_entry(iter, &ep->queue, queue) {
1019		if (&iter->req != _req)
1020			continue;
1021		req = iter;
1022		break;
1023	}
1024	if (!req) {
1025		spin_unlock_irqrestore(&ep->udc->lock, flags);
1026		return -EINVAL;
1027	}
1028
1029	if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1030		int channel = ep->dma_channel;
1031
1032		/* releasing the channel cancels the request,
1033		 * reclaiming the channel restarts the queue
1034		 */
1035		dma_channel_release(ep);
1036		dma_channel_claim(ep, channel);
1037	} else
1038		done(ep, req, -ECONNRESET);
1039	spin_unlock_irqrestore(&ep->udc->lock, flags);
1040	return 0;
1041}
1042
1043/*-------------------------------------------------------------------------*/
1044
1045static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1046{
1047	struct omap_ep	*ep = container_of(_ep, struct omap_ep, ep);
1048	unsigned long	flags;
1049	int		status = -EOPNOTSUPP;
1050
1051	spin_lock_irqsave(&ep->udc->lock, flags);
1052
1053	/* just use protocol stalls for ep0; real halts are annoying */
1054	if (ep->bEndpointAddress == 0) {
1055		if (!ep->udc->ep0_pending)
1056			status = -EINVAL;
1057		else if (value) {
1058			if (ep->udc->ep0_set_config) {
1059				WARNING("error changing config?\n");
1060				omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1061			}
1062			omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1063			ep->udc->ep0_pending = 0;
1064			status = 0;
1065		} else /* NOP */
1066			status = 0;
1067
1068	/* otherwise, all active non-ISO endpoints can halt */
1069	} else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->ep.desc) {
1070
1071		/* IN endpoints must already be idle */
1072		if ((ep->bEndpointAddress & USB_DIR_IN)
1073				&& !list_empty(&ep->queue)) {
1074			status = -EAGAIN;
1075			goto done;
1076		}
1077
1078		if (value) {
1079			int	channel;
1080
1081			if (use_dma && ep->dma_channel
1082					&& !list_empty(&ep->queue)) {
1083				channel = ep->dma_channel;
1084				dma_channel_release(ep);
1085			} else
1086				channel = 0;
1087
1088			use_ep(ep, UDC_EP_SEL);
1089			if (omap_readw(UDC_STAT_FLG) & UDC_NON_ISO_FIFO_EMPTY) {
1090				omap_writew(UDC_SET_HALT, UDC_CTRL);
1091				status = 0;
1092			} else
1093				status = -EAGAIN;
1094			deselect_ep();
1095
1096			if (channel)
1097				dma_channel_claim(ep, channel);
1098		} else {
1099			use_ep(ep, 0);
1100			omap_writew(ep->udc->clr_halt, UDC_CTRL);
1101			ep->ackwait = 0;
1102			if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1103				omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1104				ep->ackwait = 1 + ep->double_buf;
1105			}
1106		}
1107	}
1108done:
1109	VDBG("%s %s halt stat %d\n", ep->ep.name,
1110		value ? "set" : "clear", status);
1111
1112	spin_unlock_irqrestore(&ep->udc->lock, flags);
1113	return status;
1114}
1115
1116static const struct usb_ep_ops omap_ep_ops = {
1117	.enable		= omap_ep_enable,
1118	.disable	= omap_ep_disable,
1119
1120	.alloc_request	= omap_alloc_request,
1121	.free_request	= omap_free_request,
1122
1123	.queue		= omap_ep_queue,
1124	.dequeue	= omap_ep_dequeue,
1125
1126	.set_halt	= omap_ep_set_halt,
1127	/* fifo_status ... report bytes in fifo */
1128	/* fifo_flush ... flush fifo */
1129};
1130
1131/*-------------------------------------------------------------------------*/
1132
1133static int omap_get_frame(struct usb_gadget *gadget)
1134{
1135	u16	sof = omap_readw(UDC_SOF);
1136	return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1137}
1138
1139static int omap_wakeup(struct usb_gadget *gadget)
1140{
1141	struct omap_udc	*udc;
1142	unsigned long	flags;
1143	int		retval = -EHOSTUNREACH;
1144
1145	udc = container_of(gadget, struct omap_udc, gadget);
1146
1147	spin_lock_irqsave(&udc->lock, flags);
1148	if (udc->devstat & UDC_SUS) {
1149		/* NOTE:  OTG spec erratum says that OTG devices may
1150		 * issue wakeups without host enable.
1151		 */
1152		if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1153			DBG("remote wakeup...\n");
1154			omap_writew(UDC_RMT_WKP, UDC_SYSCON2);
1155			retval = 0;
1156		}
1157
1158	/* NOTE:  non-OTG systems may use SRP TOO... */
1159	} else if (!(udc->devstat & UDC_ATT)) {
1160		if (!IS_ERR_OR_NULL(udc->transceiver))
1161			retval = otg_start_srp(udc->transceiver->otg);
1162	}
1163	spin_unlock_irqrestore(&udc->lock, flags);
1164
1165	return retval;
1166}
1167
1168static int
1169omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1170{
1171	struct omap_udc	*udc;
1172	unsigned long	flags;
1173	u16		syscon1;
1174
1175	gadget->is_selfpowered = (is_selfpowered != 0);
1176	udc = container_of(gadget, struct omap_udc, gadget);
1177	spin_lock_irqsave(&udc->lock, flags);
1178	syscon1 = omap_readw(UDC_SYSCON1);
1179	if (is_selfpowered)
1180		syscon1 |= UDC_SELF_PWR;
1181	else
1182		syscon1 &= ~UDC_SELF_PWR;
1183	omap_writew(syscon1, UDC_SYSCON1);
1184	spin_unlock_irqrestore(&udc->lock, flags);
1185
1186	return 0;
1187}
1188
1189static int can_pullup(struct omap_udc *udc)
1190{
1191	return udc->driver && udc->softconnect && udc->vbus_active;
1192}
1193
1194static void pullup_enable(struct omap_udc *udc)
1195{
1196	u16 w;
1197
1198	w = omap_readw(UDC_SYSCON1);
1199	w |= UDC_PULLUP_EN;
1200	omap_writew(w, UDC_SYSCON1);
1201	if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1202		u32 l;
1203
1204		l = omap_readl(OTG_CTRL);
1205		l |= OTG_BSESSVLD;
1206		omap_writel(l, OTG_CTRL);
1207	}
1208	omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1209}
1210
1211static void pullup_disable(struct omap_udc *udc)
1212{
1213	u16 w;
1214
1215	if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1216		u32 l;
1217
1218		l = omap_readl(OTG_CTRL);
1219		l &= ~OTG_BSESSVLD;
1220		omap_writel(l, OTG_CTRL);
1221	}
1222	omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1223	w = omap_readw(UDC_SYSCON1);
1224	w &= ~UDC_PULLUP_EN;
1225	omap_writew(w, UDC_SYSCON1);
1226}
1227
1228static struct omap_udc *udc;
1229
1230static void omap_udc_enable_clock(int enable)
1231{
1232	if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1233		return;
1234
1235	if (enable) {
1236		clk_enable(udc->dc_clk);
1237		clk_enable(udc->hhc_clk);
1238		udelay(100);
1239	} else {
1240		clk_disable(udc->hhc_clk);
1241		clk_disable(udc->dc_clk);
1242	}
1243}
1244
1245/*
1246 * Called by whatever detects VBUS sessions:  external transceiver
1247 * driver, or maybe GPIO0 VBUS IRQ.  May request 48 MHz clock.
1248 */
1249static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1250{
1251	struct omap_udc	*udc;
1252	unsigned long	flags;
1253	u32 l;
1254
1255	udc = container_of(gadget, struct omap_udc, gadget);
1256	spin_lock_irqsave(&udc->lock, flags);
1257	VDBG("VBUS %s\n", is_active ? "on" : "off");
1258	udc->vbus_active = (is_active != 0);
1259	if (cpu_is_omap15xx()) {
1260		/* "software" detect, ignored if !VBUS_MODE_1510 */
1261		l = omap_readl(FUNC_MUX_CTRL_0);
1262		if (is_active)
1263			l |= VBUS_CTRL_1510;
1264		else
1265			l &= ~VBUS_CTRL_1510;
1266		omap_writel(l, FUNC_MUX_CTRL_0);
1267	}
1268	if (udc->dc_clk != NULL && is_active) {
1269		if (!udc->clk_requested) {
1270			omap_udc_enable_clock(1);
1271			udc->clk_requested = 1;
1272		}
1273	}
1274	if (can_pullup(udc))
1275		pullup_enable(udc);
1276	else
1277		pullup_disable(udc);
1278	if (udc->dc_clk != NULL && !is_active) {
1279		if (udc->clk_requested) {
1280			omap_udc_enable_clock(0);
1281			udc->clk_requested = 0;
1282		}
1283	}
1284	spin_unlock_irqrestore(&udc->lock, flags);
1285	return 0;
1286}
1287
1288static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1289{
1290	struct omap_udc	*udc;
1291
1292	udc = container_of(gadget, struct omap_udc, gadget);
1293	if (!IS_ERR_OR_NULL(udc->transceiver))
1294		return usb_phy_set_power(udc->transceiver, mA);
1295	return -EOPNOTSUPP;
1296}
1297
1298static int omap_pullup(struct usb_gadget *gadget, int is_on)
1299{
1300	struct omap_udc	*udc;
1301	unsigned long	flags;
1302
1303	udc = container_of(gadget, struct omap_udc, gadget);
1304	spin_lock_irqsave(&udc->lock, flags);
1305	udc->softconnect = (is_on != 0);
1306	if (can_pullup(udc))
1307		pullup_enable(udc);
1308	else
1309		pullup_disable(udc);
1310	spin_unlock_irqrestore(&udc->lock, flags);
1311	return 0;
1312}
1313
1314static int omap_udc_start(struct usb_gadget *g,
1315		struct usb_gadget_driver *driver);
1316static int omap_udc_stop(struct usb_gadget *g);
1317
1318static const struct usb_gadget_ops omap_gadget_ops = {
1319	.get_frame		= omap_get_frame,
1320	.wakeup			= omap_wakeup,
1321	.set_selfpowered	= omap_set_selfpowered,
1322	.vbus_session		= omap_vbus_session,
1323	.vbus_draw		= omap_vbus_draw,
1324	.pullup			= omap_pullup,
1325	.udc_start		= omap_udc_start,
1326	.udc_stop		= omap_udc_stop,
1327};
1328
1329/*-------------------------------------------------------------------------*/
1330
1331/* dequeue ALL requests; caller holds udc->lock */
1332static void nuke(struct omap_ep *ep, int status)
1333{
1334	struct omap_req	*req;
1335
1336	ep->stopped = 1;
1337
1338	if (use_dma && ep->dma_channel)
1339		dma_channel_release(ep);
1340
1341	use_ep(ep, 0);
1342	omap_writew(UDC_CLR_EP, UDC_CTRL);
1343	if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1344		omap_writew(UDC_SET_HALT, UDC_CTRL);
1345
1346	while (!list_empty(&ep->queue)) {
1347		req = list_entry(ep->queue.next, struct omap_req, queue);
1348		done(ep, req, status);
1349	}
1350}
1351
1352/* caller holds udc->lock */
1353static void udc_quiesce(struct omap_udc *udc)
1354{
1355	struct omap_ep	*ep;
1356
1357	udc->gadget.speed = USB_SPEED_UNKNOWN;
1358	nuke(&udc->ep[0], -ESHUTDOWN);
1359	list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list)
1360		nuke(ep, -ESHUTDOWN);
1361}
1362
1363/*-------------------------------------------------------------------------*/
1364
1365static void update_otg(struct omap_udc *udc)
1366{
1367	u16	devstat;
1368
1369	if (!gadget_is_otg(&udc->gadget))
1370		return;
1371
1372	if (omap_readl(OTG_CTRL) & OTG_ID)
1373		devstat = omap_readw(UDC_DEVSTAT);
1374	else
1375		devstat = 0;
1376
1377	udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1378	udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1379	udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1380
1381	/* Enable HNP early, avoiding races on suspend irq path.
1382	 * ASSUMES OTG state machine B_BUS_REQ input is true.
1383	 */
1384	if (udc->gadget.b_hnp_enable) {
1385		u32 l;
1386
1387		l = omap_readl(OTG_CTRL);
1388		l |= OTG_B_HNPEN | OTG_B_BUSREQ;
1389		l &= ~OTG_PULLUP;
1390		omap_writel(l, OTG_CTRL);
1391	}
1392}
1393
1394static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1395{
1396	struct omap_ep	*ep0 = &udc->ep[0];
1397	struct omap_req	*req = NULL;
1398
1399	ep0->irqs++;
1400
1401	/* Clear any pending requests and then scrub any rx/tx state
1402	 * before starting to handle the SETUP request.
1403	 */
1404	if (irq_src & UDC_SETUP) {
1405		u16	ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1406
1407		nuke(ep0, 0);
1408		if (ack) {
1409			omap_writew(ack, UDC_IRQ_SRC);
1410			irq_src = UDC_SETUP;
1411		}
1412	}
1413
1414	/* IN/OUT packets mean we're in the DATA or STATUS stage.
1415	 * This driver uses only uses protocol stalls (ep0 never halts),
1416	 * and if we got this far the gadget driver already had a
1417	 * chance to stall.  Tries to be forgiving of host oddities.
1418	 *
1419	 * NOTE:  the last chance gadget drivers have to stall control
1420	 * requests is during their request completion callback.
1421	 */
1422	if (!list_empty(&ep0->queue))
1423		req = container_of(ep0->queue.next, struct omap_req, queue);
1424
1425	/* IN == TX to host */
1426	if (irq_src & UDC_EP0_TX) {
1427		int	stat;
1428
1429		omap_writew(UDC_EP0_TX, UDC_IRQ_SRC);
1430		omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1431		stat = omap_readw(UDC_STAT_FLG);
1432		if (stat & UDC_ACK) {
1433			if (udc->ep0_in) {
1434				/* write next IN packet from response,
1435				 * or set up the status stage.
1436				 */
1437				if (req)
1438					stat = write_fifo(ep0, req);
1439				omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1440				if (!req && udc->ep0_pending) {
1441					omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1442					omap_writew(UDC_CLR_EP, UDC_CTRL);
1443					omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1444					omap_writew(0, UDC_EP_NUM);
1445					udc->ep0_pending = 0;
1446				} /* else:  6 wait states before it'll tx */
1447			} else {
1448				/* ack status stage of OUT transfer */
1449				omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1450				if (req)
1451					done(ep0, req, 0);
1452			}
1453			req = NULL;
1454		} else if (stat & UDC_STALL) {
1455			omap_writew(UDC_CLR_HALT, UDC_CTRL);
1456			omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1457		} else {
1458			omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1459		}
1460	}
1461
1462	/* OUT == RX from host */
1463	if (irq_src & UDC_EP0_RX) {
1464		int	stat;
1465
1466		omap_writew(UDC_EP0_RX, UDC_IRQ_SRC);
1467		omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1468		stat = omap_readw(UDC_STAT_FLG);
1469		if (stat & UDC_ACK) {
1470			if (!udc->ep0_in) {
1471				stat = 0;
1472				/* read next OUT packet of request, maybe
1473				 * reactivating the fifo; stall on errors.
1474				 */
1475				stat = read_fifo(ep0, req);
1476				if (!req || stat < 0) {
1477					omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1478					udc->ep0_pending = 0;
1479					stat = 0;
1480				} else if (stat == 0)
1481					omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1482				omap_writew(0, UDC_EP_NUM);
1483
1484				/* activate status stage */
1485				if (stat == 1) {
1486					done(ep0, req, 0);
1487					/* that may have STALLed ep0... */
1488					omap_writew(UDC_EP_SEL | UDC_EP_DIR,
1489							UDC_EP_NUM);
1490					omap_writew(UDC_CLR_EP, UDC_CTRL);
1491					omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1492					omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1493					udc->ep0_pending = 0;
1494				}
1495			} else {
1496				/* ack status stage of IN transfer */
1497				omap_writew(0, UDC_EP_NUM);
1498				if (req)
1499					done(ep0, req, 0);
1500			}
1501		} else if (stat & UDC_STALL) {
1502			omap_writew(UDC_CLR_HALT, UDC_CTRL);
1503			omap_writew(0, UDC_EP_NUM);
1504		} else {
1505			omap_writew(0, UDC_EP_NUM);
1506		}
1507	}
1508
1509	/* SETUP starts all control transfers */
1510	if (irq_src & UDC_SETUP) {
1511		union u {
1512			u16			word[4];
1513			struct usb_ctrlrequest	r;
1514		} u;
1515		int			status = -EINVAL;
1516		struct omap_ep		*ep;
1517
1518		/* read the (latest) SETUP message */
1519		do {
1520			omap_writew(UDC_SETUP_SEL, UDC_EP_NUM);
1521			/* two bytes at a time */
1522			u.word[0] = omap_readw(UDC_DATA);
1523			u.word[1] = omap_readw(UDC_DATA);
1524			u.word[2] = omap_readw(UDC_DATA);
1525			u.word[3] = omap_readw(UDC_DATA);
1526			omap_writew(0, UDC_EP_NUM);
1527		} while (omap_readw(UDC_IRQ_SRC) & UDC_SETUP);
1528
1529#define	w_value		le16_to_cpu(u.r.wValue)
1530#define	w_index		le16_to_cpu(u.r.wIndex)
1531#define	w_length	le16_to_cpu(u.r.wLength)
1532
1533		/* Delegate almost all control requests to the gadget driver,
1534		 * except for a handful of ch9 status/feature requests that
1535		 * hardware doesn't autodecode _and_ the gadget API hides.
1536		 */
1537		udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1538		udc->ep0_set_config = 0;
1539		udc->ep0_pending = 1;
1540		ep0->stopped = 0;
1541		ep0->ackwait = 0;
1542		switch (u.r.bRequest) {
1543		case USB_REQ_SET_CONFIGURATION:
1544			/* udc needs to know when ep != 0 is valid */
1545			if (u.r.bRequestType != USB_RECIP_DEVICE)
1546				goto delegate;
1547			if (w_length != 0)
1548				goto do_stall;
1549			udc->ep0_set_config = 1;
1550			udc->ep0_reset_config = (w_value == 0);
1551			VDBG("set config %d\n", w_value);
1552
1553			/* update udc NOW since gadget driver may start
1554			 * queueing requests immediately; clear config
1555			 * later if it fails the request.
1556			 */
1557			if (udc->ep0_reset_config)
1558				omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1559			else
1560				omap_writew(UDC_DEV_CFG, UDC_SYSCON2);
1561			update_otg(udc);
1562			goto delegate;
1563		case USB_REQ_CLEAR_FEATURE:
1564			/* clear endpoint halt */
1565			if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1566				goto delegate;
1567			if (w_value != USB_ENDPOINT_HALT
1568					|| w_length != 0)
1569				goto do_stall;
1570			ep = &udc->ep[w_index & 0xf];
1571			if (ep != ep0) {
1572				if (w_index & USB_DIR_IN)
1573					ep += 16;
1574				if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1575						|| !ep->ep.desc)
1576					goto do_stall;
1577				use_ep(ep, 0);
1578				omap_writew(udc->clr_halt, UDC_CTRL);
1579				ep->ackwait = 0;
1580				if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1581					omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1582					ep->ackwait = 1 + ep->double_buf;
1583				}
1584				/* NOTE:  assumes the host behaves sanely,
1585				 * only clearing real halts.  Else we may
1586				 * need to kill pending transfers and then
1587				 * restart the queue... very messy for DMA!
1588				 */
1589			}
1590			VDBG("%s halt cleared by host\n", ep->name);
1591			goto ep0out_status_stage;
1592		case USB_REQ_SET_FEATURE:
1593			/* set endpoint halt */
1594			if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1595				goto delegate;
1596			if (w_value != USB_ENDPOINT_HALT
1597					|| w_length != 0)
1598				goto do_stall;
1599			ep = &udc->ep[w_index & 0xf];
1600			if (w_index & USB_DIR_IN)
1601				ep += 16;
1602			if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1603					|| ep == ep0 || !ep->ep.desc)
1604				goto do_stall;
1605			if (use_dma && ep->has_dma) {
1606				/* this has rude side-effects (aborts) and
1607				 * can't really work if DMA-IN is active
1608				 */
1609				DBG("%s host set_halt, NYET\n", ep->name);
1610				goto do_stall;
1611			}
1612			use_ep(ep, 0);
1613			/* can't halt if fifo isn't empty... */
1614			omap_writew(UDC_CLR_EP, UDC_CTRL);
1615			omap_writew(UDC_SET_HALT, UDC_CTRL);
1616			VDBG("%s halted by host\n", ep->name);
1617ep0out_status_stage:
1618			status = 0;
1619			omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1620			omap_writew(UDC_CLR_EP, UDC_CTRL);
1621			omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1622			omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1623			udc->ep0_pending = 0;
1624			break;
1625		case USB_REQ_GET_STATUS:
1626			/* USB_ENDPOINT_HALT status? */
1627			if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT))
1628				goto intf_status;
1629
1630			/* ep0 never stalls */
1631			if (!(w_index & 0xf))
1632				goto zero_status;
1633
1634			/* only active endpoints count */
1635			ep = &udc->ep[w_index & 0xf];
1636			if (w_index & USB_DIR_IN)
1637				ep += 16;
1638			if (!ep->ep.desc)
1639				goto do_stall;
1640
1641			/* iso never stalls */
1642			if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1643				goto zero_status;
1644
1645			/* FIXME don't assume non-halted endpoints!! */
1646			ERR("%s status, can't report\n", ep->ep.name);
1647			goto do_stall;
1648
1649intf_status:
1650			/* return interface status.  if we were pedantic,
1651			 * we'd detect non-existent interfaces, and stall.
1652			 */
1653			if (u.r.bRequestType
1654					!= (USB_DIR_IN|USB_RECIP_INTERFACE))
1655				goto delegate;
1656
1657zero_status:
1658			/* return two zero bytes */
1659			omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1660			omap_writew(0, UDC_DATA);
1661			omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1662			omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1663			status = 0;
1664			VDBG("GET_STATUS, interface %d\n", w_index);
1665			/* next, status stage */
1666			break;
1667		default:
1668delegate:
1669			/* activate the ep0out fifo right away */
1670			if (!udc->ep0_in && w_length) {
1671				omap_writew(0, UDC_EP_NUM);
1672				omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1673			}
1674
1675			/* gadget drivers see class/vendor specific requests,
1676			 * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1677			 * and more
1678			 */
1679			VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1680				u.r.bRequestType, u.r.bRequest,
1681				w_value, w_index, w_length);
1682
1683#undef	w_value
1684#undef	w_index
1685#undef	w_length
1686
1687			/* The gadget driver may return an error here,
1688			 * causing an immediate protocol stall.
1689			 *
1690			 * Else it must issue a response, either queueing a
1691			 * response buffer for the DATA stage, or halting ep0
1692			 * (causing a protocol stall, not a real halt).  A
1693			 * zero length buffer means no DATA stage.
1694			 *
1695			 * It's fine to issue that response after the setup()
1696			 * call returns, and this IRQ was handled.
1697			 */
1698			udc->ep0_setup = 1;
1699			spin_unlock(&udc->lock);
1700			status = udc->driver->setup(&udc->gadget, &u.r);
1701			spin_lock(&udc->lock);
1702			udc->ep0_setup = 0;
1703		}
1704
1705		if (status < 0) {
1706do_stall:
1707			VDBG("req %02x.%02x protocol STALL; stat %d\n",
1708					u.r.bRequestType, u.r.bRequest, status);
1709			if (udc->ep0_set_config) {
1710				if (udc->ep0_reset_config)
1711					WARNING("error resetting config?\n");
1712				else
1713					omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1714			}
1715			omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1716			udc->ep0_pending = 0;
1717		}
1718	}
1719}
1720
1721/*-------------------------------------------------------------------------*/
1722
1723#define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1724
1725static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1726{
1727	u16	devstat, change;
1728
1729	devstat = omap_readw(UDC_DEVSTAT);
1730	change = devstat ^ udc->devstat;
1731	udc->devstat = devstat;
1732
1733	if (change & (UDC_USB_RESET|UDC_ATT)) {
1734		udc_quiesce(udc);
1735
1736		if (change & UDC_ATT) {
1737			/* driver for any external transceiver will
1738			 * have called omap_vbus_session() already
1739			 */
1740			if (devstat & UDC_ATT) {
1741				udc->gadget.speed = USB_SPEED_FULL;
1742				VDBG("connect\n");
1743				if (IS_ERR_OR_NULL(udc->transceiver))
1744					pullup_enable(udc);
1745				/* if (driver->connect) call it */
1746			} else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1747				udc->gadget.speed = USB_SPEED_UNKNOWN;
1748				if (IS_ERR_OR_NULL(udc->transceiver))
1749					pullup_disable(udc);
1750				DBG("disconnect, gadget %s\n",
1751					udc->driver->driver.name);
1752				if (udc->driver->disconnect) {
1753					spin_unlock(&udc->lock);
1754					udc->driver->disconnect(&udc->gadget);
1755					spin_lock(&udc->lock);
1756				}
1757			}
1758			change &= ~UDC_ATT;
1759		}
1760
1761		if (change & UDC_USB_RESET) {
1762			if (devstat & UDC_USB_RESET) {
1763				VDBG("RESET=1\n");
1764			} else {
1765				udc->gadget.speed = USB_SPEED_FULL;
1766				INFO("USB reset done, gadget %s\n",
1767					udc->driver->driver.name);
1768				/* ep0 traffic is legal from now on */
1769				omap_writew(UDC_DS_CHG_IE | UDC_EP0_IE,
1770						UDC_IRQ_EN);
1771			}
1772			change &= ~UDC_USB_RESET;
1773		}
1774	}
1775	if (change & UDC_SUS) {
1776		if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1777			/* FIXME tell isp1301 to suspend/resume (?) */
1778			if (devstat & UDC_SUS) {
1779				VDBG("suspend\n");
1780				update_otg(udc);
1781				/* HNP could be under way already */
1782				if (udc->gadget.speed == USB_SPEED_FULL
1783						&& udc->driver->suspend) {
1784					spin_unlock(&udc->lock);
1785					udc->driver->suspend(&udc->gadget);
1786					spin_lock(&udc->lock);
1787				}
1788				if (!IS_ERR_OR_NULL(udc->transceiver))
1789					usb_phy_set_suspend(
1790							udc->transceiver, 1);
1791			} else {
1792				VDBG("resume\n");
1793				if (!IS_ERR_OR_NULL(udc->transceiver))
1794					usb_phy_set_suspend(
1795							udc->transceiver, 0);
1796				if (udc->gadget.speed == USB_SPEED_FULL
1797						&& udc->driver->resume) {
1798					spin_unlock(&udc->lock);
1799					udc->driver->resume(&udc->gadget);
1800					spin_lock(&udc->lock);
1801				}
1802			}
1803		}
1804		change &= ~UDC_SUS;
1805	}
1806	if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1807		update_otg(udc);
1808		change &= ~OTG_FLAGS;
1809	}
1810
1811	change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1812	if (change)
1813		VDBG("devstat %03x, ignore change %03x\n",
1814			devstat,  change);
1815
1816	omap_writew(UDC_DS_CHG, UDC_IRQ_SRC);
1817}
1818
1819static irqreturn_t omap_udc_irq(int irq, void *_udc)
1820{
1821	struct omap_udc	*udc = _udc;
1822	u16		irq_src;
1823	irqreturn_t	status = IRQ_NONE;
1824	unsigned long	flags;
1825
1826	spin_lock_irqsave(&udc->lock, flags);
1827	irq_src = omap_readw(UDC_IRQ_SRC);
1828
1829	/* Device state change (usb ch9 stuff) */
1830	if (irq_src & UDC_DS_CHG) {
1831		devstate_irq(_udc, irq_src);
1832		status = IRQ_HANDLED;
1833		irq_src &= ~UDC_DS_CHG;
1834	}
1835
1836	/* EP0 control transfers */
1837	if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1838		ep0_irq(_udc, irq_src);
1839		status = IRQ_HANDLED;
1840		irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1841	}
1842
1843	/* DMA transfer completion */
1844	if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1845		dma_irq(_udc, irq_src);
1846		status = IRQ_HANDLED;
1847		irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1848	}
1849
1850	irq_src &= ~(UDC_IRQ_SOF | UDC_EPN_TX|UDC_EPN_RX);
1851	if (irq_src)
1852		DBG("udc_irq, unhandled %03x\n", irq_src);
1853	spin_unlock_irqrestore(&udc->lock, flags);
1854
1855	return status;
1856}
1857
1858/* workaround for seemingly-lost IRQs for RX ACKs... */
1859#define PIO_OUT_TIMEOUT	(jiffies + HZ/3)
1860#define HALF_FULL(f)	(!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1861
1862static void pio_out_timer(struct timer_list *t)
1863{
1864	struct omap_ep	*ep = from_timer(ep, t, timer);
1865	unsigned long	flags;
1866	u16		stat_flg;
1867
1868	spin_lock_irqsave(&ep->udc->lock, flags);
1869	if (!list_empty(&ep->queue) && ep->ackwait) {
1870		use_ep(ep, UDC_EP_SEL);
1871		stat_flg = omap_readw(UDC_STAT_FLG);
1872
1873		if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1874				|| (ep->double_buf && HALF_FULL(stat_flg)))) {
1875			struct omap_req	*req;
1876
1877			VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1878			req = container_of(ep->queue.next,
1879					struct omap_req, queue);
1880			(void) read_fifo(ep, req);
1881			omap_writew(ep->bEndpointAddress, UDC_EP_NUM);
1882			omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1883			ep->ackwait = 1 + ep->double_buf;
1884		} else
1885			deselect_ep();
1886	}
1887	mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1888	spin_unlock_irqrestore(&ep->udc->lock, flags);
1889}
1890
1891static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1892{
1893	u16		epn_stat, irq_src;
1894	irqreturn_t	status = IRQ_NONE;
1895	struct omap_ep	*ep;
1896	int		epnum;
1897	struct omap_udc	*udc = _dev;
1898	struct omap_req	*req;
1899	unsigned long	flags;
1900
1901	spin_lock_irqsave(&udc->lock, flags);
1902	epn_stat = omap_readw(UDC_EPN_STAT);
1903	irq_src = omap_readw(UDC_IRQ_SRC);
1904
1905	/* handle OUT first, to avoid some wasteful NAKs */
1906	if (irq_src & UDC_EPN_RX) {
1907		epnum = (epn_stat >> 8) & 0x0f;
1908		omap_writew(UDC_EPN_RX, UDC_IRQ_SRC);
1909		status = IRQ_HANDLED;
1910		ep = &udc->ep[epnum];
1911		ep->irqs++;
1912
1913		omap_writew(epnum | UDC_EP_SEL, UDC_EP_NUM);
1914		ep->fnf = 0;
1915		if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1916			ep->ackwait--;
1917			if (!list_empty(&ep->queue)) {
1918				int stat;
1919				req = container_of(ep->queue.next,
1920						struct omap_req, queue);
1921				stat = read_fifo(ep, req);
1922				if (!ep->double_buf)
1923					ep->fnf = 1;
1924			}
1925		}
1926		/* min 6 clock delay before clearing EP_SEL ... */
1927		epn_stat = omap_readw(UDC_EPN_STAT);
1928		epn_stat = omap_readw(UDC_EPN_STAT);
1929		omap_writew(epnum, UDC_EP_NUM);
1930
1931		/* enabling fifo _after_ clearing ACK, contrary to docs,
1932		 * reduces lossage; timer still needed though (sigh).
1933		 */
1934		if (ep->fnf) {
1935			omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1936			ep->ackwait = 1 + ep->double_buf;
1937		}
1938		mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1939	}
1940
1941	/* then IN transfers */
1942	else if (irq_src & UDC_EPN_TX) {
1943		epnum = epn_stat & 0x0f;
1944		omap_writew(UDC_EPN_TX, UDC_IRQ_SRC);
1945		status = IRQ_HANDLED;
1946		ep = &udc->ep[16 + epnum];
1947		ep->irqs++;
1948
1949		omap_writew(epnum | UDC_EP_DIR | UDC_EP_SEL, UDC_EP_NUM);
1950		if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1951			ep->ackwait = 0;
1952			if (!list_empty(&ep->queue)) {
1953				req = container_of(ep->queue.next,
1954						struct omap_req, queue);
1955				(void) write_fifo(ep, req);
1956			}
1957		}
1958		/* min 6 clock delay before clearing EP_SEL ... */
1959		epn_stat = omap_readw(UDC_EPN_STAT);
1960		epn_stat = omap_readw(UDC_EPN_STAT);
1961		omap_writew(epnum | UDC_EP_DIR, UDC_EP_NUM);
1962		/* then 6 clocks before it'd tx */
1963	}
1964
1965	spin_unlock_irqrestore(&udc->lock, flags);
1966	return status;
1967}
1968
1969#ifdef	USE_ISO
1970static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
1971{
1972	struct omap_udc	*udc = _dev;
1973	struct omap_ep	*ep;
1974	int		pending = 0;
1975	unsigned long	flags;
1976
1977	spin_lock_irqsave(&udc->lock, flags);
1978
1979	/* handle all non-DMA ISO transfers */
1980	list_for_each_entry(ep, &udc->iso, iso) {
1981		u16		stat;
1982		struct omap_req	*req;
1983
1984		if (ep->has_dma || list_empty(&ep->queue))
1985			continue;
1986		req = list_entry(ep->queue.next, struct omap_req, queue);
1987
1988		use_ep(ep, UDC_EP_SEL);
1989		stat = omap_readw(UDC_STAT_FLG);
1990
1991		/* NOTE: like the other controller drivers, this isn't
1992		 * currently reporting lost or damaged frames.
1993		 */
1994		if (ep->bEndpointAddress & USB_DIR_IN) {
1995			if (stat & UDC_MISS_IN)
1996				/* done(ep, req, -EPROTO) */;
1997			else
1998				write_fifo(ep, req);
1999		} else {
2000			int	status = 0;
2001
2002			if (stat & UDC_NO_RXPACKET)
2003				status = -EREMOTEIO;
2004			else if (stat & UDC_ISO_ERR)
2005				status = -EILSEQ;
2006			else if (stat & UDC_DATA_FLUSH)
2007				status = -ENOSR;
2008
2009			if (status)
2010				/* done(ep, req, status) */;
2011			else
2012				read_fifo(ep, req);
2013		}
2014		deselect_ep();
2015		/* 6 wait states before next EP */
2016
2017		ep->irqs++;
2018		if (!list_empty(&ep->queue))
2019			pending = 1;
2020	}
2021	if (!pending) {
2022		u16 w;
2023
2024		w = omap_readw(UDC_IRQ_EN);
2025		w &= ~UDC_SOF_IE;
2026		omap_writew(w, UDC_IRQ_EN);
2027	}
2028	omap_writew(UDC_IRQ_SOF, UDC_IRQ_SRC);
2029
2030	spin_unlock_irqrestore(&udc->lock, flags);
2031	return IRQ_HANDLED;
2032}
2033#endif
2034
2035/*-------------------------------------------------------------------------*/
2036
2037static inline int machine_without_vbus_sense(void)
2038{
2039	return machine_is_omap_innovator()
2040		|| machine_is_omap_osk()
2041		|| machine_is_omap_palmte()
2042		|| machine_is_sx1()
2043		/* No known omap7xx boards with vbus sense */
2044		|| cpu_is_omap7xx();
2045}
2046
2047static int omap_udc_start(struct usb_gadget *g,
2048		struct usb_gadget_driver *driver)
2049{
2050	int		status;
2051	struct omap_ep	*ep;
2052	unsigned long	flags;
2053
2054
2055	spin_lock_irqsave(&udc->lock, flags);
2056	/* reset state */
2057	list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2058		ep->irqs = 0;
2059		if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2060			continue;
2061		use_ep(ep, 0);
2062		omap_writew(UDC_SET_HALT, UDC_CTRL);
2063	}
2064	udc->ep0_pending = 0;
2065	udc->ep[0].irqs = 0;
2066	udc->softconnect = 1;
2067
2068	/* hook up the driver */
2069	udc->driver = driver;
2070	spin_unlock_irqrestore(&udc->lock, flags);
2071
2072	if (udc->dc_clk != NULL)
2073		omap_udc_enable_clock(1);
2074
2075	omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2076
2077	/* connect to bus through transceiver */
2078	if (!IS_ERR_OR_NULL(udc->transceiver)) {
2079		status = otg_set_peripheral(udc->transceiver->otg,
2080						&udc->gadget);
2081		if (status < 0) {
2082			ERR("can't bind to transceiver\n");
2083			udc->driver = NULL;
2084			goto done;
2085		}
2086	} else {
2087		status = 0;
2088		if (can_pullup(udc))
2089			pullup_enable(udc);
2090		else
2091			pullup_disable(udc);
2092	}
2093
2094	/* boards that don't have VBUS sensing can't autogate 48MHz;
2095	 * can't enter deep sleep while a gadget driver is active.
2096	 */
2097	if (machine_without_vbus_sense())
2098		omap_vbus_session(&udc->gadget, 1);
2099
2100done:
2101	if (udc->dc_clk != NULL)
2102		omap_udc_enable_clock(0);
2103
2104	return status;
2105}
2106
2107static int omap_udc_stop(struct usb_gadget *g)
2108{
2109	unsigned long	flags;
2110
2111	if (udc->dc_clk != NULL)
2112		omap_udc_enable_clock(1);
2113
2114	if (machine_without_vbus_sense())
2115		omap_vbus_session(&udc->gadget, 0);
2116
2117	if (!IS_ERR_OR_NULL(udc->transceiver))
2118		(void) otg_set_peripheral(udc->transceiver->otg, NULL);
2119	else
2120		pullup_disable(udc);
2121
2122	spin_lock_irqsave(&udc->lock, flags);
2123	udc_quiesce(udc);
2124	spin_unlock_irqrestore(&udc->lock, flags);
2125
2126	udc->driver = NULL;
2127
2128	if (udc->dc_clk != NULL)
2129		omap_udc_enable_clock(0);
2130
2131	return 0;
2132}
2133
2134/*-------------------------------------------------------------------------*/
2135
2136#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2137
2138#include <linux/seq_file.h>
2139
2140static const char proc_filename[] = "driver/udc";
2141
2142#define FOURBITS "%s%s%s%s"
2143#define EIGHTBITS "%s%s%s%s%s%s%s%s"
2144
2145static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2146{
2147	u16		stat_flg;
2148	struct omap_req	*req;
2149	char		buf[20];
2150
2151	use_ep(ep, 0);
2152
2153	if (use_dma && ep->has_dma)
2154		snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2155			(ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2156			ep->dma_channel - 1, ep->lch);
2157	else
2158		buf[0] = 0;
2159
2160	stat_flg = omap_readw(UDC_STAT_FLG);
2161	seq_printf(s,
2162		"\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2163		ep->name, buf,
2164		ep->double_buf ? "dbuf " : "",
2165		({ char *s;
2166		switch (ep->ackwait) {
2167		case 0:
2168			s = "";
2169			break;
2170		case 1:
2171			s = "(ackw) ";
2172			break;
2173		case 2:
2174			s = "(ackw2) ";
2175			break;
2176		default:
2177			s = "(?) ";
2178			break;
2179		} s; }),
2180		ep->irqs, stat_flg,
2181		(stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2182		(stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2183		(stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2184		(stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2185		(stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2186		(stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2187		(stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2188		(stat_flg & UDC_STALL) ? "STALL " : "",
2189		(stat_flg & UDC_NAK) ? "NAK " : "",
2190		(stat_flg & UDC_ACK) ? "ACK " : "",
2191		(stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2192		(stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2193		(stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2194
2195	if (list_empty(&ep->queue))
2196		seq_printf(s, "\t(queue empty)\n");
2197	else
2198		list_for_each_entry(req, &ep->queue, queue) {
2199			unsigned	length = req->req.actual;
2200
2201			if (use_dma && buf[0]) {
2202				length += ((ep->bEndpointAddress & USB_DIR_IN)
2203						? dma_src_len : dma_dest_len)
2204					(ep, req->req.dma + length);
2205				buf[0] = 0;
2206			}
2207			seq_printf(s, "\treq %p len %d/%d buf %p\n",
2208					&req->req, length,
2209					req->req.length, req->req.buf);
2210		}
2211}
2212
2213static char *trx_mode(unsigned m, int enabled)
2214{
2215	switch (m) {
2216	case 0:
2217		return enabled ? "*6wire" : "unused";
2218	case 1:
2219		return "4wire";
2220	case 2:
2221		return "3wire";
2222	case 3:
2223		return "6wire";
2224	default:
2225		return "unknown";
2226	}
2227}
2228
2229static int proc_otg_show(struct seq_file *s)
2230{
2231	u32		tmp;
2232	u32		trans = 0;
2233	char		*ctrl_name = "(UNKNOWN)";
2234
2235	tmp = omap_readl(OTG_REV);
2236	ctrl_name = "transceiver_ctrl";
2237	trans = omap_readw(USB_TRANSCEIVER_CTRL);
2238	seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
2239		tmp >> 4, tmp & 0xf, ctrl_name, trans);
2240	tmp = omap_readw(OTG_SYSCON_1);
2241	seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2242			FOURBITS "\n", tmp,
2243		trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2244		trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2245		(USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2246			? "internal"
2247			: trx_mode(USB0_TRX_MODE(tmp), 1),
2248		(tmp & OTG_IDLE_EN) ? " !otg" : "",
2249		(tmp & HST_IDLE_EN) ? " !host" : "",
2250		(tmp & DEV_IDLE_EN) ? " !dev" : "",
2251		(tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2252	tmp = omap_readl(OTG_SYSCON_2);
2253	seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2254			" b_ase_brst=%d hmc=%d\n", tmp,
2255		(tmp & OTG_EN) ? " otg_en" : "",
2256		(tmp & USBX_SYNCHRO) ? " synchro" : "",
2257		/* much more SRP stuff */
2258		(tmp & SRP_DATA) ? " srp_data" : "",
2259		(tmp & SRP_VBUS) ? " srp_vbus" : "",
2260		(tmp & OTG_PADEN) ? " otg_paden" : "",
2261		(tmp & HMC_PADEN) ? " hmc_paden" : "",
2262		(tmp & UHOST_EN) ? " uhost_en" : "",
2263		(tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2264		(tmp & HMC_TLLATTACH) ? " tllattach" : "",
2265		B_ASE_BRST(tmp),
2266		OTG_HMC(tmp));
2267	tmp = omap_readl(OTG_CTRL);
2268	seq_printf(s, "otg_ctrl    %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2269		(tmp & OTG_ASESSVLD) ? " asess" : "",
2270		(tmp & OTG_BSESSEND) ? " bsess_end" : "",
2271		(tmp & OTG_BSESSVLD) ? " bsess" : "",
2272		(tmp & OTG_VBUSVLD) ? " vbus" : "",
2273		(tmp & OTG_ID) ? " id" : "",
2274		(tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2275		(tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2276		(tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2277		(tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2278		(tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2279		(tmp & OTG_BUSDROP) ? " busdrop" : "",
2280		(tmp & OTG_PULLDOWN) ? " down" : "",
2281		(tmp & OTG_PULLUP) ? " up" : "",
2282		(tmp & OTG_DRV_VBUS) ? " drv" : "",
2283		(tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2284		(tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2285		(tmp & OTG_PU_ID) ? " pu_id" : ""
2286		);
2287	tmp = omap_readw(OTG_IRQ_EN);
2288	seq_printf(s, "otg_irq_en  %04x" "\n", tmp);
2289	tmp = omap_readw(OTG_IRQ_SRC);
2290	seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2291	tmp = omap_readw(OTG_OUTCTRL);
2292	seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2293	tmp = omap_readw(OTG_TEST);
2294	seq_printf(s, "otg_test    %04x" "\n", tmp);
2295	return 0;
2296}
2297
2298static int proc_udc_show(struct seq_file *s, void *_)
2299{
2300	u32		tmp;
2301	struct omap_ep	*ep;
2302	unsigned long	flags;
2303
2304	spin_lock_irqsave(&udc->lock, flags);
2305
2306	seq_printf(s, "%s, version: " DRIVER_VERSION
2307#ifdef	USE_ISO
2308		" (iso)"
2309#endif
2310		"%s\n",
2311		driver_desc,
2312		use_dma ?  " (dma)" : "");
2313
2314	tmp = omap_readw(UDC_REV) & 0xff;
2315	seq_printf(s,
2316		"UDC rev %d.%d, fifo mode %d, gadget %s\n"
2317		"hmc %d, transceiver %s\n",
2318		tmp >> 4, tmp & 0xf,
2319		fifo_mode,
2320		udc->driver ? udc->driver->driver.name : "(none)",
2321		HMC,
2322		udc->transceiver
2323			? udc->transceiver->label
2324			: (cpu_is_omap1710()
2325				? "external" : "(none)"));
2326	seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2327		omap_readw(ULPD_CLOCK_CTRL),
2328		omap_readw(ULPD_SOFT_REQ),
2329		omap_readw(ULPD_STATUS_REQ));
2330
2331	/* OTG controller registers */
2332	if (!cpu_is_omap15xx())
2333		proc_otg_show(s);
2334
2335	tmp = omap_readw(UDC_SYSCON1);
2336	seq_printf(s, "\nsyscon1     %04x" EIGHTBITS "\n", tmp,
2337		(tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2338		(tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2339		(tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2340		(tmp & UDC_NAK_EN) ? " nak" : "",
2341		(tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2342		(tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2343		(tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2344		(tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2345	/* syscon2 is write-only */
2346
2347	/* UDC controller registers */
2348	if (!(tmp & UDC_PULLUP_EN)) {
2349		seq_printf(s, "(suspended)\n");
2350		spin_unlock_irqrestore(&udc->lock, flags);
2351		return 0;
2352	}
2353
2354	tmp = omap_readw(UDC_DEVSTAT);
2355	seq_printf(s, "devstat     %04x" EIGHTBITS "%s%s\n", tmp,
2356		(tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2357		(tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2358		(tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2359		(tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2360		(tmp & UDC_USB_RESET) ? " usb_reset" : "",
2361		(tmp & UDC_SUS) ? " SUS" : "",
2362		(tmp & UDC_CFG) ? " CFG" : "",
2363		(tmp & UDC_ADD) ? " ADD" : "",
2364		(tmp & UDC_DEF) ? " DEF" : "",
2365		(tmp & UDC_ATT) ? " ATT" : "");
2366	seq_printf(s, "sof         %04x\n", omap_readw(UDC_SOF));
2367	tmp = omap_readw(UDC_IRQ_EN);
2368	seq_printf(s, "irq_en      %04x" FOURBITS "%s\n", tmp,
2369		(tmp & UDC_SOF_IE) ? " sof" : "",
2370		(tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2371		(tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2372		(tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2373		(tmp & UDC_EP0_IE) ? " ep0" : "");
2374	tmp = omap_readw(UDC_IRQ_SRC);
2375	seq_printf(s, "irq_src     %04x" EIGHTBITS "%s%s\n", tmp,
2376		(tmp & UDC_TXN_DONE) ? " txn_done" : "",
2377		(tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2378		(tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2379		(tmp & UDC_IRQ_SOF) ? " sof" : "",
2380		(tmp & UDC_EPN_RX) ? " epn_rx" : "",
2381		(tmp & UDC_EPN_TX) ? " epn_tx" : "",
2382		(tmp & UDC_DS_CHG) ? " ds_chg" : "",
2383		(tmp & UDC_SETUP) ? " setup" : "",
2384		(tmp & UDC_EP0_RX) ? " ep0out" : "",
2385		(tmp & UDC_EP0_TX) ? " ep0in" : "");
2386	if (use_dma) {
2387		unsigned i;
2388
2389		tmp = omap_readw(UDC_DMA_IRQ_EN);
2390		seq_printf(s, "dma_irq_en  %04x%s" EIGHTBITS "\n", tmp,
2391			(tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2392			(tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2393			(tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2394
2395			(tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2396			(tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2397			(tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2398
2399			(tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2400			(tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2401			(tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2402
2403		tmp = omap_readw(UDC_RXDMA_CFG);
2404		seq_printf(s, "rxdma_cfg   %04x\n", tmp);
2405		if (tmp) {
2406			for (i = 0; i < 3; i++) {
2407				if ((tmp & (0x0f << (i * 4))) == 0)
2408					continue;
2409				seq_printf(s, "rxdma[%d]    %04x\n", i,
2410						omap_readw(UDC_RXDMA(i + 1)));
2411			}
2412		}
2413		tmp = omap_readw(UDC_TXDMA_CFG);
2414		seq_printf(s, "txdma_cfg   %04x\n", tmp);
2415		if (tmp) {
2416			for (i = 0; i < 3; i++) {
2417				if (!(tmp & (0x0f << (i * 4))))
2418					continue;
2419				seq_printf(s, "txdma[%d]    %04x\n", i,
2420						omap_readw(UDC_TXDMA(i + 1)));
2421			}
2422		}
2423	}
2424
2425	tmp = omap_readw(UDC_DEVSTAT);
2426	if (tmp & UDC_ATT) {
2427		proc_ep_show(s, &udc->ep[0]);
2428		if (tmp & UDC_ADD) {
2429			list_for_each_entry(ep, &udc->gadget.ep_list,
2430					ep.ep_list) {
2431				if (ep->ep.desc)
2432					proc_ep_show(s, ep);
2433			}
2434		}
2435	}
2436	spin_unlock_irqrestore(&udc->lock, flags);
2437	return 0;
2438}
2439
2440static void create_proc_file(void)
2441{
2442	proc_create_single(proc_filename, 0, NULL, proc_udc_show);
2443}
2444
2445static void remove_proc_file(void)
2446{
2447	remove_proc_entry(proc_filename, NULL);
2448}
2449
2450#else
2451
2452static inline void create_proc_file(void) {}
2453static inline void remove_proc_file(void) {}
2454
2455#endif
2456
2457/*-------------------------------------------------------------------------*/
2458
2459/* Before this controller can enumerate, we need to pick an endpoint
2460 * configuration, or "fifo_mode"  That involves allocating 2KB of packet
2461 * buffer space among the endpoints we'll be operating.
2462 *
2463 * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2464 * UDC_SYSCON_1.CFG_LOCK is set can now work.  We won't use that
2465 * capability yet though.
2466 */
2467static unsigned
2468omap_ep_setup(char *name, u8 addr, u8 type,
2469		unsigned buf, unsigned maxp, int dbuf)
2470{
2471	struct omap_ep	*ep;
2472	u16		epn_rxtx = 0;
2473
2474	/* OUT endpoints first, then IN */
2475	ep = &udc->ep[addr & 0xf];
2476	if (addr & USB_DIR_IN)
2477		ep += 16;
2478
2479	/* in case of ep init table bugs */
2480	BUG_ON(ep->name[0]);
2481
2482	/* chip setup ... bit values are same for IN, OUT */
2483	if (type == USB_ENDPOINT_XFER_ISOC) {
2484		switch (maxp) {
2485		case 8:
2486			epn_rxtx = 0 << 12;
2487			break;
2488		case 16:
2489			epn_rxtx = 1 << 12;
2490			break;
2491		case 32:
2492			epn_rxtx = 2 << 12;
2493			break;
2494		case 64:
2495			epn_rxtx = 3 << 12;
2496			break;
2497		case 128:
2498			epn_rxtx = 4 << 12;
2499			break;
2500		case 256:
2501			epn_rxtx = 5 << 12;
2502			break;
2503		case 512:
2504			epn_rxtx = 6 << 12;
2505			break;
2506		default:
2507			BUG();
2508		}
2509		epn_rxtx |= UDC_EPN_RX_ISO;
2510		dbuf = 1;
2511	} else {
2512		/* double-buffering "not supported" on 15xx,
2513		 * and ignored for PIO-IN on newer chips
2514		 * (for more reliable behavior)
2515		 */
2516		if (!use_dma || cpu_is_omap15xx())
2517			dbuf = 0;
2518
2519		switch (maxp) {
2520		case 8:
2521			epn_rxtx = 0 << 12;
2522			break;
2523		case 16:
2524			epn_rxtx = 1 << 12;
2525			break;
2526		case 32:
2527			epn_rxtx = 2 << 12;
2528			break;
2529		case 64:
2530			epn_rxtx = 3 << 12;
2531			break;
2532		default:
2533			BUG();
2534		}
2535		if (dbuf && addr)
2536			epn_rxtx |= UDC_EPN_RX_DB;
2537		timer_setup(&ep->timer, pio_out_timer, 0);
2538	}
2539	if (addr)
2540		epn_rxtx |= UDC_EPN_RX_VALID;
2541	BUG_ON(buf & 0x07);
2542	epn_rxtx |= buf >> 3;
2543
2544	DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2545		name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2546
2547	if (addr & USB_DIR_IN)
2548		omap_writew(epn_rxtx, UDC_EP_TX(addr & 0xf));
2549	else
2550		omap_writew(epn_rxtx, UDC_EP_RX(addr));
2551
2552	/* next endpoint's buffer starts after this one's */
2553	buf += maxp;
2554	if (dbuf)
2555		buf += maxp;
2556	BUG_ON(buf > 2048);
2557
2558	/* set up driver data structures */
2559	BUG_ON(strlen(name) >= sizeof ep->name);
2560	strscpy(ep->name, name, sizeof(ep->name));
2561	INIT_LIST_HEAD(&ep->queue);
2562	INIT_LIST_HEAD(&ep->iso);
2563	ep->bEndpointAddress = addr;
2564	ep->bmAttributes = type;
2565	ep->double_buf = dbuf;
2566	ep->udc = udc;
2567
2568	switch (type) {
2569	case USB_ENDPOINT_XFER_CONTROL:
2570		ep->ep.caps.type_control = true;
2571		ep->ep.caps.dir_in = true;
2572		ep->ep.caps.dir_out = true;
2573		break;
2574	case USB_ENDPOINT_XFER_ISOC:
2575		ep->ep.caps.type_iso = true;
2576		break;
2577	case USB_ENDPOINT_XFER_BULK:
2578		ep->ep.caps.type_bulk = true;
2579		break;
2580	case USB_ENDPOINT_XFER_INT:
2581		ep->ep.caps.type_int = true;
2582		break;
2583	}
2584
2585	if (addr & USB_DIR_IN)
2586		ep->ep.caps.dir_in = true;
2587	else
2588		ep->ep.caps.dir_out = true;
2589
2590	ep->ep.name = ep->name;
2591	ep->ep.ops = &omap_ep_ops;
2592	ep->maxpacket = maxp;
2593	usb_ep_set_maxpacket_limit(&ep->ep, ep->maxpacket);
2594	list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2595
2596	return buf;
2597}
2598
2599static void omap_udc_release(struct device *dev)
2600{
2601	pullup_disable(udc);
2602	if (!IS_ERR_OR_NULL(udc->transceiver)) {
2603		usb_put_phy(udc->transceiver);
2604		udc->transceiver = NULL;
2605	}
2606	omap_writew(0, UDC_SYSCON1);
2607	remove_proc_file();
2608	if (udc->dc_clk) {
2609		if (udc->clk_requested)
2610			omap_udc_enable_clock(0);
2611		clk_unprepare(udc->hhc_clk);
2612		clk_unprepare(udc->dc_clk);
2613		clk_put(udc->hhc_clk);
2614		clk_put(udc->dc_clk);
2615	}
2616	if (udc->done)
2617		complete(udc->done);
2618	kfree(udc);
2619}
2620
2621static int
2622omap_udc_setup(struct platform_device *odev, struct usb_phy *xceiv)
2623{
2624	unsigned	tmp, buf;
2625
2626	/* abolish any previous hardware state */
2627	omap_writew(0, UDC_SYSCON1);
2628	omap_writew(0, UDC_IRQ_EN);
2629	omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2630	omap_writew(0, UDC_DMA_IRQ_EN);
2631	omap_writew(0, UDC_RXDMA_CFG);
2632	omap_writew(0, UDC_TXDMA_CFG);
2633
2634	/* UDC_PULLUP_EN gates the chip clock */
2635	/* OTG_SYSCON_1 |= DEV_IDLE_EN; */
2636
2637	udc = kzalloc(sizeof(*udc), GFP_KERNEL);
2638	if (!udc)
2639		return -ENOMEM;
2640
2641	spin_lock_init(&udc->lock);
2642
2643	udc->gadget.ops = &omap_gadget_ops;
2644	udc->gadget.ep0 = &udc->ep[0].ep;
2645	INIT_LIST_HEAD(&udc->gadget.ep_list);
2646	INIT_LIST_HEAD(&udc->iso);
2647	udc->gadget.speed = USB_SPEED_UNKNOWN;
2648	udc->gadget.max_speed = USB_SPEED_FULL;
2649	udc->gadget.name = driver_name;
2650	udc->gadget.quirk_ep_out_aligned_size = 1;
2651	udc->transceiver = xceiv;
2652
2653	/* ep0 is special; put it right after the SETUP buffer */
2654	buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2655			8 /* after SETUP */, 64 /* maxpacket */, 0);
2656	list_del_init(&udc->ep[0].ep.ep_list);
2657
2658	/* initially disable all non-ep0 endpoints */
2659	for (tmp = 1; tmp < 15; tmp++) {
2660		omap_writew(0, UDC_EP_RX(tmp));
2661		omap_writew(0, UDC_EP_TX(tmp));
2662	}
2663
2664#define OMAP_BULK_EP(name, addr) \
2665	buf = omap_ep_setup(name "-bulk", addr, \
2666			USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2667#define OMAP_INT_EP(name, addr, maxp) \
2668	buf = omap_ep_setup(name "-int", addr, \
2669			USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2670#define OMAP_ISO_EP(name, addr, maxp) \
2671	buf = omap_ep_setup(name "-iso", addr, \
2672			USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2673
2674	switch (fifo_mode) {
2675	case 0:
2676		OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2677		OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2678		OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2679		break;
2680	case 1:
2681		OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2682		OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2683		OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2684
2685		OMAP_BULK_EP("ep3in",  USB_DIR_IN  | 3);
2686		OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2687		OMAP_INT_EP("ep10in",  USB_DIR_IN  | 10, 16);
2688
2689		OMAP_BULK_EP("ep5in",  USB_DIR_IN  | 5);
2690		OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2691		OMAP_INT_EP("ep11in",  USB_DIR_IN  | 11, 16);
2692
2693		OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2694		OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2695		OMAP_INT_EP("ep12in",  USB_DIR_IN  | 12, 16);
2696
2697		OMAP_BULK_EP("ep7in",  USB_DIR_IN  | 7);
2698		OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2699		OMAP_INT_EP("ep13in",  USB_DIR_IN  | 13, 16);
2700		OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2701
2702		OMAP_BULK_EP("ep8in",  USB_DIR_IN  | 8);
2703		OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2704		OMAP_INT_EP("ep14in",  USB_DIR_IN  | 14, 16);
2705		OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2706
2707		OMAP_BULK_EP("ep15in",  USB_DIR_IN  | 15);
2708		OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2709
2710		break;
2711
2712#ifdef	USE_ISO
2713	case 2:			/* mixed iso/bulk */
2714		OMAP_ISO_EP("ep1in",   USB_DIR_IN  | 1, 256);
2715		OMAP_ISO_EP("ep2out",  USB_DIR_OUT | 2, 256);
2716		OMAP_ISO_EP("ep3in",   USB_DIR_IN  | 3, 128);
2717		OMAP_ISO_EP("ep4out",  USB_DIR_OUT | 4, 128);
2718
2719		OMAP_INT_EP("ep5in",   USB_DIR_IN  | 5, 16);
2720
2721		OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2722		OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2723		OMAP_INT_EP("ep8in",   USB_DIR_IN  | 8, 16);
2724		break;
2725	case 3:			/* mixed bulk/iso */
2726		OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2727		OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2728		OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2729
2730		OMAP_BULK_EP("ep4in",  USB_DIR_IN  | 4);
2731		OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2732		OMAP_INT_EP("ep6in",   USB_DIR_IN  | 6, 16);
2733
2734		OMAP_ISO_EP("ep7in",   USB_DIR_IN  | 7, 256);
2735		OMAP_ISO_EP("ep8out",  USB_DIR_OUT | 8, 256);
2736		OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2737		break;
2738#endif
2739
2740	/* add more modes as needed */
2741
2742	default:
2743		ERR("unsupported fifo_mode #%d\n", fifo_mode);
2744		return -ENODEV;
2745	}
2746	omap_writew(UDC_CFG_LOCK|UDC_SELF_PWR, UDC_SYSCON1);
2747	INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2748	return 0;
2749}
2750
2751static int omap_udc_probe(struct platform_device *pdev)
2752{
2753	int			status = -ENODEV;
2754	int			hmc;
2755	struct usb_phy		*xceiv = NULL;
2756	const char		*type = NULL;
2757	struct omap_usb_config	*config = dev_get_platdata(&pdev->dev);
2758	struct clk		*dc_clk = NULL;
2759	struct clk		*hhc_clk = NULL;
2760
2761	if (cpu_is_omap7xx())
2762		use_dma = 0;
2763
2764	/* NOTE:  "knows" the order of the resources! */
2765	if (!request_mem_region(pdev->resource[0].start,
2766			resource_size(&pdev->resource[0]),
2767			driver_name)) {
2768		DBG("request_mem_region failed\n");
2769		return -EBUSY;
2770	}
2771
2772	if (cpu_is_omap16xx()) {
2773		dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2774		hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2775		BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2776		/* can't use omap_udc_enable_clock yet */
2777		clk_prepare_enable(dc_clk);
2778		clk_prepare_enable(hhc_clk);
2779		udelay(100);
2780	}
2781
2782	if (cpu_is_omap7xx()) {
2783		dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2784		hhc_clk = clk_get(&pdev->dev, "l3_ocpi_ck");
2785		BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2786		/* can't use omap_udc_enable_clock yet */
2787		clk_prepare_enable(dc_clk);
2788		clk_prepare_enable(hhc_clk);
2789		udelay(100);
2790	}
2791
2792	INFO("OMAP UDC rev %d.%d%s\n",
2793		omap_readw(UDC_REV) >> 4, omap_readw(UDC_REV) & 0xf,
2794		config->otg ? ", Mini-AB" : "");
2795
2796	/* use the mode given to us by board init code */
2797	if (cpu_is_omap15xx()) {
2798		hmc = HMC_1510;
2799		type = "(unknown)";
2800
2801		if (machine_without_vbus_sense()) {
2802			/* just set up software VBUS detect, and then
2803			 * later rig it so we always report VBUS.
2804			 * FIXME without really sensing VBUS, we can't
2805			 * know when to turn PULLUP_EN on/off; and that
2806			 * means we always "need" the 48MHz clock.
2807			 */
2808			u32 tmp = omap_readl(FUNC_MUX_CTRL_0);
2809			tmp &= ~VBUS_CTRL_1510;
2810			omap_writel(tmp, FUNC_MUX_CTRL_0);
2811			tmp |= VBUS_MODE_1510;
2812			tmp &= ~VBUS_CTRL_1510;
2813			omap_writel(tmp, FUNC_MUX_CTRL_0);
2814		}
2815	} else {
2816		/* The transceiver may package some GPIO logic or handle
2817		 * loopback and/or transceiverless setup; if we find one,
2818		 * use it.  Except for OTG, we don't _need_ to talk to one;
2819		 * but not having one probably means no VBUS detection.
2820		 */
2821		xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
2822		if (!IS_ERR_OR_NULL(xceiv))
2823			type = xceiv->label;
2824		else if (config->otg) {
2825			DBG("OTG requires external transceiver!\n");
2826			goto cleanup0;
2827		}
2828
2829		hmc = HMC_1610;
2830
2831		switch (hmc) {
2832		case 0:			/* POWERUP DEFAULT == 0 */
2833		case 4:
2834		case 12:
2835		case 20:
2836			if (!cpu_is_omap1710()) {
2837				type = "integrated";
2838				break;
2839			}
2840			fallthrough;
2841		case 3:
2842		case 11:
2843		case 16:
2844		case 19:
2845		case 25:
2846			if (IS_ERR_OR_NULL(xceiv)) {
2847				DBG("external transceiver not registered!\n");
2848				type = "unknown";
2849			}
2850			break;
2851		case 21:			/* internal loopback */
2852			type = "loopback";
2853			break;
2854		case 14:			/* transceiverless */
2855			if (cpu_is_omap1710())
2856				goto bad_on_1710;
2857			fallthrough;
2858		case 13:
2859		case 15:
2860			type = "no";
2861			break;
2862
2863		default:
2864bad_on_1710:
2865			ERR("unrecognized UDC HMC mode %d\n", hmc);
2866			goto cleanup0;
2867		}
2868	}
2869
2870	INFO("hmc mode %d, %s transceiver\n", hmc, type);
2871
2872	/* a "gadget" abstracts/virtualizes the controller */
2873	status = omap_udc_setup(pdev, xceiv);
2874	if (status)
2875		goto cleanup0;
2876
2877	xceiv = NULL;
2878	/* "udc" is now valid */
2879	pullup_disable(udc);
2880#if	IS_ENABLED(CONFIG_USB_OHCI_HCD)
2881	udc->gadget.is_otg = (config->otg != 0);
2882#endif
2883
2884	/* starting with omap1710 es2.0, clear toggle is a separate bit */
2885	if (omap_readw(UDC_REV) >= 0x61)
2886		udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2887	else
2888		udc->clr_halt = UDC_RESET_EP;
2889
2890	/* USB general purpose IRQ:  ep0, state changes, dma, etc */
2891	status = devm_request_irq(&pdev->dev, pdev->resource[1].start,
2892				  omap_udc_irq, 0, driver_name, udc);
2893	if (status != 0) {
2894		ERR("can't get irq %d, err %d\n",
2895			(int) pdev->resource[1].start, status);
2896		goto cleanup1;
2897	}
2898
2899	/* USB "non-iso" IRQ (PIO for all but ep0) */
2900	status = devm_request_irq(&pdev->dev, pdev->resource[2].start,
2901				  omap_udc_pio_irq, 0, "omap_udc pio", udc);
2902	if (status != 0) {
2903		ERR("can't get irq %d, err %d\n",
2904			(int) pdev->resource[2].start, status);
2905		goto cleanup1;
2906	}
2907#ifdef	USE_ISO
2908	status = devm_request_irq(&pdev->dev, pdev->resource[3].start,
2909				  omap_udc_iso_irq, 0, "omap_udc iso", udc);
2910	if (status != 0) {
2911		ERR("can't get irq %d, err %d\n",
2912			(int) pdev->resource[3].start, status);
2913		goto cleanup1;
2914	}
2915#endif
2916	if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2917		udc->dc_clk = dc_clk;
2918		udc->hhc_clk = hhc_clk;
2919		clk_disable(hhc_clk);
2920		clk_disable(dc_clk);
2921	}
2922
2923	create_proc_file();
2924	return usb_add_gadget_udc_release(&pdev->dev, &udc->gadget,
2925					  omap_udc_release);
2926
2927cleanup1:
2928	kfree(udc);
2929	udc = NULL;
2930
2931cleanup0:
2932	if (!IS_ERR_OR_NULL(xceiv))
2933		usb_put_phy(xceiv);
2934
2935	if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2936		clk_disable_unprepare(hhc_clk);
2937		clk_disable_unprepare(dc_clk);
2938		clk_put(hhc_clk);
2939		clk_put(dc_clk);
2940	}
2941
2942	release_mem_region(pdev->resource[0].start,
2943			   resource_size(&pdev->resource[0]));
2944
2945	return status;
2946}
2947
2948static int omap_udc_remove(struct platform_device *pdev)
2949{
2950	DECLARE_COMPLETION_ONSTACK(done);
2951
2952	udc->done = &done;
2953
2954	usb_del_gadget_udc(&udc->gadget);
2955
2956	wait_for_completion(&done);
2957
2958	release_mem_region(pdev->resource[0].start,
2959			   resource_size(&pdev->resource[0]));
2960
2961	return 0;
2962}
2963
2964/* suspend/resume/wakeup from sysfs (echo > power/state) or when the
2965 * system is forced into deep sleep
2966 *
2967 * REVISIT we should probably reject suspend requests when there's a host
2968 * session active, rather than disconnecting, at least on boards that can
2969 * report VBUS irqs (UDC_DEVSTAT.UDC_ATT).  And in any case, we need to
2970 * make host resumes and VBUS detection trigger OMAP wakeup events; that
2971 * may involve talking to an external transceiver (e.g. isp1301).
2972 */
2973
2974static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
2975{
2976	u32	devstat;
2977
2978	devstat = omap_readw(UDC_DEVSTAT);
2979
2980	/* we're requesting 48 MHz clock if the pullup is enabled
2981	 * (== we're attached to the host) and we're not suspended,
2982	 * which would prevent entry to deep sleep...
2983	 */
2984	if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
2985		WARNING("session active; suspend requires disconnect\n");
2986		omap_pullup(&udc->gadget, 0);
2987	}
2988
2989	return 0;
2990}
2991
2992static int omap_udc_resume(struct platform_device *dev)
2993{
2994	DBG("resume + wakeup/SRP\n");
2995	omap_pullup(&udc->gadget, 1);
2996
2997	/* maybe the host would enumerate us if we nudged it */
2998	msleep(100);
2999	return omap_wakeup(&udc->gadget);
3000}
3001
3002/*-------------------------------------------------------------------------*/
3003
3004static struct platform_driver udc_driver = {
3005	.probe		= omap_udc_probe,
3006	.remove		= omap_udc_remove,
3007	.suspend	= omap_udc_suspend,
3008	.resume		= omap_udc_resume,
3009	.driver		= {
3010		.name	= driver_name,
3011	},
3012};
3013
3014module_platform_driver(udc_driver);
3015
3016MODULE_DESCRIPTION(DRIVER_DESC);
3017MODULE_LICENSE("GPL");
3018MODULE_ALIAS("platform:omap_udc");