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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * R-Car PWM Timer driver
4 *
5 * Copyright (C) 2015 Renesas Electronics Corporation
6 *
7 * Limitations:
8 * - The hardware cannot generate a 0% duty cycle.
9 */
10
11#include <linux/clk.h>
12#include <linux/err.h>
13#include <linux/io.h>
14#include <linux/log2.h>
15#include <linux/math64.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/platform_device.h>
19#include <linux/pm_runtime.h>
20#include <linux/pwm.h>
21#include <linux/slab.h>
22
23#define RCAR_PWM_MAX_DIVISION 24
24#define RCAR_PWM_MAX_CYCLE 1023
25
26#define RCAR_PWMCR 0x00
27#define RCAR_PWMCR_CC0_MASK 0x000f0000
28#define RCAR_PWMCR_CC0_SHIFT 16
29#define RCAR_PWMCR_CCMD BIT(15)
30#define RCAR_PWMCR_SYNC BIT(11)
31#define RCAR_PWMCR_SS0 BIT(4)
32#define RCAR_PWMCR_EN0 BIT(0)
33
34#define RCAR_PWMCNT 0x04
35#define RCAR_PWMCNT_CYC0_MASK 0x03ff0000
36#define RCAR_PWMCNT_CYC0_SHIFT 16
37#define RCAR_PWMCNT_PH0_MASK 0x000003ff
38#define RCAR_PWMCNT_PH0_SHIFT 0
39
40struct rcar_pwm_chip {
41 struct pwm_chip chip;
42 void __iomem *base;
43 struct clk *clk;
44};
45
46static inline struct rcar_pwm_chip *to_rcar_pwm_chip(struct pwm_chip *chip)
47{
48 return container_of(chip, struct rcar_pwm_chip, chip);
49}
50
51static void rcar_pwm_write(struct rcar_pwm_chip *rp, u32 data,
52 unsigned int offset)
53{
54 writel(data, rp->base + offset);
55}
56
57static u32 rcar_pwm_read(struct rcar_pwm_chip *rp, unsigned int offset)
58{
59 return readl(rp->base + offset);
60}
61
62static void rcar_pwm_update(struct rcar_pwm_chip *rp, u32 mask, u32 data,
63 unsigned int offset)
64{
65 u32 value;
66
67 value = rcar_pwm_read(rp, offset);
68 value &= ~mask;
69 value |= data & mask;
70 rcar_pwm_write(rp, value, offset);
71}
72
73static int rcar_pwm_get_clock_division(struct rcar_pwm_chip *rp, int period_ns)
74{
75 unsigned long clk_rate = clk_get_rate(rp->clk);
76 u64 div, tmp;
77
78 if (clk_rate == 0)
79 return -EINVAL;
80
81 div = (u64)NSEC_PER_SEC * RCAR_PWM_MAX_CYCLE;
82 tmp = (u64)period_ns * clk_rate + div - 1;
83 tmp = div64_u64(tmp, div);
84 div = ilog2(tmp - 1) + 1;
85
86 return (div <= RCAR_PWM_MAX_DIVISION) ? div : -ERANGE;
87}
88
89static void rcar_pwm_set_clock_control(struct rcar_pwm_chip *rp,
90 unsigned int div)
91{
92 u32 value;
93
94 value = rcar_pwm_read(rp, RCAR_PWMCR);
95 value &= ~(RCAR_PWMCR_CCMD | RCAR_PWMCR_CC0_MASK);
96
97 if (div & 1)
98 value |= RCAR_PWMCR_CCMD;
99
100 div >>= 1;
101
102 value |= div << RCAR_PWMCR_CC0_SHIFT;
103 rcar_pwm_write(rp, value, RCAR_PWMCR);
104}
105
106static int rcar_pwm_set_counter(struct rcar_pwm_chip *rp, int div, int duty_ns,
107 int period_ns)
108{
109 unsigned long long one_cycle, tmp; /* 0.01 nanoseconds */
110 unsigned long clk_rate = clk_get_rate(rp->clk);
111 u32 cyc, ph;
112
113 one_cycle = NSEC_PER_SEC * 100ULL << div;
114 do_div(one_cycle, clk_rate);
115
116 tmp = period_ns * 100ULL;
117 do_div(tmp, one_cycle);
118 cyc = (tmp << RCAR_PWMCNT_CYC0_SHIFT) & RCAR_PWMCNT_CYC0_MASK;
119
120 tmp = duty_ns * 100ULL;
121 do_div(tmp, one_cycle);
122 ph = tmp & RCAR_PWMCNT_PH0_MASK;
123
124 /* Avoid prohibited setting */
125 if (cyc == 0 || ph == 0)
126 return -EINVAL;
127
128 rcar_pwm_write(rp, cyc | ph, RCAR_PWMCNT);
129
130 return 0;
131}
132
133static int rcar_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
134{
135 return pm_runtime_get_sync(chip->dev);
136}
137
138static void rcar_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
139{
140 pm_runtime_put(chip->dev);
141}
142
143static int rcar_pwm_enable(struct rcar_pwm_chip *rp)
144{
145 u32 value;
146
147 /* Don't enable the PWM device if CYC0 or PH0 is 0 */
148 value = rcar_pwm_read(rp, RCAR_PWMCNT);
149 if ((value & RCAR_PWMCNT_CYC0_MASK) == 0 ||
150 (value & RCAR_PWMCNT_PH0_MASK) == 0)
151 return -EINVAL;
152
153 rcar_pwm_update(rp, RCAR_PWMCR_EN0, RCAR_PWMCR_EN0, RCAR_PWMCR);
154
155 return 0;
156}
157
158static void rcar_pwm_disable(struct rcar_pwm_chip *rp)
159{
160 rcar_pwm_update(rp, RCAR_PWMCR_EN0, 0, RCAR_PWMCR);
161}
162
163static int rcar_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
164 const struct pwm_state *state)
165{
166 struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip);
167 int div, ret;
168
169 /* This HW/driver only supports normal polarity */
170 if (state->polarity != PWM_POLARITY_NORMAL)
171 return -EINVAL;
172
173 if (!state->enabled) {
174 rcar_pwm_disable(rp);
175 return 0;
176 }
177
178 div = rcar_pwm_get_clock_division(rp, state->period);
179 if (div < 0)
180 return div;
181
182 rcar_pwm_update(rp, RCAR_PWMCR_SYNC, RCAR_PWMCR_SYNC, RCAR_PWMCR);
183
184 ret = rcar_pwm_set_counter(rp, div, state->duty_cycle, state->period);
185 if (!ret)
186 rcar_pwm_set_clock_control(rp, div);
187
188 /* The SYNC should be set to 0 even if rcar_pwm_set_counter failed */
189 rcar_pwm_update(rp, RCAR_PWMCR_SYNC, 0, RCAR_PWMCR);
190
191 if (!ret)
192 ret = rcar_pwm_enable(rp);
193
194 return ret;
195}
196
197static const struct pwm_ops rcar_pwm_ops = {
198 .request = rcar_pwm_request,
199 .free = rcar_pwm_free,
200 .apply = rcar_pwm_apply,
201 .owner = THIS_MODULE,
202};
203
204static int rcar_pwm_probe(struct platform_device *pdev)
205{
206 struct rcar_pwm_chip *rcar_pwm;
207 int ret;
208
209 rcar_pwm = devm_kzalloc(&pdev->dev, sizeof(*rcar_pwm), GFP_KERNEL);
210 if (rcar_pwm == NULL)
211 return -ENOMEM;
212
213 rcar_pwm->base = devm_platform_ioremap_resource(pdev, 0);
214 if (IS_ERR(rcar_pwm->base))
215 return PTR_ERR(rcar_pwm->base);
216
217 rcar_pwm->clk = devm_clk_get(&pdev->dev, NULL);
218 if (IS_ERR(rcar_pwm->clk)) {
219 dev_err(&pdev->dev, "cannot get clock\n");
220 return PTR_ERR(rcar_pwm->clk);
221 }
222
223 platform_set_drvdata(pdev, rcar_pwm);
224
225 rcar_pwm->chip.dev = &pdev->dev;
226 rcar_pwm->chip.ops = &rcar_pwm_ops;
227 rcar_pwm->chip.npwm = 1;
228
229 pm_runtime_enable(&pdev->dev);
230
231 ret = pwmchip_add(&rcar_pwm->chip);
232 if (ret < 0) {
233 dev_err(&pdev->dev, "failed to register PWM chip: %d\n", ret);
234 pm_runtime_disable(&pdev->dev);
235 return ret;
236 }
237
238 return 0;
239}
240
241static int rcar_pwm_remove(struct platform_device *pdev)
242{
243 struct rcar_pwm_chip *rcar_pwm = platform_get_drvdata(pdev);
244
245 pwmchip_remove(&rcar_pwm->chip);
246
247 pm_runtime_disable(&pdev->dev);
248
249 return 0;
250}
251
252static const struct of_device_id rcar_pwm_of_table[] = {
253 { .compatible = "renesas,pwm-rcar", },
254 { },
255};
256MODULE_DEVICE_TABLE(of, rcar_pwm_of_table);
257
258static struct platform_driver rcar_pwm_driver = {
259 .probe = rcar_pwm_probe,
260 .remove = rcar_pwm_remove,
261 .driver = {
262 .name = "pwm-rcar",
263 .of_match_table = of_match_ptr(rcar_pwm_of_table),
264 }
265};
266module_platform_driver(rcar_pwm_driver);
267
268MODULE_AUTHOR("Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>");
269MODULE_DESCRIPTION("Renesas PWM Timer Driver");
270MODULE_LICENSE("GPL v2");
271MODULE_ALIAS("platform:pwm-rcar");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * R-Car PWM Timer driver
4 *
5 * Copyright (C) 2015 Renesas Electronics Corporation
6 *
7 * Limitations:
8 * - The hardware cannot generate a 0% duty cycle.
9 */
10
11#include <linux/clk.h>
12#include <linux/err.h>
13#include <linux/io.h>
14#include <linux/log2.h>
15#include <linux/math64.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/platform_device.h>
19#include <linux/pm_runtime.h>
20#include <linux/pwm.h>
21#include <linux/slab.h>
22
23#define RCAR_PWM_MAX_DIVISION 24
24#define RCAR_PWM_MAX_CYCLE 1023
25
26#define RCAR_PWMCR 0x00
27#define RCAR_PWMCR_CC0_MASK 0x000f0000
28#define RCAR_PWMCR_CC0_SHIFT 16
29#define RCAR_PWMCR_CCMD BIT(15)
30#define RCAR_PWMCR_SYNC BIT(11)
31#define RCAR_PWMCR_SS0 BIT(4)
32#define RCAR_PWMCR_EN0 BIT(0)
33
34#define RCAR_PWMCNT 0x04
35#define RCAR_PWMCNT_CYC0_MASK 0x03ff0000
36#define RCAR_PWMCNT_CYC0_SHIFT 16
37#define RCAR_PWMCNT_PH0_MASK 0x000003ff
38#define RCAR_PWMCNT_PH0_SHIFT 0
39
40struct rcar_pwm_chip {
41 void __iomem *base;
42 struct clk *clk;
43};
44
45static inline struct rcar_pwm_chip *to_rcar_pwm_chip(struct pwm_chip *chip)
46{
47 return pwmchip_get_drvdata(chip);
48}
49
50static void rcar_pwm_write(struct rcar_pwm_chip *rp, u32 data,
51 unsigned int offset)
52{
53 writel(data, rp->base + offset);
54}
55
56static u32 rcar_pwm_read(struct rcar_pwm_chip *rp, unsigned int offset)
57{
58 return readl(rp->base + offset);
59}
60
61static void rcar_pwm_update(struct rcar_pwm_chip *rp, u32 mask, u32 data,
62 unsigned int offset)
63{
64 u32 value;
65
66 value = rcar_pwm_read(rp, offset);
67 value &= ~mask;
68 value |= data & mask;
69 rcar_pwm_write(rp, value, offset);
70}
71
72static int rcar_pwm_get_clock_division(struct rcar_pwm_chip *rp, int period_ns)
73{
74 unsigned long clk_rate = clk_get_rate(rp->clk);
75 u64 div, tmp;
76
77 if (clk_rate == 0)
78 return -EINVAL;
79
80 div = (u64)NSEC_PER_SEC * RCAR_PWM_MAX_CYCLE;
81 tmp = (u64)period_ns * clk_rate + div - 1;
82 tmp = div64_u64(tmp, div);
83 div = ilog2(tmp - 1) + 1;
84
85 return (div <= RCAR_PWM_MAX_DIVISION) ? div : -ERANGE;
86}
87
88static void rcar_pwm_set_clock_control(struct rcar_pwm_chip *rp,
89 unsigned int div)
90{
91 u32 value;
92
93 value = rcar_pwm_read(rp, RCAR_PWMCR);
94 value &= ~(RCAR_PWMCR_CCMD | RCAR_PWMCR_CC0_MASK);
95
96 if (div & 1)
97 value |= RCAR_PWMCR_CCMD;
98
99 div >>= 1;
100
101 value |= div << RCAR_PWMCR_CC0_SHIFT;
102 rcar_pwm_write(rp, value, RCAR_PWMCR);
103}
104
105static int rcar_pwm_set_counter(struct rcar_pwm_chip *rp, int div, int duty_ns,
106 int period_ns)
107{
108 unsigned long long one_cycle, tmp; /* 0.01 nanoseconds */
109 unsigned long clk_rate = clk_get_rate(rp->clk);
110 u32 cyc, ph;
111
112 one_cycle = NSEC_PER_SEC * 100ULL << div;
113 do_div(one_cycle, clk_rate);
114
115 tmp = period_ns * 100ULL;
116 do_div(tmp, one_cycle);
117 cyc = (tmp << RCAR_PWMCNT_CYC0_SHIFT) & RCAR_PWMCNT_CYC0_MASK;
118
119 tmp = duty_ns * 100ULL;
120 do_div(tmp, one_cycle);
121 ph = tmp & RCAR_PWMCNT_PH0_MASK;
122
123 /* Avoid prohibited setting */
124 if (cyc == 0 || ph == 0)
125 return -EINVAL;
126
127 rcar_pwm_write(rp, cyc | ph, RCAR_PWMCNT);
128
129 return 0;
130}
131
132static int rcar_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
133{
134 return pm_runtime_get_sync(pwmchip_parent(chip));
135}
136
137static void rcar_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
138{
139 pm_runtime_put(pwmchip_parent(chip));
140}
141
142static int rcar_pwm_enable(struct rcar_pwm_chip *rp)
143{
144 u32 value;
145
146 /* Don't enable the PWM device if CYC0 or PH0 is 0 */
147 value = rcar_pwm_read(rp, RCAR_PWMCNT);
148 if ((value & RCAR_PWMCNT_CYC0_MASK) == 0 ||
149 (value & RCAR_PWMCNT_PH0_MASK) == 0)
150 return -EINVAL;
151
152 rcar_pwm_update(rp, RCAR_PWMCR_EN0, RCAR_PWMCR_EN0, RCAR_PWMCR);
153
154 return 0;
155}
156
157static void rcar_pwm_disable(struct rcar_pwm_chip *rp)
158{
159 rcar_pwm_update(rp, RCAR_PWMCR_EN0, 0, RCAR_PWMCR);
160}
161
162static int rcar_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
163 const struct pwm_state *state)
164{
165 struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip);
166 int div, ret;
167
168 /* This HW/driver only supports normal polarity */
169 if (state->polarity != PWM_POLARITY_NORMAL)
170 return -EINVAL;
171
172 if (!state->enabled) {
173 rcar_pwm_disable(rp);
174 return 0;
175 }
176
177 div = rcar_pwm_get_clock_division(rp, state->period);
178 if (div < 0)
179 return div;
180
181 rcar_pwm_update(rp, RCAR_PWMCR_SYNC, RCAR_PWMCR_SYNC, RCAR_PWMCR);
182
183 ret = rcar_pwm_set_counter(rp, div, state->duty_cycle, state->period);
184 if (!ret)
185 rcar_pwm_set_clock_control(rp, div);
186
187 /* The SYNC should be set to 0 even if rcar_pwm_set_counter failed */
188 rcar_pwm_update(rp, RCAR_PWMCR_SYNC, 0, RCAR_PWMCR);
189
190 if (!ret)
191 ret = rcar_pwm_enable(rp);
192
193 return ret;
194}
195
196static const struct pwm_ops rcar_pwm_ops = {
197 .request = rcar_pwm_request,
198 .free = rcar_pwm_free,
199 .apply = rcar_pwm_apply,
200};
201
202static int rcar_pwm_probe(struct platform_device *pdev)
203{
204 struct pwm_chip *chip;
205 struct rcar_pwm_chip *rcar_pwm;
206 int ret;
207
208 chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*rcar_pwm));
209 if (IS_ERR(chip))
210 return PTR_ERR(chip);
211 rcar_pwm = to_rcar_pwm_chip(chip);
212
213 rcar_pwm->base = devm_platform_ioremap_resource(pdev, 0);
214 if (IS_ERR(rcar_pwm->base))
215 return PTR_ERR(rcar_pwm->base);
216
217 rcar_pwm->clk = devm_clk_get(&pdev->dev, NULL);
218 if (IS_ERR(rcar_pwm->clk)) {
219 dev_err(&pdev->dev, "cannot get clock\n");
220 return PTR_ERR(rcar_pwm->clk);
221 }
222
223 chip->ops = &rcar_pwm_ops;
224
225 platform_set_drvdata(pdev, chip);
226
227 pm_runtime_enable(&pdev->dev);
228
229 ret = pwmchip_add(chip);
230 if (ret < 0) {
231 dev_err(&pdev->dev, "failed to register PWM chip: %d\n", ret);
232 pm_runtime_disable(&pdev->dev);
233 return ret;
234 }
235
236 return 0;
237}
238
239static void rcar_pwm_remove(struct platform_device *pdev)
240{
241 struct pwm_chip *chip = platform_get_drvdata(pdev);
242
243 pwmchip_remove(chip);
244
245 pm_runtime_disable(&pdev->dev);
246}
247
248static const struct of_device_id rcar_pwm_of_table[] = {
249 { .compatible = "renesas,pwm-rcar", },
250 { },
251};
252MODULE_DEVICE_TABLE(of, rcar_pwm_of_table);
253
254static struct platform_driver rcar_pwm_driver = {
255 .probe = rcar_pwm_probe,
256 .remove = rcar_pwm_remove,
257 .driver = {
258 .name = "pwm-rcar",
259 .of_match_table = rcar_pwm_of_table,
260 }
261};
262module_platform_driver(rcar_pwm_driver);
263
264MODULE_AUTHOR("Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>");
265MODULE_DESCRIPTION("Renesas PWM Timer Driver");
266MODULE_LICENSE("GPL v2");
267MODULE_ALIAS("platform:pwm-rcar");