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1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/*
3 * Copyright (C) 2005-2014, 2018-2022 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
6 */
7#ifndef __iwl_trans_h__
8#define __iwl_trans_h__
9
10#include <linux/ieee80211.h>
11#include <linux/mm.h> /* for page_address */
12#include <linux/lockdep.h>
13#include <linux/kernel.h>
14
15#include "iwl-debug.h"
16#include "iwl-config.h"
17#include "fw/img.h"
18#include "iwl-op-mode.h"
19#include <linux/firmware.h>
20#include "fw/api/cmdhdr.h"
21#include "fw/api/txq.h"
22#include "fw/api/dbg-tlv.h"
23#include "iwl-dbg-tlv.h"
24
25/**
26 * DOC: Transport layer - what is it ?
27 *
28 * The transport layer is the layer that deals with the HW directly. It provides
29 * an abstraction of the underlying HW to the upper layer. The transport layer
30 * doesn't provide any policy, algorithm or anything of this kind, but only
31 * mechanisms to make the HW do something. It is not completely stateless but
32 * close to it.
33 * We will have an implementation for each different supported bus.
34 */
35
36/**
37 * DOC: Life cycle of the transport layer
38 *
39 * The transport layer has a very precise life cycle.
40 *
41 * 1) A helper function is called during the module initialization and
42 * registers the bus driver's ops with the transport's alloc function.
43 * 2) Bus's probe calls to the transport layer's allocation functions.
44 * Of course this function is bus specific.
45 * 3) This allocation functions will spawn the upper layer which will
46 * register mac80211.
47 *
48 * 4) At some point (i.e. mac80211's start call), the op_mode will call
49 * the following sequence:
50 * start_hw
51 * start_fw
52 *
53 * 5) Then when finished (or reset):
54 * stop_device
55 *
56 * 6) Eventually, the free function will be called.
57 */
58
59#define IWL_TRANS_FW_DBG_DOMAIN(trans) IWL_FW_INI_DOMAIN_ALWAYS_ON
60
61#define FH_RSCSR_FRAME_SIZE_MSK 0x00003FFF /* bits 0-13 */
62#define FH_RSCSR_FRAME_INVALID 0x55550000
63#define FH_RSCSR_FRAME_ALIGN 0x40
64#define FH_RSCSR_RPA_EN BIT(25)
65#define FH_RSCSR_RADA_EN BIT(26)
66#define FH_RSCSR_RXQ_POS 16
67#define FH_RSCSR_RXQ_MASK 0x3F0000
68
69struct iwl_rx_packet {
70 /*
71 * The first 4 bytes of the RX frame header contain both the RX frame
72 * size and some flags.
73 * Bit fields:
74 * 31: flag flush RB request
75 * 30: flag ignore TC (terminal counter) request
76 * 29: flag fast IRQ request
77 * 28-27: Reserved
78 * 26: RADA enabled
79 * 25: Offload enabled
80 * 24: RPF enabled
81 * 23: RSS enabled
82 * 22: Checksum enabled
83 * 21-16: RX queue
84 * 15-14: Reserved
85 * 13-00: RX frame size
86 */
87 __le32 len_n_flags;
88 struct iwl_cmd_header hdr;
89 u8 data[];
90} __packed;
91
92static inline u32 iwl_rx_packet_len(const struct iwl_rx_packet *pkt)
93{
94 return le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
95}
96
97static inline u32 iwl_rx_packet_payload_len(const struct iwl_rx_packet *pkt)
98{
99 return iwl_rx_packet_len(pkt) - sizeof(pkt->hdr);
100}
101
102/**
103 * enum CMD_MODE - how to send the host commands ?
104 *
105 * @CMD_ASYNC: Return right away and don't wait for the response
106 * @CMD_WANT_SKB: Not valid with CMD_ASYNC. The caller needs the buffer of
107 * the response. The caller needs to call iwl_free_resp when done.
108 * @CMD_WANT_ASYNC_CALLBACK: the op_mode's async callback function must be
109 * called after this command completes. Valid only with CMD_ASYNC.
110 * @CMD_SEND_IN_D3: Allow the command to be sent in D3 mode, relevant to
111 * SUSPEND and RESUME commands. We are in D3 mode when we set
112 * trans->system_pm_mode to IWL_PLAT_PM_MODE_D3.
113 */
114enum CMD_MODE {
115 CMD_ASYNC = BIT(0),
116 CMD_WANT_SKB = BIT(1),
117 CMD_SEND_IN_RFKILL = BIT(2),
118 CMD_WANT_ASYNC_CALLBACK = BIT(3),
119 CMD_SEND_IN_D3 = BIT(4),
120};
121
122#define DEF_CMD_PAYLOAD_SIZE 320
123
124/**
125 * struct iwl_device_cmd
126 *
127 * For allocation of the command and tx queues, this establishes the overall
128 * size of the largest command we send to uCode, except for commands that
129 * aren't fully copied and use other TFD space.
130 */
131struct iwl_device_cmd {
132 union {
133 struct {
134 struct iwl_cmd_header hdr; /* uCode API */
135 u8 payload[DEF_CMD_PAYLOAD_SIZE];
136 };
137 struct {
138 struct iwl_cmd_header_wide hdr_wide;
139 u8 payload_wide[DEF_CMD_PAYLOAD_SIZE -
140 sizeof(struct iwl_cmd_header_wide) +
141 sizeof(struct iwl_cmd_header)];
142 };
143 };
144} __packed;
145
146/**
147 * struct iwl_device_tx_cmd - buffer for TX command
148 * @hdr: the header
149 * @payload: the payload placeholder
150 *
151 * The actual structure is sized dynamically according to need.
152 */
153struct iwl_device_tx_cmd {
154 struct iwl_cmd_header hdr;
155 u8 payload[];
156} __packed;
157
158#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd))
159
160/*
161 * number of transfer buffers (fragments) per transmit frame descriptor;
162 * this is just the driver's idea, the hardware supports 20
163 */
164#define IWL_MAX_CMD_TBS_PER_TFD 2
165
166/* We need 2 entries for the TX command and header, and another one might
167 * be needed for potential data in the SKB's head. The remaining ones can
168 * be used for frags.
169 */
170#define IWL_TRANS_MAX_FRAGS(trans) ((trans)->txqs.tfd.max_tbs - 3)
171
172/**
173 * enum iwl_hcmd_dataflag - flag for each one of the chunks of the command
174 *
175 * @IWL_HCMD_DFL_NOCOPY: By default, the command is copied to the host command's
176 * ring. The transport layer doesn't map the command's buffer to DMA, but
177 * rather copies it to a previously allocated DMA buffer. This flag tells
178 * the transport layer not to copy the command, but to map the existing
179 * buffer (that is passed in) instead. This saves the memcpy and allows
180 * commands that are bigger than the fixed buffer to be submitted.
181 * Note that a TFD entry after a NOCOPY one cannot be a normal copied one.
182 * @IWL_HCMD_DFL_DUP: Only valid without NOCOPY, duplicate the memory for this
183 * chunk internally and free it again after the command completes. This
184 * can (currently) be used only once per command.
185 * Note that a TFD entry after a DUP one cannot be a normal copied one.
186 */
187enum iwl_hcmd_dataflag {
188 IWL_HCMD_DFL_NOCOPY = BIT(0),
189 IWL_HCMD_DFL_DUP = BIT(1),
190};
191
192enum iwl_error_event_table_status {
193 IWL_ERROR_EVENT_TABLE_LMAC1 = BIT(0),
194 IWL_ERROR_EVENT_TABLE_LMAC2 = BIT(1),
195 IWL_ERROR_EVENT_TABLE_UMAC = BIT(2),
196 IWL_ERROR_EVENT_TABLE_TCM1 = BIT(3),
197 IWL_ERROR_EVENT_TABLE_TCM2 = BIT(4),
198 IWL_ERROR_EVENT_TABLE_RCM1 = BIT(5),
199 IWL_ERROR_EVENT_TABLE_RCM2 = BIT(6),
200};
201
202/**
203 * struct iwl_host_cmd - Host command to the uCode
204 *
205 * @data: array of chunks that composes the data of the host command
206 * @resp_pkt: response packet, if %CMD_WANT_SKB was set
207 * @_rx_page_order: (internally used to free response packet)
208 * @_rx_page_addr: (internally used to free response packet)
209 * @flags: can be CMD_*
210 * @len: array of the lengths of the chunks in data
211 * @dataflags: IWL_HCMD_DFL_*
212 * @id: command id of the host command, for wide commands encoding the
213 * version and group as well
214 */
215struct iwl_host_cmd {
216 const void *data[IWL_MAX_CMD_TBS_PER_TFD];
217 struct iwl_rx_packet *resp_pkt;
218 unsigned long _rx_page_addr;
219 u32 _rx_page_order;
220
221 u32 flags;
222 u32 id;
223 u16 len[IWL_MAX_CMD_TBS_PER_TFD];
224 u8 dataflags[IWL_MAX_CMD_TBS_PER_TFD];
225};
226
227static inline void iwl_free_resp(struct iwl_host_cmd *cmd)
228{
229 free_pages(cmd->_rx_page_addr, cmd->_rx_page_order);
230}
231
232struct iwl_rx_cmd_buffer {
233 struct page *_page;
234 int _offset;
235 bool _page_stolen;
236 u32 _rx_page_order;
237 unsigned int truesize;
238};
239
240static inline void *rxb_addr(struct iwl_rx_cmd_buffer *r)
241{
242 return (void *)((unsigned long)page_address(r->_page) + r->_offset);
243}
244
245static inline int rxb_offset(struct iwl_rx_cmd_buffer *r)
246{
247 return r->_offset;
248}
249
250static inline struct page *rxb_steal_page(struct iwl_rx_cmd_buffer *r)
251{
252 r->_page_stolen = true;
253 get_page(r->_page);
254 return r->_page;
255}
256
257static inline void iwl_free_rxb(struct iwl_rx_cmd_buffer *r)
258{
259 __free_pages(r->_page, r->_rx_page_order);
260}
261
262#define MAX_NO_RECLAIM_CMDS 6
263
264#define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
265
266/*
267 * Maximum number of HW queues the transport layer
268 * currently supports
269 */
270#define IWL_MAX_HW_QUEUES 32
271#define IWL_MAX_TVQM_QUEUES 512
272
273#define IWL_MAX_TID_COUNT 8
274#define IWL_MGMT_TID 15
275#define IWL_FRAME_LIMIT 64
276#define IWL_MAX_RX_HW_QUEUES 16
277#define IWL_9000_MAX_RX_HW_QUEUES 6
278
279/**
280 * enum iwl_wowlan_status - WoWLAN image/device status
281 * @IWL_D3_STATUS_ALIVE: firmware is still running after resume
282 * @IWL_D3_STATUS_RESET: device was reset while suspended
283 */
284enum iwl_d3_status {
285 IWL_D3_STATUS_ALIVE,
286 IWL_D3_STATUS_RESET,
287};
288
289/**
290 * enum iwl_trans_status: transport status flags
291 * @STATUS_SYNC_HCMD_ACTIVE: a SYNC command is being processed
292 * @STATUS_DEVICE_ENABLED: APM is enabled
293 * @STATUS_TPOWER_PMI: the device might be asleep (need to wake it up)
294 * @STATUS_INT_ENABLED: interrupts are enabled
295 * @STATUS_RFKILL_HW: the actual HW state of the RF-kill switch
296 * @STATUS_RFKILL_OPMODE: RF-kill state reported to opmode
297 * @STATUS_FW_ERROR: the fw is in error state
298 * @STATUS_TRANS_GOING_IDLE: shutting down the trans, only special commands
299 * are sent
300 * @STATUS_TRANS_IDLE: the trans is idle - general commands are not to be sent
301 * @STATUS_TRANS_DEAD: trans is dead - avoid any read/write operation
302 * @STATUS_SUPPRESS_CMD_ERROR_ONCE: suppress "FW error in SYNC CMD" once,
303 * e.g. for testing
304 */
305enum iwl_trans_status {
306 STATUS_SYNC_HCMD_ACTIVE,
307 STATUS_DEVICE_ENABLED,
308 STATUS_TPOWER_PMI,
309 STATUS_INT_ENABLED,
310 STATUS_RFKILL_HW,
311 STATUS_RFKILL_OPMODE,
312 STATUS_FW_ERROR,
313 STATUS_TRANS_GOING_IDLE,
314 STATUS_TRANS_IDLE,
315 STATUS_TRANS_DEAD,
316 STATUS_SUPPRESS_CMD_ERROR_ONCE,
317};
318
319static inline int
320iwl_trans_get_rb_size_order(enum iwl_amsdu_size rb_size)
321{
322 switch (rb_size) {
323 case IWL_AMSDU_2K:
324 return get_order(2 * 1024);
325 case IWL_AMSDU_4K:
326 return get_order(4 * 1024);
327 case IWL_AMSDU_8K:
328 return get_order(8 * 1024);
329 case IWL_AMSDU_12K:
330 return get_order(16 * 1024);
331 default:
332 WARN_ON(1);
333 return -1;
334 }
335}
336
337static inline int
338iwl_trans_get_rb_size(enum iwl_amsdu_size rb_size)
339{
340 switch (rb_size) {
341 case IWL_AMSDU_2K:
342 return 2 * 1024;
343 case IWL_AMSDU_4K:
344 return 4 * 1024;
345 case IWL_AMSDU_8K:
346 return 8 * 1024;
347 case IWL_AMSDU_12K:
348 return 16 * 1024;
349 default:
350 WARN_ON(1);
351 return 0;
352 }
353}
354
355struct iwl_hcmd_names {
356 u8 cmd_id;
357 const char *const cmd_name;
358};
359
360#define HCMD_NAME(x) \
361 { .cmd_id = x, .cmd_name = #x }
362
363struct iwl_hcmd_arr {
364 const struct iwl_hcmd_names *arr;
365 int size;
366};
367
368#define HCMD_ARR(x) \
369 { .arr = x, .size = ARRAY_SIZE(x) }
370
371/**
372 * struct iwl_dump_sanitize_ops - dump sanitization operations
373 * @frob_txf: Scrub the TX FIFO data
374 * @frob_hcmd: Scrub a host command, the %hcmd pointer is to the header
375 * but that might be short or long (&struct iwl_cmd_header or
376 * &struct iwl_cmd_header_wide)
377 * @frob_mem: Scrub memory data
378 */
379struct iwl_dump_sanitize_ops {
380 void (*frob_txf)(void *ctx, void *buf, size_t buflen);
381 void (*frob_hcmd)(void *ctx, void *hcmd, size_t buflen);
382 void (*frob_mem)(void *ctx, u32 mem_addr, void *mem, size_t buflen);
383};
384
385/**
386 * struct iwl_trans_config - transport configuration
387 *
388 * @op_mode: pointer to the upper layer.
389 * @cmd_queue: the index of the command queue.
390 * Must be set before start_fw.
391 * @cmd_fifo: the fifo for host commands
392 * @cmd_q_wdg_timeout: the timeout of the watchdog timer for the command queue.
393 * @no_reclaim_cmds: Some devices erroneously don't set the
394 * SEQ_RX_FRAME bit on some notifications, this is the
395 * list of such notifications to filter. Max length is
396 * %MAX_NO_RECLAIM_CMDS.
397 * @n_no_reclaim_cmds: # of commands in list
398 * @rx_buf_size: RX buffer size needed for A-MSDUs
399 * if unset 4k will be the RX buffer size
400 * @bc_table_dword: set to true if the BC table expects the byte count to be
401 * in DWORD (as opposed to bytes)
402 * @scd_set_active: should the transport configure the SCD for HCMD queue
403 * @command_groups: array of command groups, each member is an array of the
404 * commands in the group; for debugging only
405 * @command_groups_size: number of command groups, to avoid illegal access
406 * @cb_data_offs: offset inside skb->cb to store transport data at, must have
407 * space for at least two pointers
408 * @fw_reset_handshake: firmware supports reset flow handshake
409 * @queue_alloc_cmd_ver: queue allocation command version, set to 0
410 * for using the older SCD_QUEUE_CFG, set to the version of
411 * SCD_QUEUE_CONFIG_CMD otherwise.
412 */
413struct iwl_trans_config {
414 struct iwl_op_mode *op_mode;
415
416 u8 cmd_queue;
417 u8 cmd_fifo;
418 unsigned int cmd_q_wdg_timeout;
419 const u8 *no_reclaim_cmds;
420 unsigned int n_no_reclaim_cmds;
421
422 enum iwl_amsdu_size rx_buf_size;
423 bool bc_table_dword;
424 bool scd_set_active;
425 const struct iwl_hcmd_arr *command_groups;
426 int command_groups_size;
427
428 u8 cb_data_offs;
429 bool fw_reset_handshake;
430 u8 queue_alloc_cmd_ver;
431};
432
433struct iwl_trans_dump_data {
434 u32 len;
435 u8 data[];
436};
437
438struct iwl_trans;
439
440struct iwl_trans_txq_scd_cfg {
441 u8 fifo;
442 u8 sta_id;
443 u8 tid;
444 bool aggregate;
445 int frame_limit;
446};
447
448/**
449 * struct iwl_trans_rxq_dma_data - RX queue DMA data
450 * @fr_bd_cb: DMA address of free BD cyclic buffer
451 * @fr_bd_wid: Initial write index of the free BD cyclic buffer
452 * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr
453 * @ur_bd_cb: DMA address of used BD cyclic buffer
454 */
455struct iwl_trans_rxq_dma_data {
456 u64 fr_bd_cb;
457 u32 fr_bd_wid;
458 u64 urbd_stts_wrptr;
459 u64 ur_bd_cb;
460};
461
462/**
463 * struct iwl_trans_ops - transport specific operations
464 *
465 * All the handlers MUST be implemented
466 *
467 * @start_hw: starts the HW. From that point on, the HW can send interrupts.
468 * May sleep.
469 * @op_mode_leave: Turn off the HW RF kill indication if on
470 * May sleep
471 * @start_fw: allocates and inits all the resources for the transport
472 * layer. Also kick a fw image.
473 * May sleep
474 * @fw_alive: called when the fw sends alive notification. If the fw provides
475 * the SCD base address in SRAM, then provide it here, or 0 otherwise.
476 * May sleep
477 * @stop_device: stops the whole device (embedded CPU put to reset) and stops
478 * the HW. From that point on, the HW will be stopped but will still issue
479 * an interrupt if the HW RF kill switch is triggered.
480 * This callback must do the right thing and not crash even if %start_hw()
481 * was called but not &start_fw(). May sleep.
482 * @d3_suspend: put the device into the correct mode for WoWLAN during
483 * suspend. This is optional, if not implemented WoWLAN will not be
484 * supported. This callback may sleep.
485 * @d3_resume: resume the device after WoWLAN, enabling the opmode to
486 * talk to the WoWLAN image to get its status. This is optional, if not
487 * implemented WoWLAN will not be supported. This callback may sleep.
488 * @send_cmd:send a host command. Must return -ERFKILL if RFkill is asserted.
489 * If RFkill is asserted in the middle of a SYNC host command, it must
490 * return -ERFKILL straight away.
491 * May sleep only if CMD_ASYNC is not set
492 * @tx: send an skb. The transport relies on the op_mode to zero the
493 * the ieee80211_tx_info->driver_data. If the MPDU is an A-MSDU, all
494 * the CSUM will be taken care of (TCP CSUM and IP header in case of
495 * IPv4). If the MPDU is a single MSDU, the op_mode must compute the IP
496 * header if it is IPv4.
497 * Must be atomic
498 * @reclaim: free packet until ssn. Returns a list of freed packets.
499 * Must be atomic
500 * @txq_enable: setup a queue. To setup an AC queue, use the
501 * iwl_trans_ac_txq_enable wrapper. fw_alive must have been called before
502 * this one. The op_mode must not configure the HCMD queue. The scheduler
503 * configuration may be %NULL, in which case the hardware will not be
504 * configured. If true is returned, the operation mode needs to increment
505 * the sequence number of the packets routed to this queue because of a
506 * hardware scheduler bug. May sleep.
507 * @txq_disable: de-configure a Tx queue to send AMPDUs
508 * Must be atomic
509 * @txq_set_shared_mode: change Tx queue shared/unshared marking
510 * @wait_tx_queues_empty: wait until tx queues are empty. May sleep.
511 * @wait_txq_empty: wait until specific tx queue is empty. May sleep.
512 * @freeze_txq_timer: prevents the timer of the queue from firing until the
513 * queue is set to awake. Must be atomic.
514 * @block_txq_ptrs: stop updating the write pointers of the Tx queues. Note
515 * that the transport needs to refcount the calls since this function
516 * will be called several times with block = true, and then the queues
517 * need to be unblocked only after the same number of calls with
518 * block = false.
519 * @write8: write a u8 to a register at offset ofs from the BAR
520 * @write32: write a u32 to a register at offset ofs from the BAR
521 * @read32: read a u32 register at offset ofs from the BAR
522 * @read_prph: read a DWORD from a periphery register
523 * @write_prph: write a DWORD to a periphery register
524 * @read_mem: read device's SRAM in DWORD
525 * @write_mem: write device's SRAM in DWORD. If %buf is %NULL, then the memory
526 * will be zeroed.
527 * @read_config32: read a u32 value from the device's config space at
528 * the given offset.
529 * @configure: configure parameters required by the transport layer from
530 * the op_mode. May be called several times before start_fw, can't be
531 * called after that.
532 * @set_pmi: set the power pmi state
533 * @grab_nic_access: wake the NIC to be able to access non-HBUS regs.
534 * Sleeping is not allowed between grab_nic_access and
535 * release_nic_access.
536 * @release_nic_access: let the NIC go to sleep. The "flags" parameter
537 * must be the same one that was sent before to the grab_nic_access.
538 * @set_bits_mask - set SRAM register according to value and mask.
539 * @dump_data: return a vmalloc'ed buffer with debug data, maybe containing last
540 * TX'ed commands and similar. The buffer will be vfree'd by the caller.
541 * Note that the transport must fill in the proper file headers.
542 * @debugfs_cleanup: used in the driver unload flow to make a proper cleanup
543 * of the trans debugfs
544 * @set_pnvm: set the pnvm data in the prph scratch buffer, inside the
545 * context info.
546 * @interrupts: disable/enable interrupts to transport
547 */
548struct iwl_trans_ops {
549
550 int (*start_hw)(struct iwl_trans *iwl_trans);
551 void (*op_mode_leave)(struct iwl_trans *iwl_trans);
552 int (*start_fw)(struct iwl_trans *trans, const struct fw_img *fw,
553 bool run_in_rfkill);
554 void (*fw_alive)(struct iwl_trans *trans, u32 scd_addr);
555 void (*stop_device)(struct iwl_trans *trans);
556
557 int (*d3_suspend)(struct iwl_trans *trans, bool test, bool reset);
558 int (*d3_resume)(struct iwl_trans *trans, enum iwl_d3_status *status,
559 bool test, bool reset);
560
561 int (*send_cmd)(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
562
563 int (*tx)(struct iwl_trans *trans, struct sk_buff *skb,
564 struct iwl_device_tx_cmd *dev_cmd, int queue);
565 void (*reclaim)(struct iwl_trans *trans, int queue, int ssn,
566 struct sk_buff_head *skbs);
567
568 void (*set_q_ptrs)(struct iwl_trans *trans, int queue, int ptr);
569
570 bool (*txq_enable)(struct iwl_trans *trans, int queue, u16 ssn,
571 const struct iwl_trans_txq_scd_cfg *cfg,
572 unsigned int queue_wdg_timeout);
573 void (*txq_disable)(struct iwl_trans *trans, int queue,
574 bool configure_scd);
575 /* 22000 functions */
576 int (*txq_alloc)(struct iwl_trans *trans, u32 flags,
577 u32 sta_mask, u8 tid,
578 int size, unsigned int queue_wdg_timeout);
579 void (*txq_free)(struct iwl_trans *trans, int queue);
580 int (*rxq_dma_data)(struct iwl_trans *trans, int queue,
581 struct iwl_trans_rxq_dma_data *data);
582
583 void (*txq_set_shared_mode)(struct iwl_trans *trans, u32 txq_id,
584 bool shared);
585
586 int (*wait_tx_queues_empty)(struct iwl_trans *trans, u32 txq_bm);
587 int (*wait_txq_empty)(struct iwl_trans *trans, int queue);
588 void (*freeze_txq_timer)(struct iwl_trans *trans, unsigned long txqs,
589 bool freeze);
590 void (*block_txq_ptrs)(struct iwl_trans *trans, bool block);
591
592 void (*write8)(struct iwl_trans *trans, u32 ofs, u8 val);
593 void (*write32)(struct iwl_trans *trans, u32 ofs, u32 val);
594 u32 (*read32)(struct iwl_trans *trans, u32 ofs);
595 u32 (*read_prph)(struct iwl_trans *trans, u32 ofs);
596 void (*write_prph)(struct iwl_trans *trans, u32 ofs, u32 val);
597 int (*read_mem)(struct iwl_trans *trans, u32 addr,
598 void *buf, int dwords);
599 int (*write_mem)(struct iwl_trans *trans, u32 addr,
600 const void *buf, int dwords);
601 int (*read_config32)(struct iwl_trans *trans, u32 ofs, u32 *val);
602 void (*configure)(struct iwl_trans *trans,
603 const struct iwl_trans_config *trans_cfg);
604 void (*set_pmi)(struct iwl_trans *trans, bool state);
605 int (*sw_reset)(struct iwl_trans *trans, bool retake_ownership);
606 bool (*grab_nic_access)(struct iwl_trans *trans);
607 void (*release_nic_access)(struct iwl_trans *trans);
608 void (*set_bits_mask)(struct iwl_trans *trans, u32 reg, u32 mask,
609 u32 value);
610
611 struct iwl_trans_dump_data *(*dump_data)(struct iwl_trans *trans,
612 u32 dump_mask,
613 const struct iwl_dump_sanitize_ops *sanitize_ops,
614 void *sanitize_ctx);
615 void (*debugfs_cleanup)(struct iwl_trans *trans);
616 void (*sync_nmi)(struct iwl_trans *trans);
617 int (*set_pnvm)(struct iwl_trans *trans, const void *data, u32 len);
618 int (*set_reduce_power)(struct iwl_trans *trans,
619 const void *data, u32 len);
620 void (*interrupts)(struct iwl_trans *trans, bool enable);
621 int (*imr_dma_data)(struct iwl_trans *trans,
622 u32 dst_addr, u64 src_addr,
623 u32 byte_cnt);
624
625};
626
627/**
628 * enum iwl_trans_state - state of the transport layer
629 *
630 * @IWL_TRANS_NO_FW: firmware wasn't started yet, or crashed
631 * @IWL_TRANS_FW_STARTED: FW was started, but not alive yet
632 * @IWL_TRANS_FW_ALIVE: FW has sent an alive response
633 */
634enum iwl_trans_state {
635 IWL_TRANS_NO_FW,
636 IWL_TRANS_FW_STARTED,
637 IWL_TRANS_FW_ALIVE,
638};
639
640/**
641 * DOC: Platform power management
642 *
643 * In system-wide power management the entire platform goes into a low
644 * power state (e.g. idle or suspend to RAM) at the same time and the
645 * device is configured as a wakeup source for the entire platform.
646 * This is usually triggered by userspace activity (e.g. the user
647 * presses the suspend button or a power management daemon decides to
648 * put the platform in low power mode). The device's behavior in this
649 * mode is dictated by the wake-on-WLAN configuration.
650 *
651 * The terms used for the device's behavior are as follows:
652 *
653 * - D0: the device is fully powered and the host is awake;
654 * - D3: the device is in low power mode and only reacts to
655 * specific events (e.g. magic-packet received or scan
656 * results found);
657 *
658 * These terms reflect the power modes in the firmware and are not to
659 * be confused with the physical device power state.
660 */
661
662/**
663 * enum iwl_plat_pm_mode - platform power management mode
664 *
665 * This enumeration describes the device's platform power management
666 * behavior when in system-wide suspend (i.e WoWLAN).
667 *
668 * @IWL_PLAT_PM_MODE_DISABLED: power management is disabled for this
669 * device. In system-wide suspend mode, it means that the all
670 * connections will be closed automatically by mac80211 before
671 * the platform is suspended.
672 * @IWL_PLAT_PM_MODE_D3: the device goes into D3 mode (i.e. WoWLAN).
673 */
674enum iwl_plat_pm_mode {
675 IWL_PLAT_PM_MODE_DISABLED,
676 IWL_PLAT_PM_MODE_D3,
677};
678
679/**
680 * enum iwl_ini_cfg_state
681 * @IWL_INI_CFG_STATE_NOT_LOADED: no debug cfg was given
682 * @IWL_INI_CFG_STATE_LOADED: debug cfg was found and loaded
683 * @IWL_INI_CFG_STATE_CORRUPTED: debug cfg was found and some of the TLVs
684 * are corrupted. The rest of the debug TLVs will still be used
685 */
686enum iwl_ini_cfg_state {
687 IWL_INI_CFG_STATE_NOT_LOADED,
688 IWL_INI_CFG_STATE_LOADED,
689 IWL_INI_CFG_STATE_CORRUPTED,
690};
691
692/* Max time to wait for nmi interrupt */
693#define IWL_TRANS_NMI_TIMEOUT (HZ / 4)
694
695/**
696 * struct iwl_dram_data
697 * @physical: page phy pointer
698 * @block: pointer to the allocated block/page
699 * @size: size of the block/page
700 */
701struct iwl_dram_data {
702 dma_addr_t physical;
703 void *block;
704 int size;
705};
706
707/**
708 * struct iwl_fw_mon - fw monitor per allocation id
709 * @num_frags: number of fragments
710 * @frags: an array of DRAM buffer fragments
711 */
712struct iwl_fw_mon {
713 u32 num_frags;
714 struct iwl_dram_data *frags;
715};
716
717/**
718 * struct iwl_self_init_dram - dram data used by self init process
719 * @fw: lmac and umac dram data
720 * @fw_cnt: total number of items in array
721 * @paging: paging dram data
722 * @paging_cnt: total number of items in array
723 */
724struct iwl_self_init_dram {
725 struct iwl_dram_data *fw;
726 int fw_cnt;
727 struct iwl_dram_data *paging;
728 int paging_cnt;
729};
730
731/**
732 * struct iwl_imr_data - imr dram data used during debug process
733 * @imr_enable: imr enable status received from fw
734 * @imr_size: imr dram size received from fw
735 * @sram_addr: sram address from debug tlv
736 * @sram_size: sram size from debug tlv
737 * @imr2sram_remainbyte`: size remained after each dma transfer
738 * @imr_curr_addr: current dst address used during dma transfer
739 * @imr_base_addr: imr address received from fw
740 */
741struct iwl_imr_data {
742 u32 imr_enable;
743 u32 imr_size;
744 u32 sram_addr;
745 u32 sram_size;
746 u32 imr2sram_remainbyte;
747 u64 imr_curr_addr;
748 __le64 imr_base_addr;
749};
750
751/**
752 * struct iwl_trans_debug - transport debug related data
753 *
754 * @n_dest_reg: num of reg_ops in %dbg_dest_tlv
755 * @rec_on: true iff there is a fw debug recording currently active
756 * @dest_tlv: points to the destination TLV for debug
757 * @conf_tlv: array of pointers to configuration TLVs for debug
758 * @trigger_tlv: array of pointers to triggers TLVs for debug
759 * @lmac_error_event_table: addrs of lmacs error tables
760 * @umac_error_event_table: addr of umac error table
761 * @tcm_error_event_table: address(es) of TCM error table(s)
762 * @rcm_error_event_table: address(es) of RCM error table(s)
763 * @error_event_table_tlv_status: bitmap that indicates what error table
764 * pointers was recevied via TLV. uses enum &iwl_error_event_table_status
765 * @internal_ini_cfg: internal debug cfg state. Uses &enum iwl_ini_cfg_state
766 * @external_ini_cfg: external debug cfg state. Uses &enum iwl_ini_cfg_state
767 * @fw_mon_cfg: debug buffer allocation configuration
768 * @fw_mon_ini: DRAM buffer fragments per allocation id
769 * @fw_mon: DRAM buffer for firmware monitor
770 * @hw_error: equals true if hw error interrupt was received from the FW
771 * @ini_dest: debug monitor destination uses &enum iwl_fw_ini_buffer_location
772 * @active_regions: active regions
773 * @debug_info_tlv_list: list of debug info TLVs
774 * @time_point: array of debug time points
775 * @periodic_trig_list: periodic triggers list
776 * @domains_bitmap: bitmap of active domains other than &IWL_FW_INI_DOMAIN_ALWAYS_ON
777 * @ucode_preset: preset based on ucode
778 */
779struct iwl_trans_debug {
780 u8 n_dest_reg;
781 bool rec_on;
782
783 const struct iwl_fw_dbg_dest_tlv_v1 *dest_tlv;
784 const struct iwl_fw_dbg_conf_tlv *conf_tlv[FW_DBG_CONF_MAX];
785 struct iwl_fw_dbg_trigger_tlv * const *trigger_tlv;
786
787 u32 lmac_error_event_table[2];
788 u32 umac_error_event_table;
789 u32 tcm_error_event_table[2];
790 u32 rcm_error_event_table[2];
791 unsigned int error_event_table_tlv_status;
792
793 enum iwl_ini_cfg_state internal_ini_cfg;
794 enum iwl_ini_cfg_state external_ini_cfg;
795
796 struct iwl_fw_ini_allocation_tlv fw_mon_cfg[IWL_FW_INI_ALLOCATION_NUM];
797 struct iwl_fw_mon fw_mon_ini[IWL_FW_INI_ALLOCATION_NUM];
798
799 struct iwl_dram_data fw_mon;
800
801 bool hw_error;
802 enum iwl_fw_ini_buffer_location ini_dest;
803
804 u64 unsupported_region_msk;
805 struct iwl_ucode_tlv *active_regions[IWL_FW_INI_MAX_REGION_ID];
806 struct list_head debug_info_tlv_list;
807 struct iwl_dbg_tlv_time_point_data
808 time_point[IWL_FW_INI_TIME_POINT_NUM];
809 struct list_head periodic_trig_list;
810
811 u32 domains_bitmap;
812 u32 ucode_preset;
813 bool restart_required;
814 u32 last_tp_resetfw;
815 struct iwl_imr_data imr_data;
816};
817
818struct iwl_dma_ptr {
819 dma_addr_t dma;
820 void *addr;
821 size_t size;
822};
823
824struct iwl_cmd_meta {
825 /* only for SYNC commands, iff the reply skb is wanted */
826 struct iwl_host_cmd *source;
827 u32 flags;
828 u32 tbs;
829};
830
831/*
832 * The FH will write back to the first TB only, so we need to copy some data
833 * into the buffer regardless of whether it should be mapped or not.
834 * This indicates how big the first TB must be to include the scratch buffer
835 * and the assigned PN.
836 * Since PN location is 8 bytes at offset 12, it's 20 now.
837 * If we make it bigger then allocations will be bigger and copy slower, so
838 * that's probably not useful.
839 */
840#define IWL_FIRST_TB_SIZE 20
841#define IWL_FIRST_TB_SIZE_ALIGN ALIGN(IWL_FIRST_TB_SIZE, 64)
842
843struct iwl_pcie_txq_entry {
844 void *cmd;
845 struct sk_buff *skb;
846 /* buffer to free after command completes */
847 const void *free_buf;
848 struct iwl_cmd_meta meta;
849};
850
851struct iwl_pcie_first_tb_buf {
852 u8 buf[IWL_FIRST_TB_SIZE_ALIGN];
853};
854
855/**
856 * struct iwl_txq - Tx Queue for DMA
857 * @q: generic Rx/Tx queue descriptor
858 * @tfds: transmit frame descriptors (DMA memory)
859 * @first_tb_bufs: start of command headers, including scratch buffers, for
860 * the writeback -- this is DMA memory and an array holding one buffer
861 * for each command on the queue
862 * @first_tb_dma: DMA address for the first_tb_bufs start
863 * @entries: transmit entries (driver state)
864 * @lock: queue lock
865 * @stuck_timer: timer that fires if queue gets stuck
866 * @trans: pointer back to transport (for timer)
867 * @need_update: indicates need to update read/write index
868 * @ampdu: true if this queue is an ampdu queue for an specific RA/TID
869 * @wd_timeout: queue watchdog timeout (jiffies) - per queue
870 * @frozen: tx stuck queue timer is frozen
871 * @frozen_expiry_remainder: remember how long until the timer fires
872 * @bc_tbl: byte count table of the queue (relevant only for gen2 transport)
873 * @write_ptr: 1-st empty entry (index) host_w
874 * @read_ptr: last used entry (index) host_r
875 * @dma_addr: physical addr for BD's
876 * @n_window: safe queue window
877 * @id: queue id
878 * @low_mark: low watermark, resume queue if free space more than this
879 * @high_mark: high watermark, stop queue if free space less than this
880 *
881 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
882 * descriptors) and required locking structures.
883 *
884 * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware
885 * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless
886 * there might be HW changes in the future). For the normal TX
887 * queues, n_window, which is the size of the software queue data
888 * is also 256; however, for the command queue, n_window is only
889 * 32 since we don't need so many commands pending. Since the HW
890 * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256.
891 * This means that we end up with the following:
892 * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 |
893 * SW entries: | 0 | ... | 31 |
894 * where N is a number between 0 and 7. This means that the SW
895 * data is a window overlayed over the HW queue.
896 */
897struct iwl_txq {
898 void *tfds;
899 struct iwl_pcie_first_tb_buf *first_tb_bufs;
900 dma_addr_t first_tb_dma;
901 struct iwl_pcie_txq_entry *entries;
902 /* lock for syncing changes on the queue */
903 spinlock_t lock;
904 unsigned long frozen_expiry_remainder;
905 struct timer_list stuck_timer;
906 struct iwl_trans *trans;
907 bool need_update;
908 bool frozen;
909 bool ampdu;
910 int block;
911 unsigned long wd_timeout;
912 struct sk_buff_head overflow_q;
913 struct iwl_dma_ptr bc_tbl;
914
915 int write_ptr;
916 int read_ptr;
917 dma_addr_t dma_addr;
918 int n_window;
919 u32 id;
920 int low_mark;
921 int high_mark;
922
923 bool overflow_tx;
924};
925
926/**
927 * struct iwl_trans_txqs - transport tx queues data
928 *
929 * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes)
930 * @page_offs: offset from skb->cb to mac header page pointer
931 * @dev_cmd_offs: offset from skb->cb to iwl_device_tx_cmd pointer
932 * @queue_used - bit mask of used queues
933 * @queue_stopped - bit mask of stopped queues
934 * @scd_bc_tbls: gen1 pointer to the byte count table of the scheduler
935 * @queue_alloc_cmd_ver: queue allocation command version
936 */
937struct iwl_trans_txqs {
938 unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)];
939 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)];
940 struct iwl_txq *txq[IWL_MAX_TVQM_QUEUES];
941 struct dma_pool *bc_pool;
942 size_t bc_tbl_size;
943 bool bc_table_dword;
944 u8 page_offs;
945 u8 dev_cmd_offs;
946 struct iwl_tso_hdr_page __percpu *tso_hdr_page;
947
948 struct {
949 u8 fifo;
950 u8 q_id;
951 unsigned int wdg_timeout;
952 } cmd;
953
954 struct {
955 u8 max_tbs;
956 u16 size;
957 u8 addr_size;
958 } tfd;
959
960 struct iwl_dma_ptr scd_bc_tbls;
961
962 u8 queue_alloc_cmd_ver;
963};
964
965/**
966 * struct iwl_trans - transport common data
967 *
968 * @csme_own - true if we couldn't get ownership on the device
969 * @ops - pointer to iwl_trans_ops
970 * @op_mode - pointer to the op_mode
971 * @trans_cfg: the trans-specific configuration part
972 * @cfg - pointer to the configuration
973 * @drv - pointer to iwl_drv
974 * @status: a bit-mask of transport status flags
975 * @dev - pointer to struct device * that represents the device
976 * @max_skb_frags: maximum number of fragments an SKB can have when transmitted.
977 * 0 indicates that frag SKBs (NETIF_F_SG) aren't supported.
978 * @hw_rf_id a u32 with the device RF ID
979 * @hw_crf_id a u32 with the device CRF ID
980 * @hw_cdb_id a u32 with the device CDB ID
981 * @hw_id: a u32 with the ID of the device / sub-device.
982 * Set during transport allocation.
983 * @hw_id_str: a string with info about HW ID. Set during transport allocation.
984 * @hw_rev_step: The mac step of the HW
985 * @pm_support: set to true in start_hw if link pm is supported
986 * @ltr_enabled: set to true if the LTR is enabled
987 * @wide_cmd_header: true when ucode supports wide command header format
988 * @wait_command_queue: wait queue for sync commands
989 * @num_rx_queues: number of RX queues allocated by the transport;
990 * the transport must set this before calling iwl_drv_start()
991 * @iml_len: the length of the image loader
992 * @iml: a pointer to the image loader itself
993 * @dev_cmd_pool: pool for Tx cmd allocation - for internal use only.
994 * The user should use iwl_trans_{alloc,free}_tx_cmd.
995 * @rx_mpdu_cmd: MPDU RX command ID, must be assigned by opmode before
996 * starting the firmware, used for tracing
997 * @rx_mpdu_cmd_hdr_size: used for tracing, amount of data before the
998 * start of the 802.11 header in the @rx_mpdu_cmd
999 * @dflt_pwr_limit: default power limit fetched from the platform (ACPI)
1000 * @system_pm_mode: the system-wide power management mode in use.
1001 * This mode is set dynamically, depending on the WoWLAN values
1002 * configured from the userspace at runtime.
1003 * @iwl_trans_txqs: transport tx queues data.
1004 */
1005struct iwl_trans {
1006 bool csme_own;
1007 const struct iwl_trans_ops *ops;
1008 struct iwl_op_mode *op_mode;
1009 const struct iwl_cfg_trans_params *trans_cfg;
1010 const struct iwl_cfg *cfg;
1011 struct iwl_drv *drv;
1012 enum iwl_trans_state state;
1013 unsigned long status;
1014
1015 struct device *dev;
1016 u32 max_skb_frags;
1017 u32 hw_rev;
1018 u32 hw_rev_step;
1019 u32 hw_rf_id;
1020 u32 hw_crf_id;
1021 u32 hw_cdb_id;
1022 u32 hw_id;
1023 char hw_id_str[52];
1024 u32 sku_id[3];
1025
1026 u8 rx_mpdu_cmd, rx_mpdu_cmd_hdr_size;
1027
1028 bool pm_support;
1029 bool ltr_enabled;
1030 u8 pnvm_loaded:1;
1031 u8 reduce_power_loaded:1;
1032
1033 const struct iwl_hcmd_arr *command_groups;
1034 int command_groups_size;
1035 bool wide_cmd_header;
1036
1037 wait_queue_head_t wait_command_queue;
1038 u8 num_rx_queues;
1039
1040 size_t iml_len;
1041 u8 *iml;
1042
1043 /* The following fields are internal only */
1044 struct kmem_cache *dev_cmd_pool;
1045 char dev_cmd_pool_name[50];
1046
1047 struct dentry *dbgfs_dir;
1048
1049#ifdef CONFIG_LOCKDEP
1050 struct lockdep_map sync_cmd_lockdep_map;
1051#endif
1052
1053 struct iwl_trans_debug dbg;
1054 struct iwl_self_init_dram init_dram;
1055
1056 enum iwl_plat_pm_mode system_pm_mode;
1057
1058 const char *name;
1059 struct iwl_trans_txqs txqs;
1060
1061 /* pointer to trans specific struct */
1062 /*Ensure that this pointer will always be aligned to sizeof pointer */
1063 char trans_specific[] __aligned(sizeof(void *));
1064};
1065
1066const char *iwl_get_cmd_string(struct iwl_trans *trans, u32 id);
1067int iwl_cmd_groups_verify_sorted(const struct iwl_trans_config *trans);
1068
1069static inline void iwl_trans_configure(struct iwl_trans *trans,
1070 const struct iwl_trans_config *trans_cfg)
1071{
1072 trans->op_mode = trans_cfg->op_mode;
1073
1074 trans->ops->configure(trans, trans_cfg);
1075 WARN_ON(iwl_cmd_groups_verify_sorted(trans_cfg));
1076}
1077
1078static inline int iwl_trans_start_hw(struct iwl_trans *trans)
1079{
1080 might_sleep();
1081
1082 return trans->ops->start_hw(trans);
1083}
1084
1085static inline void iwl_trans_op_mode_leave(struct iwl_trans *trans)
1086{
1087 might_sleep();
1088
1089 if (trans->ops->op_mode_leave)
1090 trans->ops->op_mode_leave(trans);
1091
1092 trans->op_mode = NULL;
1093
1094 trans->state = IWL_TRANS_NO_FW;
1095}
1096
1097static inline void iwl_trans_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1098{
1099 might_sleep();
1100
1101 trans->state = IWL_TRANS_FW_ALIVE;
1102
1103 trans->ops->fw_alive(trans, scd_addr);
1104}
1105
1106static inline int iwl_trans_start_fw(struct iwl_trans *trans,
1107 const struct fw_img *fw,
1108 bool run_in_rfkill)
1109{
1110 int ret;
1111
1112 might_sleep();
1113
1114 WARN_ON_ONCE(!trans->rx_mpdu_cmd);
1115
1116 clear_bit(STATUS_FW_ERROR, &trans->status);
1117 ret = trans->ops->start_fw(trans, fw, run_in_rfkill);
1118 if (ret == 0)
1119 trans->state = IWL_TRANS_FW_STARTED;
1120
1121 return ret;
1122}
1123
1124static inline void iwl_trans_stop_device(struct iwl_trans *trans)
1125{
1126 might_sleep();
1127
1128 trans->ops->stop_device(trans);
1129
1130 trans->state = IWL_TRANS_NO_FW;
1131}
1132
1133static inline int iwl_trans_d3_suspend(struct iwl_trans *trans, bool test,
1134 bool reset)
1135{
1136 might_sleep();
1137 if (!trans->ops->d3_suspend)
1138 return 0;
1139
1140 return trans->ops->d3_suspend(trans, test, reset);
1141}
1142
1143static inline int iwl_trans_d3_resume(struct iwl_trans *trans,
1144 enum iwl_d3_status *status,
1145 bool test, bool reset)
1146{
1147 might_sleep();
1148 if (!trans->ops->d3_resume)
1149 return 0;
1150
1151 return trans->ops->d3_resume(trans, status, test, reset);
1152}
1153
1154static inline struct iwl_trans_dump_data *
1155iwl_trans_dump_data(struct iwl_trans *trans, u32 dump_mask,
1156 const struct iwl_dump_sanitize_ops *sanitize_ops,
1157 void *sanitize_ctx)
1158{
1159 if (!trans->ops->dump_data)
1160 return NULL;
1161 return trans->ops->dump_data(trans, dump_mask,
1162 sanitize_ops, sanitize_ctx);
1163}
1164
1165static inline struct iwl_device_tx_cmd *
1166iwl_trans_alloc_tx_cmd(struct iwl_trans *trans)
1167{
1168 return kmem_cache_zalloc(trans->dev_cmd_pool, GFP_ATOMIC);
1169}
1170
1171int iwl_trans_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
1172
1173static inline void iwl_trans_free_tx_cmd(struct iwl_trans *trans,
1174 struct iwl_device_tx_cmd *dev_cmd)
1175{
1176 kmem_cache_free(trans->dev_cmd_pool, dev_cmd);
1177}
1178
1179static inline int iwl_trans_tx(struct iwl_trans *trans, struct sk_buff *skb,
1180 struct iwl_device_tx_cmd *dev_cmd, int queue)
1181{
1182 if (unlikely(test_bit(STATUS_FW_ERROR, &trans->status)))
1183 return -EIO;
1184
1185 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1186 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1187 return -EIO;
1188 }
1189
1190 return trans->ops->tx(trans, skb, dev_cmd, queue);
1191}
1192
1193static inline void iwl_trans_reclaim(struct iwl_trans *trans, int queue,
1194 int ssn, struct sk_buff_head *skbs)
1195{
1196 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1197 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1198 return;
1199 }
1200
1201 trans->ops->reclaim(trans, queue, ssn, skbs);
1202}
1203
1204static inline void iwl_trans_set_q_ptrs(struct iwl_trans *trans, int queue,
1205 int ptr)
1206{
1207 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1208 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1209 return;
1210 }
1211
1212 trans->ops->set_q_ptrs(trans, queue, ptr);
1213}
1214
1215static inline void iwl_trans_txq_disable(struct iwl_trans *trans, int queue,
1216 bool configure_scd)
1217{
1218 trans->ops->txq_disable(trans, queue, configure_scd);
1219}
1220
1221static inline bool
1222iwl_trans_txq_enable_cfg(struct iwl_trans *trans, int queue, u16 ssn,
1223 const struct iwl_trans_txq_scd_cfg *cfg,
1224 unsigned int queue_wdg_timeout)
1225{
1226 might_sleep();
1227
1228 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1229 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1230 return false;
1231 }
1232
1233 return trans->ops->txq_enable(trans, queue, ssn,
1234 cfg, queue_wdg_timeout);
1235}
1236
1237static inline int
1238iwl_trans_get_rxq_dma_data(struct iwl_trans *trans, int queue,
1239 struct iwl_trans_rxq_dma_data *data)
1240{
1241 if (WARN_ON_ONCE(!trans->ops->rxq_dma_data))
1242 return -ENOTSUPP;
1243
1244 return trans->ops->rxq_dma_data(trans, queue, data);
1245}
1246
1247static inline void
1248iwl_trans_txq_free(struct iwl_trans *trans, int queue)
1249{
1250 if (WARN_ON_ONCE(!trans->ops->txq_free))
1251 return;
1252
1253 trans->ops->txq_free(trans, queue);
1254}
1255
1256static inline int
1257iwl_trans_txq_alloc(struct iwl_trans *trans,
1258 u32 flags, u32 sta_mask, u8 tid,
1259 int size, unsigned int wdg_timeout)
1260{
1261 might_sleep();
1262
1263 if (WARN_ON_ONCE(!trans->ops->txq_alloc))
1264 return -ENOTSUPP;
1265
1266 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1267 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1268 return -EIO;
1269 }
1270
1271 return trans->ops->txq_alloc(trans, flags, sta_mask, tid,
1272 size, wdg_timeout);
1273}
1274
1275static inline void iwl_trans_txq_set_shared_mode(struct iwl_trans *trans,
1276 int queue, bool shared_mode)
1277{
1278 if (trans->ops->txq_set_shared_mode)
1279 trans->ops->txq_set_shared_mode(trans, queue, shared_mode);
1280}
1281
1282static inline void iwl_trans_txq_enable(struct iwl_trans *trans, int queue,
1283 int fifo, int sta_id, int tid,
1284 int frame_limit, u16 ssn,
1285 unsigned int queue_wdg_timeout)
1286{
1287 struct iwl_trans_txq_scd_cfg cfg = {
1288 .fifo = fifo,
1289 .sta_id = sta_id,
1290 .tid = tid,
1291 .frame_limit = frame_limit,
1292 .aggregate = sta_id >= 0,
1293 };
1294
1295 iwl_trans_txq_enable_cfg(trans, queue, ssn, &cfg, queue_wdg_timeout);
1296}
1297
1298static inline
1299void iwl_trans_ac_txq_enable(struct iwl_trans *trans, int queue, int fifo,
1300 unsigned int queue_wdg_timeout)
1301{
1302 struct iwl_trans_txq_scd_cfg cfg = {
1303 .fifo = fifo,
1304 .sta_id = -1,
1305 .tid = IWL_MAX_TID_COUNT,
1306 .frame_limit = IWL_FRAME_LIMIT,
1307 .aggregate = false,
1308 };
1309
1310 iwl_trans_txq_enable_cfg(trans, queue, 0, &cfg, queue_wdg_timeout);
1311}
1312
1313static inline void iwl_trans_freeze_txq_timer(struct iwl_trans *trans,
1314 unsigned long txqs,
1315 bool freeze)
1316{
1317 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1318 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1319 return;
1320 }
1321
1322 if (trans->ops->freeze_txq_timer)
1323 trans->ops->freeze_txq_timer(trans, txqs, freeze);
1324}
1325
1326static inline void iwl_trans_block_txq_ptrs(struct iwl_trans *trans,
1327 bool block)
1328{
1329 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1330 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1331 return;
1332 }
1333
1334 if (trans->ops->block_txq_ptrs)
1335 trans->ops->block_txq_ptrs(trans, block);
1336}
1337
1338static inline int iwl_trans_wait_tx_queues_empty(struct iwl_trans *trans,
1339 u32 txqs)
1340{
1341 if (WARN_ON_ONCE(!trans->ops->wait_tx_queues_empty))
1342 return -ENOTSUPP;
1343
1344 /* No need to wait if the firmware is not alive */
1345 if (trans->state != IWL_TRANS_FW_ALIVE) {
1346 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1347 return -EIO;
1348 }
1349
1350 return trans->ops->wait_tx_queues_empty(trans, txqs);
1351}
1352
1353static inline int iwl_trans_wait_txq_empty(struct iwl_trans *trans, int queue)
1354{
1355 if (WARN_ON_ONCE(!trans->ops->wait_txq_empty))
1356 return -ENOTSUPP;
1357
1358 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1359 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1360 return -EIO;
1361 }
1362
1363 return trans->ops->wait_txq_empty(trans, queue);
1364}
1365
1366static inline void iwl_trans_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1367{
1368 trans->ops->write8(trans, ofs, val);
1369}
1370
1371static inline void iwl_trans_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1372{
1373 trans->ops->write32(trans, ofs, val);
1374}
1375
1376static inline u32 iwl_trans_read32(struct iwl_trans *trans, u32 ofs)
1377{
1378 return trans->ops->read32(trans, ofs);
1379}
1380
1381static inline u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs)
1382{
1383 return trans->ops->read_prph(trans, ofs);
1384}
1385
1386static inline void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs,
1387 u32 val)
1388{
1389 return trans->ops->write_prph(trans, ofs, val);
1390}
1391
1392static inline int iwl_trans_read_mem(struct iwl_trans *trans, u32 addr,
1393 void *buf, int dwords)
1394{
1395 return trans->ops->read_mem(trans, addr, buf, dwords);
1396}
1397
1398#define iwl_trans_read_mem_bytes(trans, addr, buf, bufsize) \
1399 do { \
1400 if (__builtin_constant_p(bufsize)) \
1401 BUILD_BUG_ON((bufsize) % sizeof(u32)); \
1402 iwl_trans_read_mem(trans, addr, buf, (bufsize) / sizeof(u32));\
1403 } while (0)
1404
1405static inline int iwl_trans_write_imr_mem(struct iwl_trans *trans,
1406 u32 dst_addr, u64 src_addr,
1407 u32 byte_cnt)
1408{
1409 if (trans->ops->imr_dma_data)
1410 return trans->ops->imr_dma_data(trans, dst_addr, src_addr, byte_cnt);
1411 return 0;
1412}
1413
1414static inline u32 iwl_trans_read_mem32(struct iwl_trans *trans, u32 addr)
1415{
1416 u32 value;
1417
1418 if (WARN_ON(iwl_trans_read_mem(trans, addr, &value, 1)))
1419 return 0xa5a5a5a5;
1420
1421 return value;
1422}
1423
1424static inline int iwl_trans_write_mem(struct iwl_trans *trans, u32 addr,
1425 const void *buf, int dwords)
1426{
1427 return trans->ops->write_mem(trans, addr, buf, dwords);
1428}
1429
1430static inline u32 iwl_trans_write_mem32(struct iwl_trans *trans, u32 addr,
1431 u32 val)
1432{
1433 return iwl_trans_write_mem(trans, addr, &val, 1);
1434}
1435
1436static inline void iwl_trans_set_pmi(struct iwl_trans *trans, bool state)
1437{
1438 if (trans->ops->set_pmi)
1439 trans->ops->set_pmi(trans, state);
1440}
1441
1442static inline int iwl_trans_sw_reset(struct iwl_trans *trans,
1443 bool retake_ownership)
1444{
1445 if (trans->ops->sw_reset)
1446 return trans->ops->sw_reset(trans, retake_ownership);
1447 return 0;
1448}
1449
1450static inline void
1451iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg, u32 mask, u32 value)
1452{
1453 trans->ops->set_bits_mask(trans, reg, mask, value);
1454}
1455
1456#define iwl_trans_grab_nic_access(trans) \
1457 __cond_lock(nic_access, \
1458 likely((trans)->ops->grab_nic_access(trans)))
1459
1460static inline void __releases(nic_access)
1461iwl_trans_release_nic_access(struct iwl_trans *trans)
1462{
1463 trans->ops->release_nic_access(trans);
1464 __release(nic_access);
1465}
1466
1467static inline void iwl_trans_fw_error(struct iwl_trans *trans, bool sync)
1468{
1469 if (WARN_ON_ONCE(!trans->op_mode))
1470 return;
1471
1472 /* prevent double restarts due to the same erroneous FW */
1473 if (!test_and_set_bit(STATUS_FW_ERROR, &trans->status)) {
1474 iwl_op_mode_nic_error(trans->op_mode, sync);
1475 trans->state = IWL_TRANS_NO_FW;
1476 }
1477}
1478
1479static inline bool iwl_trans_fw_running(struct iwl_trans *trans)
1480{
1481 return trans->state == IWL_TRANS_FW_ALIVE;
1482}
1483
1484static inline void iwl_trans_sync_nmi(struct iwl_trans *trans)
1485{
1486 if (trans->ops->sync_nmi)
1487 trans->ops->sync_nmi(trans);
1488}
1489
1490void iwl_trans_sync_nmi_with_addr(struct iwl_trans *trans, u32 inta_addr,
1491 u32 sw_err_bit);
1492
1493static inline int iwl_trans_set_pnvm(struct iwl_trans *trans,
1494 const void *data, u32 len)
1495{
1496 if (trans->ops->set_pnvm) {
1497 int ret = trans->ops->set_pnvm(trans, data, len);
1498
1499 if (ret)
1500 return ret;
1501 }
1502
1503 trans->pnvm_loaded = true;
1504
1505 return 0;
1506}
1507
1508static inline int iwl_trans_set_reduce_power(struct iwl_trans *trans,
1509 const void *data, u32 len)
1510{
1511 if (trans->ops->set_reduce_power) {
1512 int ret = trans->ops->set_reduce_power(trans, data, len);
1513
1514 if (ret)
1515 return ret;
1516 }
1517
1518 trans->reduce_power_loaded = true;
1519 return 0;
1520}
1521
1522static inline bool iwl_trans_dbg_ini_valid(struct iwl_trans *trans)
1523{
1524 return trans->dbg.internal_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED ||
1525 trans->dbg.external_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED;
1526}
1527
1528static inline void iwl_trans_interrupts(struct iwl_trans *trans, bool enable)
1529{
1530 if (trans->ops->interrupts)
1531 trans->ops->interrupts(trans, enable);
1532}
1533
1534/*****************************************************
1535 * transport helper functions
1536 *****************************************************/
1537struct iwl_trans *iwl_trans_alloc(unsigned int priv_size,
1538 struct device *dev,
1539 const struct iwl_trans_ops *ops,
1540 const struct iwl_cfg_trans_params *cfg_trans);
1541int iwl_trans_init(struct iwl_trans *trans);
1542void iwl_trans_free(struct iwl_trans *trans);
1543
1544/*****************************************************
1545* driver (transport) register/unregister functions
1546******************************************************/
1547int __must_check iwl_pci_register_driver(void);
1548void iwl_pci_unregister_driver(void);
1549void iwl_trans_pcie_remove(struct iwl_trans *trans, bool rescan);
1550
1551#endif /* __iwl_trans_h__ */
1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/*
3 * Copyright (C) 2005-2014, 2018-2023 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
6 */
7#ifndef __iwl_trans_h__
8#define __iwl_trans_h__
9
10#include <linux/ieee80211.h>
11#include <linux/mm.h> /* for page_address */
12#include <linux/lockdep.h>
13#include <linux/kernel.h>
14
15#include "iwl-debug.h"
16#include "iwl-config.h"
17#include "fw/img.h"
18#include "iwl-op-mode.h"
19#include <linux/firmware.h>
20#include "fw/api/cmdhdr.h"
21#include "fw/api/txq.h"
22#include "fw/api/dbg-tlv.h"
23#include "iwl-dbg-tlv.h"
24
25/**
26 * DOC: Transport layer - what is it ?
27 *
28 * The transport layer is the layer that deals with the HW directly. It provides
29 * the PCIe access to the underlying hardwarwe. The transport layer doesn't
30 * provide any policy, algorithm or anything of this kind, but only mechanisms
31 * to make the HW do something. It is not completely stateless but close to it.
32 */
33
34/**
35 * DOC: Life cycle of the transport layer
36 *
37 * The transport layer has a very precise life cycle.
38 *
39 * 1) A helper function is called during the module initialization and
40 * registers the bus driver's ops with the transport's alloc function.
41 * 2) Bus's probe calls to the transport layer's allocation functions.
42 * Of course this function is bus specific.
43 * 3) This allocation functions will spawn the upper layer which will
44 * register mac80211.
45 *
46 * 4) At some point (i.e. mac80211's start call), the op_mode will call
47 * the following sequence:
48 * start_hw
49 * start_fw
50 *
51 * 5) Then when finished (or reset):
52 * stop_device
53 *
54 * 6) Eventually, the free function will be called.
55 */
56
57/* default preset 0 (start from bit 16)*/
58#define IWL_FW_DBG_DOMAIN_POS 16
59#define IWL_FW_DBG_DOMAIN BIT(IWL_FW_DBG_DOMAIN_POS)
60
61#define IWL_TRANS_FW_DBG_DOMAIN(trans) IWL_FW_INI_DOMAIN_ALWAYS_ON
62
63#define FH_RSCSR_FRAME_SIZE_MSK 0x00003FFF /* bits 0-13 */
64#define FH_RSCSR_FRAME_INVALID 0x55550000
65#define FH_RSCSR_FRAME_ALIGN 0x40
66#define FH_RSCSR_RPA_EN BIT(25)
67#define FH_RSCSR_RADA_EN BIT(26)
68#define FH_RSCSR_RXQ_POS 16
69#define FH_RSCSR_RXQ_MASK 0x3F0000
70
71struct iwl_rx_packet {
72 /*
73 * The first 4 bytes of the RX frame header contain both the RX frame
74 * size and some flags.
75 * Bit fields:
76 * 31: flag flush RB request
77 * 30: flag ignore TC (terminal counter) request
78 * 29: flag fast IRQ request
79 * 28-27: Reserved
80 * 26: RADA enabled
81 * 25: Offload enabled
82 * 24: RPF enabled
83 * 23: RSS enabled
84 * 22: Checksum enabled
85 * 21-16: RX queue
86 * 15-14: Reserved
87 * 13-00: RX frame size
88 */
89 __le32 len_n_flags;
90 struct iwl_cmd_header hdr;
91 u8 data[];
92} __packed;
93
94static inline u32 iwl_rx_packet_len(const struct iwl_rx_packet *pkt)
95{
96 return le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
97}
98
99static inline u32 iwl_rx_packet_payload_len(const struct iwl_rx_packet *pkt)
100{
101 return iwl_rx_packet_len(pkt) - sizeof(pkt->hdr);
102}
103
104/**
105 * enum CMD_MODE - how to send the host commands ?
106 *
107 * @CMD_ASYNC: Return right away and don't wait for the response
108 * @CMD_WANT_SKB: Not valid with CMD_ASYNC. The caller needs the buffer of
109 * the response. The caller needs to call iwl_free_resp when done.
110 * @CMD_SEND_IN_RFKILL: Send the command even if the NIC is in RF-kill.
111 * @CMD_BLOCK_TXQS: Block TXQs while the comment is executing.
112 * @CMD_SEND_IN_D3: Allow the command to be sent in D3 mode, relevant to
113 * SUSPEND and RESUME commands. We are in D3 mode when we set
114 * trans->system_pm_mode to IWL_PLAT_PM_MODE_D3.
115 */
116enum CMD_MODE {
117 CMD_ASYNC = BIT(0),
118 CMD_WANT_SKB = BIT(1),
119 CMD_SEND_IN_RFKILL = BIT(2),
120 CMD_BLOCK_TXQS = BIT(3),
121 CMD_SEND_IN_D3 = BIT(4),
122};
123#define CMD_MODE_BITS 5
124
125#define DEF_CMD_PAYLOAD_SIZE 320
126
127/**
128 * struct iwl_device_cmd
129 *
130 * For allocation of the command and tx queues, this establishes the overall
131 * size of the largest command we send to uCode, except for commands that
132 * aren't fully copied and use other TFD space.
133 *
134 * @hdr: command header
135 * @payload: payload for the command
136 * @hdr_wide: wide command header
137 * @payload_wide: payload for the wide command
138 */
139struct iwl_device_cmd {
140 union {
141 struct {
142 struct iwl_cmd_header hdr; /* uCode API */
143 u8 payload[DEF_CMD_PAYLOAD_SIZE];
144 };
145 struct {
146 struct iwl_cmd_header_wide hdr_wide;
147 u8 payload_wide[DEF_CMD_PAYLOAD_SIZE -
148 sizeof(struct iwl_cmd_header_wide) +
149 sizeof(struct iwl_cmd_header)];
150 };
151 };
152} __packed;
153
154/**
155 * struct iwl_device_tx_cmd - buffer for TX command
156 * @hdr: the header
157 * @payload: the payload placeholder
158 *
159 * The actual structure is sized dynamically according to need.
160 */
161struct iwl_device_tx_cmd {
162 struct iwl_cmd_header hdr;
163 u8 payload[];
164} __packed;
165
166#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd))
167
168/*
169 * number of transfer buffers (fragments) per transmit frame descriptor;
170 * this is just the driver's idea, the hardware supports 20
171 */
172#define IWL_MAX_CMD_TBS_PER_TFD 2
173
174/**
175 * enum iwl_hcmd_dataflag - flag for each one of the chunks of the command
176 *
177 * @IWL_HCMD_DFL_NOCOPY: By default, the command is copied to the host command's
178 * ring. The transport layer doesn't map the command's buffer to DMA, but
179 * rather copies it to a previously allocated DMA buffer. This flag tells
180 * the transport layer not to copy the command, but to map the existing
181 * buffer (that is passed in) instead. This saves the memcpy and allows
182 * commands that are bigger than the fixed buffer to be submitted.
183 * Note that a TFD entry after a NOCOPY one cannot be a normal copied one.
184 * @IWL_HCMD_DFL_DUP: Only valid without NOCOPY, duplicate the memory for this
185 * chunk internally and free it again after the command completes. This
186 * can (currently) be used only once per command.
187 * Note that a TFD entry after a DUP one cannot be a normal copied one.
188 */
189enum iwl_hcmd_dataflag {
190 IWL_HCMD_DFL_NOCOPY = BIT(0),
191 IWL_HCMD_DFL_DUP = BIT(1),
192};
193
194enum iwl_error_event_table_status {
195 IWL_ERROR_EVENT_TABLE_LMAC1 = BIT(0),
196 IWL_ERROR_EVENT_TABLE_LMAC2 = BIT(1),
197 IWL_ERROR_EVENT_TABLE_UMAC = BIT(2),
198 IWL_ERROR_EVENT_TABLE_TCM1 = BIT(3),
199 IWL_ERROR_EVENT_TABLE_TCM2 = BIT(4),
200 IWL_ERROR_EVENT_TABLE_RCM1 = BIT(5),
201 IWL_ERROR_EVENT_TABLE_RCM2 = BIT(6),
202};
203
204/**
205 * struct iwl_host_cmd - Host command to the uCode
206 *
207 * @data: array of chunks that composes the data of the host command
208 * @resp_pkt: response packet, if %CMD_WANT_SKB was set
209 * @_rx_page_order: (internally used to free response packet)
210 * @_rx_page_addr: (internally used to free response packet)
211 * @flags: can be CMD_*
212 * @len: array of the lengths of the chunks in data
213 * @dataflags: IWL_HCMD_DFL_*
214 * @id: command id of the host command, for wide commands encoding the
215 * version and group as well
216 */
217struct iwl_host_cmd {
218 const void *data[IWL_MAX_CMD_TBS_PER_TFD];
219 struct iwl_rx_packet *resp_pkt;
220 unsigned long _rx_page_addr;
221 u32 _rx_page_order;
222
223 u32 flags;
224 u32 id;
225 u16 len[IWL_MAX_CMD_TBS_PER_TFD];
226 u8 dataflags[IWL_MAX_CMD_TBS_PER_TFD];
227};
228
229static inline void iwl_free_resp(struct iwl_host_cmd *cmd)
230{
231 free_pages(cmd->_rx_page_addr, cmd->_rx_page_order);
232}
233
234struct iwl_rx_cmd_buffer {
235 struct page *_page;
236 int _offset;
237 bool _page_stolen;
238 u32 _rx_page_order;
239 unsigned int truesize;
240};
241
242static inline void *rxb_addr(struct iwl_rx_cmd_buffer *r)
243{
244 return (void *)((unsigned long)page_address(r->_page) + r->_offset);
245}
246
247static inline int rxb_offset(struct iwl_rx_cmd_buffer *r)
248{
249 return r->_offset;
250}
251
252static inline struct page *rxb_steal_page(struct iwl_rx_cmd_buffer *r)
253{
254 r->_page_stolen = true;
255 get_page(r->_page);
256 return r->_page;
257}
258
259static inline void iwl_free_rxb(struct iwl_rx_cmd_buffer *r)
260{
261 __free_pages(r->_page, r->_rx_page_order);
262}
263
264#define MAX_NO_RECLAIM_CMDS 6
265
266#define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
267
268/*
269 * Maximum number of HW queues the transport layer
270 * currently supports
271 */
272#define IWL_MAX_HW_QUEUES 32
273#define IWL_MAX_TVQM_QUEUES 512
274
275#define IWL_MAX_TID_COUNT 8
276#define IWL_MGMT_TID 15
277#define IWL_FRAME_LIMIT 64
278#define IWL_MAX_RX_HW_QUEUES 16
279#define IWL_9000_MAX_RX_HW_QUEUES 1
280
281/**
282 * enum iwl_d3_status - WoWLAN image/device status
283 * @IWL_D3_STATUS_ALIVE: firmware is still running after resume
284 * @IWL_D3_STATUS_RESET: device was reset while suspended
285 */
286enum iwl_d3_status {
287 IWL_D3_STATUS_ALIVE,
288 IWL_D3_STATUS_RESET,
289};
290
291/**
292 * enum iwl_trans_status: transport status flags
293 * @STATUS_SYNC_HCMD_ACTIVE: a SYNC command is being processed
294 * @STATUS_DEVICE_ENABLED: APM is enabled
295 * @STATUS_TPOWER_PMI: the device might be asleep (need to wake it up)
296 * @STATUS_INT_ENABLED: interrupts are enabled
297 * @STATUS_RFKILL_HW: the actual HW state of the RF-kill switch
298 * @STATUS_RFKILL_OPMODE: RF-kill state reported to opmode
299 * @STATUS_FW_ERROR: the fw is in error state
300 * @STATUS_TRANS_DEAD: trans is dead - avoid any read/write operation
301 * @STATUS_SUPPRESS_CMD_ERROR_ONCE: suppress "FW error in SYNC CMD" once,
302 * e.g. for testing
303 */
304enum iwl_trans_status {
305 STATUS_SYNC_HCMD_ACTIVE,
306 STATUS_DEVICE_ENABLED,
307 STATUS_TPOWER_PMI,
308 STATUS_INT_ENABLED,
309 STATUS_RFKILL_HW,
310 STATUS_RFKILL_OPMODE,
311 STATUS_FW_ERROR,
312 STATUS_TRANS_DEAD,
313 STATUS_SUPPRESS_CMD_ERROR_ONCE,
314};
315
316static inline int
317iwl_trans_get_rb_size_order(enum iwl_amsdu_size rb_size)
318{
319 switch (rb_size) {
320 case IWL_AMSDU_2K:
321 return get_order(2 * 1024);
322 case IWL_AMSDU_4K:
323 return get_order(4 * 1024);
324 case IWL_AMSDU_8K:
325 return get_order(8 * 1024);
326 case IWL_AMSDU_12K:
327 return get_order(16 * 1024);
328 default:
329 WARN_ON(1);
330 return -1;
331 }
332}
333
334static inline int
335iwl_trans_get_rb_size(enum iwl_amsdu_size rb_size)
336{
337 switch (rb_size) {
338 case IWL_AMSDU_2K:
339 return 2 * 1024;
340 case IWL_AMSDU_4K:
341 return 4 * 1024;
342 case IWL_AMSDU_8K:
343 return 8 * 1024;
344 case IWL_AMSDU_12K:
345 return 16 * 1024;
346 default:
347 WARN_ON(1);
348 return 0;
349 }
350}
351
352struct iwl_hcmd_names {
353 u8 cmd_id;
354 const char *const cmd_name;
355};
356
357#define HCMD_NAME(x) \
358 { .cmd_id = x, .cmd_name = #x }
359
360struct iwl_hcmd_arr {
361 const struct iwl_hcmd_names *arr;
362 int size;
363};
364
365#define HCMD_ARR(x) \
366 { .arr = x, .size = ARRAY_SIZE(x) }
367
368/**
369 * struct iwl_dump_sanitize_ops - dump sanitization operations
370 * @frob_txf: Scrub the TX FIFO data
371 * @frob_hcmd: Scrub a host command, the %hcmd pointer is to the header
372 * but that might be short or long (&struct iwl_cmd_header or
373 * &struct iwl_cmd_header_wide)
374 * @frob_mem: Scrub memory data
375 */
376struct iwl_dump_sanitize_ops {
377 void (*frob_txf)(void *ctx, void *buf, size_t buflen);
378 void (*frob_hcmd)(void *ctx, void *hcmd, size_t buflen);
379 void (*frob_mem)(void *ctx, u32 mem_addr, void *mem, size_t buflen);
380};
381
382/**
383 * struct iwl_trans_config - transport configuration
384 *
385 * @op_mode: pointer to the upper layer.
386 * @cmd_queue: the index of the command queue.
387 * Must be set before start_fw.
388 * @cmd_fifo: the fifo for host commands
389 * @no_reclaim_cmds: Some devices erroneously don't set the
390 * SEQ_RX_FRAME bit on some notifications, this is the
391 * list of such notifications to filter. Max length is
392 * %MAX_NO_RECLAIM_CMDS.
393 * @n_no_reclaim_cmds: # of commands in list
394 * @rx_buf_size: RX buffer size needed for A-MSDUs
395 * if unset 4k will be the RX buffer size
396 * @bc_table_dword: set to true if the BC table expects the byte count to be
397 * in DWORD (as opposed to bytes)
398 * @scd_set_active: should the transport configure the SCD for HCMD queue
399 * @command_groups: array of command groups, each member is an array of the
400 * commands in the group; for debugging only
401 * @command_groups_size: number of command groups, to avoid illegal access
402 * @cb_data_offs: offset inside skb->cb to store transport data at, must have
403 * space for at least two pointers
404 * @fw_reset_handshake: firmware supports reset flow handshake
405 * @queue_alloc_cmd_ver: queue allocation command version, set to 0
406 * for using the older SCD_QUEUE_CFG, set to the version of
407 * SCD_QUEUE_CONFIG_CMD otherwise.
408 */
409struct iwl_trans_config {
410 struct iwl_op_mode *op_mode;
411
412 u8 cmd_queue;
413 u8 cmd_fifo;
414 const u8 *no_reclaim_cmds;
415 unsigned int n_no_reclaim_cmds;
416
417 enum iwl_amsdu_size rx_buf_size;
418 bool bc_table_dword;
419 bool scd_set_active;
420 const struct iwl_hcmd_arr *command_groups;
421 int command_groups_size;
422
423 u8 cb_data_offs;
424 bool fw_reset_handshake;
425 u8 queue_alloc_cmd_ver;
426};
427
428struct iwl_trans_dump_data {
429 u32 len;
430 u8 data[];
431};
432
433struct iwl_trans;
434
435struct iwl_trans_txq_scd_cfg {
436 u8 fifo;
437 u8 sta_id;
438 u8 tid;
439 bool aggregate;
440 int frame_limit;
441};
442
443/**
444 * struct iwl_trans_rxq_dma_data - RX queue DMA data
445 * @fr_bd_cb: DMA address of free BD cyclic buffer
446 * @fr_bd_wid: Initial write index of the free BD cyclic buffer
447 * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr
448 * @ur_bd_cb: DMA address of used BD cyclic buffer
449 */
450struct iwl_trans_rxq_dma_data {
451 u64 fr_bd_cb;
452 u32 fr_bd_wid;
453 u64 urbd_stts_wrptr;
454 u64 ur_bd_cb;
455};
456
457/* maximal number of DRAM MAP entries supported by FW */
458#define IPC_DRAM_MAP_ENTRY_NUM_MAX 64
459
460/**
461 * struct iwl_pnvm_image - contains info about the parsed pnvm image
462 * @chunks: array of pointers to pnvm payloads and their sizes
463 * @n_chunks: the number of the pnvm payloads.
464 * @version: the version of the loaded PNVM image
465 */
466struct iwl_pnvm_image {
467 struct {
468 const void *data;
469 u32 len;
470 } chunks[IPC_DRAM_MAP_ENTRY_NUM_MAX];
471 u32 n_chunks;
472 u32 version;
473};
474
475/**
476 * enum iwl_trans_state - state of the transport layer
477 *
478 * @IWL_TRANS_NO_FW: firmware wasn't started yet, or crashed
479 * @IWL_TRANS_FW_STARTED: FW was started, but not alive yet
480 * @IWL_TRANS_FW_ALIVE: FW has sent an alive response
481 */
482enum iwl_trans_state {
483 IWL_TRANS_NO_FW,
484 IWL_TRANS_FW_STARTED,
485 IWL_TRANS_FW_ALIVE,
486};
487
488/**
489 * DOC: Platform power management
490 *
491 * In system-wide power management the entire platform goes into a low
492 * power state (e.g. idle or suspend to RAM) at the same time and the
493 * device is configured as a wakeup source for the entire platform.
494 * This is usually triggered by userspace activity (e.g. the user
495 * presses the suspend button or a power management daemon decides to
496 * put the platform in low power mode). The device's behavior in this
497 * mode is dictated by the wake-on-WLAN configuration.
498 *
499 * The terms used for the device's behavior are as follows:
500 *
501 * - D0: the device is fully powered and the host is awake;
502 * - D3: the device is in low power mode and only reacts to
503 * specific events (e.g. magic-packet received or scan
504 * results found);
505 *
506 * These terms reflect the power modes in the firmware and are not to
507 * be confused with the physical device power state.
508 */
509
510/**
511 * enum iwl_plat_pm_mode - platform power management mode
512 *
513 * This enumeration describes the device's platform power management
514 * behavior when in system-wide suspend (i.e WoWLAN).
515 *
516 * @IWL_PLAT_PM_MODE_DISABLED: power management is disabled for this
517 * device. In system-wide suspend mode, it means that the all
518 * connections will be closed automatically by mac80211 before
519 * the platform is suspended.
520 * @IWL_PLAT_PM_MODE_D3: the device goes into D3 mode (i.e. WoWLAN).
521 */
522enum iwl_plat_pm_mode {
523 IWL_PLAT_PM_MODE_DISABLED,
524 IWL_PLAT_PM_MODE_D3,
525};
526
527/**
528 * enum iwl_ini_cfg_state
529 * @IWL_INI_CFG_STATE_NOT_LOADED: no debug cfg was given
530 * @IWL_INI_CFG_STATE_LOADED: debug cfg was found and loaded
531 * @IWL_INI_CFG_STATE_CORRUPTED: debug cfg was found and some of the TLVs
532 * are corrupted. The rest of the debug TLVs will still be used
533 */
534enum iwl_ini_cfg_state {
535 IWL_INI_CFG_STATE_NOT_LOADED,
536 IWL_INI_CFG_STATE_LOADED,
537 IWL_INI_CFG_STATE_CORRUPTED,
538};
539
540/* Max time to wait for nmi interrupt */
541#define IWL_TRANS_NMI_TIMEOUT (HZ / 4)
542
543/**
544 * struct iwl_dram_data
545 * @physical: page phy pointer
546 * @block: pointer to the allocated block/page
547 * @size: size of the block/page
548 */
549struct iwl_dram_data {
550 dma_addr_t physical;
551 void *block;
552 int size;
553};
554
555/**
556 * struct iwl_dram_regions - DRAM regions container structure
557 * @drams: array of several DRAM areas that contains the pnvm and power
558 * reduction table payloads.
559 * @n_regions: number of DRAM regions that were allocated
560 * @prph_scratch_mem_desc: points to a structure allocated in dram,
561 * designed to show FW where all the payloads are.
562 */
563struct iwl_dram_regions {
564 struct iwl_dram_data drams[IPC_DRAM_MAP_ENTRY_NUM_MAX];
565 struct iwl_dram_data prph_scratch_mem_desc;
566 u8 n_regions;
567};
568
569/**
570 * struct iwl_fw_mon - fw monitor per allocation id
571 * @num_frags: number of fragments
572 * @frags: an array of DRAM buffer fragments
573 */
574struct iwl_fw_mon {
575 u32 num_frags;
576 struct iwl_dram_data *frags;
577};
578
579/**
580 * struct iwl_self_init_dram - dram data used by self init process
581 * @fw: lmac and umac dram data
582 * @fw_cnt: total number of items in array
583 * @paging: paging dram data
584 * @paging_cnt: total number of items in array
585 */
586struct iwl_self_init_dram {
587 struct iwl_dram_data *fw;
588 int fw_cnt;
589 struct iwl_dram_data *paging;
590 int paging_cnt;
591};
592
593/**
594 * struct iwl_imr_data - imr dram data used during debug process
595 * @imr_enable: imr enable status received from fw
596 * @imr_size: imr dram size received from fw
597 * @sram_addr: sram address from debug tlv
598 * @sram_size: sram size from debug tlv
599 * @imr2sram_remainbyte: size remained after each dma transfer
600 * @imr_curr_addr: current dst address used during dma transfer
601 * @imr_base_addr: imr address received from fw
602 */
603struct iwl_imr_data {
604 u32 imr_enable;
605 u32 imr_size;
606 u32 sram_addr;
607 u32 sram_size;
608 u32 imr2sram_remainbyte;
609 u64 imr_curr_addr;
610 __le64 imr_base_addr;
611};
612
613#define IWL_TRANS_CURRENT_PC_NAME_MAX_BYTES 32
614
615/**
616 * struct iwl_pc_data - program counter details
617 * @pc_name: cpu name
618 * @pc_address: cpu program counter
619 */
620struct iwl_pc_data {
621 u8 pc_name[IWL_TRANS_CURRENT_PC_NAME_MAX_BYTES];
622 u32 pc_address;
623};
624
625/**
626 * struct iwl_trans_debug - transport debug related data
627 *
628 * @n_dest_reg: num of reg_ops in %dbg_dest_tlv
629 * @rec_on: true iff there is a fw debug recording currently active
630 * @dest_tlv: points to the destination TLV for debug
631 * @conf_tlv: array of pointers to configuration TLVs for debug
632 * @trigger_tlv: array of pointers to triggers TLVs for debug
633 * @lmac_error_event_table: addrs of lmacs error tables
634 * @umac_error_event_table: addr of umac error table
635 * @tcm_error_event_table: address(es) of TCM error table(s)
636 * @rcm_error_event_table: address(es) of RCM error table(s)
637 * @error_event_table_tlv_status: bitmap that indicates what error table
638 * pointers was recevied via TLV. uses enum &iwl_error_event_table_status
639 * @internal_ini_cfg: internal debug cfg state. Uses &enum iwl_ini_cfg_state
640 * @external_ini_cfg: external debug cfg state. Uses &enum iwl_ini_cfg_state
641 * @fw_mon_cfg: debug buffer allocation configuration
642 * @fw_mon_ini: DRAM buffer fragments per allocation id
643 * @fw_mon: DRAM buffer for firmware monitor
644 * @hw_error: equals true if hw error interrupt was received from the FW
645 * @ini_dest: debug monitor destination uses &enum iwl_fw_ini_buffer_location
646 * @unsupported_region_msk: unsupported regions out of active_regions
647 * @active_regions: active regions
648 * @debug_info_tlv_list: list of debug info TLVs
649 * @time_point: array of debug time points
650 * @periodic_trig_list: periodic triggers list
651 * @domains_bitmap: bitmap of active domains other than &IWL_FW_INI_DOMAIN_ALWAYS_ON
652 * @ucode_preset: preset based on ucode
653 * @restart_required: indicates debug restart is required
654 * @last_tp_resetfw: last handling of reset during debug timepoint
655 * @imr_data: IMR debug data allocation
656 * @dump_file_name_ext: dump file name extension
657 * @dump_file_name_ext_valid: dump file name extension if valid or not
658 * @num_pc: number of program counter for cpu
659 * @pc_data: details of the program counter
660 * @yoyo_bin_loaded: tells if a yoyo debug file has been loaded
661 */
662struct iwl_trans_debug {
663 u8 n_dest_reg;
664 bool rec_on;
665
666 const struct iwl_fw_dbg_dest_tlv_v1 *dest_tlv;
667 const struct iwl_fw_dbg_conf_tlv *conf_tlv[FW_DBG_CONF_MAX];
668 struct iwl_fw_dbg_trigger_tlv * const *trigger_tlv;
669
670 u32 lmac_error_event_table[2];
671 u32 umac_error_event_table;
672 u32 tcm_error_event_table[2];
673 u32 rcm_error_event_table[2];
674 unsigned int error_event_table_tlv_status;
675
676 enum iwl_ini_cfg_state internal_ini_cfg;
677 enum iwl_ini_cfg_state external_ini_cfg;
678
679 struct iwl_fw_ini_allocation_tlv fw_mon_cfg[IWL_FW_INI_ALLOCATION_NUM];
680 struct iwl_fw_mon fw_mon_ini[IWL_FW_INI_ALLOCATION_NUM];
681
682 struct iwl_dram_data fw_mon;
683
684 bool hw_error;
685 enum iwl_fw_ini_buffer_location ini_dest;
686
687 u64 unsupported_region_msk;
688 struct iwl_ucode_tlv *active_regions[IWL_FW_INI_MAX_REGION_ID];
689 struct list_head debug_info_tlv_list;
690 struct iwl_dbg_tlv_time_point_data time_point[IWL_FW_INI_TIME_POINT_NUM];
691 struct list_head periodic_trig_list;
692
693 u32 domains_bitmap;
694 u32 ucode_preset;
695 bool restart_required;
696 u32 last_tp_resetfw;
697 struct iwl_imr_data imr_data;
698 u8 dump_file_name_ext[IWL_FW_INI_MAX_NAME];
699 bool dump_file_name_ext_valid;
700 u32 num_pc;
701 struct iwl_pc_data *pc_data;
702 bool yoyo_bin_loaded;
703};
704
705struct iwl_dma_ptr {
706 dma_addr_t dma;
707 void *addr;
708 size_t size;
709};
710
711struct iwl_cmd_meta {
712 /* only for SYNC commands, iff the reply skb is wanted */
713 struct iwl_host_cmd *source;
714 u32 flags: CMD_MODE_BITS;
715 /* sg_offset is valid if it is non-zero */
716 u32 sg_offset: PAGE_SHIFT;
717 u32 tbs;
718};
719
720/*
721 * The FH will write back to the first TB only, so we need to copy some data
722 * into the buffer regardless of whether it should be mapped or not.
723 * This indicates how big the first TB must be to include the scratch buffer
724 * and the assigned PN.
725 * Since PN location is 8 bytes at offset 12, it's 20 now.
726 * If we make it bigger then allocations will be bigger and copy slower, so
727 * that's probably not useful.
728 */
729#define IWL_FIRST_TB_SIZE 20
730#define IWL_FIRST_TB_SIZE_ALIGN ALIGN(IWL_FIRST_TB_SIZE, 64)
731
732struct iwl_pcie_txq_entry {
733 void *cmd;
734 struct sk_buff *skb;
735 /* buffer to free after command completes */
736 const void *free_buf;
737 struct iwl_cmd_meta meta;
738};
739
740struct iwl_pcie_first_tb_buf {
741 u8 buf[IWL_FIRST_TB_SIZE_ALIGN];
742};
743
744/**
745 * struct iwl_txq - Tx Queue for DMA
746 * @tfds: transmit frame descriptors (DMA memory)
747 * @first_tb_bufs: start of command headers, including scratch buffers, for
748 * the writeback -- this is DMA memory and an array holding one buffer
749 * for each command on the queue
750 * @first_tb_dma: DMA address for the first_tb_bufs start
751 * @entries: transmit entries (driver state)
752 * @lock: queue lock
753 * @reclaim_lock: reclaim lock
754 * @stuck_timer: timer that fires if queue gets stuck
755 * @trans: pointer back to transport (for timer)
756 * @need_update: indicates need to update read/write index
757 * @ampdu: true if this queue is an ampdu queue for an specific RA/TID
758 * @wd_timeout: queue watchdog timeout (jiffies) - per queue
759 * @frozen: tx stuck queue timer is frozen
760 * @frozen_expiry_remainder: remember how long until the timer fires
761 * @block: queue is blocked
762 * @bc_tbl: byte count table of the queue (relevant only for gen2 transport)
763 * @write_ptr: 1-st empty entry (index) host_w
764 * @read_ptr: last used entry (index) host_r
765 * @dma_addr: physical addr for BD's
766 * @n_window: safe queue window
767 * @id: queue id
768 * @low_mark: low watermark, resume queue if free space more than this
769 * @high_mark: high watermark, stop queue if free space less than this
770 * @overflow_q: overflow queue for handling frames that didn't fit on HW queue
771 * @overflow_tx: need to transmit from overflow
772 *
773 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
774 * descriptors) and required locking structures.
775 *
776 * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware
777 * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless
778 * there might be HW changes in the future). For the normal TX
779 * queues, n_window, which is the size of the software queue data
780 * is also 256; however, for the command queue, n_window is only
781 * 32 since we don't need so many commands pending. Since the HW
782 * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256.
783 * This means that we end up with the following:
784 * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 |
785 * SW entries: | 0 | ... | 31 |
786 * where N is a number between 0 and 7. This means that the SW
787 * data is a window overlayed over the HW queue.
788 */
789struct iwl_txq {
790 void *tfds;
791 struct iwl_pcie_first_tb_buf *first_tb_bufs;
792 dma_addr_t first_tb_dma;
793 struct iwl_pcie_txq_entry *entries;
794 /* lock for syncing changes on the queue */
795 spinlock_t lock;
796 /* lock to prevent concurrent reclaim */
797 spinlock_t reclaim_lock;
798 unsigned long frozen_expiry_remainder;
799 struct timer_list stuck_timer;
800 struct iwl_trans *trans;
801 bool need_update;
802 bool frozen;
803 bool ampdu;
804 int block;
805 unsigned long wd_timeout;
806 struct sk_buff_head overflow_q;
807 struct iwl_dma_ptr bc_tbl;
808
809 int write_ptr;
810 int read_ptr;
811 dma_addr_t dma_addr;
812 int n_window;
813 u32 id;
814 int low_mark;
815 int high_mark;
816
817 bool overflow_tx;
818};
819
820/**
821 * struct iwl_trans - transport common data
822 *
823 * @csme_own: true if we couldn't get ownership on the device
824 * @op_mode: pointer to the op_mode
825 * @trans_cfg: the trans-specific configuration part
826 * @cfg: pointer to the configuration
827 * @drv: pointer to iwl_drv
828 * @state: current device state
829 * @status: a bit-mask of transport status flags
830 * @dev: pointer to struct device * that represents the device
831 * @max_skb_frags: maximum number of fragments an SKB can have when transmitted.
832 * 0 indicates that frag SKBs (NETIF_F_SG) aren't supported.
833 * @hw_rf_id: a u32 with the device RF ID
834 * @hw_cnv_id: a u32 with the device CNV ID
835 * @hw_crf_id: a u32 with the device CRF ID
836 * @hw_wfpm_id: a u32 with the device wfpm ID
837 * @hw_id: a u32 with the ID of the device / sub-device.
838 * Set during transport allocation.
839 * @hw_id_str: a string with info about HW ID. Set during transport allocation.
840 * @sku_id: the SKU identifier (for PNVM matching)
841 * @pnvm_loaded: indicates PNVM was loaded
842 * @hw_rev: the revision data of the HW
843 * @hw_rev_step: The mac step of the HW
844 * @pm_support: set to true in start_hw if link pm is supported
845 * @ltr_enabled: set to true if the LTR is enabled
846 * @fail_to_parse_pnvm_image: set to true if pnvm parsing failed
847 * @reduce_power_loaded: indicates reduced power section was loaded
848 * @failed_to_load_reduce_power_image: set to true if pnvm loading failed
849 * @command_groups: pointer to command group name list array
850 * @command_groups_size: array size of @command_groups
851 * @wide_cmd_header: true when ucode supports wide command header format
852 * @wait_command_queue: wait queue for sync commands
853 * @num_rx_queues: number of RX queues allocated by the transport;
854 * the transport must set this before calling iwl_drv_start()
855 * @iml_len: the length of the image loader
856 * @iml: a pointer to the image loader itself
857 * @dev_cmd_pool: pool for Tx cmd allocation - for internal use only.
858 * The user should use iwl_trans_{alloc,free}_tx_cmd.
859 * @dev_cmd_pool_name: name for the TX command allocation pool
860 * @dbgfs_dir: iwlwifi debugfs base dir for this device
861 * @sync_cmd_lockdep_map: lockdep map for checking sync commands
862 * @rx_mpdu_cmd: MPDU RX command ID, must be assigned by opmode before
863 * starting the firmware, used for tracing
864 * @rx_mpdu_cmd_hdr_size: used for tracing, amount of data before the
865 * start of the 802.11 header in the @rx_mpdu_cmd
866 * @dbg: additional debug data, see &struct iwl_trans_debug
867 * @init_dram: FW initialization DMA data
868 * @system_pm_mode: the system-wide power management mode in use.
869 * This mode is set dynamically, depending on the WoWLAN values
870 * configured from the userspace at runtime.
871 * @name: the device name
872 * @mbx_addr_0_step: step address data 0
873 * @mbx_addr_1_step: step address data 1
874 * @pcie_link_speed: current PCIe link speed (%PCI_EXP_LNKSTA_CLS_*),
875 * only valid for discrete (not integrated) NICs
876 * @invalid_tx_cmd: invalid TX command buffer
877 * @reduced_cap_sku: reduced capability supported SKU
878 * @no_160: device not supporting 160 MHz
879 * @step_urm: STEP is in URM, no support for MCS>9 in 320 MHz
880 * @trans_specific: data for the specific transport this is allocated for/with
881 */
882struct iwl_trans {
883 bool csme_own;
884 struct iwl_op_mode *op_mode;
885 const struct iwl_cfg_trans_params *trans_cfg;
886 const struct iwl_cfg *cfg;
887 struct iwl_drv *drv;
888 enum iwl_trans_state state;
889 unsigned long status;
890
891 struct device *dev;
892 u32 max_skb_frags;
893 u32 hw_rev;
894 u32 hw_rev_step;
895 u32 hw_rf_id;
896 u32 hw_crf_id;
897 u32 hw_cnv_id;
898 u32 hw_wfpm_id;
899 u32 hw_id;
900 char hw_id_str[52];
901 u32 sku_id[3];
902 bool reduced_cap_sku;
903 u8 no_160:1, step_urm:1;
904
905 u8 rx_mpdu_cmd, rx_mpdu_cmd_hdr_size;
906
907 bool pm_support;
908 bool ltr_enabled;
909 u8 pnvm_loaded:1;
910 u8 fail_to_parse_pnvm_image:1;
911 u8 reduce_power_loaded:1;
912 u8 failed_to_load_reduce_power_image:1;
913
914 const struct iwl_hcmd_arr *command_groups;
915 int command_groups_size;
916 bool wide_cmd_header;
917
918 wait_queue_head_t wait_command_queue;
919 u8 num_rx_queues;
920
921 size_t iml_len;
922 u8 *iml;
923
924 /* The following fields are internal only */
925 struct kmem_cache *dev_cmd_pool;
926 char dev_cmd_pool_name[50];
927
928 struct dentry *dbgfs_dir;
929
930#ifdef CONFIG_LOCKDEP
931 struct lockdep_map sync_cmd_lockdep_map;
932#endif
933
934 struct iwl_trans_debug dbg;
935 struct iwl_self_init_dram init_dram;
936
937 enum iwl_plat_pm_mode system_pm_mode;
938
939 const char *name;
940 u32 mbx_addr_0_step;
941 u32 mbx_addr_1_step;
942
943 u8 pcie_link_speed;
944
945 struct iwl_dma_ptr invalid_tx_cmd;
946
947 /* pointer to trans specific struct */
948 /*Ensure that this pointer will always be aligned to sizeof pointer */
949 char trans_specific[] __aligned(sizeof(void *));
950};
951
952const char *iwl_get_cmd_string(struct iwl_trans *trans, u32 id);
953int iwl_cmd_groups_verify_sorted(const struct iwl_trans_config *trans);
954
955void iwl_trans_configure(struct iwl_trans *trans,
956 const struct iwl_trans_config *trans_cfg);
957
958int iwl_trans_start_hw(struct iwl_trans *trans);
959
960void iwl_trans_op_mode_leave(struct iwl_trans *trans);
961
962void iwl_trans_fw_alive(struct iwl_trans *trans, u32 scd_addr);
963
964int iwl_trans_start_fw(struct iwl_trans *trans, const struct fw_img *fw,
965 bool run_in_rfkill);
966
967void iwl_trans_stop_device(struct iwl_trans *trans);
968
969int iwl_trans_d3_suspend(struct iwl_trans *trans, bool test, bool reset);
970
971int iwl_trans_d3_resume(struct iwl_trans *trans, enum iwl_d3_status *status,
972 bool test, bool reset);
973
974struct iwl_trans_dump_data *
975iwl_trans_dump_data(struct iwl_trans *trans, u32 dump_mask,
976 const struct iwl_dump_sanitize_ops *sanitize_ops,
977 void *sanitize_ctx);
978
979static inline struct iwl_device_tx_cmd *
980iwl_trans_alloc_tx_cmd(struct iwl_trans *trans)
981{
982 return kmem_cache_zalloc(trans->dev_cmd_pool, GFP_ATOMIC);
983}
984
985int iwl_trans_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
986
987static inline void iwl_trans_free_tx_cmd(struct iwl_trans *trans,
988 struct iwl_device_tx_cmd *dev_cmd)
989{
990 kmem_cache_free(trans->dev_cmd_pool, dev_cmd);
991}
992
993int iwl_trans_tx(struct iwl_trans *trans, struct sk_buff *skb,
994 struct iwl_device_tx_cmd *dev_cmd, int queue);
995
996void iwl_trans_reclaim(struct iwl_trans *trans, int queue, int ssn,
997 struct sk_buff_head *skbs, bool is_flush);
998
999void iwl_trans_set_q_ptrs(struct iwl_trans *trans, int queue, int ptr);
1000
1001void iwl_trans_txq_disable(struct iwl_trans *trans, int queue,
1002 bool configure_scd);
1003
1004bool iwl_trans_txq_enable_cfg(struct iwl_trans *trans, int queue, u16 ssn,
1005 const struct iwl_trans_txq_scd_cfg *cfg,
1006 unsigned int queue_wdg_timeout);
1007
1008int iwl_trans_get_rxq_dma_data(struct iwl_trans *trans, int queue,
1009 struct iwl_trans_rxq_dma_data *data);
1010
1011void iwl_trans_txq_free(struct iwl_trans *trans, int queue);
1012
1013int iwl_trans_txq_alloc(struct iwl_trans *trans, u32 flags, u32 sta_mask,
1014 u8 tid, int size, unsigned int wdg_timeout);
1015
1016void iwl_trans_txq_set_shared_mode(struct iwl_trans *trans,
1017 int txq_id, bool shared_mode);
1018
1019static inline void iwl_trans_txq_enable(struct iwl_trans *trans, int queue,
1020 int fifo, int sta_id, int tid,
1021 int frame_limit, u16 ssn,
1022 unsigned int queue_wdg_timeout)
1023{
1024 struct iwl_trans_txq_scd_cfg cfg = {
1025 .fifo = fifo,
1026 .sta_id = sta_id,
1027 .tid = tid,
1028 .frame_limit = frame_limit,
1029 .aggregate = sta_id >= 0,
1030 };
1031
1032 iwl_trans_txq_enable_cfg(trans, queue, ssn, &cfg, queue_wdg_timeout);
1033}
1034
1035static inline
1036void iwl_trans_ac_txq_enable(struct iwl_trans *trans, int queue, int fifo,
1037 unsigned int queue_wdg_timeout)
1038{
1039 struct iwl_trans_txq_scd_cfg cfg = {
1040 .fifo = fifo,
1041 .sta_id = -1,
1042 .tid = IWL_MAX_TID_COUNT,
1043 .frame_limit = IWL_FRAME_LIMIT,
1044 .aggregate = false,
1045 };
1046
1047 iwl_trans_txq_enable_cfg(trans, queue, 0, &cfg, queue_wdg_timeout);
1048}
1049
1050void iwl_trans_freeze_txq_timer(struct iwl_trans *trans,
1051 unsigned long txqs, bool freeze);
1052
1053int iwl_trans_wait_tx_queues_empty(struct iwl_trans *trans, u32 txqs);
1054
1055int iwl_trans_wait_txq_empty(struct iwl_trans *trans, int queue);
1056
1057void iwl_trans_write8(struct iwl_trans *trans, u32 ofs, u8 val);
1058
1059void iwl_trans_write32(struct iwl_trans *trans, u32 ofs, u32 val);
1060
1061u32 iwl_trans_read32(struct iwl_trans *trans, u32 ofs);
1062
1063u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs);
1064
1065void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs, u32 val);
1066
1067int iwl_trans_read_mem(struct iwl_trans *trans, u32 addr,
1068 void *buf, int dwords);
1069
1070int iwl_trans_read_config32(struct iwl_trans *trans, u32 ofs,
1071 u32 *val);
1072
1073#ifdef CONFIG_IWLWIFI_DEBUGFS
1074void iwl_trans_debugfs_cleanup(struct iwl_trans *trans);
1075#endif
1076
1077#define iwl_trans_read_mem_bytes(trans, addr, buf, bufsize) \
1078 ({ \
1079 if (__builtin_constant_p(bufsize)) \
1080 BUILD_BUG_ON((bufsize) % sizeof(u32)); \
1081 iwl_trans_read_mem(trans, addr, buf, \
1082 (bufsize) / sizeof(u32)); \
1083 })
1084
1085int iwl_trans_write_imr_mem(struct iwl_trans *trans, u32 dst_addr,
1086 u64 src_addr, u32 byte_cnt);
1087
1088static inline u32 iwl_trans_read_mem32(struct iwl_trans *trans, u32 addr)
1089{
1090 u32 value;
1091
1092 if (iwl_trans_read_mem(trans, addr, &value, 1))
1093 return 0xa5a5a5a5;
1094
1095 return value;
1096}
1097
1098int iwl_trans_write_mem(struct iwl_trans *trans, u32 addr,
1099 const void *buf, int dwords);
1100
1101static inline u32 iwl_trans_write_mem32(struct iwl_trans *trans, u32 addr,
1102 u32 val)
1103{
1104 return iwl_trans_write_mem(trans, addr, &val, 1);
1105}
1106
1107void iwl_trans_set_pmi(struct iwl_trans *trans, bool state);
1108
1109int iwl_trans_sw_reset(struct iwl_trans *trans, bool retake_ownership);
1110
1111void iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg,
1112 u32 mask, u32 value);
1113
1114bool _iwl_trans_grab_nic_access(struct iwl_trans *trans);
1115
1116#define iwl_trans_grab_nic_access(trans) \
1117 __cond_lock(nic_access, \
1118 likely(_iwl_trans_grab_nic_access(trans)))
1119
1120void __releases(nic_access)
1121iwl_trans_release_nic_access(struct iwl_trans *trans);
1122
1123static inline void iwl_trans_fw_error(struct iwl_trans *trans, bool sync)
1124{
1125 if (WARN_ON_ONCE(!trans->op_mode))
1126 return;
1127
1128 /* prevent double restarts due to the same erroneous FW */
1129 if (!test_and_set_bit(STATUS_FW_ERROR, &trans->status)) {
1130 trans->state = IWL_TRANS_NO_FW;
1131 iwl_op_mode_nic_error(trans->op_mode, sync);
1132 }
1133}
1134
1135static inline bool iwl_trans_fw_running(struct iwl_trans *trans)
1136{
1137 return trans->state == IWL_TRANS_FW_ALIVE;
1138}
1139
1140void iwl_trans_sync_nmi(struct iwl_trans *trans);
1141
1142void iwl_trans_sync_nmi_with_addr(struct iwl_trans *trans, u32 inta_addr,
1143 u32 sw_err_bit);
1144
1145int iwl_trans_load_pnvm(struct iwl_trans *trans,
1146 const struct iwl_pnvm_image *pnvm_data,
1147 const struct iwl_ucode_capabilities *capa);
1148
1149void iwl_trans_set_pnvm(struct iwl_trans *trans,
1150 const struct iwl_ucode_capabilities *capa);
1151
1152int iwl_trans_load_reduce_power(struct iwl_trans *trans,
1153 const struct iwl_pnvm_image *payloads,
1154 const struct iwl_ucode_capabilities *capa);
1155
1156void iwl_trans_set_reduce_power(struct iwl_trans *trans,
1157 const struct iwl_ucode_capabilities *capa);
1158
1159static inline bool iwl_trans_dbg_ini_valid(struct iwl_trans *trans)
1160{
1161 return trans->dbg.internal_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED ||
1162 trans->dbg.external_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED;
1163}
1164
1165void iwl_trans_interrupts(struct iwl_trans *trans, bool enable);
1166
1167/*****************************************************
1168 * transport helper functions
1169 *****************************************************/
1170struct iwl_trans *iwl_trans_alloc(unsigned int priv_size,
1171 struct device *dev,
1172 const struct iwl_cfg_trans_params *cfg_trans);
1173int iwl_trans_init(struct iwl_trans *trans);
1174void iwl_trans_free(struct iwl_trans *trans);
1175
1176static inline bool iwl_trans_is_hw_error_value(u32 val)
1177{
1178 return ((val & ~0xf) == 0xa5a5a5a0) || ((val & ~0xf) == 0x5a5a5a50);
1179}
1180
1181/*****************************************************
1182 * PCIe handling
1183 *****************************************************/
1184int __must_check iwl_pci_register_driver(void);
1185void iwl_pci_unregister_driver(void);
1186void iwl_trans_pcie_remove(struct iwl_trans *trans, bool rescan);
1187
1188int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans,
1189 struct iwl_host_cmd *cmd);
1190
1191#endif /* __iwl_trans_h__ */