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1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/*
3 * Copyright (C) 2005-2014, 2018-2022 Intel Corporation
4 * Copyright (C) 2013-2014 Intel Mobile Communications GmbH
5 * Copyright (C) 2016 Intel Deutschland GmbH
6 */
7#ifndef __iwl_csr_h__
8#define __iwl_csr_h__
9/*
10 * CSR (control and status registers)
11 *
12 * CSR registers are mapped directly into PCI bus space, and are accessible
13 * whenever platform supplies power to device, even when device is in
14 * low power states due to driver-invoked device resets
15 * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
16 *
17 * Use iwl_write32() and iwl_read32() family to access these registers;
18 * these provide simple PCI bus access, without waking up the MAC.
19 * Do not use iwl_write_direct32() family for these registers;
20 * no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.
21 * The MAC (uCode processor, etc.) does not need to be powered up for accessing
22 * the CSR registers.
23 *
24 * NOTE: Device does need to be awake in order to read this memory
25 * via CSR_EEPROM and CSR_OTP registers
26 */
27#define CSR_BASE (0x000)
28
29#define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
30#define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
31#define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
32#define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
33#define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/
34#define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
35#define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
36#define CSR_GP_CNTRL (CSR_BASE+0x024)
37#define CSR_FUNC_SCRATCH (CSR_BASE+0x02c) /* Scratch register - used for FW dbg */
38
39/* 2nd byte of CSR_INT_COALESCING, not accessible via iwl_write32()! */
40#define CSR_INT_PERIODIC_REG (CSR_BASE+0x005)
41
42/*
43 * Hardware revision info
44 * Bit fields:
45 * 31-16: Reserved
46 * 15-4: Type of device: see CSR_HW_REV_TYPE_xxx definitions
47 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
48 * 1-0: "Dash" (-) value, as in A-1, etc.
49 */
50#define CSR_HW_REV (CSR_BASE+0x028)
51
52/*
53 * RF ID revision info
54 * Bit fields:
55 * 31:24: Reserved (set to 0x0)
56 * 23:12: Type
57 * 11:8: Step (A - 0x0, B - 0x1, etc)
58 * 7:4: Dash
59 * 3:0: Flavor
60 */
61#define CSR_HW_RF_ID (CSR_BASE+0x09c)
62
63/*
64 * EEPROM and OTP (one-time-programmable) memory reads
65 *
66 * NOTE: Device must be awake, initialized via apm_ops.init(),
67 * in order to read.
68 */
69#define CSR_EEPROM_REG (CSR_BASE+0x02c)
70#define CSR_EEPROM_GP (CSR_BASE+0x030)
71#define CSR_OTP_GP_REG (CSR_BASE+0x034)
72
73#define CSR_GIO_REG (CSR_BASE+0x03C)
74#define CSR_GP_UCODE_REG (CSR_BASE+0x048)
75#define CSR_GP_DRIVER_REG (CSR_BASE+0x050)
76
77/*
78 * UCODE-DRIVER GP (general purpose) mailbox registers.
79 * SET/CLR registers set/clear bit(s) if "1" is written.
80 */
81#define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054)
82#define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058)
83#define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
84#define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
85
86#define CSR_MBOX_SET_REG (CSR_BASE + 0x88)
87
88#define CSR_LED_REG (CSR_BASE+0x094)
89#define CSR_DRAM_INT_TBL_REG (CSR_BASE+0x0A0)
90#define CSR_MAC_SHADOW_REG_CTRL (CSR_BASE + 0x0A8) /* 6000 and up */
91#define CSR_MAC_SHADOW_REG_CTRL_RX_WAKE BIT(20)
92#define CSR_MAC_SHADOW_REG_CTL2 (CSR_BASE + 0x0AC)
93#define CSR_MAC_SHADOW_REG_CTL2_RX_WAKE 0xFFFF
94
95/* LTR control (since IWL_DEVICE_FAMILY_22000) */
96#define CSR_LTR_LONG_VAL_AD (CSR_BASE + 0x0D4)
97#define CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ 0x80000000
98#define CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE 0x1c000000
99#define CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL 0x03ff0000
100#define CSR_LTR_LONG_VAL_AD_SNOOP_REQ 0x00008000
101#define CSR_LTR_LONG_VAL_AD_SNOOP_SCALE 0x00001c00
102#define CSR_LTR_LONG_VAL_AD_SNOOP_VAL 0x000003ff
103#define CSR_LTR_LONG_VAL_AD_SCALE_USEC 2
104
105/* GIO Chicken Bits (PCI Express bus link power management) */
106#define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
107
108#define CSR_IPC_SLEEP_CONTROL (CSR_BASE + 0x114)
109#define CSR_IPC_SLEEP_CONTROL_SUSPEND 0x3
110#define CSR_IPC_SLEEP_CONTROL_RESUME 0
111
112/* Doorbell - since Bz
113 * connected to UREG_DOORBELL_TO_ISR6 (lower 16 bits only)
114 */
115#define CSR_DOORBELL_VECTOR (CSR_BASE + 0x130)
116
117/* host chicken bits */
118#define CSR_HOST_CHICKEN (CSR_BASE + 0x204)
119#define CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME BIT(19)
120
121/* Analog phase-lock-loop configuration */
122#define CSR_ANA_PLL_CFG (CSR_BASE+0x20c)
123
124/*
125 * CSR HW resources monitor registers
126 */
127#define CSR_MONITOR_CFG_REG (CSR_BASE+0x214)
128#define CSR_MONITOR_STATUS_REG (CSR_BASE+0x228)
129#define CSR_MONITOR_XTAL_RESOURCES (0x00000010)
130
131/*
132 * CSR Hardware Revision Workaround Register. Indicates hardware rev;
133 * "step" determines CCK backoff for txpower calculation.
134 * See also CSR_HW_REV register.
135 * Bit fields:
136 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
137 * 1-0: "Dash" (-) value, as in C-1, etc.
138 */
139#define CSR_HW_REV_WA_REG (CSR_BASE+0x22C)
140
141#define CSR_DBG_HPET_MEM_REG (CSR_BASE+0x240)
142#define CSR_DBG_LINK_PWR_MGMT_REG (CSR_BASE+0x250)
143
144/*
145 * Scratch register initial configuration - this is set on init, and read
146 * during a error FW error.
147 */
148#define CSR_FUNC_SCRATCH_INIT_VALUE (0x01010101)
149
150/* Bits for CSR_HW_IF_CONFIG_REG */
151#define CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP_DASH (0x0000000F)
152#define CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM (0x00000080)
153#define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0)
154#define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
155#define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
156#define CSR_HW_IF_CONFIG_REG_D3_DEBUG (0x00000200)
157#define CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00)
158#define CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000)
159#define CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000)
160
161#define CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0)
162#define CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2)
163#define CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6)
164#define CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10)
165#define CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12)
166#define CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14)
167
168#define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000)
169#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
170#define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */
171#define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
172#define CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */
173#define CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000)
174#define CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */
175
176#define CSR_MBOX_SET_REG_OS_ALIVE BIT(5)
177
178#define CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/
179#define CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/
180
181/* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
182 * acknowledged (reset) by host writing "1" to flagged bits. */
183#define CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
184#define CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */
185#define CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */
186#define CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
187#define CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */
188#define CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */
189#define CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */
190#define CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */
191#define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */
192#define CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */
193#define CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */
194
195#define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \
196 CSR_INT_BIT_HW_ERR | \
197 CSR_INT_BIT_FH_TX | \
198 CSR_INT_BIT_SW_ERR | \
199 CSR_INT_BIT_RF_KILL | \
200 CSR_INT_BIT_SW_RX | \
201 CSR_INT_BIT_WAKEUP | \
202 CSR_INT_BIT_ALIVE | \
203 CSR_INT_BIT_RX_PERIODIC)
204
205/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
206#define CSR_FH_INT_BIT_ERR (1 << 31) /* Error */
207#define CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
208#define CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
209#define CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
210#define CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */
211#define CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
212
213#define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \
214 CSR_FH_INT_BIT_RX_CHNL1 | \
215 CSR_FH_INT_BIT_RX_CHNL0)
216
217#define CSR_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 | \
218 CSR_FH_INT_BIT_TX_CHNL0)
219
220/* GPIO */
221#define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
222#define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
223#define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200)
224
225/* RESET */
226#define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
227#define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
228#define CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
229#define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
230#define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
231#define CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000)
232
233/*
234 * GP (general purpose) CONTROL REGISTER
235 * Bit fields:
236 * 27: HW_RF_KILL_SW
237 * Indicates state of (platform's) hardware RF-Kill switch
238 * 26-24: POWER_SAVE_TYPE
239 * Indicates current power-saving mode:
240 * 000 -- No power saving
241 * 001 -- MAC power-down
242 * 010 -- PHY (radio) power-down
243 * 011 -- Error
244 * 10: XTAL ON request
245 * 9-6: SYS_CONFIG
246 * Indicates current system configuration, reflecting pins on chip
247 * as forced high/low by device circuit board.
248 * 4: GOING_TO_SLEEP
249 * Indicates MAC is entering a power-saving sleep power-down.
250 * Not a good time to access device-internal resources.
251 * 3: MAC_ACCESS_REQ
252 * Host sets this to request and maintain MAC wakeup, to allow host
253 * access to device-internal resources. Host must wait for
254 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
255 * device registers.
256 * 2: INIT_DONE
257 * Host sets this to put device into fully operational D0 power mode.
258 * Host resets this after SW_RESET to put device into low power mode.
259 * 0: MAC_CLOCK_READY
260 * Indicates MAC (ucode processor, etc.) is powered up and can run.
261 * Internal resources are accessible.
262 * NOTE: This does not indicate that the processor is actually running.
263 * NOTE: This does not indicate that device has completed
264 * init or post-power-down restore of internal SRAM memory.
265 * Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
266 * SRAM is restored and uCode is in normal operation mode.
267 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
268 * do not need to save/restore it.
269 * NOTE: After device reset, this bit remains "0" until host sets
270 * INIT_DONE
271 */
272#define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
273#define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
274#define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
275#define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
276#define CSR_GP_CNTRL_REG_FLAG_XTAL_ON (0x00000400)
277
278#define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
279
280#define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
281#define CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN (0x04000000)
282#define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
283
284/* From Bz we use these instead during init/reset flow */
285#define CSR_GP_CNTRL_REG_FLAG_MAC_INIT BIT(6)
286#define CSR_GP_CNTRL_REG_FLAG_ROM_START BIT(7)
287#define CSR_GP_CNTRL_REG_FLAG_MAC_STATUS BIT(20)
288#define CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ BIT(21)
289#define CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS BIT(28)
290#define CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ BIT(29)
291#define CSR_GP_CNTRL_REG_FLAG_SW_RESET BIT(31)
292
293/* HW REV */
294#define CSR_HW_REV_STEP_DASH(_val) ((_val) & CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP_DASH)
295#define CSR_HW_REV_TYPE(_val) (((_val) & 0x000FFF0) >> 4)
296
297/* HW RFID */
298#define CSR_HW_RFID_FLAVOR(_val) (((_val) & 0x000000F) >> 0)
299#define CSR_HW_RFID_DASH(_val) (((_val) & 0x00000F0) >> 4)
300#define CSR_HW_RFID_STEP(_val) (((_val) & 0x0000F00) >> 8)
301#define CSR_HW_RFID_TYPE(_val) (((_val) & 0x0FFF000) >> 12)
302#define CSR_HW_RFID_IS_CDB(_val) (((_val) & 0x10000000) >> 28)
303#define CSR_HW_RFID_IS_JACKET(_val) (((_val) & 0x20000000) >> 29)
304
305/**
306 * hw_rev values
307 */
308enum {
309 SILICON_A_STEP = 0,
310 SILICON_B_STEP,
311 SILICON_C_STEP,
312 SILICON_Z_STEP = 0xf,
313};
314
315
316#define CSR_HW_REV_TYPE_MSK (0x000FFF0)
317#define CSR_HW_REV_TYPE_5300 (0x0000020)
318#define CSR_HW_REV_TYPE_5350 (0x0000030)
319#define CSR_HW_REV_TYPE_5100 (0x0000050)
320#define CSR_HW_REV_TYPE_5150 (0x0000040)
321#define CSR_HW_REV_TYPE_1000 (0x0000060)
322#define CSR_HW_REV_TYPE_6x00 (0x0000070)
323#define CSR_HW_REV_TYPE_6x50 (0x0000080)
324#define CSR_HW_REV_TYPE_6150 (0x0000084)
325#define CSR_HW_REV_TYPE_6x05 (0x00000B0)
326#define CSR_HW_REV_TYPE_6x30 CSR_HW_REV_TYPE_6x05
327#define CSR_HW_REV_TYPE_6x35 CSR_HW_REV_TYPE_6x05
328#define CSR_HW_REV_TYPE_2x30 (0x00000C0)
329#define CSR_HW_REV_TYPE_2x00 (0x0000100)
330#define CSR_HW_REV_TYPE_105 (0x0000110)
331#define CSR_HW_REV_TYPE_135 (0x0000120)
332#define CSR_HW_REV_TYPE_3160 (0x0000164)
333#define CSR_HW_REV_TYPE_7265D (0x0000210)
334#define CSR_HW_REV_TYPE_NONE (0x00001F0)
335#define CSR_HW_REV_TYPE_QNJ (0x0000360)
336#define CSR_HW_REV_TYPE_QNJ_B0 (0x0000361)
337#define CSR_HW_REV_TYPE_QU_B0 (0x0000331)
338#define CSR_HW_REV_TYPE_QU_C0 (0x0000332)
339#define CSR_HW_REV_TYPE_QUZ (0x0000351)
340#define CSR_HW_REV_TYPE_HR_CDB (0x0000340)
341#define CSR_HW_REV_TYPE_SO (0x0000370)
342#define CSR_HW_REV_TYPE_TY (0x0000420)
343
344/* RF_ID value */
345#define CSR_HW_RF_ID_TYPE_JF (0x00105100)
346#define CSR_HW_RF_ID_TYPE_HR (0x0010A000)
347#define CSR_HW_RF_ID_TYPE_HR1 (0x0010c100)
348#define CSR_HW_RF_ID_TYPE_HRCDB (0x00109F00)
349#define CSR_HW_RF_ID_TYPE_GF (0x0010D000)
350#define CSR_HW_RF_ID_TYPE_GF4 (0x0010E000)
351
352/* HW_RF CHIP STEP */
353#define CSR_HW_RF_STEP(_val) (((_val) >> 8) & 0xF)
354
355/* EEPROM REG */
356#define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
357#define CSR_EEPROM_REG_BIT_CMD (0x00000002)
358#define CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC)
359#define CSR_EEPROM_REG_MSK_DATA (0xFFFF0000)
360
361/* EEPROM GP */
362#define CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */
363#define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
364#define CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000)
365#define CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001)
366#define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002)
367#define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004)
368
369/* One-time-programmable memory general purpose reg */
370#define CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */
371#define CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */
372#define CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */
373#define CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */
374
375/* GP REG */
376#define CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */
377#define CSR_GP_REG_NO_POWER_SAVE (0x00000000)
378#define CSR_GP_REG_MAC_POWER_SAVE (0x01000000)
379#define CSR_GP_REG_PHY_POWER_SAVE (0x02000000)
380#define CSR_GP_REG_POWER_SAVE_ERROR (0x03000000)
381
382
383/* CSR GIO */
384#define CSR_GIO_REG_VAL_L0S_DISABLED (0x00000002)
385
386/*
387 * UCODE-DRIVER GP (general purpose) mailbox register 1
388 * Host driver and uCode write and/or read this register to communicate with
389 * each other.
390 * Bit fields:
391 * 4: UCODE_DISABLE
392 * Host sets this to request permanent halt of uCode, same as
393 * sending CARD_STATE command with "halt" bit set.
394 * 3: CT_KILL_EXIT
395 * Host sets this to request exit from CT_KILL state, i.e. host thinks
396 * device temperature is low enough to continue normal operation.
397 * 2: CMD_BLOCKED
398 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
399 * to release uCode to clear all Tx and command queues, enter
400 * unassociated mode, and power down.
401 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit.
402 * 1: SW_BIT_RFKILL
403 * Host sets this when issuing CARD_STATE command to request
404 * device sleep.
405 * 0: MAC_SLEEP
406 * uCode sets this when preparing a power-saving power-down.
407 * uCode resets this when power-up is complete and SRAM is sane.
408 * NOTE: device saves internal SRAM data to host when powering down,
409 * and must restore this data after powering back up.
410 * MAC_SLEEP is the best indication that restore is complete.
411 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
412 * do not need to save/restore it.
413 */
414#define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
415#define CSR_UCODE_SW_BIT_RFKILL (0x00000002)
416#define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
417#define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
418#define CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020)
419
420/* GP Driver */
421#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003)
422#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000)
423#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001)
424#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002)
425#define CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004)
426#define CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008)
427
428#define CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080)
429
430/* GIO Chicken Bits (PCI Express bus link power management) */
431#define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
432#define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
433
434/* LED */
435#define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
436#define CSR_LED_REG_TURN_ON (0x60)
437#define CSR_LED_REG_TURN_OFF (0x20)
438
439/* ANA_PLL */
440#define CSR50_ANA_PLL_CFG_VAL (0x00880300)
441
442/* HPET MEM debug */
443#define CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000)
444
445/* DRAM INT TABLE */
446#define CSR_DRAM_INT_TBL_ENABLE (1 << 31)
447#define CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28)
448#define CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27)
449
450/*
451 * SHR target access (Shared block memory space)
452 *
453 * Shared internal registers can be accessed directly from PCI bus through SHR
454 * arbiter without need for the MAC HW to be powered up. This is possible due to
455 * indirect read/write via HEEP_CTRL_WRD_PCIEX_CTRL (0xEC) and
456 * HEEP_CTRL_WRD_PCIEX_DATA (0xF4) registers.
457 *
458 * Use iwl_write32()/iwl_read32() family to access these registers. The MAC HW
459 * need not be powered up so no "grab inc access" is required.
460 */
461
462/*
463 * Registers for accessing shared registers (e.g. SHR_APMG_GP1,
464 * SHR_APMG_XTAL_CFG). For example, to read from SHR_APMG_GP1 register (0x1DC),
465 * first, write to the control register:
466 * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register)
467 * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 2 (read access)
468 * second, read from the data register HEEP_CTRL_WRD_PCIEX_DATA[31:0].
469 *
470 * To write the register, first, write to the data register
471 * HEEP_CTRL_WRD_PCIEX_DATA[31:0] and then:
472 * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register)
473 * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 3 (write access)
474 */
475#define HEEP_CTRL_WRD_PCIEX_CTRL_REG (CSR_BASE+0x0ec)
476#define HEEP_CTRL_WRD_PCIEX_DATA_REG (CSR_BASE+0x0f4)
477
478/*
479 * HBUS (Host-side Bus)
480 *
481 * HBUS registers are mapped directly into PCI bus space, but are used
482 * to indirectly access device's internal memory or registers that
483 * may be powered-down.
484 *
485 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers;
486 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
487 * to make sure the MAC (uCode processor, etc.) is powered up for accessing
488 * internal resources.
489 *
490 * Do not use iwl_write32()/iwl_read32() family to access these registers;
491 * these provide only simple PCI bus access, without waking up the MAC.
492 */
493#define HBUS_BASE (0x400)
494
495/*
496 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
497 * structures, error log, event log, verifying uCode load).
498 * First write to address register, then read from or write to data register
499 * to complete the job. Once the address register is set up, accesses to
500 * data registers auto-increment the address by one dword.
501 * Bit usage for address registers (read or write):
502 * 0-31: memory address within device
503 */
504#define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c)
505#define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010)
506#define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018)
507#define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c)
508
509/* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */
510#define HBUS_TARG_MBX_C (HBUS_BASE+0x030)
511#define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
512
513/*
514 * Registers for accessing device's internal peripheral registers
515 * (e.g. SCD, BSM, etc.). First write to address register,
516 * then read from or write to data register to complete the job.
517 * Bit usage for address registers (read or write):
518 * 0-15: register address (offset) within device
519 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
520 */
521#define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044)
522#define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048)
523#define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c)
524#define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050)
525
526/* Used to enable DBGM */
527#define HBUS_TARG_TEST_REG (HBUS_BASE+0x05c)
528
529/*
530 * Per-Tx-queue write pointer (index, really!)
531 * Indicates index to next TFD that driver will fill (1 past latest filled).
532 * Bit usage:
533 * 0-7: queue write index
534 * 11-8: queue selector
535 */
536#define HBUS_TARG_WRPTR (HBUS_BASE+0x060)
537/* This register is common for Tx and Rx, Rx queues start from 512 */
538#define HBUS_TARG_WRPTR_Q_SHIFT (16)
539#define HBUS_TARG_WRPTR_RX_Q(q) (((q) + 512) << HBUS_TARG_WRPTR_Q_SHIFT)
540
541/**********************************************************
542 * CSR values
543 **********************************************************/
544 /*
545 * host interrupt timeout value
546 * used with setting interrupt coalescing timer
547 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
548 *
549 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
550 */
551#define IWL_HOST_INT_TIMEOUT_MAX (0xFF)
552#define IWL_HOST_INT_TIMEOUT_DEF (0x40)
553#define IWL_HOST_INT_TIMEOUT_MIN (0x0)
554#define IWL_HOST_INT_OPER_MODE BIT(31)
555
556/*****************************************************************************
557 * 7000/3000 series SHR DTS addresses *
558 *****************************************************************************/
559
560/* Diode Results Register Structure: */
561enum dtd_diode_reg {
562 DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */
563 DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */
564 DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */
565 DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */
566 DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */
567 DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */
568/* Those are the masks INSIDE the flags bit-field: */
569 DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0,
570 DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */
571 DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7,
572 DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */
573};
574
575/*****************************************************************************
576 * MSIX related registers *
577 *****************************************************************************/
578
579#define CSR_MSIX_BASE (0x2000)
580#define CSR_MSIX_FH_INT_CAUSES_AD (CSR_MSIX_BASE + 0x800)
581#define CSR_MSIX_FH_INT_MASK_AD (CSR_MSIX_BASE + 0x804)
582#define CSR_MSIX_HW_INT_CAUSES_AD (CSR_MSIX_BASE + 0x808)
583#define CSR_MSIX_HW_INT_MASK_AD (CSR_MSIX_BASE + 0x80C)
584#define CSR_MSIX_AUTOMASK_ST_AD (CSR_MSIX_BASE + 0x810)
585#define CSR_MSIX_RX_IVAR_AD_REG (CSR_MSIX_BASE + 0x880)
586#define CSR_MSIX_IVAR_AD_REG (CSR_MSIX_BASE + 0x890)
587#define CSR_MSIX_PENDING_PBA_AD (CSR_MSIX_BASE + 0x1000)
588#define CSR_MSIX_RX_IVAR(cause) (CSR_MSIX_RX_IVAR_AD_REG + (cause))
589#define CSR_MSIX_IVAR(cause) (CSR_MSIX_IVAR_AD_REG + (cause))
590
591#define MSIX_FH_INT_CAUSES_Q(q) (q)
592
593/*
594 * Causes for the FH register interrupts
595 */
596enum msix_fh_int_causes {
597 MSIX_FH_INT_CAUSES_Q0 = BIT(0),
598 MSIX_FH_INT_CAUSES_Q1 = BIT(1),
599 MSIX_FH_INT_CAUSES_D2S_CH0_NUM = BIT(16),
600 MSIX_FH_INT_CAUSES_D2S_CH1_NUM = BIT(17),
601 MSIX_FH_INT_CAUSES_S2D = BIT(19),
602 MSIX_FH_INT_CAUSES_FH_ERR = BIT(21),
603};
604
605/* The low 16 bits are for rx data queue indication */
606#define MSIX_FH_INT_CAUSES_DATA_QUEUE 0xffff
607
608/*
609 * Causes for the HW register interrupts
610 */
611enum msix_hw_int_causes {
612 MSIX_HW_INT_CAUSES_REG_ALIVE = BIT(0),
613 MSIX_HW_INT_CAUSES_REG_WAKEUP = BIT(1),
614 MSIX_HW_INT_CAUSES_REG_IML = BIT(1),
615 MSIX_HW_INT_CAUSES_REG_RESET_DONE = BIT(2),
616 MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ = BIT(5),
617 MSIX_HW_INT_CAUSES_REG_CT_KILL = BIT(6),
618 MSIX_HW_INT_CAUSES_REG_RF_KILL = BIT(7),
619 MSIX_HW_INT_CAUSES_REG_PERIODIC = BIT(8),
620 MSIX_HW_INT_CAUSES_REG_SW_ERR = BIT(25),
621 MSIX_HW_INT_CAUSES_REG_SCD = BIT(26),
622 MSIX_HW_INT_CAUSES_REG_FH_TX = BIT(27),
623 MSIX_HW_INT_CAUSES_REG_HW_ERR = BIT(29),
624 MSIX_HW_INT_CAUSES_REG_HAP = BIT(30),
625};
626
627#define MSIX_MIN_INTERRUPT_VECTORS 2
628#define MSIX_AUTO_CLEAR_CAUSE 0
629#define MSIX_NON_AUTO_CLEAR_CAUSE BIT(7)
630
631/*****************************************************************************
632 * HW address related registers *
633 *****************************************************************************/
634
635#define CSR_ADDR_BASE(trans) ((trans)->cfg->mac_addr_from_csr)
636#define CSR_MAC_ADDR0_OTP(trans) (CSR_ADDR_BASE(trans) + 0x00)
637#define CSR_MAC_ADDR1_OTP(trans) (CSR_ADDR_BASE(trans) + 0x04)
638#define CSR_MAC_ADDR0_STRAP(trans) (CSR_ADDR_BASE(trans) + 0x08)
639#define CSR_MAC_ADDR1_STRAP(trans) (CSR_ADDR_BASE(trans) + 0x0c)
640
641#endif /* !__iwl_csr_h__ */
1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/*
3 * Copyright (C) 2005-2014, 2018-2024 Intel Corporation
4 * Copyright (C) 2013-2014 Intel Mobile Communications GmbH
5 * Copyright (C) 2016 Intel Deutschland GmbH
6 */
7#ifndef __iwl_csr_h__
8#define __iwl_csr_h__
9/*
10 * CSR (control and status registers)
11 *
12 * CSR registers are mapped directly into PCI bus space, and are accessible
13 * whenever platform supplies power to device, even when device is in
14 * low power states due to driver-invoked device resets
15 * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
16 *
17 * Use iwl_write32() and iwl_read32() family to access these registers;
18 * these provide simple PCI bus access, without waking up the MAC.
19 * Do not use iwl_write_direct32() family for these registers;
20 * no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.
21 * The MAC (uCode processor, etc.) does not need to be powered up for accessing
22 * the CSR registers.
23 *
24 * NOTE: Device does need to be awake in order to read this memory
25 * via CSR_EEPROM and CSR_OTP registers
26 */
27#define CSR_BASE (0x000)
28
29#define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
30#define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
31#define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
32#define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
33#define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/
34#define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
35#define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
36#define CSR_GP_CNTRL (CSR_BASE+0x024)
37#define CSR_FUNC_SCRATCH (CSR_BASE+0x02c) /* Scratch register - used for FW dbg */
38
39/* 2nd byte of CSR_INT_COALESCING, not accessible via iwl_write32()! */
40#define CSR_INT_PERIODIC_REG (CSR_BASE+0x005)
41
42/*
43 * Hardware revision info
44 * Bit fields:
45 * 31-16: Reserved
46 * 15-4: Type of device: see CSR_HW_REV_TYPE_xxx definitions
47 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
48 * 1-0: "Dash" (-) value, as in A-1, etc.
49 */
50#define CSR_HW_REV (CSR_BASE+0x028)
51
52/*
53 * RF ID revision info
54 * Bit fields:
55 * 31:24: Reserved (set to 0x0)
56 * 23:12: Type
57 * 11:8: Step (A - 0x0, B - 0x1, etc)
58 * 7:4: Dash
59 * 3:0: Flavor
60 */
61#define CSR_HW_RF_ID (CSR_BASE+0x09c)
62
63/*
64 * EEPROM and OTP (one-time-programmable) memory reads
65 *
66 * NOTE: Device must be awake, initialized via apm_ops.init(),
67 * in order to read.
68 */
69#define CSR_EEPROM_REG (CSR_BASE+0x02c)
70#define CSR_EEPROM_GP (CSR_BASE+0x030)
71#define CSR_OTP_GP_REG (CSR_BASE+0x034)
72
73#define CSR_GIO_REG (CSR_BASE+0x03C)
74#define CSR_GP_UCODE_REG (CSR_BASE+0x048)
75#define CSR_GP_DRIVER_REG (CSR_BASE+0x050)
76
77/*
78 * UCODE-DRIVER GP (general purpose) mailbox registers.
79 * SET/CLR registers set/clear bit(s) if "1" is written.
80 */
81#define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054)
82#define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058)
83#define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
84#define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
85
86#define CSR_MBOX_SET_REG (CSR_BASE + 0x88)
87
88#define CSR_LED_REG (CSR_BASE+0x094)
89#define CSR_DRAM_INT_TBL_REG (CSR_BASE+0x0A0)
90#define CSR_MAC_SHADOW_REG_CTRL (CSR_BASE + 0x0A8) /* 6000 and up */
91#define CSR_MAC_SHADOW_REG_CTRL_RX_WAKE BIT(20)
92#define CSR_MAC_SHADOW_REG_CTL2 (CSR_BASE + 0x0AC)
93#define CSR_MAC_SHADOW_REG_CTL2_RX_WAKE 0xFFFF
94
95/* LTR control (since IWL_DEVICE_FAMILY_22000) */
96#define CSR_LTR_LONG_VAL_AD (CSR_BASE + 0x0D4)
97#define CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ 0x80000000
98#define CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE 0x1c000000
99#define CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL 0x03ff0000
100#define CSR_LTR_LONG_VAL_AD_SNOOP_REQ 0x00008000
101#define CSR_LTR_LONG_VAL_AD_SNOOP_SCALE 0x00001c00
102#define CSR_LTR_LONG_VAL_AD_SNOOP_VAL 0x000003ff
103#define CSR_LTR_LONG_VAL_AD_SCALE_USEC 2
104
105#define CSR_LTR_LAST_MSG (CSR_BASE + 0x0DC)
106
107/* GIO Chicken Bits (PCI Express bus link power management) */
108#define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
109
110#define CSR_IPC_SLEEP_CONTROL (CSR_BASE + 0x114)
111#define CSR_IPC_SLEEP_CONTROL_SUSPEND 0x3
112#define CSR_IPC_SLEEP_CONTROL_RESUME 0
113
114/* Doorbell - since Bz
115 * connected to UREG_DOORBELL_TO_ISR6 (lower 16 bits only)
116 */
117#define CSR_DOORBELL_VECTOR (CSR_BASE + 0x130)
118
119/* host chicken bits */
120#define CSR_HOST_CHICKEN (CSR_BASE + 0x204)
121#define CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME BIT(19)
122
123/* Analog phase-lock-loop configuration */
124#define CSR_ANA_PLL_CFG (CSR_BASE+0x20c)
125
126/*
127 * CSR HW resources monitor registers
128 */
129#define CSR_MONITOR_CFG_REG (CSR_BASE+0x214)
130#define CSR_MONITOR_STATUS_REG (CSR_BASE+0x228)
131#define CSR_MONITOR_XTAL_RESOURCES (0x00000010)
132
133/*
134 * CSR Hardware Revision Workaround Register. Indicates hardware rev;
135 * "step" determines CCK backoff for txpower calculation.
136 * See also CSR_HW_REV register.
137 * Bit fields:
138 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
139 * 1-0: "Dash" (-) value, as in C-1, etc.
140 */
141#define CSR_HW_REV_WA_REG (CSR_BASE+0x22C)
142
143#define CSR_DBG_HPET_MEM_REG (CSR_BASE+0x240)
144#define CSR_DBG_LINK_PWR_MGMT_REG (CSR_BASE+0x250)
145
146/*
147 * Scratch register initial configuration - this is set on init, and read
148 * during a error FW error.
149 */
150#define CSR_FUNC_SCRATCH_INIT_VALUE (0x01010101)
151
152/* Bits for CSR_HW_IF_CONFIG_REG */
153#define CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP_DASH (0x0000000F)
154#define CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM (0x00000080)
155#define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0)
156#define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
157#define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
158#define CSR_HW_IF_CONFIG_REG_D3_DEBUG (0x00000200)
159#define CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00)
160#define CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000)
161#define CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000)
162
163#define CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0)
164#define CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2)
165#define CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6)
166#define CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10)
167#define CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12)
168#define CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14)
169
170#define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000)
171#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
172#define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */
173#define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
174#define CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */
175#define CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000)
176#define CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */
177
178#define CSR_MBOX_SET_REG_OS_ALIVE BIT(5)
179
180#define CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/
181#define CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/
182
183/* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
184 * acknowledged (reset) by host writing "1" to flagged bits. */
185#define CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
186#define CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */
187#define CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */
188#define CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
189#define CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */
190#define CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */
191#define CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */
192#define CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */
193#define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */
194#define CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */
195#define CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */
196
197#define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \
198 CSR_INT_BIT_HW_ERR | \
199 CSR_INT_BIT_FH_TX | \
200 CSR_INT_BIT_SW_ERR | \
201 CSR_INT_BIT_RF_KILL | \
202 CSR_INT_BIT_SW_RX | \
203 CSR_INT_BIT_WAKEUP | \
204 CSR_INT_BIT_ALIVE | \
205 CSR_INT_BIT_RX_PERIODIC)
206
207/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
208#define CSR_FH_INT_BIT_ERR (1 << 31) /* Error */
209#define CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
210#define CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
211#define CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
212#define CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */
213#define CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
214
215#define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \
216 CSR_FH_INT_BIT_RX_CHNL1 | \
217 CSR_FH_INT_BIT_RX_CHNL0)
218
219#define CSR_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 | \
220 CSR_FH_INT_BIT_TX_CHNL0)
221
222/* GPIO */
223#define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
224#define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
225#define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200)
226
227/* RESET */
228#define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
229#define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
230#define CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
231#define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
232#define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
233#define CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000)
234
235/*
236 * GP (general purpose) CONTROL REGISTER
237 * Bit fields:
238 * 27: HW_RF_KILL_SW
239 * Indicates state of (platform's) hardware RF-Kill switch
240 * 26-24: POWER_SAVE_TYPE
241 * Indicates current power-saving mode:
242 * 000 -- No power saving
243 * 001 -- MAC power-down
244 * 010 -- PHY (radio) power-down
245 * 011 -- Error
246 * 10: XTAL ON request
247 * 9-6: SYS_CONFIG
248 * Indicates current system configuration, reflecting pins on chip
249 * as forced high/low by device circuit board.
250 * 4: GOING_TO_SLEEP
251 * Indicates MAC is entering a power-saving sleep power-down.
252 * Not a good time to access device-internal resources.
253 * 3: MAC_ACCESS_REQ
254 * Host sets this to request and maintain MAC wakeup, to allow host
255 * access to device-internal resources. Host must wait for
256 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
257 * device registers.
258 * 2: INIT_DONE
259 * Host sets this to put device into fully operational D0 power mode.
260 * Host resets this after SW_RESET to put device into low power mode.
261 * 0: MAC_CLOCK_READY
262 * Indicates MAC (ucode processor, etc.) is powered up and can run.
263 * Internal resources are accessible.
264 * NOTE: This does not indicate that the processor is actually running.
265 * NOTE: This does not indicate that device has completed
266 * init or post-power-down restore of internal SRAM memory.
267 * Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
268 * SRAM is restored and uCode is in normal operation mode.
269 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
270 * do not need to save/restore it.
271 * NOTE: After device reset, this bit remains "0" until host sets
272 * INIT_DONE
273 */
274#define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
275#define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
276#define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
277#define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
278#define CSR_GP_CNTRL_REG_FLAG_XTAL_ON (0x00000400)
279
280#define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
281
282#define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
283#define CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN (0x04000000)
284#define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
285
286/* From Bz we use these instead during init/reset flow */
287#define CSR_GP_CNTRL_REG_FLAG_MAC_INIT BIT(6)
288#define CSR_GP_CNTRL_REG_FLAG_ROM_START BIT(7)
289#define CSR_GP_CNTRL_REG_FLAG_MAC_STATUS BIT(20)
290#define CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ BIT(21)
291#define CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS BIT(28)
292#define CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ BIT(29)
293#define CSR_GP_CNTRL_REG_FLAG_SW_RESET BIT(31)
294
295/* HW REV */
296#define CSR_HW_REV_STEP_DASH(_val) ((_val) & CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP_DASH)
297#define CSR_HW_REV_TYPE(_val) (((_val) & 0x000FFF0) >> 4)
298
299/* HW RFID */
300#define CSR_HW_RFID_FLAVOR(_val) (((_val) & 0x000000F) >> 0)
301#define CSR_HW_RFID_DASH(_val) (((_val) & 0x00000F0) >> 4)
302#define CSR_HW_RFID_STEP(_val) (((_val) & 0x0000F00) >> 8)
303#define CSR_HW_RFID_TYPE(_val) (((_val) & 0x0FFF000) >> 12)
304#define CSR_HW_RFID_IS_CDB(_val) (((_val) & 0x10000000) >> 28)
305#define CSR_HW_RFID_IS_JACKET(_val) (((_val) & 0x20000000) >> 29)
306
307/* hw_rev values */
308enum {
309 SILICON_A_STEP = 0,
310 SILICON_B_STEP,
311 SILICON_C_STEP,
312 SILICON_D_STEP,
313 SILICON_E_STEP,
314 SILICON_TC_STEP = 0xe,
315 SILICON_Z_STEP = 0xf,
316};
317
318
319#define CSR_HW_REV_TYPE_MSK (0x000FFF0)
320#define CSR_HW_REV_TYPE_5300 (0x0000020)
321#define CSR_HW_REV_TYPE_5350 (0x0000030)
322#define CSR_HW_REV_TYPE_5100 (0x0000050)
323#define CSR_HW_REV_TYPE_5150 (0x0000040)
324#define CSR_HW_REV_TYPE_1000 (0x0000060)
325#define CSR_HW_REV_TYPE_6x00 (0x0000070)
326#define CSR_HW_REV_TYPE_6x50 (0x0000080)
327#define CSR_HW_REV_TYPE_6150 (0x0000084)
328#define CSR_HW_REV_TYPE_6x05 (0x00000B0)
329#define CSR_HW_REV_TYPE_6x30 CSR_HW_REV_TYPE_6x05
330#define CSR_HW_REV_TYPE_6x35 CSR_HW_REV_TYPE_6x05
331#define CSR_HW_REV_TYPE_2x30 (0x00000C0)
332#define CSR_HW_REV_TYPE_2x00 (0x0000100)
333#define CSR_HW_REV_TYPE_105 (0x0000110)
334#define CSR_HW_REV_TYPE_135 (0x0000120)
335#define CSR_HW_REV_TYPE_3160 (0x0000164)
336#define CSR_HW_REV_TYPE_7265D (0x0000210)
337#define CSR_HW_REV_TYPE_NONE (0x00001F0)
338#define CSR_HW_REV_TYPE_QNJ (0x0000360)
339#define CSR_HW_REV_TYPE_QNJ_B0 (0x0000361)
340#define CSR_HW_REV_TYPE_QU_B0 (0x0000331)
341#define CSR_HW_REV_TYPE_QU_C0 (0x0000332)
342#define CSR_HW_REV_TYPE_QUZ (0x0000351)
343#define CSR_HW_REV_TYPE_HR_CDB (0x0000340)
344#define CSR_HW_REV_TYPE_SO (0x0000370)
345#define CSR_HW_REV_TYPE_TY (0x0000420)
346
347/* RF_ID value */
348#define CSR_HW_RF_ID_TYPE_JF (0x00105100)
349#define CSR_HW_RF_ID_TYPE_HR (0x0010A000)
350#define CSR_HW_RF_ID_TYPE_HR1 (0x0010c100)
351#define CSR_HW_RF_ID_TYPE_HRCDB (0x00109F00)
352#define CSR_HW_RF_ID_TYPE_GF (0x0010D000)
353#define CSR_HW_RF_ID_TYPE_GF4 (0x0010E000)
354#define CSR_HW_RF_ID_TYPE_MS (0x00111000)
355#define CSR_HW_RF_ID_TYPE_FM (0x00112000)
356#define CSR_HW_RF_ID_TYPE_WP (0x00113000)
357
358/* HW_RF CHIP STEP */
359#define CSR_HW_RF_STEP(_val) (((_val) >> 8) & 0xF)
360
361/* EEPROM REG */
362#define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
363#define CSR_EEPROM_REG_BIT_CMD (0x00000002)
364#define CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC)
365#define CSR_EEPROM_REG_MSK_DATA (0xFFFF0000)
366
367/* EEPROM GP */
368#define CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */
369#define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
370#define CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000)
371#define CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001)
372#define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002)
373#define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004)
374
375/* One-time-programmable memory general purpose reg */
376#define CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */
377#define CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */
378#define CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */
379#define CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */
380
381/* GP REG */
382#define CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */
383#define CSR_GP_REG_NO_POWER_SAVE (0x00000000)
384#define CSR_GP_REG_MAC_POWER_SAVE (0x01000000)
385#define CSR_GP_REG_PHY_POWER_SAVE (0x02000000)
386#define CSR_GP_REG_POWER_SAVE_ERROR (0x03000000)
387
388
389/* CSR GIO */
390#define CSR_GIO_REG_VAL_L0S_DISABLED (0x00000002)
391
392/*
393 * UCODE-DRIVER GP (general purpose) mailbox register 1
394 * Host driver and uCode write and/or read this register to communicate with
395 * each other.
396 * Bit fields:
397 * 4: UCODE_DISABLE
398 * Host sets this to request permanent halt of uCode, same as
399 * sending CARD_STATE command with "halt" bit set.
400 * 3: CT_KILL_EXIT
401 * Host sets this to request exit from CT_KILL state, i.e. host thinks
402 * device temperature is low enough to continue normal operation.
403 * 2: CMD_BLOCKED
404 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
405 * to release uCode to clear all Tx and command queues, enter
406 * unassociated mode, and power down.
407 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit.
408 * 1: SW_BIT_RFKILL
409 * Host sets this when issuing CARD_STATE command to request
410 * device sleep.
411 * 0: MAC_SLEEP
412 * uCode sets this when preparing a power-saving power-down.
413 * uCode resets this when power-up is complete and SRAM is sane.
414 * NOTE: device saves internal SRAM data to host when powering down,
415 * and must restore this data after powering back up.
416 * MAC_SLEEP is the best indication that restore is complete.
417 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
418 * do not need to save/restore it.
419 */
420#define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
421#define CSR_UCODE_SW_BIT_RFKILL (0x00000002)
422#define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
423#define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
424#define CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020)
425
426/* GP Driver */
427#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003)
428#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000)
429#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001)
430#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002)
431#define CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004)
432#define CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008)
433
434#define CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080)
435
436/* GIO Chicken Bits (PCI Express bus link power management) */
437#define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
438#define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
439
440/* LED */
441#define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
442#define CSR_LED_REG_TURN_ON (0x60)
443#define CSR_LED_REG_TURN_OFF (0x20)
444
445/* ANA_PLL */
446#define CSR50_ANA_PLL_CFG_VAL (0x00880300)
447
448/* HPET MEM debug */
449#define CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000)
450
451/* DRAM INT TABLE */
452#define CSR_DRAM_INT_TBL_ENABLE (1 << 31)
453#define CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28)
454#define CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27)
455
456/*
457 * SHR target access (Shared block memory space)
458 *
459 * Shared internal registers can be accessed directly from PCI bus through SHR
460 * arbiter without need for the MAC HW to be powered up. This is possible due to
461 * indirect read/write via HEEP_CTRL_WRD_PCIEX_CTRL (0xEC) and
462 * HEEP_CTRL_WRD_PCIEX_DATA (0xF4) registers.
463 *
464 * Use iwl_write32()/iwl_read32() family to access these registers. The MAC HW
465 * need not be powered up so no "grab inc access" is required.
466 */
467
468/*
469 * Registers for accessing shared registers (e.g. SHR_APMG_GP1,
470 * SHR_APMG_XTAL_CFG). For example, to read from SHR_APMG_GP1 register (0x1DC),
471 * first, write to the control register:
472 * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register)
473 * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 2 (read access)
474 * second, read from the data register HEEP_CTRL_WRD_PCIEX_DATA[31:0].
475 *
476 * To write the register, first, write to the data register
477 * HEEP_CTRL_WRD_PCIEX_DATA[31:0] and then:
478 * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register)
479 * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 3 (write access)
480 */
481#define HEEP_CTRL_WRD_PCIEX_CTRL_REG (CSR_BASE+0x0ec)
482#define HEEP_CTRL_WRD_PCIEX_DATA_REG (CSR_BASE+0x0f4)
483
484/*
485 * HBUS (Host-side Bus)
486 *
487 * HBUS registers are mapped directly into PCI bus space, but are used
488 * to indirectly access device's internal memory or registers that
489 * may be powered-down.
490 *
491 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers;
492 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
493 * to make sure the MAC (uCode processor, etc.) is powered up for accessing
494 * internal resources.
495 *
496 * Do not use iwl_write32()/iwl_read32() family to access these registers;
497 * these provide only simple PCI bus access, without waking up the MAC.
498 */
499#define HBUS_BASE (0x400)
500
501/*
502 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
503 * structures, error log, event log, verifying uCode load).
504 * First write to address register, then read from or write to data register
505 * to complete the job. Once the address register is set up, accesses to
506 * data registers auto-increment the address by one dword.
507 * Bit usage for address registers (read or write):
508 * 0-31: memory address within device
509 */
510#define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c)
511#define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010)
512#define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018)
513#define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c)
514
515/* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */
516#define HBUS_TARG_MBX_C (HBUS_BASE+0x030)
517#define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
518
519/*
520 * Registers for accessing device's internal peripheral registers
521 * (e.g. SCD, BSM, etc.). First write to address register,
522 * then read from or write to data register to complete the job.
523 * Bit usage for address registers (read or write):
524 * 0-15: register address (offset) within device
525 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
526 */
527#define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044)
528#define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048)
529#define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c)
530#define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050)
531
532/* Used to enable DBGM */
533#define HBUS_TARG_TEST_REG (HBUS_BASE+0x05c)
534
535/*
536 * Per-Tx-queue write pointer (index, really!)
537 * Indicates index to next TFD that driver will fill (1 past latest filled).
538 * Bit usage:
539 * 0-7: queue write index
540 * 11-8: queue selector
541 */
542#define HBUS_TARG_WRPTR (HBUS_BASE+0x060)
543/* This register is common for Tx and Rx, Rx queues start from 512 */
544#define HBUS_TARG_WRPTR_Q_SHIFT (16)
545#define HBUS_TARG_WRPTR_RX_Q(q) (((q) + 512) << HBUS_TARG_WRPTR_Q_SHIFT)
546
547/**********************************************************
548 * CSR values
549 **********************************************************/
550 /*
551 * host interrupt timeout value
552 * used with setting interrupt coalescing timer
553 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
554 *
555 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
556 */
557#define IWL_HOST_INT_TIMEOUT_MAX (0xFF)
558#define IWL_HOST_INT_TIMEOUT_DEF (0x40)
559#define IWL_HOST_INT_TIMEOUT_MIN (0x0)
560#define IWL_HOST_INT_OPER_MODE BIT(31)
561
562/*****************************************************************************
563 * 7000/3000 series SHR DTS addresses *
564 *****************************************************************************/
565
566/* Diode Results Register Structure: */
567enum dtd_diode_reg {
568 DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */
569 DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */
570 DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */
571 DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */
572 DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */
573 DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */
574/* Those are the masks INSIDE the flags bit-field: */
575 DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0,
576 DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */
577 DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7,
578 DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */
579};
580
581/*****************************************************************************
582 * MSIX related registers *
583 *****************************************************************************/
584
585#define CSR_MSIX_BASE (0x2000)
586#define CSR_MSIX_FH_INT_CAUSES_AD (CSR_MSIX_BASE + 0x800)
587#define CSR_MSIX_FH_INT_MASK_AD (CSR_MSIX_BASE + 0x804)
588#define CSR_MSIX_HW_INT_CAUSES_AD (CSR_MSIX_BASE + 0x808)
589#define CSR_MSIX_HW_INT_MASK_AD (CSR_MSIX_BASE + 0x80C)
590#define CSR_MSIX_AUTOMASK_ST_AD (CSR_MSIX_BASE + 0x810)
591#define CSR_MSIX_RX_IVAR_AD_REG (CSR_MSIX_BASE + 0x880)
592#define CSR_MSIX_IVAR_AD_REG (CSR_MSIX_BASE + 0x890)
593#define CSR_MSIX_PENDING_PBA_AD (CSR_MSIX_BASE + 0x1000)
594#define CSR_MSIX_RX_IVAR(cause) (CSR_MSIX_RX_IVAR_AD_REG + (cause))
595#define CSR_MSIX_IVAR(cause) (CSR_MSIX_IVAR_AD_REG + (cause))
596
597#define MSIX_FH_INT_CAUSES_Q(q) (q)
598
599/*
600 * Causes for the FH register interrupts
601 */
602enum msix_fh_int_causes {
603 MSIX_FH_INT_CAUSES_Q0 = BIT(0),
604 MSIX_FH_INT_CAUSES_Q1 = BIT(1),
605 MSIX_FH_INT_CAUSES_D2S_CH0_NUM = BIT(16),
606 MSIX_FH_INT_CAUSES_D2S_CH1_NUM = BIT(17),
607 MSIX_FH_INT_CAUSES_S2D = BIT(19),
608 MSIX_FH_INT_CAUSES_FH_ERR = BIT(21),
609};
610
611/* The low 16 bits are for rx data queue indication */
612#define MSIX_FH_INT_CAUSES_DATA_QUEUE 0xffff
613
614/*
615 * Causes for the HW register interrupts
616 */
617enum msix_hw_int_causes {
618 MSIX_HW_INT_CAUSES_REG_ALIVE = BIT(0),
619 MSIX_HW_INT_CAUSES_REG_WAKEUP = BIT(1),
620 MSIX_HW_INT_CAUSES_REG_IML = BIT(1),
621 MSIX_HW_INT_CAUSES_REG_RESET_DONE = BIT(2),
622 MSIX_HW_INT_CAUSES_REG_TOP_FATAL_ERR = BIT(3),
623 MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ = BIT(5),
624 MSIX_HW_INT_CAUSES_REG_CT_KILL = BIT(6),
625 MSIX_HW_INT_CAUSES_REG_RF_KILL = BIT(7),
626 MSIX_HW_INT_CAUSES_REG_PERIODIC = BIT(8),
627 MSIX_HW_INT_CAUSES_REG_SW_ERR = BIT(25),
628 MSIX_HW_INT_CAUSES_REG_SCD = BIT(26),
629 MSIX_HW_INT_CAUSES_REG_FH_TX = BIT(27),
630 MSIX_HW_INT_CAUSES_REG_HW_ERR = BIT(29),
631 MSIX_HW_INT_CAUSES_REG_HAP = BIT(30),
632};
633
634#define MSIX_MIN_INTERRUPT_VECTORS 2
635#define MSIX_AUTO_CLEAR_CAUSE 0
636#define MSIX_NON_AUTO_CLEAR_CAUSE BIT(7)
637
638/*****************************************************************************
639 * HW address related registers *
640 *****************************************************************************/
641
642#define CSR_ADDR_BASE(trans) ((trans)->cfg->mac_addr_from_csr)
643#define CSR_MAC_ADDR0_OTP(trans) (CSR_ADDR_BASE(trans) + 0x00)
644#define CSR_MAC_ADDR1_OTP(trans) (CSR_ADDR_BASE(trans) + 0x04)
645#define CSR_MAC_ADDR0_STRAP(trans) (CSR_ADDR_BASE(trans) + 0x08)
646#define CSR_MAC_ADDR1_STRAP(trans) (CSR_ADDR_BASE(trans) + 0x0c)
647
648#endif /* !__iwl_csr_h__ */