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1// SPDX-License-Identifier: GPL-2.0-only
2/* linux/drivers/mmc/host/sdhci-s3c.c
3 *
4 * Copyright 2008 Openmoko Inc.
5 * Copyright 2008 Simtec Electronics
6 * Ben Dooks <ben@simtec.co.uk>
7 * http://armlinux.simtec.co.uk/
8 *
9 * SDHCI (HSMMC) support for Samsung SoC
10 */
11
12#include <linux/spinlock.h>
13#include <linux/delay.h>
14#include <linux/dma-mapping.h>
15#include <linux/platform_device.h>
16#include <linux/platform_data/mmc-sdhci-s3c.h>
17#include <linux/slab.h>
18#include <linux/clk.h>
19#include <linux/io.h>
20#include <linux/gpio.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/of_device.h>
24#include <linux/of_gpio.h>
25#include <linux/pm.h>
26#include <linux/pm_runtime.h>
27
28#include <linux/mmc/host.h>
29
30#include "sdhci.h"
31
32#define MAX_BUS_CLK (4)
33
34#define S3C_SDHCI_CONTROL2 (0x80)
35#define S3C_SDHCI_CONTROL3 (0x84)
36#define S3C64XX_SDHCI_CONTROL4 (0x8C)
37
38#define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR BIT(31)
39#define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK BIT(30)
40#define S3C_SDHCI_CTRL2_CDINVRXD3 BIT(29)
41#define S3C_SDHCI_CTRL2_SLCARDOUT BIT(28)
42
43#define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24)
44#define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT (24)
45#define S3C_SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24)
46
47#define S3C_SDHCI_CTRL2_LVLDAT_MASK (0xff << 16)
48#define S3C_SDHCI_CTRL2_LVLDAT_SHIFT (16)
49#define S3C_SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16)
50
51#define S3C_SDHCI_CTRL2_ENFBCLKTX BIT(15)
52#define S3C_SDHCI_CTRL2_ENFBCLKRX BIT(14)
53#define S3C_SDHCI_CTRL2_SDCDSEL BIT(13)
54#define S3C_SDHCI_CTRL2_SDSIGPC BIT(12)
55#define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART BIT(11)
56
57#define S3C_SDHCI_CTRL2_DFCNT_MASK (0x3 << 9)
58#define S3C_SDHCI_CTRL2_DFCNT_SHIFT (9)
59#define S3C_SDHCI_CTRL2_DFCNT_NONE (0x0 << 9)
60#define S3C_SDHCI_CTRL2_DFCNT_4SDCLK (0x1 << 9)
61#define S3C_SDHCI_CTRL2_DFCNT_16SDCLK (0x2 << 9)
62#define S3C_SDHCI_CTRL2_DFCNT_64SDCLK (0x3 << 9)
63
64#define S3C_SDHCI_CTRL2_ENCLKOUTHOLD BIT(8)
65#define S3C_SDHCI_CTRL2_RWAITMODE BIT(7)
66#define S3C_SDHCI_CTRL2_DISBUFRD BIT(6)
67
68#define S3C_SDHCI_CTRL2_SELBASECLK_MASK (0x3 << 4)
69#define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT (4)
70#define S3C_SDHCI_CTRL2_PWRSYNC BIT(3)
71#define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON BIT(1)
72#define S3C_SDHCI_CTRL2_HWINITFIN BIT(0)
73
74#define S3C_SDHCI_CTRL3_FCSEL3 BIT(31)
75#define S3C_SDHCI_CTRL3_FCSEL2 BIT(23)
76#define S3C_SDHCI_CTRL3_FCSEL1 BIT(15)
77#define S3C_SDHCI_CTRL3_FCSEL0 BIT(7)
78
79#define S3C_SDHCI_CTRL3_FIA3_MASK (0x7f << 24)
80#define S3C_SDHCI_CTRL3_FIA3_SHIFT (24)
81#define S3C_SDHCI_CTRL3_FIA3(_x) ((_x) << 24)
82
83#define S3C_SDHCI_CTRL3_FIA2_MASK (0x7f << 16)
84#define S3C_SDHCI_CTRL3_FIA2_SHIFT (16)
85#define S3C_SDHCI_CTRL3_FIA2(_x) ((_x) << 16)
86
87#define S3C_SDHCI_CTRL3_FIA1_MASK (0x7f << 8)
88#define S3C_SDHCI_CTRL3_FIA1_SHIFT (8)
89#define S3C_SDHCI_CTRL3_FIA1(_x) ((_x) << 8)
90
91#define S3C_SDHCI_CTRL3_FIA0_MASK (0x7f << 0)
92#define S3C_SDHCI_CTRL3_FIA0_SHIFT (0)
93#define S3C_SDHCI_CTRL3_FIA0(_x) ((_x) << 0)
94
95#define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK (0x3 << 16)
96#define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT (16)
97#define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA (0x0 << 16)
98#define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA (0x1 << 16)
99#define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA (0x2 << 16)
100#define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA (0x3 << 16)
101
102#define S3C64XX_SDHCI_CONTROL4_BUSY (1)
103
104/**
105 * struct sdhci_s3c - S3C SDHCI instance
106 * @host: The SDHCI host created
107 * @pdev: The platform device we where created from.
108 * @ioarea: The resource created when we claimed the IO area.
109 * @pdata: The platform data for this controller.
110 * @cur_clk: The index of the current bus clock.
111 * @ext_cd_irq: External card detect interrupt.
112 * @clk_io: The clock for the internal bus interface.
113 * @clk_rates: Clock frequencies.
114 * @clk_bus: The clocks that are available for the SD/MMC bus clock.
115 * @no_divider: No or non-standard internal clock divider.
116 */
117struct sdhci_s3c {
118 struct sdhci_host *host;
119 struct platform_device *pdev;
120 struct resource *ioarea;
121 struct s3c_sdhci_platdata *pdata;
122 int cur_clk;
123 int ext_cd_irq;
124
125 struct clk *clk_io;
126 struct clk *clk_bus[MAX_BUS_CLK];
127 unsigned long clk_rates[MAX_BUS_CLK];
128
129 bool no_divider;
130};
131
132/**
133 * struct sdhci_s3c_drv_data - S3C SDHCI platform specific driver data
134 * @sdhci_quirks: sdhci host specific quirks.
135 * @no_divider: no or non-standard internal clock divider.
136 *
137 * Specifies platform specific configuration of sdhci controller.
138 * Note: A structure for driver specific platform data is used for future
139 * expansion of its usage.
140 */
141struct sdhci_s3c_drv_data {
142 unsigned int sdhci_quirks;
143 bool no_divider;
144};
145
146static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
147{
148 return sdhci_priv(host);
149}
150
151/**
152 * sdhci_s3c_get_max_clk - callback to get maximum clock frequency.
153 * @host: The SDHCI host instance.
154 *
155 * Callback to return the maximum clock rate acheivable by the controller.
156*/
157static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
158{
159 struct sdhci_s3c *ourhost = to_s3c(host);
160 unsigned long rate, max = 0;
161 int src;
162
163 for (src = 0; src < MAX_BUS_CLK; src++) {
164 rate = ourhost->clk_rates[src];
165 if (rate > max)
166 max = rate;
167 }
168
169 return max;
170}
171
172/**
173 * sdhci_s3c_consider_clock - consider one the bus clocks for current setting
174 * @ourhost: Our SDHCI instance.
175 * @src: The source clock index.
176 * @wanted: The clock frequency wanted.
177 */
178static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
179 unsigned int src,
180 unsigned int wanted)
181{
182 unsigned long rate;
183 struct clk *clksrc = ourhost->clk_bus[src];
184 int shift;
185
186 if (IS_ERR(clksrc))
187 return UINT_MAX;
188
189 /*
190 * If controller uses a non-standard clock division, find the best clock
191 * speed possible with selected clock source and skip the division.
192 */
193 if (ourhost->no_divider) {
194 rate = clk_round_rate(clksrc, wanted);
195 return wanted - rate;
196 }
197
198 rate = ourhost->clk_rates[src];
199
200 for (shift = 0; shift <= 8; ++shift) {
201 if ((rate >> shift) <= wanted)
202 break;
203 }
204
205 if (shift > 8) {
206 dev_dbg(&ourhost->pdev->dev,
207 "clk %d: rate %ld, min rate %lu > wanted %u\n",
208 src, rate, rate / 256, wanted);
209 return UINT_MAX;
210 }
211
212 dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n",
213 src, rate, wanted, rate >> shift);
214
215 return wanted - (rate >> shift);
216}
217
218/**
219 * sdhci_s3c_set_clock - callback on clock change
220 * @host: The SDHCI host being changed
221 * @clock: The clock rate being requested.
222 *
223 * When the card's clock is going to be changed, look at the new frequency
224 * and find the best clock source to go with it.
225*/
226static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
227{
228 struct sdhci_s3c *ourhost = to_s3c(host);
229 unsigned int best = UINT_MAX;
230 unsigned int delta;
231 int best_src = 0;
232 int src;
233 u32 ctrl;
234
235 host->mmc->actual_clock = 0;
236
237 /* don't bother if the clock is going off. */
238 if (clock == 0) {
239 sdhci_set_clock(host, clock);
240 return;
241 }
242
243 for (src = 0; src < MAX_BUS_CLK; src++) {
244 delta = sdhci_s3c_consider_clock(ourhost, src, clock);
245 if (delta < best) {
246 best = delta;
247 best_src = src;
248 }
249 }
250
251 dev_dbg(&ourhost->pdev->dev,
252 "selected source %d, clock %d, delta %d\n",
253 best_src, clock, best);
254
255 /* select the new clock source */
256 if (ourhost->cur_clk != best_src) {
257 struct clk *clk = ourhost->clk_bus[best_src];
258
259 clk_prepare_enable(clk);
260 if (ourhost->cur_clk >= 0)
261 clk_disable_unprepare(
262 ourhost->clk_bus[ourhost->cur_clk]);
263
264 ourhost->cur_clk = best_src;
265 host->max_clk = ourhost->clk_rates[best_src];
266 }
267
268 /* turn clock off to card before changing clock source */
269 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
270
271 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
272 ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
273 ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
274 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
275
276 /* reprogram default hardware configuration */
277 writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA,
278 host->ioaddr + S3C64XX_SDHCI_CONTROL4);
279
280 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
281 ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
282 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
283 S3C_SDHCI_CTRL2_ENFBCLKRX |
284 S3C_SDHCI_CTRL2_DFCNT_NONE |
285 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
286 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
287
288 /* reconfigure the controller for new clock rate */
289 ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
290 if (clock < 25 * 1000000)
291 ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2);
292 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3);
293
294 sdhci_set_clock(host, clock);
295}
296
297/**
298 * sdhci_s3c_get_min_clock - callback to get minimal supported clock value
299 * @host: The SDHCI host being queried
300 *
301 * To init mmc host properly a minimal clock value is needed. For high system
302 * bus clock's values the standard formula gives values out of allowed range.
303 * The clock still can be set to lower values, if clock source other then
304 * system bus is selected.
305*/
306static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host)
307{
308 struct sdhci_s3c *ourhost = to_s3c(host);
309 unsigned long rate, min = ULONG_MAX;
310 int src;
311
312 for (src = 0; src < MAX_BUS_CLK; src++) {
313 rate = ourhost->clk_rates[src] / 256;
314 if (!rate)
315 continue;
316 if (rate < min)
317 min = rate;
318 }
319
320 return min;
321}
322
323/* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/
324static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host)
325{
326 struct sdhci_s3c *ourhost = to_s3c(host);
327 unsigned long rate, max = 0;
328 int src;
329
330 for (src = 0; src < MAX_BUS_CLK; src++) {
331 struct clk *clk;
332
333 clk = ourhost->clk_bus[src];
334 if (IS_ERR(clk))
335 continue;
336
337 rate = clk_round_rate(clk, ULONG_MAX);
338 if (rate > max)
339 max = rate;
340 }
341
342 return max;
343}
344
345/* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */
346static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host)
347{
348 struct sdhci_s3c *ourhost = to_s3c(host);
349 unsigned long rate, min = ULONG_MAX;
350 int src;
351
352 for (src = 0; src < MAX_BUS_CLK; src++) {
353 struct clk *clk;
354
355 clk = ourhost->clk_bus[src];
356 if (IS_ERR(clk))
357 continue;
358
359 rate = clk_round_rate(clk, 0);
360 if (rate < min)
361 min = rate;
362 }
363
364 return min;
365}
366
367/* sdhci_cmu_set_clock - callback on clock change.*/
368static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
369{
370 struct sdhci_s3c *ourhost = to_s3c(host);
371 struct device *dev = &ourhost->pdev->dev;
372 unsigned long timeout;
373 u16 clk = 0;
374 int ret;
375
376 host->mmc->actual_clock = 0;
377
378 /* If the clock is going off, set to 0 at clock control register */
379 if (clock == 0) {
380 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
381 return;
382 }
383
384 sdhci_s3c_set_clock(host, clock);
385
386 /* Reset SD Clock Enable */
387 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
388 clk &= ~SDHCI_CLOCK_CARD_EN;
389 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
390
391 ret = clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
392 if (ret != 0) {
393 dev_err(dev, "%s: failed to set clock rate %uHz\n",
394 mmc_hostname(host->mmc), clock);
395 return;
396 }
397
398 clk = SDHCI_CLOCK_INT_EN;
399 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
400
401 /* Wait max 20 ms */
402 timeout = 20;
403 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
404 & SDHCI_CLOCK_INT_STABLE)) {
405 if (timeout == 0) {
406 dev_err(dev, "%s: Internal clock never stabilised.\n",
407 mmc_hostname(host->mmc));
408 return;
409 }
410 timeout--;
411 mdelay(1);
412 }
413
414 clk |= SDHCI_CLOCK_CARD_EN;
415 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
416}
417
418static struct sdhci_ops sdhci_s3c_ops = {
419 .get_max_clock = sdhci_s3c_get_max_clk,
420 .set_clock = sdhci_s3c_set_clock,
421 .get_min_clock = sdhci_s3c_get_min_clock,
422 .set_bus_width = sdhci_set_bus_width,
423 .reset = sdhci_reset,
424 .set_uhs_signaling = sdhci_set_uhs_signaling,
425};
426
427#ifdef CONFIG_OF
428static int sdhci_s3c_parse_dt(struct device *dev,
429 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
430{
431 struct device_node *node = dev->of_node;
432 u32 max_width;
433
434 /* if the bus-width property is not specified, assume width as 1 */
435 if (of_property_read_u32(node, "bus-width", &max_width))
436 max_width = 1;
437 pdata->max_width = max_width;
438
439 /* get the card detection method */
440 if (of_get_property(node, "broken-cd", NULL)) {
441 pdata->cd_type = S3C_SDHCI_CD_NONE;
442 return 0;
443 }
444
445 if (of_get_property(node, "non-removable", NULL)) {
446 pdata->cd_type = S3C_SDHCI_CD_PERMANENT;
447 return 0;
448 }
449
450 if (of_get_named_gpio(node, "cd-gpios", 0))
451 return 0;
452
453 /* assuming internal card detect that will be configured by pinctrl */
454 pdata->cd_type = S3C_SDHCI_CD_INTERNAL;
455 return 0;
456}
457#else
458static int sdhci_s3c_parse_dt(struct device *dev,
459 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
460{
461 return -EINVAL;
462}
463#endif
464
465static inline const struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data(
466 struct platform_device *pdev)
467{
468#ifdef CONFIG_OF
469 if (pdev->dev.of_node)
470 return of_device_get_match_data(&pdev->dev);
471#endif
472 return (const struct sdhci_s3c_drv_data *)
473 platform_get_device_id(pdev)->driver_data;
474}
475
476static int sdhci_s3c_probe(struct platform_device *pdev)
477{
478 struct s3c_sdhci_platdata *pdata;
479 const struct sdhci_s3c_drv_data *drv_data;
480 struct device *dev = &pdev->dev;
481 struct sdhci_host *host;
482 struct sdhci_s3c *sc;
483 int ret, irq, ptr, clks;
484
485 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
486 dev_err(dev, "no device data specified\n");
487 return -ENOENT;
488 }
489
490 irq = platform_get_irq(pdev, 0);
491 if (irq < 0)
492 return irq;
493
494 host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
495 if (IS_ERR(host)) {
496 dev_err(dev, "sdhci_alloc_host() failed\n");
497 return PTR_ERR(host);
498 }
499 sc = sdhci_priv(host);
500
501 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
502 if (!pdata) {
503 ret = -ENOMEM;
504 goto err_pdata_io_clk;
505 }
506
507 if (pdev->dev.of_node) {
508 ret = sdhci_s3c_parse_dt(&pdev->dev, host, pdata);
509 if (ret)
510 goto err_pdata_io_clk;
511 } else {
512 memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata));
513 }
514
515 drv_data = sdhci_s3c_get_driver_data(pdev);
516
517 sc->host = host;
518 sc->pdev = pdev;
519 sc->pdata = pdata;
520 sc->cur_clk = -1;
521
522 platform_set_drvdata(pdev, host);
523
524 sc->clk_io = devm_clk_get(dev, "hsmmc");
525 if (IS_ERR(sc->clk_io)) {
526 dev_err(dev, "failed to get io clock\n");
527 ret = PTR_ERR(sc->clk_io);
528 goto err_pdata_io_clk;
529 }
530
531 /* enable the local io clock and keep it running for the moment. */
532 clk_prepare_enable(sc->clk_io);
533
534 for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
535 char name[14];
536
537 snprintf(name, 14, "mmc_busclk.%d", ptr);
538 sc->clk_bus[ptr] = devm_clk_get(dev, name);
539 if (IS_ERR(sc->clk_bus[ptr]))
540 continue;
541
542 clks++;
543 sc->clk_rates[ptr] = clk_get_rate(sc->clk_bus[ptr]);
544
545 dev_info(dev, "clock source %d: %s (%ld Hz)\n",
546 ptr, name, sc->clk_rates[ptr]);
547 }
548
549 if (clks == 0) {
550 dev_err(dev, "failed to find any bus clocks\n");
551 ret = -ENOENT;
552 goto err_no_busclks;
553 }
554
555 host->ioaddr = devm_platform_ioremap_resource(pdev, 0);
556 if (IS_ERR(host->ioaddr)) {
557 ret = PTR_ERR(host->ioaddr);
558 goto err_req_regs;
559 }
560
561 /* Ensure we have minimal gpio selected CMD/CLK/Detect */
562 if (pdata->cfg_gpio)
563 pdata->cfg_gpio(pdev, pdata->max_width);
564
565 host->hw_name = "samsung-hsmmc";
566 host->ops = &sdhci_s3c_ops;
567 host->quirks = 0;
568 host->quirks2 = 0;
569 host->irq = irq;
570
571 /* Setup quirks for the controller */
572 host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
573 host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
574 if (drv_data) {
575 host->quirks |= drv_data->sdhci_quirks;
576 sc->no_divider = drv_data->no_divider;
577 }
578
579#ifndef CONFIG_MMC_SDHCI_S3C_DMA
580
581 /* we currently see overruns on errors, so disable the SDMA
582 * support as well. */
583 host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
584
585#endif /* CONFIG_MMC_SDHCI_S3C_DMA */
586
587 /* It seems we do not get an DATA transfer complete on non-busy
588 * transfers, not sure if this is a problem with this specific
589 * SDHCI block, or a missing configuration that needs to be set. */
590 host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
591
592 /* This host supports the Auto CMD12 */
593 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
594
595 /* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */
596 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC;
597
598 if (pdata->cd_type == S3C_SDHCI_CD_NONE ||
599 pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
600 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
601
602 if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
603 host->mmc->caps = MMC_CAP_NONREMOVABLE;
604
605 switch (pdata->max_width) {
606 case 8:
607 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
608 fallthrough;
609 case 4:
610 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
611 break;
612 }
613
614 if (pdata->pm_caps)
615 host->mmc->pm_caps |= pdata->pm_caps;
616
617 host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
618 SDHCI_QUIRK_32BIT_DMA_SIZE);
619
620 /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */
621 host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
622
623 /*
624 * If controller does not have internal clock divider,
625 * we can use overriding functions instead of default.
626 */
627 if (sc->no_divider) {
628 sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock;
629 sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock;
630 sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock;
631 }
632
633 /* It supports additional host capabilities if needed */
634 if (pdata->host_caps)
635 host->mmc->caps |= pdata->host_caps;
636
637 if (pdata->host_caps2)
638 host->mmc->caps2 |= pdata->host_caps2;
639
640 pm_runtime_enable(&pdev->dev);
641 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
642 pm_runtime_use_autosuspend(&pdev->dev);
643 pm_suspend_ignore_children(&pdev->dev, 1);
644
645 ret = mmc_of_parse(host->mmc);
646 if (ret)
647 goto err_req_regs;
648
649 ret = sdhci_add_host(host);
650 if (ret)
651 goto err_req_regs;
652
653#ifdef CONFIG_PM
654 if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
655 clk_disable_unprepare(sc->clk_io);
656#endif
657 return 0;
658
659 err_req_regs:
660 pm_runtime_disable(&pdev->dev);
661
662 err_no_busclks:
663 clk_disable_unprepare(sc->clk_io);
664
665 err_pdata_io_clk:
666 sdhci_free_host(host);
667
668 return ret;
669}
670
671static int sdhci_s3c_remove(struct platform_device *pdev)
672{
673 struct sdhci_host *host = platform_get_drvdata(pdev);
674 struct sdhci_s3c *sc = sdhci_priv(host);
675
676 if (sc->ext_cd_irq)
677 free_irq(sc->ext_cd_irq, sc);
678
679#ifdef CONFIG_PM
680 if (sc->pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
681 clk_prepare_enable(sc->clk_io);
682#endif
683 sdhci_remove_host(host, 1);
684
685 pm_runtime_dont_use_autosuspend(&pdev->dev);
686 pm_runtime_disable(&pdev->dev);
687
688 clk_disable_unprepare(sc->clk_io);
689
690 sdhci_free_host(host);
691
692 return 0;
693}
694
695#ifdef CONFIG_PM_SLEEP
696static int sdhci_s3c_suspend(struct device *dev)
697{
698 struct sdhci_host *host = dev_get_drvdata(dev);
699
700 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
701 mmc_retune_needed(host->mmc);
702
703 return sdhci_suspend_host(host);
704}
705
706static int sdhci_s3c_resume(struct device *dev)
707{
708 struct sdhci_host *host = dev_get_drvdata(dev);
709
710 return sdhci_resume_host(host);
711}
712#endif
713
714#ifdef CONFIG_PM
715static int sdhci_s3c_runtime_suspend(struct device *dev)
716{
717 struct sdhci_host *host = dev_get_drvdata(dev);
718 struct sdhci_s3c *ourhost = to_s3c(host);
719 struct clk *busclk = ourhost->clk_io;
720 int ret;
721
722 ret = sdhci_runtime_suspend_host(host);
723
724 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
725 mmc_retune_needed(host->mmc);
726
727 if (ourhost->cur_clk >= 0)
728 clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]);
729 clk_disable_unprepare(busclk);
730 return ret;
731}
732
733static int sdhci_s3c_runtime_resume(struct device *dev)
734{
735 struct sdhci_host *host = dev_get_drvdata(dev);
736 struct sdhci_s3c *ourhost = to_s3c(host);
737 struct clk *busclk = ourhost->clk_io;
738 int ret;
739
740 clk_prepare_enable(busclk);
741 if (ourhost->cur_clk >= 0)
742 clk_prepare_enable(ourhost->clk_bus[ourhost->cur_clk]);
743 ret = sdhci_runtime_resume_host(host, 0);
744 return ret;
745}
746#endif
747
748static const struct dev_pm_ops sdhci_s3c_pmops = {
749 SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume)
750 SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume,
751 NULL)
752};
753
754static const struct platform_device_id sdhci_s3c_driver_ids[] = {
755 {
756 .name = "s3c-sdhci",
757 .driver_data = (kernel_ulong_t)NULL,
758 },
759 { }
760};
761MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids);
762
763#ifdef CONFIG_OF
764static const struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = {
765 .no_divider = true,
766};
767
768static const struct of_device_id sdhci_s3c_dt_match[] = {
769 { .compatible = "samsung,s3c6410-sdhci", },
770 { .compatible = "samsung,exynos4210-sdhci",
771 .data = &exynos4_sdhci_drv_data },
772 {},
773};
774MODULE_DEVICE_TABLE(of, sdhci_s3c_dt_match);
775#endif
776
777static struct platform_driver sdhci_s3c_driver = {
778 .probe = sdhci_s3c_probe,
779 .remove = sdhci_s3c_remove,
780 .id_table = sdhci_s3c_driver_ids,
781 .driver = {
782 .name = "s3c-sdhci",
783 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
784 .of_match_table = of_match_ptr(sdhci_s3c_dt_match),
785 .pm = &sdhci_s3c_pmops,
786 },
787};
788
789module_platform_driver(sdhci_s3c_driver);
790
791MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
792MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
793MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/* linux/drivers/mmc/host/sdhci-s3c.c
3 *
4 * Copyright 2008 Openmoko Inc.
5 * Copyright 2008 Simtec Electronics
6 * Ben Dooks <ben@simtec.co.uk>
7 * http://armlinux.simtec.co.uk/
8 *
9 * SDHCI (HSMMC) support for Samsung SoC
10 */
11
12#include <linux/spinlock.h>
13#include <linux/delay.h>
14#include <linux/dma-mapping.h>
15#include <linux/platform_device.h>
16#include <linux/platform_data/mmc-sdhci-s3c.h>
17#include <linux/slab.h>
18#include <linux/clk.h>
19#include <linux/io.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/pm.h>
23#include <linux/pm_runtime.h>
24
25#include <linux/mmc/host.h>
26
27#include "sdhci.h"
28
29#define MAX_BUS_CLK (4)
30
31#define S3C_SDHCI_CONTROL2 (0x80)
32#define S3C_SDHCI_CONTROL3 (0x84)
33#define S3C64XX_SDHCI_CONTROL4 (0x8C)
34
35#define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR BIT(31)
36#define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK BIT(30)
37#define S3C_SDHCI_CTRL2_CDINVRXD3 BIT(29)
38#define S3C_SDHCI_CTRL2_SLCARDOUT BIT(28)
39
40#define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24)
41#define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT (24)
42#define S3C_SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24)
43
44#define S3C_SDHCI_CTRL2_LVLDAT_MASK (0xff << 16)
45#define S3C_SDHCI_CTRL2_LVLDAT_SHIFT (16)
46#define S3C_SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16)
47
48#define S3C_SDHCI_CTRL2_ENFBCLKTX BIT(15)
49#define S3C_SDHCI_CTRL2_ENFBCLKRX BIT(14)
50#define S3C_SDHCI_CTRL2_SDCDSEL BIT(13)
51#define S3C_SDHCI_CTRL2_SDSIGPC BIT(12)
52#define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART BIT(11)
53
54#define S3C_SDHCI_CTRL2_DFCNT_MASK (0x3 << 9)
55#define S3C_SDHCI_CTRL2_DFCNT_SHIFT (9)
56#define S3C_SDHCI_CTRL2_DFCNT_NONE (0x0 << 9)
57#define S3C_SDHCI_CTRL2_DFCNT_4SDCLK (0x1 << 9)
58#define S3C_SDHCI_CTRL2_DFCNT_16SDCLK (0x2 << 9)
59#define S3C_SDHCI_CTRL2_DFCNT_64SDCLK (0x3 << 9)
60
61#define S3C_SDHCI_CTRL2_ENCLKOUTHOLD BIT(8)
62#define S3C_SDHCI_CTRL2_RWAITMODE BIT(7)
63#define S3C_SDHCI_CTRL2_DISBUFRD BIT(6)
64
65#define S3C_SDHCI_CTRL2_SELBASECLK_MASK (0x3 << 4)
66#define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT (4)
67#define S3C_SDHCI_CTRL2_PWRSYNC BIT(3)
68#define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON BIT(1)
69#define S3C_SDHCI_CTRL2_HWINITFIN BIT(0)
70
71#define S3C_SDHCI_CTRL3_FCSEL3 BIT(31)
72#define S3C_SDHCI_CTRL3_FCSEL2 BIT(23)
73#define S3C_SDHCI_CTRL3_FCSEL1 BIT(15)
74#define S3C_SDHCI_CTRL3_FCSEL0 BIT(7)
75
76#define S3C_SDHCI_CTRL3_FIA3_MASK (0x7f << 24)
77#define S3C_SDHCI_CTRL3_FIA3_SHIFT (24)
78#define S3C_SDHCI_CTRL3_FIA3(_x) ((_x) << 24)
79
80#define S3C_SDHCI_CTRL3_FIA2_MASK (0x7f << 16)
81#define S3C_SDHCI_CTRL3_FIA2_SHIFT (16)
82#define S3C_SDHCI_CTRL3_FIA2(_x) ((_x) << 16)
83
84#define S3C_SDHCI_CTRL3_FIA1_MASK (0x7f << 8)
85#define S3C_SDHCI_CTRL3_FIA1_SHIFT (8)
86#define S3C_SDHCI_CTRL3_FIA1(_x) ((_x) << 8)
87
88#define S3C_SDHCI_CTRL3_FIA0_MASK (0x7f << 0)
89#define S3C_SDHCI_CTRL3_FIA0_SHIFT (0)
90#define S3C_SDHCI_CTRL3_FIA0(_x) ((_x) << 0)
91
92#define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK (0x3 << 16)
93#define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT (16)
94#define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA (0x0 << 16)
95#define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA (0x1 << 16)
96#define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA (0x2 << 16)
97#define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA (0x3 << 16)
98
99#define S3C64XX_SDHCI_CONTROL4_BUSY (1)
100
101/**
102 * struct sdhci_s3c - S3C SDHCI instance
103 * @host: The SDHCI host created
104 * @pdev: The platform device we where created from.
105 * @ioarea: The resource created when we claimed the IO area.
106 * @pdata: The platform data for this controller.
107 * @cur_clk: The index of the current bus clock.
108 * @ext_cd_irq: External card detect interrupt.
109 * @clk_io: The clock for the internal bus interface.
110 * @clk_rates: Clock frequencies.
111 * @clk_bus: The clocks that are available for the SD/MMC bus clock.
112 * @no_divider: No or non-standard internal clock divider.
113 */
114struct sdhci_s3c {
115 struct sdhci_host *host;
116 struct platform_device *pdev;
117 struct resource *ioarea;
118 struct s3c_sdhci_platdata *pdata;
119 int cur_clk;
120 int ext_cd_irq;
121
122 struct clk *clk_io;
123 struct clk *clk_bus[MAX_BUS_CLK];
124 unsigned long clk_rates[MAX_BUS_CLK];
125
126 bool no_divider;
127};
128
129/**
130 * struct sdhci_s3c_drv_data - S3C SDHCI platform specific driver data
131 * @sdhci_quirks: sdhci host specific quirks.
132 * @no_divider: no or non-standard internal clock divider.
133 * @ops: sdhci_ops to use for this variant
134 *
135 * Specifies platform specific configuration of sdhci controller.
136 * Note: A structure for driver specific platform data is used for future
137 * expansion of its usage.
138 */
139struct sdhci_s3c_drv_data {
140 unsigned int sdhci_quirks;
141 bool no_divider;
142 const struct sdhci_ops *ops;
143};
144
145static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
146{
147 return sdhci_priv(host);
148}
149
150/**
151 * sdhci_s3c_get_max_clk - callback to get maximum clock frequency.
152 * @host: The SDHCI host instance.
153 *
154 * Callback to return the maximum clock rate acheivable by the controller.
155*/
156static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
157{
158 struct sdhci_s3c *ourhost = to_s3c(host);
159 unsigned long rate, max = 0;
160 int src;
161
162 for (src = 0; src < MAX_BUS_CLK; src++) {
163 rate = ourhost->clk_rates[src];
164 if (rate > max)
165 max = rate;
166 }
167
168 return max;
169}
170
171/**
172 * sdhci_s3c_consider_clock - consider one the bus clocks for current setting
173 * @ourhost: Our SDHCI instance.
174 * @src: The source clock index.
175 * @wanted: The clock frequency wanted.
176 */
177static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
178 unsigned int src,
179 unsigned int wanted)
180{
181 unsigned long rate;
182 struct clk *clksrc = ourhost->clk_bus[src];
183 int shift;
184
185 if (IS_ERR(clksrc))
186 return UINT_MAX;
187
188 /*
189 * If controller uses a non-standard clock division, find the best clock
190 * speed possible with selected clock source and skip the division.
191 */
192 if (ourhost->no_divider) {
193 rate = clk_round_rate(clksrc, wanted);
194 return wanted - rate;
195 }
196
197 rate = ourhost->clk_rates[src];
198
199 for (shift = 0; shift <= 8; ++shift) {
200 if ((rate >> shift) <= wanted)
201 break;
202 }
203
204 if (shift > 8) {
205 dev_dbg(&ourhost->pdev->dev,
206 "clk %d: rate %ld, min rate %lu > wanted %u\n",
207 src, rate, rate / 256, wanted);
208 return UINT_MAX;
209 }
210
211 dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n",
212 src, rate, wanted, rate >> shift);
213
214 return wanted - (rate >> shift);
215}
216
217/**
218 * sdhci_s3c_set_clock - callback on clock change
219 * @host: The SDHCI host being changed
220 * @clock: The clock rate being requested.
221 *
222 * When the card's clock is going to be changed, look at the new frequency
223 * and find the best clock source to go with it.
224*/
225static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
226{
227 struct sdhci_s3c *ourhost = to_s3c(host);
228 unsigned int best = UINT_MAX;
229 unsigned int delta;
230 int best_src = 0;
231 int src;
232 u32 ctrl;
233
234 host->mmc->actual_clock = 0;
235
236 /* don't bother if the clock is going off. */
237 if (clock == 0) {
238 sdhci_set_clock(host, clock);
239 return;
240 }
241
242 for (src = 0; src < MAX_BUS_CLK; src++) {
243 delta = sdhci_s3c_consider_clock(ourhost, src, clock);
244 if (delta < best) {
245 best = delta;
246 best_src = src;
247 }
248 }
249
250 dev_dbg(&ourhost->pdev->dev,
251 "selected source %d, clock %d, delta %d\n",
252 best_src, clock, best);
253
254 /* select the new clock source */
255 if (ourhost->cur_clk != best_src) {
256 struct clk *clk = ourhost->clk_bus[best_src];
257
258 clk_prepare_enable(clk);
259 if (ourhost->cur_clk >= 0)
260 clk_disable_unprepare(
261 ourhost->clk_bus[ourhost->cur_clk]);
262
263 ourhost->cur_clk = best_src;
264 host->max_clk = ourhost->clk_rates[best_src];
265 }
266
267 /* turn clock off to card before changing clock source */
268 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
269
270 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
271 ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
272 ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
273 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
274
275 /* reprogram default hardware configuration */
276 writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA,
277 host->ioaddr + S3C64XX_SDHCI_CONTROL4);
278
279 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
280 ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
281 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
282 S3C_SDHCI_CTRL2_ENFBCLKRX |
283 S3C_SDHCI_CTRL2_DFCNT_NONE |
284 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
285 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
286
287 /* reconfigure the controller for new clock rate */
288 ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
289 if (clock < 25 * 1000000)
290 ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2);
291 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3);
292
293 sdhci_set_clock(host, clock);
294}
295
296/**
297 * sdhci_s3c_get_min_clock - callback to get minimal supported clock value
298 * @host: The SDHCI host being queried
299 *
300 * To init mmc host properly a minimal clock value is needed. For high system
301 * bus clock's values the standard formula gives values out of allowed range.
302 * The clock still can be set to lower values, if clock source other then
303 * system bus is selected.
304*/
305static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host)
306{
307 struct sdhci_s3c *ourhost = to_s3c(host);
308 unsigned long rate, min = ULONG_MAX;
309 int src;
310
311 for (src = 0; src < MAX_BUS_CLK; src++) {
312 rate = ourhost->clk_rates[src] / 256;
313 if (!rate)
314 continue;
315 if (rate < min)
316 min = rate;
317 }
318
319 return min;
320}
321
322/* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/
323static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host)
324{
325 struct sdhci_s3c *ourhost = to_s3c(host);
326 unsigned long rate, max = 0;
327 int src;
328
329 for (src = 0; src < MAX_BUS_CLK; src++) {
330 struct clk *clk;
331
332 clk = ourhost->clk_bus[src];
333 if (IS_ERR(clk))
334 continue;
335
336 rate = clk_round_rate(clk, ULONG_MAX);
337 if (rate > max)
338 max = rate;
339 }
340
341 return max;
342}
343
344/* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */
345static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host)
346{
347 struct sdhci_s3c *ourhost = to_s3c(host);
348 unsigned long rate, min = ULONG_MAX;
349 int src;
350
351 for (src = 0; src < MAX_BUS_CLK; src++) {
352 struct clk *clk;
353
354 clk = ourhost->clk_bus[src];
355 if (IS_ERR(clk))
356 continue;
357
358 rate = clk_round_rate(clk, 0);
359 if (rate < min)
360 min = rate;
361 }
362
363 return min;
364}
365
366/* sdhci_cmu_set_clock - callback on clock change.*/
367static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
368{
369 struct sdhci_s3c *ourhost = to_s3c(host);
370 struct device *dev = &ourhost->pdev->dev;
371 unsigned long timeout;
372 u16 clk = 0;
373 int ret;
374
375 host->mmc->actual_clock = 0;
376
377 /* If the clock is going off, set to 0 at clock control register */
378 if (clock == 0) {
379 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
380 return;
381 }
382
383 sdhci_s3c_set_clock(host, clock);
384
385 /* Reset SD Clock Enable */
386 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
387 clk &= ~SDHCI_CLOCK_CARD_EN;
388 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
389
390 ret = clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
391 if (ret != 0) {
392 dev_err(dev, "%s: failed to set clock rate %uHz\n",
393 mmc_hostname(host->mmc), clock);
394 return;
395 }
396
397 clk = SDHCI_CLOCK_INT_EN;
398 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
399
400 /* Wait max 20 ms */
401 timeout = 20;
402 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
403 & SDHCI_CLOCK_INT_STABLE)) {
404 if (timeout == 0) {
405 dev_err(dev, "%s: Internal clock never stabilised.\n",
406 mmc_hostname(host->mmc));
407 return;
408 }
409 timeout--;
410 mdelay(1);
411 }
412
413 clk |= SDHCI_CLOCK_CARD_EN;
414 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
415}
416
417static const struct sdhci_ops sdhci_s3c_ops_s3c6410 = {
418 .get_max_clock = sdhci_s3c_get_max_clk,
419 .set_clock = sdhci_s3c_set_clock,
420 .get_min_clock = sdhci_s3c_get_min_clock,
421 .set_bus_width = sdhci_set_bus_width,
422 .reset = sdhci_reset,
423 .set_uhs_signaling = sdhci_set_uhs_signaling,
424};
425
426static const struct sdhci_ops sdhci_s3c_ops_exynos4 __maybe_unused = {
427 .get_max_clock = sdhci_cmu_get_max_clock,
428 .set_clock = sdhci_cmu_set_clock,
429 .get_min_clock = sdhci_cmu_get_min_clock,
430 .set_bus_width = sdhci_set_bus_width,
431 .reset = sdhci_reset,
432 .set_uhs_signaling = sdhci_set_uhs_signaling,
433};
434
435#ifdef CONFIG_OF
436static int sdhci_s3c_parse_dt(struct device *dev,
437 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
438{
439 struct device_node *node = dev->of_node;
440 u32 max_width;
441
442 /* if the bus-width property is not specified, assume width as 1 */
443 if (of_property_read_u32(node, "bus-width", &max_width))
444 max_width = 1;
445 pdata->max_width = max_width;
446
447 /* get the card detection method */
448 if (of_property_read_bool(node, "broken-cd")) {
449 pdata->cd_type = S3C_SDHCI_CD_NONE;
450 return 0;
451 }
452
453 if (of_property_read_bool(node, "non-removable")) {
454 pdata->cd_type = S3C_SDHCI_CD_PERMANENT;
455 return 0;
456 }
457
458 if (of_property_present(node, "cd-gpios"))
459 return 0;
460
461 /* assuming internal card detect that will be configured by pinctrl */
462 pdata->cd_type = S3C_SDHCI_CD_INTERNAL;
463 return 0;
464}
465#else
466static int sdhci_s3c_parse_dt(struct device *dev,
467 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
468{
469 return -EINVAL;
470}
471#endif
472
473static inline const struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data(
474 struct platform_device *pdev)
475{
476#ifdef CONFIG_OF
477 if (pdev->dev.of_node)
478 return of_device_get_match_data(&pdev->dev);
479#endif
480 return (const struct sdhci_s3c_drv_data *)
481 platform_get_device_id(pdev)->driver_data;
482}
483
484static int sdhci_s3c_probe(struct platform_device *pdev)
485{
486 struct s3c_sdhci_platdata *pdata;
487 const struct sdhci_s3c_drv_data *drv_data;
488 struct device *dev = &pdev->dev;
489 struct sdhci_host *host;
490 struct sdhci_s3c *sc;
491 int ret, irq, ptr, clks;
492
493 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
494 dev_err(dev, "no device data specified\n");
495 return -ENOENT;
496 }
497
498 irq = platform_get_irq(pdev, 0);
499 if (irq < 0)
500 return irq;
501
502 host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
503 if (IS_ERR(host)) {
504 dev_err(dev, "sdhci_alloc_host() failed\n");
505 return PTR_ERR(host);
506 }
507 sc = sdhci_priv(host);
508
509 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
510 if (!pdata) {
511 ret = -ENOMEM;
512 goto err_pdata_io_clk;
513 }
514
515 if (pdev->dev.of_node) {
516 ret = sdhci_s3c_parse_dt(&pdev->dev, host, pdata);
517 if (ret)
518 goto err_pdata_io_clk;
519 } else {
520 memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata));
521 }
522
523 drv_data = sdhci_s3c_get_driver_data(pdev);
524
525 sc->host = host;
526 sc->pdev = pdev;
527 sc->pdata = pdata;
528 sc->cur_clk = -1;
529
530 platform_set_drvdata(pdev, host);
531
532 sc->clk_io = devm_clk_get(dev, "hsmmc");
533 if (IS_ERR(sc->clk_io)) {
534 dev_err(dev, "failed to get io clock\n");
535 ret = PTR_ERR(sc->clk_io);
536 goto err_pdata_io_clk;
537 }
538
539 /* enable the local io clock and keep it running for the moment. */
540 clk_prepare_enable(sc->clk_io);
541
542 for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
543 char name[14];
544
545 snprintf(name, 14, "mmc_busclk.%d", ptr);
546 sc->clk_bus[ptr] = devm_clk_get(dev, name);
547 if (IS_ERR(sc->clk_bus[ptr]))
548 continue;
549
550 clks++;
551 sc->clk_rates[ptr] = clk_get_rate(sc->clk_bus[ptr]);
552
553 dev_info(dev, "clock source %d: %s (%ld Hz)\n",
554 ptr, name, sc->clk_rates[ptr]);
555 }
556
557 if (clks == 0) {
558 dev_err(dev, "failed to find any bus clocks\n");
559 ret = -ENOENT;
560 goto err_no_busclks;
561 }
562
563 host->ioaddr = devm_platform_ioremap_resource(pdev, 0);
564 if (IS_ERR(host->ioaddr)) {
565 ret = PTR_ERR(host->ioaddr);
566 goto err_req_regs;
567 }
568
569 /* Ensure we have minimal gpio selected CMD/CLK/Detect */
570 if (pdata->cfg_gpio)
571 pdata->cfg_gpio(pdev, pdata->max_width);
572
573 host->hw_name = "samsung-hsmmc";
574 host->ops = &sdhci_s3c_ops_s3c6410;
575 host->quirks = 0;
576 host->quirks2 = 0;
577 host->irq = irq;
578
579 /* Setup quirks for the controller */
580 host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
581 host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
582 if (drv_data) {
583 host->quirks |= drv_data->sdhci_quirks;
584 host->ops = drv_data->ops;
585 sc->no_divider = drv_data->no_divider;
586 }
587
588#ifndef CONFIG_MMC_SDHCI_S3C_DMA
589
590 /* we currently see overruns on errors, so disable the SDMA
591 * support as well. */
592 host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
593
594#endif /* CONFIG_MMC_SDHCI_S3C_DMA */
595
596 /* It seems we do not get an DATA transfer complete on non-busy
597 * transfers, not sure if this is a problem with this specific
598 * SDHCI block, or a missing configuration that needs to be set. */
599 host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
600
601 /* This host supports the Auto CMD12 */
602 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
603
604 /* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */
605 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC;
606
607 if (pdata->cd_type == S3C_SDHCI_CD_NONE ||
608 pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
609 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
610
611 if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
612 host->mmc->caps = MMC_CAP_NONREMOVABLE;
613
614 switch (pdata->max_width) {
615 case 8:
616 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
617 fallthrough;
618 case 4:
619 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
620 break;
621 }
622
623 if (pdata->pm_caps)
624 host->mmc->pm_caps |= pdata->pm_caps;
625
626 host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
627 SDHCI_QUIRK_32BIT_DMA_SIZE);
628
629 /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */
630 host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
631
632 /* It supports additional host capabilities if needed */
633 if (pdata->host_caps)
634 host->mmc->caps |= pdata->host_caps;
635
636 if (pdata->host_caps2)
637 host->mmc->caps2 |= pdata->host_caps2;
638
639 pm_runtime_enable(&pdev->dev);
640 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
641 pm_runtime_use_autosuspend(&pdev->dev);
642 pm_suspend_ignore_children(&pdev->dev, 1);
643
644 ret = mmc_of_parse(host->mmc);
645 if (ret)
646 goto err_req_regs;
647
648 ret = sdhci_add_host(host);
649 if (ret)
650 goto err_req_regs;
651
652#ifdef CONFIG_PM
653 if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
654 clk_disable_unprepare(sc->clk_io);
655#endif
656 return 0;
657
658 err_req_regs:
659 pm_runtime_disable(&pdev->dev);
660
661 err_no_busclks:
662 clk_disable_unprepare(sc->clk_io);
663
664 err_pdata_io_clk:
665 sdhci_free_host(host);
666
667 return ret;
668}
669
670static void sdhci_s3c_remove(struct platform_device *pdev)
671{
672 struct sdhci_host *host = platform_get_drvdata(pdev);
673 struct sdhci_s3c *sc = sdhci_priv(host);
674
675 if (sc->ext_cd_irq)
676 free_irq(sc->ext_cd_irq, sc);
677
678#ifdef CONFIG_PM
679 if (sc->pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
680 clk_prepare_enable(sc->clk_io);
681#endif
682 sdhci_remove_host(host, 1);
683
684 pm_runtime_dont_use_autosuspend(&pdev->dev);
685 pm_runtime_disable(&pdev->dev);
686
687 clk_disable_unprepare(sc->clk_io);
688
689 sdhci_free_host(host);
690}
691
692#ifdef CONFIG_PM_SLEEP
693static int sdhci_s3c_suspend(struct device *dev)
694{
695 struct sdhci_host *host = dev_get_drvdata(dev);
696
697 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
698 mmc_retune_needed(host->mmc);
699
700 return sdhci_suspend_host(host);
701}
702
703static int sdhci_s3c_resume(struct device *dev)
704{
705 struct sdhci_host *host = dev_get_drvdata(dev);
706
707 return sdhci_resume_host(host);
708}
709#endif
710
711#ifdef CONFIG_PM
712static int sdhci_s3c_runtime_suspend(struct device *dev)
713{
714 struct sdhci_host *host = dev_get_drvdata(dev);
715 struct sdhci_s3c *ourhost = to_s3c(host);
716 struct clk *busclk = ourhost->clk_io;
717 int ret;
718
719 ret = sdhci_runtime_suspend_host(host);
720
721 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
722 mmc_retune_needed(host->mmc);
723
724 if (ourhost->cur_clk >= 0)
725 clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]);
726 clk_disable_unprepare(busclk);
727 return ret;
728}
729
730static int sdhci_s3c_runtime_resume(struct device *dev)
731{
732 struct sdhci_host *host = dev_get_drvdata(dev);
733 struct sdhci_s3c *ourhost = to_s3c(host);
734 struct clk *busclk = ourhost->clk_io;
735 int ret;
736
737 clk_prepare_enable(busclk);
738 if (ourhost->cur_clk >= 0)
739 clk_prepare_enable(ourhost->clk_bus[ourhost->cur_clk]);
740 ret = sdhci_runtime_resume_host(host, 0);
741 return ret;
742}
743#endif
744
745static const struct dev_pm_ops sdhci_s3c_pmops = {
746 SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume)
747 SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume,
748 NULL)
749};
750
751static const struct platform_device_id sdhci_s3c_driver_ids[] = {
752 {
753 .name = "s3c-sdhci",
754 .driver_data = (kernel_ulong_t)NULL,
755 },
756 { }
757};
758MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids);
759
760#ifdef CONFIG_OF
761static const struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = {
762 .no_divider = true,
763 .ops = &sdhci_s3c_ops_exynos4,
764};
765
766static const struct of_device_id sdhci_s3c_dt_match[] = {
767 { .compatible = "samsung,s3c6410-sdhci", },
768 { .compatible = "samsung,exynos4210-sdhci",
769 .data = &exynos4_sdhci_drv_data },
770 {},
771};
772MODULE_DEVICE_TABLE(of, sdhci_s3c_dt_match);
773#endif
774
775static struct platform_driver sdhci_s3c_driver = {
776 .probe = sdhci_s3c_probe,
777 .remove = sdhci_s3c_remove,
778 .id_table = sdhci_s3c_driver_ids,
779 .driver = {
780 .name = "s3c-sdhci",
781 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
782 .of_match_table = of_match_ptr(sdhci_s3c_dt_match),
783 .pm = &sdhci_s3c_pmops,
784 },
785};
786
787module_platform_driver(sdhci_s3c_driver);
788
789MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
790MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
791MODULE_LICENSE("GPL v2");