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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver
4 *
5 * This is a driver for the SDHC controller found in Freescale MX2/MX3
6 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
7 * Unlike the hardware found on MX1, this hardware just works and does
8 * not need all the quirks found in imxmmc.c, hence the separate driver.
9 *
10 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
11 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
12 *
13 * derived from pxamci.c by Russell King
14 */
15
16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/ioport.h>
19#include <linux/platform_device.h>
20#include <linux/highmem.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/blkdev.h>
24#include <linux/dma-mapping.h>
25#include <linux/mmc/host.h>
26#include <linux/mmc/card.h>
27#include <linux/delay.h>
28#include <linux/clk.h>
29#include <linux/io.h>
30#include <linux/regulator/consumer.h>
31#include <linux/dmaengine.h>
32#include <linux/types.h>
33#include <linux/of.h>
34#include <linux/of_device.h>
35#include <linux/of_dma.h>
36#include <linux/mmc/slot-gpio.h>
37
38#include <asm/dma.h>
39#include <asm/irq.h>
40#include <linux/platform_data/mmc-mxcmmc.h>
41
42#include <linux/dma/imx-dma.h>
43
44#define DRIVER_NAME "mxc-mmc"
45#define MXCMCI_TIMEOUT_MS 10000
46
47#define MMC_REG_STR_STP_CLK 0x00
48#define MMC_REG_STATUS 0x04
49#define MMC_REG_CLK_RATE 0x08
50#define MMC_REG_CMD_DAT_CONT 0x0C
51#define MMC_REG_RES_TO 0x10
52#define MMC_REG_READ_TO 0x14
53#define MMC_REG_BLK_LEN 0x18
54#define MMC_REG_NOB 0x1C
55#define MMC_REG_REV_NO 0x20
56#define MMC_REG_INT_CNTR 0x24
57#define MMC_REG_CMD 0x28
58#define MMC_REG_ARG 0x2C
59#define MMC_REG_RES_FIFO 0x34
60#define MMC_REG_BUFFER_ACCESS 0x38
61
62#define STR_STP_CLK_RESET (1 << 3)
63#define STR_STP_CLK_START_CLK (1 << 1)
64#define STR_STP_CLK_STOP_CLK (1 << 0)
65
66#define STATUS_CARD_INSERTION (1 << 31)
67#define STATUS_CARD_REMOVAL (1 << 30)
68#define STATUS_YBUF_EMPTY (1 << 29)
69#define STATUS_XBUF_EMPTY (1 << 28)
70#define STATUS_YBUF_FULL (1 << 27)
71#define STATUS_XBUF_FULL (1 << 26)
72#define STATUS_BUF_UND_RUN (1 << 25)
73#define STATUS_BUF_OVFL (1 << 24)
74#define STATUS_SDIO_INT_ACTIVE (1 << 14)
75#define STATUS_END_CMD_RESP (1 << 13)
76#define STATUS_WRITE_OP_DONE (1 << 12)
77#define STATUS_DATA_TRANS_DONE (1 << 11)
78#define STATUS_READ_OP_DONE (1 << 11)
79#define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
80#define STATUS_CARD_BUS_CLK_RUN (1 << 8)
81#define STATUS_BUF_READ_RDY (1 << 7)
82#define STATUS_BUF_WRITE_RDY (1 << 6)
83#define STATUS_RESP_CRC_ERR (1 << 5)
84#define STATUS_CRC_READ_ERR (1 << 3)
85#define STATUS_CRC_WRITE_ERR (1 << 2)
86#define STATUS_TIME_OUT_RESP (1 << 1)
87#define STATUS_TIME_OUT_READ (1 << 0)
88#define STATUS_ERR_MASK 0x2f
89
90#define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
91#define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
92#define CMD_DAT_CONT_START_READWAIT (1 << 10)
93#define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
94#define CMD_DAT_CONT_INIT (1 << 7)
95#define CMD_DAT_CONT_WRITE (1 << 4)
96#define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
97#define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
98#define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
99#define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
100
101#define INT_SDIO_INT_WKP_EN (1 << 18)
102#define INT_CARD_INSERTION_WKP_EN (1 << 17)
103#define INT_CARD_REMOVAL_WKP_EN (1 << 16)
104#define INT_CARD_INSERTION_EN (1 << 15)
105#define INT_CARD_REMOVAL_EN (1 << 14)
106#define INT_SDIO_IRQ_EN (1 << 13)
107#define INT_DAT0_EN (1 << 12)
108#define INT_BUF_READ_EN (1 << 4)
109#define INT_BUF_WRITE_EN (1 << 3)
110#define INT_END_CMD_RES_EN (1 << 2)
111#define INT_WRITE_OP_DONE_EN (1 << 1)
112#define INT_READ_OP_EN (1 << 0)
113
114enum mxcmci_type {
115 IMX21_MMC,
116 IMX31_MMC,
117 MPC512X_MMC,
118};
119
120struct mxcmci_host {
121 struct mmc_host *mmc;
122 void __iomem *base;
123 dma_addr_t phys_base;
124 int detect_irq;
125 struct dma_chan *dma;
126 struct dma_async_tx_descriptor *desc;
127 int do_dma;
128 int default_irq_mask;
129 int use_sdio;
130 unsigned int power_mode;
131 struct imxmmc_platform_data *pdata;
132
133 struct mmc_request *req;
134 struct mmc_command *cmd;
135 struct mmc_data *data;
136
137 unsigned int datasize;
138 unsigned int dma_dir;
139
140 u16 rev_no;
141 unsigned int cmdat;
142
143 struct clk *clk_ipg;
144 struct clk *clk_per;
145
146 int clock;
147
148 struct work_struct datawork;
149 spinlock_t lock;
150
151 int burstlen;
152 int dmareq;
153 struct dma_slave_config dma_slave_config;
154 struct imx_dma_data dma_data;
155
156 struct timer_list watchdog;
157 enum mxcmci_type devtype;
158};
159
160static const struct of_device_id mxcmci_of_match[] = {
161 {
162 .compatible = "fsl,imx21-mmc",
163 .data = (void *) IMX21_MMC,
164 }, {
165 .compatible = "fsl,imx31-mmc",
166 .data = (void *) IMX31_MMC,
167 }, {
168 .compatible = "fsl,mpc5121-sdhc",
169 .data = (void *) MPC512X_MMC,
170 }, {
171 /* sentinel */
172 }
173};
174MODULE_DEVICE_TABLE(of, mxcmci_of_match);
175
176static inline int is_imx31_mmc(struct mxcmci_host *host)
177{
178 return host->devtype == IMX31_MMC;
179}
180
181static inline int is_mpc512x_mmc(struct mxcmci_host *host)
182{
183 return host->devtype == MPC512X_MMC;
184}
185
186static inline u32 mxcmci_readl(struct mxcmci_host *host, int reg)
187{
188 if (IS_ENABLED(CONFIG_PPC_MPC512x))
189 return ioread32be(host->base + reg);
190 else
191 return readl(host->base + reg);
192}
193
194static inline void mxcmci_writel(struct mxcmci_host *host, u32 val, int reg)
195{
196 if (IS_ENABLED(CONFIG_PPC_MPC512x))
197 iowrite32be(val, host->base + reg);
198 else
199 writel(val, host->base + reg);
200}
201
202static inline u16 mxcmci_readw(struct mxcmci_host *host, int reg)
203{
204 if (IS_ENABLED(CONFIG_PPC_MPC512x))
205 return ioread32be(host->base + reg);
206 else
207 return readw(host->base + reg);
208}
209
210static inline void mxcmci_writew(struct mxcmci_host *host, u16 val, int reg)
211{
212 if (IS_ENABLED(CONFIG_PPC_MPC512x))
213 iowrite32be(val, host->base + reg);
214 else
215 writew(val, host->base + reg);
216}
217
218static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios);
219
220static void mxcmci_set_power(struct mxcmci_host *host, unsigned int vdd)
221{
222 if (!IS_ERR(host->mmc->supply.vmmc)) {
223 if (host->power_mode == MMC_POWER_UP)
224 mmc_regulator_set_ocr(host->mmc,
225 host->mmc->supply.vmmc, vdd);
226 else if (host->power_mode == MMC_POWER_OFF)
227 mmc_regulator_set_ocr(host->mmc,
228 host->mmc->supply.vmmc, 0);
229 }
230
231 if (host->pdata && host->pdata->setpower)
232 host->pdata->setpower(mmc_dev(host->mmc), vdd);
233}
234
235static inline int mxcmci_use_dma(struct mxcmci_host *host)
236{
237 return host->do_dma;
238}
239
240static void mxcmci_softreset(struct mxcmci_host *host)
241{
242 int i;
243
244 dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n");
245
246 /* reset sequence */
247 mxcmci_writew(host, STR_STP_CLK_RESET, MMC_REG_STR_STP_CLK);
248 mxcmci_writew(host, STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
249 MMC_REG_STR_STP_CLK);
250
251 for (i = 0; i < 8; i++)
252 mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK);
253
254 mxcmci_writew(host, 0xff, MMC_REG_RES_TO);
255}
256
257#if IS_ENABLED(CONFIG_PPC_MPC512x)
258static inline void buffer_swap32(u32 *buf, int len)
259{
260 int i;
261
262 for (i = 0; i < ((len + 3) / 4); i++) {
263 *buf = swab32(*buf);
264 buf++;
265 }
266}
267
268static void mxcmci_swap_buffers(struct mmc_data *data)
269{
270 struct scatterlist *sg;
271 int i;
272
273 for_each_sg(data->sg, sg, data->sg_len, i)
274 buffer_swap32(sg_virt(sg), sg->length);
275}
276#else
277static inline void mxcmci_swap_buffers(struct mmc_data *data) {}
278#endif
279
280static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
281{
282 unsigned int nob = data->blocks;
283 unsigned int blksz = data->blksz;
284 unsigned int datasize = nob * blksz;
285 struct scatterlist *sg;
286 enum dma_transfer_direction slave_dirn;
287 int i, nents;
288
289 host->data = data;
290 data->bytes_xfered = 0;
291
292 mxcmci_writew(host, nob, MMC_REG_NOB);
293 mxcmci_writew(host, blksz, MMC_REG_BLK_LEN);
294 host->datasize = datasize;
295
296 if (!mxcmci_use_dma(host))
297 return 0;
298
299 for_each_sg(data->sg, sg, data->sg_len, i) {
300 if (sg->offset & 3 || sg->length & 3 || sg->length < 512) {
301 host->do_dma = 0;
302 return 0;
303 }
304 }
305
306 if (data->flags & MMC_DATA_READ) {
307 host->dma_dir = DMA_FROM_DEVICE;
308 slave_dirn = DMA_DEV_TO_MEM;
309 } else {
310 host->dma_dir = DMA_TO_DEVICE;
311 slave_dirn = DMA_MEM_TO_DEV;
312
313 mxcmci_swap_buffers(data);
314 }
315
316 nents = dma_map_sg(host->dma->device->dev, data->sg,
317 data->sg_len, host->dma_dir);
318 if (nents != data->sg_len)
319 return -EINVAL;
320
321 host->desc = dmaengine_prep_slave_sg(host->dma,
322 data->sg, data->sg_len, slave_dirn,
323 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
324
325 if (!host->desc) {
326 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
327 host->dma_dir);
328 host->do_dma = 0;
329 return 0; /* Fall back to PIO */
330 }
331 wmb();
332
333 dmaengine_submit(host->desc);
334 dma_async_issue_pending(host->dma);
335
336 mod_timer(&host->watchdog, jiffies + msecs_to_jiffies(MXCMCI_TIMEOUT_MS));
337
338 return 0;
339}
340
341static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat);
342static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat);
343
344static void mxcmci_dma_callback(void *data)
345{
346 struct mxcmci_host *host = data;
347 u32 stat;
348
349 del_timer(&host->watchdog);
350
351 stat = mxcmci_readl(host, MMC_REG_STATUS);
352
353 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
354
355 mxcmci_data_done(host, stat);
356}
357
358static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
359 unsigned int cmdat)
360{
361 u32 int_cntr = host->default_irq_mask;
362 unsigned long flags;
363
364 WARN_ON(host->cmd != NULL);
365 host->cmd = cmd;
366
367 switch (mmc_resp_type(cmd)) {
368 case MMC_RSP_R1: /* short CRC, OPCODE */
369 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
370 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
371 break;
372 case MMC_RSP_R2: /* long 136 bit + CRC */
373 cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
374 break;
375 case MMC_RSP_R3: /* short */
376 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
377 break;
378 case MMC_RSP_NONE:
379 break;
380 default:
381 dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n",
382 mmc_resp_type(cmd));
383 cmd->error = -EINVAL;
384 return -EINVAL;
385 }
386
387 int_cntr = INT_END_CMD_RES_EN;
388
389 if (mxcmci_use_dma(host)) {
390 if (host->dma_dir == DMA_FROM_DEVICE) {
391 host->desc->callback = mxcmci_dma_callback;
392 host->desc->callback_param = host;
393 } else {
394 int_cntr |= INT_WRITE_OP_DONE_EN;
395 }
396 }
397
398 spin_lock_irqsave(&host->lock, flags);
399 if (host->use_sdio)
400 int_cntr |= INT_SDIO_IRQ_EN;
401 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
402 spin_unlock_irqrestore(&host->lock, flags);
403
404 mxcmci_writew(host, cmd->opcode, MMC_REG_CMD);
405 mxcmci_writel(host, cmd->arg, MMC_REG_ARG);
406 mxcmci_writew(host, cmdat, MMC_REG_CMD_DAT_CONT);
407
408 return 0;
409}
410
411static void mxcmci_finish_request(struct mxcmci_host *host,
412 struct mmc_request *req)
413{
414 u32 int_cntr = host->default_irq_mask;
415 unsigned long flags;
416
417 spin_lock_irqsave(&host->lock, flags);
418 if (host->use_sdio)
419 int_cntr |= INT_SDIO_IRQ_EN;
420 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
421 spin_unlock_irqrestore(&host->lock, flags);
422
423 host->req = NULL;
424 host->cmd = NULL;
425 host->data = NULL;
426
427 mmc_request_done(host->mmc, req);
428}
429
430static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
431{
432 struct mmc_data *data = host->data;
433 int data_error;
434
435 if (mxcmci_use_dma(host)) {
436 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
437 host->dma_dir);
438 mxcmci_swap_buffers(data);
439 }
440
441 if (stat & STATUS_ERR_MASK) {
442 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",
443 stat);
444 if (stat & STATUS_CRC_READ_ERR) {
445 dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__);
446 data->error = -EILSEQ;
447 } else if (stat & STATUS_CRC_WRITE_ERR) {
448 u32 err_code = (stat >> 9) & 0x3;
449 if (err_code == 2) { /* No CRC response */
450 dev_err(mmc_dev(host->mmc),
451 "%s: No CRC -ETIMEDOUT\n", __func__);
452 data->error = -ETIMEDOUT;
453 } else {
454 dev_err(mmc_dev(host->mmc),
455 "%s: -EILSEQ\n", __func__);
456 data->error = -EILSEQ;
457 }
458 } else if (stat & STATUS_TIME_OUT_READ) {
459 dev_err(mmc_dev(host->mmc),
460 "%s: read -ETIMEDOUT\n", __func__);
461 data->error = -ETIMEDOUT;
462 } else {
463 dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__);
464 data->error = -EIO;
465 }
466 } else {
467 data->bytes_xfered = host->datasize;
468 }
469
470 data_error = data->error;
471
472 host->data = NULL;
473
474 return data_error;
475}
476
477static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
478{
479 struct mmc_command *cmd = host->cmd;
480 int i;
481 u32 a, b, c;
482
483 if (!cmd)
484 return;
485
486 if (stat & STATUS_TIME_OUT_RESP) {
487 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
488 cmd->error = -ETIMEDOUT;
489 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
490 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
491 cmd->error = -EILSEQ;
492 }
493
494 if (cmd->flags & MMC_RSP_PRESENT) {
495 if (cmd->flags & MMC_RSP_136) {
496 for (i = 0; i < 4; i++) {
497 a = mxcmci_readw(host, MMC_REG_RES_FIFO);
498 b = mxcmci_readw(host, MMC_REG_RES_FIFO);
499 cmd->resp[i] = a << 16 | b;
500 }
501 } else {
502 a = mxcmci_readw(host, MMC_REG_RES_FIFO);
503 b = mxcmci_readw(host, MMC_REG_RES_FIFO);
504 c = mxcmci_readw(host, MMC_REG_RES_FIFO);
505 cmd->resp[0] = a << 24 | b << 8 | c >> 8;
506 }
507 }
508}
509
510static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
511{
512 u32 stat;
513 unsigned long timeout = jiffies + HZ;
514
515 do {
516 stat = mxcmci_readl(host, MMC_REG_STATUS);
517 if (stat & STATUS_ERR_MASK)
518 return stat;
519 if (time_after(jiffies, timeout)) {
520 mxcmci_softreset(host);
521 mxcmci_set_clk_rate(host, host->clock);
522 return STATUS_TIME_OUT_READ;
523 }
524 if (stat & mask)
525 return 0;
526 cpu_relax();
527 } while (1);
528}
529
530static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes)
531{
532 unsigned int stat;
533 u32 *buf = _buf;
534
535 while (bytes > 3) {
536 stat = mxcmci_poll_status(host,
537 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
538 if (stat)
539 return stat;
540 *buf++ = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS));
541 bytes -= 4;
542 }
543
544 if (bytes) {
545 u8 *b = (u8 *)buf;
546 u32 tmp;
547
548 stat = mxcmci_poll_status(host,
549 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
550 if (stat)
551 return stat;
552 tmp = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS));
553 memcpy(b, &tmp, bytes);
554 }
555
556 return 0;
557}
558
559static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes)
560{
561 unsigned int stat;
562 u32 *buf = _buf;
563
564 while (bytes > 3) {
565 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
566 if (stat)
567 return stat;
568 mxcmci_writel(host, cpu_to_le32(*buf++), MMC_REG_BUFFER_ACCESS);
569 bytes -= 4;
570 }
571
572 if (bytes) {
573 u8 *b = (u8 *)buf;
574 u32 tmp;
575
576 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
577 if (stat)
578 return stat;
579
580 memcpy(&tmp, b, bytes);
581 mxcmci_writel(host, cpu_to_le32(tmp), MMC_REG_BUFFER_ACCESS);
582 }
583
584 return mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
585}
586
587static int mxcmci_transfer_data(struct mxcmci_host *host)
588{
589 struct mmc_data *data = host->req->data;
590 struct scatterlist *sg;
591 int stat, i;
592
593 host->data = data;
594 host->datasize = 0;
595
596 if (data->flags & MMC_DATA_READ) {
597 for_each_sg(data->sg, sg, data->sg_len, i) {
598 stat = mxcmci_pull(host, sg_virt(sg), sg->length);
599 if (stat)
600 return stat;
601 host->datasize += sg->length;
602 }
603 } else {
604 for_each_sg(data->sg, sg, data->sg_len, i) {
605 stat = mxcmci_push(host, sg_virt(sg), sg->length);
606 if (stat)
607 return stat;
608 host->datasize += sg->length;
609 }
610 stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
611 if (stat)
612 return stat;
613 }
614 return 0;
615}
616
617static void mxcmci_datawork(struct work_struct *work)
618{
619 struct mxcmci_host *host = container_of(work, struct mxcmci_host,
620 datawork);
621 int datastat = mxcmci_transfer_data(host);
622
623 mxcmci_writel(host, STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
624 MMC_REG_STATUS);
625 mxcmci_finish_data(host, datastat);
626
627 if (host->req->stop) {
628 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
629 mxcmci_finish_request(host, host->req);
630 return;
631 }
632 } else {
633 mxcmci_finish_request(host, host->req);
634 }
635}
636
637static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat)
638{
639 struct mmc_request *req;
640 int data_error;
641 unsigned long flags;
642
643 spin_lock_irqsave(&host->lock, flags);
644
645 if (!host->data) {
646 spin_unlock_irqrestore(&host->lock, flags);
647 return;
648 }
649
650 if (!host->req) {
651 spin_unlock_irqrestore(&host->lock, flags);
652 return;
653 }
654
655 req = host->req;
656 if (!req->stop)
657 host->req = NULL; /* we will handle finish req below */
658
659 data_error = mxcmci_finish_data(host, stat);
660
661 spin_unlock_irqrestore(&host->lock, flags);
662
663 if (data_error)
664 return;
665
666 mxcmci_read_response(host, stat);
667 host->cmd = NULL;
668
669 if (req->stop) {
670 if (mxcmci_start_cmd(host, req->stop, 0)) {
671 mxcmci_finish_request(host, req);
672 return;
673 }
674 } else {
675 mxcmci_finish_request(host, req);
676 }
677}
678
679static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
680{
681 mxcmci_read_response(host, stat);
682 host->cmd = NULL;
683
684 if (!host->data && host->req) {
685 mxcmci_finish_request(host, host->req);
686 return;
687 }
688
689 /* For the DMA case the DMA engine handles the data transfer
690 * automatically. For non DMA we have to do it ourselves.
691 * Don't do it in interrupt context though.
692 */
693 if (!mxcmci_use_dma(host) && host->data)
694 schedule_work(&host->datawork);
695
696}
697
698static irqreturn_t mxcmci_irq(int irq, void *devid)
699{
700 struct mxcmci_host *host = devid;
701 bool sdio_irq;
702 u32 stat;
703
704 stat = mxcmci_readl(host, MMC_REG_STATUS);
705 mxcmci_writel(host,
706 stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE |
707 STATUS_WRITE_OP_DONE),
708 MMC_REG_STATUS);
709
710 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
711
712 spin_lock(&host->lock);
713 sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio;
714 spin_unlock(&host->lock);
715
716 if (mxcmci_use_dma(host) && (stat & (STATUS_WRITE_OP_DONE)))
717 mxcmci_writel(host, STATUS_WRITE_OP_DONE, MMC_REG_STATUS);
718
719 if (sdio_irq) {
720 mxcmci_writel(host, STATUS_SDIO_INT_ACTIVE, MMC_REG_STATUS);
721 mmc_signal_sdio_irq(host->mmc);
722 }
723
724 if (stat & STATUS_END_CMD_RESP)
725 mxcmci_cmd_done(host, stat);
726
727 if (mxcmci_use_dma(host) && (stat & STATUS_WRITE_OP_DONE)) {
728 del_timer(&host->watchdog);
729 mxcmci_data_done(host, stat);
730 }
731
732 if (host->default_irq_mask &&
733 (stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL)))
734 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
735
736 return IRQ_HANDLED;
737}
738
739static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req)
740{
741 struct mxcmci_host *host = mmc_priv(mmc);
742 unsigned int cmdat = host->cmdat;
743 int error;
744
745 WARN_ON(host->req != NULL);
746
747 host->req = req;
748 host->cmdat &= ~CMD_DAT_CONT_INIT;
749
750 if (host->dma)
751 host->do_dma = 1;
752
753 if (req->data) {
754 error = mxcmci_setup_data(host, req->data);
755 if (error) {
756 req->cmd->error = error;
757 goto out;
758 }
759
760
761 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
762
763 if (req->data->flags & MMC_DATA_WRITE)
764 cmdat |= CMD_DAT_CONT_WRITE;
765 }
766
767 error = mxcmci_start_cmd(host, req->cmd, cmdat);
768
769out:
770 if (error)
771 mxcmci_finish_request(host, req);
772}
773
774static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
775{
776 unsigned int divider;
777 int prescaler = 0;
778 unsigned int clk_in = clk_get_rate(host->clk_per);
779
780 while (prescaler <= 0x800) {
781 for (divider = 1; divider <= 0xF; divider++) {
782 int x;
783
784 x = (clk_in / (divider + 1));
785
786 if (prescaler)
787 x /= (prescaler * 2);
788
789 if (x <= clk_ios)
790 break;
791 }
792 if (divider < 0x10)
793 break;
794
795 if (prescaler == 0)
796 prescaler = 1;
797 else
798 prescaler <<= 1;
799 }
800
801 mxcmci_writew(host, (prescaler << 4) | divider, MMC_REG_CLK_RATE);
802
803 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n",
804 prescaler, divider, clk_in, clk_ios);
805}
806
807static int mxcmci_setup_dma(struct mmc_host *mmc)
808{
809 struct mxcmci_host *host = mmc_priv(mmc);
810 struct dma_slave_config *config = &host->dma_slave_config;
811
812 config->dst_addr = host->phys_base + MMC_REG_BUFFER_ACCESS;
813 config->src_addr = host->phys_base + MMC_REG_BUFFER_ACCESS;
814 config->dst_addr_width = 4;
815 config->src_addr_width = 4;
816 config->dst_maxburst = host->burstlen;
817 config->src_maxburst = host->burstlen;
818 config->device_fc = false;
819
820 return dmaengine_slave_config(host->dma, config);
821}
822
823static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
824{
825 struct mxcmci_host *host = mmc_priv(mmc);
826 int burstlen, ret;
827
828 /*
829 * use burstlen of 64 (16 words) in 4 bit mode (--> reg value 0)
830 * use burstlen of 16 (4 words) in 1 bit mode (--> reg value 16)
831 */
832 if (ios->bus_width == MMC_BUS_WIDTH_4)
833 burstlen = 16;
834 else
835 burstlen = 4;
836
837 if (mxcmci_use_dma(host) && burstlen != host->burstlen) {
838 host->burstlen = burstlen;
839 ret = mxcmci_setup_dma(mmc);
840 if (ret) {
841 dev_err(mmc_dev(host->mmc),
842 "failed to config DMA channel. Falling back to PIO\n");
843 dma_release_channel(host->dma);
844 host->do_dma = 0;
845 host->dma = NULL;
846 }
847 }
848
849 if (ios->bus_width == MMC_BUS_WIDTH_4)
850 host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
851 else
852 host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
853
854 if (host->power_mode != ios->power_mode) {
855 host->power_mode = ios->power_mode;
856 mxcmci_set_power(host, ios->vdd);
857
858 if (ios->power_mode == MMC_POWER_ON)
859 host->cmdat |= CMD_DAT_CONT_INIT;
860 }
861
862 if (ios->clock) {
863 mxcmci_set_clk_rate(host, ios->clock);
864 mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK);
865 } else {
866 mxcmci_writew(host, STR_STP_CLK_STOP_CLK, MMC_REG_STR_STP_CLK);
867 }
868
869 host->clock = ios->clock;
870}
871
872static irqreturn_t mxcmci_detect_irq(int irq, void *data)
873{
874 struct mmc_host *mmc = data;
875
876 dev_dbg(mmc_dev(mmc), "%s\n", __func__);
877
878 mmc_detect_change(mmc, msecs_to_jiffies(250));
879 return IRQ_HANDLED;
880}
881
882static int mxcmci_get_ro(struct mmc_host *mmc)
883{
884 struct mxcmci_host *host = mmc_priv(mmc);
885
886 if (host->pdata && host->pdata->get_ro)
887 return !!host->pdata->get_ro(mmc_dev(mmc));
888 /*
889 * If board doesn't support read only detection (no mmc_gpio
890 * context or gpio is invalid), then let the mmc core decide
891 * what to do.
892 */
893 return mmc_gpio_get_ro(mmc);
894}
895
896static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
897{
898 struct mxcmci_host *host = mmc_priv(mmc);
899 unsigned long flags;
900 u32 int_cntr;
901
902 spin_lock_irqsave(&host->lock, flags);
903 host->use_sdio = enable;
904 int_cntr = mxcmci_readl(host, MMC_REG_INT_CNTR);
905
906 if (enable)
907 int_cntr |= INT_SDIO_IRQ_EN;
908 else
909 int_cntr &= ~INT_SDIO_IRQ_EN;
910
911 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
912 spin_unlock_irqrestore(&host->lock, flags);
913}
914
915static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card)
916{
917 struct mxcmci_host *mxcmci = mmc_priv(host);
918
919 /*
920 * MX3 SoCs have a silicon bug which corrupts CRC calculation of
921 * multi-block transfers when connected SDIO peripheral doesn't
922 * drive the BUSY line as required by the specs.
923 * One way to prevent this is to only allow 1-bit transfers.
924 */
925
926 if (is_imx31_mmc(mxcmci) && mmc_card_sdio(card))
927 host->caps &= ~MMC_CAP_4_BIT_DATA;
928 else
929 host->caps |= MMC_CAP_4_BIT_DATA;
930}
931
932static bool filter(struct dma_chan *chan, void *param)
933{
934 struct mxcmci_host *host = param;
935
936 if (!imx_dma_is_general_purpose(chan))
937 return false;
938
939 chan->private = &host->dma_data;
940
941 return true;
942}
943
944static void mxcmci_watchdog(struct timer_list *t)
945{
946 struct mxcmci_host *host = from_timer(host, t, watchdog);
947 struct mmc_request *req = host->req;
948 unsigned int stat = mxcmci_readl(host, MMC_REG_STATUS);
949
950 if (host->dma_dir == DMA_FROM_DEVICE) {
951 dmaengine_terminate_all(host->dma);
952 dev_err(mmc_dev(host->mmc),
953 "%s: read time out (status = 0x%08x)\n",
954 __func__, stat);
955 } else {
956 dev_err(mmc_dev(host->mmc),
957 "%s: write time out (status = 0x%08x)\n",
958 __func__, stat);
959 mxcmci_softreset(host);
960 }
961
962 /* Mark transfer as erroneus and inform the upper layers */
963
964 if (host->data)
965 host->data->error = -ETIMEDOUT;
966 host->req = NULL;
967 host->cmd = NULL;
968 host->data = NULL;
969 mmc_request_done(host->mmc, req);
970}
971
972static const struct mmc_host_ops mxcmci_ops = {
973 .request = mxcmci_request,
974 .set_ios = mxcmci_set_ios,
975 .get_ro = mxcmci_get_ro,
976 .enable_sdio_irq = mxcmci_enable_sdio_irq,
977 .init_card = mxcmci_init_card,
978};
979
980static int mxcmci_probe(struct platform_device *pdev)
981{
982 struct mmc_host *mmc;
983 struct mxcmci_host *host;
984 struct resource *res;
985 int ret = 0, irq;
986 bool dat3_card_detect = false;
987 dma_cap_mask_t mask;
988 struct imxmmc_platform_data *pdata = pdev->dev.platform_data;
989
990 pr_info("i.MX/MPC512x SDHC driver\n");
991
992 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
993 irq = platform_get_irq(pdev, 0);
994 if (irq < 0)
995 return irq;
996
997 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
998 if (!mmc)
999 return -ENOMEM;
1000
1001 host = mmc_priv(mmc);
1002
1003 host->base = devm_ioremap_resource(&pdev->dev, res);
1004 if (IS_ERR(host->base)) {
1005 ret = PTR_ERR(host->base);
1006 goto out_free;
1007 }
1008
1009 host->phys_base = res->start;
1010
1011 ret = mmc_of_parse(mmc);
1012 if (ret)
1013 goto out_free;
1014 mmc->ops = &mxcmci_ops;
1015
1016 /* For devicetree parsing, the bus width is read from devicetree */
1017 if (pdata)
1018 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1019 else
1020 mmc->caps |= MMC_CAP_SDIO_IRQ;
1021
1022 /* MMC core transfer sizes tunable parameters */
1023 mmc->max_blk_size = 2048;
1024 mmc->max_blk_count = 65535;
1025 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1026 mmc->max_seg_size = mmc->max_req_size;
1027
1028 host->devtype = (uintptr_t)of_device_get_match_data(&pdev->dev);
1029
1030 /* adjust max_segs after devtype detection */
1031 if (!is_mpc512x_mmc(host))
1032 mmc->max_segs = 64;
1033
1034 host->mmc = mmc;
1035 host->pdata = pdata;
1036 spin_lock_init(&host->lock);
1037
1038 if (pdata)
1039 dat3_card_detect = pdata->dat3_card_detect;
1040 else if (mmc_card_is_removable(mmc)
1041 && !of_property_read_bool(pdev->dev.of_node, "cd-gpios"))
1042 dat3_card_detect = true;
1043
1044 ret = mmc_regulator_get_supply(mmc);
1045 if (ret)
1046 goto out_free;
1047
1048 if (!mmc->ocr_avail) {
1049 if (pdata && pdata->ocr_avail)
1050 mmc->ocr_avail = pdata->ocr_avail;
1051 else
1052 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1053 }
1054
1055 if (dat3_card_detect)
1056 host->default_irq_mask =
1057 INT_CARD_INSERTION_EN | INT_CARD_REMOVAL_EN;
1058 else
1059 host->default_irq_mask = 0;
1060
1061 host->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1062 if (IS_ERR(host->clk_ipg)) {
1063 ret = PTR_ERR(host->clk_ipg);
1064 goto out_free;
1065 }
1066
1067 host->clk_per = devm_clk_get(&pdev->dev, "per");
1068 if (IS_ERR(host->clk_per)) {
1069 ret = PTR_ERR(host->clk_per);
1070 goto out_free;
1071 }
1072
1073 ret = clk_prepare_enable(host->clk_per);
1074 if (ret)
1075 goto out_free;
1076
1077 ret = clk_prepare_enable(host->clk_ipg);
1078 if (ret)
1079 goto out_clk_per_put;
1080
1081 mxcmci_softreset(host);
1082
1083 host->rev_no = mxcmci_readw(host, MMC_REG_REV_NO);
1084 if (host->rev_no != 0x400) {
1085 ret = -ENODEV;
1086 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
1087 host->rev_no);
1088 goto out_clk_put;
1089 }
1090
1091 mmc->f_min = clk_get_rate(host->clk_per) >> 16;
1092 mmc->f_max = clk_get_rate(host->clk_per) >> 1;
1093
1094 /* recommended in data sheet */
1095 mxcmci_writew(host, 0x2db4, MMC_REG_READ_TO);
1096
1097 mxcmci_writel(host, host->default_irq_mask, MMC_REG_INT_CNTR);
1098
1099 if (!host->pdata) {
1100 host->dma = dma_request_chan(&pdev->dev, "rx-tx");
1101 if (IS_ERR(host->dma)) {
1102 if (PTR_ERR(host->dma) == -EPROBE_DEFER) {
1103 ret = -EPROBE_DEFER;
1104 goto out_clk_put;
1105 }
1106
1107 /* Ignore errors to fall back to PIO mode */
1108 host->dma = NULL;
1109 }
1110 } else {
1111 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1112 if (res) {
1113 host->dmareq = res->start;
1114 host->dma_data.peripheral_type = IMX_DMATYPE_SDHC;
1115 host->dma_data.priority = DMA_PRIO_LOW;
1116 host->dma_data.dma_request = host->dmareq;
1117 dma_cap_zero(mask);
1118 dma_cap_set(DMA_SLAVE, mask);
1119 host->dma = dma_request_channel(mask, filter, host);
1120 }
1121 }
1122 if (host->dma)
1123 mmc->max_seg_size = dma_get_max_seg_size(
1124 host->dma->device->dev);
1125 else
1126 dev_info(mmc_dev(host->mmc), "dma not available. Using PIO\n");
1127
1128 INIT_WORK(&host->datawork, mxcmci_datawork);
1129
1130 ret = devm_request_irq(&pdev->dev, irq, mxcmci_irq, 0,
1131 dev_name(&pdev->dev), host);
1132 if (ret)
1133 goto out_free_dma;
1134
1135 platform_set_drvdata(pdev, mmc);
1136
1137 if (host->pdata && host->pdata->init) {
1138 ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq,
1139 host->mmc);
1140 if (ret)
1141 goto out_free_dma;
1142 }
1143
1144 timer_setup(&host->watchdog, mxcmci_watchdog, 0);
1145
1146 ret = mmc_add_host(mmc);
1147 if (ret)
1148 goto out_free_dma;
1149
1150 return 0;
1151
1152out_free_dma:
1153 if (host->dma)
1154 dma_release_channel(host->dma);
1155
1156out_clk_put:
1157 clk_disable_unprepare(host->clk_ipg);
1158out_clk_per_put:
1159 clk_disable_unprepare(host->clk_per);
1160
1161out_free:
1162 mmc_free_host(mmc);
1163
1164 return ret;
1165}
1166
1167static int mxcmci_remove(struct platform_device *pdev)
1168{
1169 struct mmc_host *mmc = platform_get_drvdata(pdev);
1170 struct mxcmci_host *host = mmc_priv(mmc);
1171
1172 mmc_remove_host(mmc);
1173
1174 if (host->pdata && host->pdata->exit)
1175 host->pdata->exit(&pdev->dev, mmc);
1176
1177 if (host->dma)
1178 dma_release_channel(host->dma);
1179
1180 clk_disable_unprepare(host->clk_per);
1181 clk_disable_unprepare(host->clk_ipg);
1182
1183 mmc_free_host(mmc);
1184
1185 return 0;
1186}
1187
1188static int mxcmci_suspend(struct device *dev)
1189{
1190 struct mmc_host *mmc = dev_get_drvdata(dev);
1191 struct mxcmci_host *host = mmc_priv(mmc);
1192
1193 clk_disable_unprepare(host->clk_per);
1194 clk_disable_unprepare(host->clk_ipg);
1195 return 0;
1196}
1197
1198static int mxcmci_resume(struct device *dev)
1199{
1200 struct mmc_host *mmc = dev_get_drvdata(dev);
1201 struct mxcmci_host *host = mmc_priv(mmc);
1202 int ret;
1203
1204 ret = clk_prepare_enable(host->clk_per);
1205 if (ret)
1206 return ret;
1207
1208 ret = clk_prepare_enable(host->clk_ipg);
1209 if (ret)
1210 clk_disable_unprepare(host->clk_per);
1211
1212 return ret;
1213}
1214
1215static DEFINE_SIMPLE_DEV_PM_OPS(mxcmci_pm_ops, mxcmci_suspend, mxcmci_resume);
1216
1217static struct platform_driver mxcmci_driver = {
1218 .probe = mxcmci_probe,
1219 .remove = mxcmci_remove,
1220 .driver = {
1221 .name = DRIVER_NAME,
1222 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1223 .pm = pm_sleep_ptr(&mxcmci_pm_ops),
1224 .of_match_table = mxcmci_of_match,
1225 }
1226};
1227
1228module_platform_driver(mxcmci_driver);
1229
1230MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
1231MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1232MODULE_LICENSE("GPL");
1233MODULE_ALIAS("platform:mxc-mmc");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver
4 *
5 * This is a driver for the SDHC controller found in Freescale MX2/MX3
6 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
7 * Unlike the hardware found on MX1, this hardware just works and does
8 * not need all the quirks found in imxmmc.c, hence the separate driver.
9 *
10 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
11 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
12 *
13 * derived from pxamci.c by Russell King
14 */
15
16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/ioport.h>
19#include <linux/platform_device.h>
20#include <linux/highmem.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/blkdev.h>
24#include <linux/dma-mapping.h>
25#include <linux/mmc/host.h>
26#include <linux/mmc/card.h>
27#include <linux/delay.h>
28#include <linux/clk.h>
29#include <linux/io.h>
30#include <linux/regulator/consumer.h>
31#include <linux/dmaengine.h>
32#include <linux/types.h>
33#include <linux/of.h>
34#include <linux/of_dma.h>
35#include <linux/mmc/slot-gpio.h>
36
37#include <asm/dma.h>
38#include <asm/irq.h>
39#include <linux/platform_data/mmc-mxcmmc.h>
40
41#include <linux/dma/imx-dma.h>
42
43#define DRIVER_NAME "mxc-mmc"
44#define MXCMCI_TIMEOUT_MS 10000
45
46#define MMC_REG_STR_STP_CLK 0x00
47#define MMC_REG_STATUS 0x04
48#define MMC_REG_CLK_RATE 0x08
49#define MMC_REG_CMD_DAT_CONT 0x0C
50#define MMC_REG_RES_TO 0x10
51#define MMC_REG_READ_TO 0x14
52#define MMC_REG_BLK_LEN 0x18
53#define MMC_REG_NOB 0x1C
54#define MMC_REG_REV_NO 0x20
55#define MMC_REG_INT_CNTR 0x24
56#define MMC_REG_CMD 0x28
57#define MMC_REG_ARG 0x2C
58#define MMC_REG_RES_FIFO 0x34
59#define MMC_REG_BUFFER_ACCESS 0x38
60
61#define STR_STP_CLK_RESET (1 << 3)
62#define STR_STP_CLK_START_CLK (1 << 1)
63#define STR_STP_CLK_STOP_CLK (1 << 0)
64
65#define STATUS_CARD_INSERTION (1 << 31)
66#define STATUS_CARD_REMOVAL (1 << 30)
67#define STATUS_YBUF_EMPTY (1 << 29)
68#define STATUS_XBUF_EMPTY (1 << 28)
69#define STATUS_YBUF_FULL (1 << 27)
70#define STATUS_XBUF_FULL (1 << 26)
71#define STATUS_BUF_UND_RUN (1 << 25)
72#define STATUS_BUF_OVFL (1 << 24)
73#define STATUS_SDIO_INT_ACTIVE (1 << 14)
74#define STATUS_END_CMD_RESP (1 << 13)
75#define STATUS_WRITE_OP_DONE (1 << 12)
76#define STATUS_DATA_TRANS_DONE (1 << 11)
77#define STATUS_READ_OP_DONE (1 << 11)
78#define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
79#define STATUS_CARD_BUS_CLK_RUN (1 << 8)
80#define STATUS_BUF_READ_RDY (1 << 7)
81#define STATUS_BUF_WRITE_RDY (1 << 6)
82#define STATUS_RESP_CRC_ERR (1 << 5)
83#define STATUS_CRC_READ_ERR (1 << 3)
84#define STATUS_CRC_WRITE_ERR (1 << 2)
85#define STATUS_TIME_OUT_RESP (1 << 1)
86#define STATUS_TIME_OUT_READ (1 << 0)
87#define STATUS_ERR_MASK 0x2f
88
89#define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
90#define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
91#define CMD_DAT_CONT_START_READWAIT (1 << 10)
92#define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
93#define CMD_DAT_CONT_INIT (1 << 7)
94#define CMD_DAT_CONT_WRITE (1 << 4)
95#define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
96#define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
97#define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
98#define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
99
100#define INT_SDIO_INT_WKP_EN (1 << 18)
101#define INT_CARD_INSERTION_WKP_EN (1 << 17)
102#define INT_CARD_REMOVAL_WKP_EN (1 << 16)
103#define INT_CARD_INSERTION_EN (1 << 15)
104#define INT_CARD_REMOVAL_EN (1 << 14)
105#define INT_SDIO_IRQ_EN (1 << 13)
106#define INT_DAT0_EN (1 << 12)
107#define INT_BUF_READ_EN (1 << 4)
108#define INT_BUF_WRITE_EN (1 << 3)
109#define INT_END_CMD_RES_EN (1 << 2)
110#define INT_WRITE_OP_DONE_EN (1 << 1)
111#define INT_READ_OP_EN (1 << 0)
112
113enum mxcmci_type {
114 IMX21_MMC,
115 IMX31_MMC,
116 MPC512X_MMC,
117};
118
119struct mxcmci_host {
120 struct mmc_host *mmc;
121 void __iomem *base;
122 dma_addr_t phys_base;
123 int detect_irq;
124 struct dma_chan *dma;
125 struct dma_async_tx_descriptor *desc;
126 int do_dma;
127 int default_irq_mask;
128 int use_sdio;
129 unsigned int power_mode;
130 struct imxmmc_platform_data *pdata;
131
132 struct mmc_request *req;
133 struct mmc_command *cmd;
134 struct mmc_data *data;
135
136 unsigned int datasize;
137 unsigned int dma_dir;
138
139 u16 rev_no;
140 unsigned int cmdat;
141
142 struct clk *clk_ipg;
143 struct clk *clk_per;
144
145 int clock;
146
147 struct work_struct datawork;
148 spinlock_t lock;
149
150 int burstlen;
151 int dmareq;
152 struct dma_slave_config dma_slave_config;
153 struct imx_dma_data dma_data;
154
155 struct timer_list watchdog;
156 enum mxcmci_type devtype;
157};
158
159static const struct of_device_id mxcmci_of_match[] = {
160 {
161 .compatible = "fsl,imx21-mmc",
162 .data = (void *) IMX21_MMC,
163 }, {
164 .compatible = "fsl,imx31-mmc",
165 .data = (void *) IMX31_MMC,
166 }, {
167 .compatible = "fsl,mpc5121-sdhc",
168 .data = (void *) MPC512X_MMC,
169 }, {
170 /* sentinel */
171 }
172};
173MODULE_DEVICE_TABLE(of, mxcmci_of_match);
174
175static inline int is_imx31_mmc(struct mxcmci_host *host)
176{
177 return host->devtype == IMX31_MMC;
178}
179
180static inline int is_mpc512x_mmc(struct mxcmci_host *host)
181{
182 return host->devtype == MPC512X_MMC;
183}
184
185static inline u32 mxcmci_readl(struct mxcmci_host *host, int reg)
186{
187 if (IS_ENABLED(CONFIG_PPC_MPC512x))
188 return ioread32be(host->base + reg);
189 else
190 return readl(host->base + reg);
191}
192
193static inline void mxcmci_writel(struct mxcmci_host *host, u32 val, int reg)
194{
195 if (IS_ENABLED(CONFIG_PPC_MPC512x))
196 iowrite32be(val, host->base + reg);
197 else
198 writel(val, host->base + reg);
199}
200
201static inline u16 mxcmci_readw(struct mxcmci_host *host, int reg)
202{
203 if (IS_ENABLED(CONFIG_PPC_MPC512x))
204 return ioread32be(host->base + reg);
205 else
206 return readw(host->base + reg);
207}
208
209static inline void mxcmci_writew(struct mxcmci_host *host, u16 val, int reg)
210{
211 if (IS_ENABLED(CONFIG_PPC_MPC512x))
212 iowrite32be(val, host->base + reg);
213 else
214 writew(val, host->base + reg);
215}
216
217static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios);
218
219static void mxcmci_set_power(struct mxcmci_host *host, unsigned int vdd)
220{
221 if (!IS_ERR(host->mmc->supply.vmmc)) {
222 if (host->power_mode == MMC_POWER_UP)
223 mmc_regulator_set_ocr(host->mmc,
224 host->mmc->supply.vmmc, vdd);
225 else if (host->power_mode == MMC_POWER_OFF)
226 mmc_regulator_set_ocr(host->mmc,
227 host->mmc->supply.vmmc, 0);
228 }
229
230 if (host->pdata && host->pdata->setpower)
231 host->pdata->setpower(mmc_dev(host->mmc), vdd);
232}
233
234static inline int mxcmci_use_dma(struct mxcmci_host *host)
235{
236 return host->do_dma;
237}
238
239static void mxcmci_softreset(struct mxcmci_host *host)
240{
241 int i;
242
243 dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n");
244
245 /* reset sequence */
246 mxcmci_writew(host, STR_STP_CLK_RESET, MMC_REG_STR_STP_CLK);
247 mxcmci_writew(host, STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
248 MMC_REG_STR_STP_CLK);
249
250 for (i = 0; i < 8; i++)
251 mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK);
252
253 mxcmci_writew(host, 0xff, MMC_REG_RES_TO);
254}
255
256#if IS_ENABLED(CONFIG_PPC_MPC512x)
257static inline void buffer_swap32(u32 *buf, int len)
258{
259 int i;
260
261 for (i = 0; i < ((len + 3) / 4); i++) {
262 *buf = swab32(*buf);
263 buf++;
264 }
265}
266
267static void mxcmci_swap_buffers(struct mmc_data *data)
268{
269 struct sg_mapping_iter sgm;
270 u32 *buf;
271
272 sg_miter_start(&sgm, data->sg, data->sg_len,
273 SG_MITER_TO_SG | SG_MITER_FROM_SG);
274
275 while (sg_miter_next(&sgm)) {
276 buf = sgm.addr;
277 buffer_swap32(buf, sgm.length);
278 }
279
280 sg_miter_stop(&sgm);
281}
282#else
283static inline void mxcmci_swap_buffers(struct mmc_data *data) {}
284#endif
285
286static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
287{
288 unsigned int nob = data->blocks;
289 unsigned int blksz = data->blksz;
290 unsigned int datasize = nob * blksz;
291 struct scatterlist *sg;
292 enum dma_transfer_direction slave_dirn;
293 int i, nents;
294
295 host->data = data;
296 data->bytes_xfered = 0;
297
298 mxcmci_writew(host, nob, MMC_REG_NOB);
299 mxcmci_writew(host, blksz, MMC_REG_BLK_LEN);
300 host->datasize = datasize;
301
302 if (!mxcmci_use_dma(host))
303 return 0;
304
305 for_each_sg(data->sg, sg, data->sg_len, i) {
306 if (sg->offset & 3 || sg->length & 3 || sg->length < 512) {
307 host->do_dma = 0;
308 return 0;
309 }
310 }
311
312 if (data->flags & MMC_DATA_READ) {
313 host->dma_dir = DMA_FROM_DEVICE;
314 slave_dirn = DMA_DEV_TO_MEM;
315 } else {
316 host->dma_dir = DMA_TO_DEVICE;
317 slave_dirn = DMA_MEM_TO_DEV;
318
319 mxcmci_swap_buffers(data);
320 }
321
322 nents = dma_map_sg(host->dma->device->dev, data->sg,
323 data->sg_len, host->dma_dir);
324 if (nents != data->sg_len)
325 return -EINVAL;
326
327 host->desc = dmaengine_prep_slave_sg(host->dma,
328 data->sg, data->sg_len, slave_dirn,
329 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
330
331 if (!host->desc) {
332 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
333 host->dma_dir);
334 host->do_dma = 0;
335 return 0; /* Fall back to PIO */
336 }
337 wmb();
338
339 dmaengine_submit(host->desc);
340 dma_async_issue_pending(host->dma);
341
342 mod_timer(&host->watchdog, jiffies + msecs_to_jiffies(MXCMCI_TIMEOUT_MS));
343
344 return 0;
345}
346
347static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat);
348static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat);
349
350static void mxcmci_dma_callback(void *data)
351{
352 struct mxcmci_host *host = data;
353 u32 stat;
354
355 del_timer(&host->watchdog);
356
357 stat = mxcmci_readl(host, MMC_REG_STATUS);
358
359 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
360
361 mxcmci_data_done(host, stat);
362}
363
364static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
365 unsigned int cmdat)
366{
367 u32 int_cntr = host->default_irq_mask;
368 unsigned long flags;
369
370 WARN_ON(host->cmd != NULL);
371 host->cmd = cmd;
372
373 switch (mmc_resp_type(cmd)) {
374 case MMC_RSP_R1: /* short CRC, OPCODE */
375 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
376 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
377 break;
378 case MMC_RSP_R2: /* long 136 bit + CRC */
379 cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
380 break;
381 case MMC_RSP_R3: /* short */
382 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
383 break;
384 case MMC_RSP_NONE:
385 break;
386 default:
387 dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n",
388 mmc_resp_type(cmd));
389 cmd->error = -EINVAL;
390 return -EINVAL;
391 }
392
393 int_cntr = INT_END_CMD_RES_EN;
394
395 if (mxcmci_use_dma(host)) {
396 if (host->dma_dir == DMA_FROM_DEVICE) {
397 host->desc->callback = mxcmci_dma_callback;
398 host->desc->callback_param = host;
399 } else {
400 int_cntr |= INT_WRITE_OP_DONE_EN;
401 }
402 }
403
404 spin_lock_irqsave(&host->lock, flags);
405 if (host->use_sdio)
406 int_cntr |= INT_SDIO_IRQ_EN;
407 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
408 spin_unlock_irqrestore(&host->lock, flags);
409
410 mxcmci_writew(host, cmd->opcode, MMC_REG_CMD);
411 mxcmci_writel(host, cmd->arg, MMC_REG_ARG);
412 mxcmci_writew(host, cmdat, MMC_REG_CMD_DAT_CONT);
413
414 return 0;
415}
416
417static void mxcmci_finish_request(struct mxcmci_host *host,
418 struct mmc_request *req)
419{
420 u32 int_cntr = host->default_irq_mask;
421 unsigned long flags;
422
423 spin_lock_irqsave(&host->lock, flags);
424 if (host->use_sdio)
425 int_cntr |= INT_SDIO_IRQ_EN;
426 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
427 spin_unlock_irqrestore(&host->lock, flags);
428
429 host->req = NULL;
430 host->cmd = NULL;
431 host->data = NULL;
432
433 mmc_request_done(host->mmc, req);
434}
435
436static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
437{
438 struct mmc_data *data = host->data;
439 int data_error;
440
441 if (mxcmci_use_dma(host)) {
442 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
443 host->dma_dir);
444 mxcmci_swap_buffers(data);
445 }
446
447 if (stat & STATUS_ERR_MASK) {
448 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",
449 stat);
450 if (stat & STATUS_CRC_READ_ERR) {
451 dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__);
452 data->error = -EILSEQ;
453 } else if (stat & STATUS_CRC_WRITE_ERR) {
454 u32 err_code = (stat >> 9) & 0x3;
455 if (err_code == 2) { /* No CRC response */
456 dev_err(mmc_dev(host->mmc),
457 "%s: No CRC -ETIMEDOUT\n", __func__);
458 data->error = -ETIMEDOUT;
459 } else {
460 dev_err(mmc_dev(host->mmc),
461 "%s: -EILSEQ\n", __func__);
462 data->error = -EILSEQ;
463 }
464 } else if (stat & STATUS_TIME_OUT_READ) {
465 dev_err(mmc_dev(host->mmc),
466 "%s: read -ETIMEDOUT\n", __func__);
467 data->error = -ETIMEDOUT;
468 } else {
469 dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__);
470 data->error = -EIO;
471 }
472 } else {
473 data->bytes_xfered = host->datasize;
474 }
475
476 data_error = data->error;
477
478 host->data = NULL;
479
480 return data_error;
481}
482
483static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
484{
485 struct mmc_command *cmd = host->cmd;
486 int i;
487 u32 a, b, c;
488
489 if (!cmd)
490 return;
491
492 if (stat & STATUS_TIME_OUT_RESP) {
493 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
494 cmd->error = -ETIMEDOUT;
495 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
496 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
497 cmd->error = -EILSEQ;
498 }
499
500 if (cmd->flags & MMC_RSP_PRESENT) {
501 if (cmd->flags & MMC_RSP_136) {
502 for (i = 0; i < 4; i++) {
503 a = mxcmci_readw(host, MMC_REG_RES_FIFO);
504 b = mxcmci_readw(host, MMC_REG_RES_FIFO);
505 cmd->resp[i] = a << 16 | b;
506 }
507 } else {
508 a = mxcmci_readw(host, MMC_REG_RES_FIFO);
509 b = mxcmci_readw(host, MMC_REG_RES_FIFO);
510 c = mxcmci_readw(host, MMC_REG_RES_FIFO);
511 cmd->resp[0] = a << 24 | b << 8 | c >> 8;
512 }
513 }
514}
515
516static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
517{
518 u32 stat;
519 unsigned long timeout = jiffies + HZ;
520
521 do {
522 stat = mxcmci_readl(host, MMC_REG_STATUS);
523 if (stat & STATUS_ERR_MASK)
524 return stat;
525 if (time_after(jiffies, timeout)) {
526 mxcmci_softreset(host);
527 mxcmci_set_clk_rate(host, host->clock);
528 return STATUS_TIME_OUT_READ;
529 }
530 if (stat & mask)
531 return 0;
532 cpu_relax();
533 } while (1);
534}
535
536static int mxcmci_pull(struct mxcmci_host *host, u32 *buf, int bytes)
537{
538 unsigned int stat;
539
540 while (bytes > 3) {
541 stat = mxcmci_poll_status(host,
542 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
543 if (stat)
544 return stat;
545 *buf++ = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS));
546 bytes -= 4;
547 }
548
549 if (bytes) {
550 u8 *b = (u8 *)buf;
551 u32 tmp;
552
553 stat = mxcmci_poll_status(host,
554 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
555 if (stat)
556 return stat;
557 tmp = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS));
558 memcpy(b, &tmp, bytes);
559 }
560
561 return 0;
562}
563
564static int mxcmci_push(struct mxcmci_host *host, u32 *buf, int bytes)
565{
566 unsigned int stat;
567
568 while (bytes > 3) {
569 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
570 if (stat)
571 return stat;
572 mxcmci_writel(host, cpu_to_le32(*buf++), MMC_REG_BUFFER_ACCESS);
573 bytes -= 4;
574 }
575
576 if (bytes) {
577 u8 *b = (u8 *)buf;
578 u32 tmp;
579
580 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
581 if (stat)
582 return stat;
583
584 memcpy(&tmp, b, bytes);
585 mxcmci_writel(host, cpu_to_le32(tmp), MMC_REG_BUFFER_ACCESS);
586 }
587
588 return mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
589}
590
591static int mxcmci_transfer_data(struct mxcmci_host *host)
592{
593 struct mmc_data *data = host->req->data;
594 struct sg_mapping_iter sgm;
595 int stat;
596 u32 *buf;
597
598 host->data = data;
599 host->datasize = 0;
600 sg_miter_start(&sgm, data->sg, data->sg_len,
601 (data->flags & MMC_DATA_READ) ? SG_MITER_TO_SG : SG_MITER_FROM_SG);
602
603 if (data->flags & MMC_DATA_READ) {
604 while (sg_miter_next(&sgm)) {
605 buf = sgm.addr;
606 stat = mxcmci_pull(host, buf, sgm.length);
607 if (stat)
608 goto transfer_error;
609 host->datasize += sgm.length;
610 }
611 } else {
612 while (sg_miter_next(&sgm)) {
613 buf = sgm.addr;
614 stat = mxcmci_push(host, buf, sgm.length);
615 if (stat)
616 goto transfer_error;
617 host->datasize += sgm.length;
618 }
619 stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
620 if (stat)
621 goto transfer_error;
622 }
623
624transfer_error:
625 sg_miter_stop(&sgm);
626 return stat;
627}
628
629static void mxcmci_datawork(struct work_struct *work)
630{
631 struct mxcmci_host *host = container_of(work, struct mxcmci_host,
632 datawork);
633 int datastat = mxcmci_transfer_data(host);
634
635 mxcmci_writel(host, STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
636 MMC_REG_STATUS);
637 mxcmci_finish_data(host, datastat);
638
639 if (host->req->stop) {
640 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
641 mxcmci_finish_request(host, host->req);
642 return;
643 }
644 } else {
645 mxcmci_finish_request(host, host->req);
646 }
647}
648
649static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat)
650{
651 struct mmc_request *req;
652 int data_error;
653 unsigned long flags;
654
655 spin_lock_irqsave(&host->lock, flags);
656
657 if (!host->data) {
658 spin_unlock_irqrestore(&host->lock, flags);
659 return;
660 }
661
662 if (!host->req) {
663 spin_unlock_irqrestore(&host->lock, flags);
664 return;
665 }
666
667 req = host->req;
668 if (!req->stop)
669 host->req = NULL; /* we will handle finish req below */
670
671 data_error = mxcmci_finish_data(host, stat);
672
673 spin_unlock_irqrestore(&host->lock, flags);
674
675 if (data_error)
676 return;
677
678 mxcmci_read_response(host, stat);
679 host->cmd = NULL;
680
681 if (req->stop) {
682 if (mxcmci_start_cmd(host, req->stop, 0)) {
683 mxcmci_finish_request(host, req);
684 return;
685 }
686 } else {
687 mxcmci_finish_request(host, req);
688 }
689}
690
691static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
692{
693 mxcmci_read_response(host, stat);
694 host->cmd = NULL;
695
696 if (!host->data && host->req) {
697 mxcmci_finish_request(host, host->req);
698 return;
699 }
700
701 /* For the DMA case the DMA engine handles the data transfer
702 * automatically. For non DMA we have to do it ourselves.
703 * Don't do it in interrupt context though.
704 */
705 if (!mxcmci_use_dma(host) && host->data)
706 schedule_work(&host->datawork);
707
708}
709
710static irqreturn_t mxcmci_irq(int irq, void *devid)
711{
712 struct mxcmci_host *host = devid;
713 bool sdio_irq;
714 u32 stat;
715
716 stat = mxcmci_readl(host, MMC_REG_STATUS);
717 mxcmci_writel(host,
718 stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE |
719 STATUS_WRITE_OP_DONE),
720 MMC_REG_STATUS);
721
722 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
723
724 spin_lock(&host->lock);
725 sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio;
726 spin_unlock(&host->lock);
727
728 if (mxcmci_use_dma(host) && (stat & (STATUS_WRITE_OP_DONE)))
729 mxcmci_writel(host, STATUS_WRITE_OP_DONE, MMC_REG_STATUS);
730
731 if (sdio_irq) {
732 mxcmci_writel(host, STATUS_SDIO_INT_ACTIVE, MMC_REG_STATUS);
733 mmc_signal_sdio_irq(host->mmc);
734 }
735
736 if (stat & STATUS_END_CMD_RESP)
737 mxcmci_cmd_done(host, stat);
738
739 if (mxcmci_use_dma(host) && (stat & STATUS_WRITE_OP_DONE)) {
740 del_timer(&host->watchdog);
741 mxcmci_data_done(host, stat);
742 }
743
744 if (host->default_irq_mask &&
745 (stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL)))
746 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
747
748 return IRQ_HANDLED;
749}
750
751static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req)
752{
753 struct mxcmci_host *host = mmc_priv(mmc);
754 unsigned int cmdat = host->cmdat;
755 int error;
756
757 WARN_ON(host->req != NULL);
758
759 host->req = req;
760 host->cmdat &= ~CMD_DAT_CONT_INIT;
761
762 if (host->dma)
763 host->do_dma = 1;
764
765 if (req->data) {
766 error = mxcmci_setup_data(host, req->data);
767 if (error) {
768 req->cmd->error = error;
769 goto out;
770 }
771
772
773 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
774
775 if (req->data->flags & MMC_DATA_WRITE)
776 cmdat |= CMD_DAT_CONT_WRITE;
777 }
778
779 error = mxcmci_start_cmd(host, req->cmd, cmdat);
780
781out:
782 if (error)
783 mxcmci_finish_request(host, req);
784}
785
786static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
787{
788 unsigned int divider;
789 int prescaler = 0;
790 unsigned int clk_in = clk_get_rate(host->clk_per);
791
792 while (prescaler <= 0x800) {
793 for (divider = 1; divider <= 0xF; divider++) {
794 int x;
795
796 x = (clk_in / (divider + 1));
797
798 if (prescaler)
799 x /= (prescaler * 2);
800
801 if (x <= clk_ios)
802 break;
803 }
804 if (divider < 0x10)
805 break;
806
807 if (prescaler == 0)
808 prescaler = 1;
809 else
810 prescaler <<= 1;
811 }
812
813 mxcmci_writew(host, (prescaler << 4) | divider, MMC_REG_CLK_RATE);
814
815 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n",
816 prescaler, divider, clk_in, clk_ios);
817}
818
819static int mxcmci_setup_dma(struct mmc_host *mmc)
820{
821 struct mxcmci_host *host = mmc_priv(mmc);
822 struct dma_slave_config *config = &host->dma_slave_config;
823
824 config->dst_addr = host->phys_base + MMC_REG_BUFFER_ACCESS;
825 config->src_addr = host->phys_base + MMC_REG_BUFFER_ACCESS;
826 config->dst_addr_width = 4;
827 config->src_addr_width = 4;
828 config->dst_maxburst = host->burstlen;
829 config->src_maxburst = host->burstlen;
830 config->device_fc = false;
831
832 return dmaengine_slave_config(host->dma, config);
833}
834
835static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
836{
837 struct mxcmci_host *host = mmc_priv(mmc);
838 int burstlen, ret;
839
840 /*
841 * use burstlen of 64 (16 words) in 4 bit mode (--> reg value 0)
842 * use burstlen of 16 (4 words) in 1 bit mode (--> reg value 16)
843 */
844 if (ios->bus_width == MMC_BUS_WIDTH_4)
845 burstlen = 16;
846 else
847 burstlen = 4;
848
849 if (mxcmci_use_dma(host) && burstlen != host->burstlen) {
850 host->burstlen = burstlen;
851 ret = mxcmci_setup_dma(mmc);
852 if (ret) {
853 dev_err(mmc_dev(host->mmc),
854 "failed to config DMA channel. Falling back to PIO\n");
855 dma_release_channel(host->dma);
856 host->do_dma = 0;
857 host->dma = NULL;
858 }
859 }
860
861 if (ios->bus_width == MMC_BUS_WIDTH_4)
862 host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
863 else
864 host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
865
866 if (host->power_mode != ios->power_mode) {
867 host->power_mode = ios->power_mode;
868 mxcmci_set_power(host, ios->vdd);
869
870 if (ios->power_mode == MMC_POWER_ON)
871 host->cmdat |= CMD_DAT_CONT_INIT;
872 }
873
874 if (ios->clock) {
875 mxcmci_set_clk_rate(host, ios->clock);
876 mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK);
877 } else {
878 mxcmci_writew(host, STR_STP_CLK_STOP_CLK, MMC_REG_STR_STP_CLK);
879 }
880
881 host->clock = ios->clock;
882}
883
884static irqreturn_t mxcmci_detect_irq(int irq, void *data)
885{
886 struct mmc_host *mmc = data;
887
888 dev_dbg(mmc_dev(mmc), "%s\n", __func__);
889
890 mmc_detect_change(mmc, msecs_to_jiffies(250));
891 return IRQ_HANDLED;
892}
893
894static int mxcmci_get_ro(struct mmc_host *mmc)
895{
896 struct mxcmci_host *host = mmc_priv(mmc);
897
898 if (host->pdata && host->pdata->get_ro)
899 return !!host->pdata->get_ro(mmc_dev(mmc));
900 /*
901 * If board doesn't support read only detection (no mmc_gpio
902 * context or gpio is invalid), then let the mmc core decide
903 * what to do.
904 */
905 return mmc_gpio_get_ro(mmc);
906}
907
908static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
909{
910 struct mxcmci_host *host = mmc_priv(mmc);
911 unsigned long flags;
912 u32 int_cntr;
913
914 spin_lock_irqsave(&host->lock, flags);
915 host->use_sdio = enable;
916 int_cntr = mxcmci_readl(host, MMC_REG_INT_CNTR);
917
918 if (enable)
919 int_cntr |= INT_SDIO_IRQ_EN;
920 else
921 int_cntr &= ~INT_SDIO_IRQ_EN;
922
923 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
924 spin_unlock_irqrestore(&host->lock, flags);
925}
926
927static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card)
928{
929 struct mxcmci_host *mxcmci = mmc_priv(host);
930
931 /*
932 * MX3 SoCs have a silicon bug which corrupts CRC calculation of
933 * multi-block transfers when connected SDIO peripheral doesn't
934 * drive the BUSY line as required by the specs.
935 * One way to prevent this is to only allow 1-bit transfers.
936 */
937
938 if (is_imx31_mmc(mxcmci) && mmc_card_sdio(card))
939 host->caps &= ~MMC_CAP_4_BIT_DATA;
940 else
941 host->caps |= MMC_CAP_4_BIT_DATA;
942}
943
944static bool filter(struct dma_chan *chan, void *param)
945{
946 struct mxcmci_host *host = param;
947
948 if (!imx_dma_is_general_purpose(chan))
949 return false;
950
951 chan->private = &host->dma_data;
952
953 return true;
954}
955
956static void mxcmci_watchdog(struct timer_list *t)
957{
958 struct mxcmci_host *host = from_timer(host, t, watchdog);
959 struct mmc_request *req = host->req;
960 unsigned int stat = mxcmci_readl(host, MMC_REG_STATUS);
961
962 if (host->dma_dir == DMA_FROM_DEVICE) {
963 dmaengine_terminate_all(host->dma);
964 dev_err(mmc_dev(host->mmc),
965 "%s: read time out (status = 0x%08x)\n",
966 __func__, stat);
967 } else {
968 dev_err(mmc_dev(host->mmc),
969 "%s: write time out (status = 0x%08x)\n",
970 __func__, stat);
971 mxcmci_softreset(host);
972 }
973
974 /* Mark transfer as erroneus and inform the upper layers */
975
976 if (host->data)
977 host->data->error = -ETIMEDOUT;
978 host->req = NULL;
979 host->cmd = NULL;
980 host->data = NULL;
981 mmc_request_done(host->mmc, req);
982}
983
984static const struct mmc_host_ops mxcmci_ops = {
985 .request = mxcmci_request,
986 .set_ios = mxcmci_set_ios,
987 .get_ro = mxcmci_get_ro,
988 .enable_sdio_irq = mxcmci_enable_sdio_irq,
989 .init_card = mxcmci_init_card,
990};
991
992static int mxcmci_probe(struct platform_device *pdev)
993{
994 struct mmc_host *mmc;
995 struct mxcmci_host *host;
996 struct resource *res;
997 int ret = 0, irq;
998 bool dat3_card_detect = false;
999 dma_cap_mask_t mask;
1000 struct imxmmc_platform_data *pdata = pdev->dev.platform_data;
1001
1002 pr_info("i.MX/MPC512x SDHC driver\n");
1003
1004 irq = platform_get_irq(pdev, 0);
1005 if (irq < 0)
1006 return irq;
1007
1008 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1009 if (!mmc)
1010 return -ENOMEM;
1011
1012 host = mmc_priv(mmc);
1013
1014 host->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1015 if (IS_ERR(host->base)) {
1016 ret = PTR_ERR(host->base);
1017 goto out_free;
1018 }
1019
1020 host->phys_base = res->start;
1021
1022 ret = mmc_of_parse(mmc);
1023 if (ret)
1024 goto out_free;
1025 mmc->ops = &mxcmci_ops;
1026
1027 /* For devicetree parsing, the bus width is read from devicetree */
1028 if (pdata)
1029 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1030 else
1031 mmc->caps |= MMC_CAP_SDIO_IRQ;
1032
1033 /* MMC core transfer sizes tunable parameters */
1034 mmc->max_blk_size = 2048;
1035 mmc->max_blk_count = 65535;
1036 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1037 mmc->max_seg_size = mmc->max_req_size;
1038
1039 host->devtype = (uintptr_t)of_device_get_match_data(&pdev->dev);
1040
1041 /* adjust max_segs after devtype detection */
1042 if (!is_mpc512x_mmc(host))
1043 mmc->max_segs = 64;
1044
1045 host->mmc = mmc;
1046 host->pdata = pdata;
1047 spin_lock_init(&host->lock);
1048
1049 if (pdata)
1050 dat3_card_detect = pdata->dat3_card_detect;
1051 else if (mmc_card_is_removable(mmc)
1052 && !of_property_read_bool(pdev->dev.of_node, "cd-gpios"))
1053 dat3_card_detect = true;
1054
1055 ret = mmc_regulator_get_supply(mmc);
1056 if (ret)
1057 goto out_free;
1058
1059 if (!mmc->ocr_avail) {
1060 if (pdata && pdata->ocr_avail)
1061 mmc->ocr_avail = pdata->ocr_avail;
1062 else
1063 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1064 }
1065
1066 if (dat3_card_detect)
1067 host->default_irq_mask =
1068 INT_CARD_INSERTION_EN | INT_CARD_REMOVAL_EN;
1069 else
1070 host->default_irq_mask = 0;
1071
1072 host->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1073 if (IS_ERR(host->clk_ipg)) {
1074 ret = PTR_ERR(host->clk_ipg);
1075 goto out_free;
1076 }
1077
1078 host->clk_per = devm_clk_get(&pdev->dev, "per");
1079 if (IS_ERR(host->clk_per)) {
1080 ret = PTR_ERR(host->clk_per);
1081 goto out_free;
1082 }
1083
1084 ret = clk_prepare_enable(host->clk_per);
1085 if (ret)
1086 goto out_free;
1087
1088 ret = clk_prepare_enable(host->clk_ipg);
1089 if (ret)
1090 goto out_clk_per_put;
1091
1092 mxcmci_softreset(host);
1093
1094 host->rev_no = mxcmci_readw(host, MMC_REG_REV_NO);
1095 if (host->rev_no != 0x400) {
1096 ret = -ENODEV;
1097 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
1098 host->rev_no);
1099 goto out_clk_put;
1100 }
1101
1102 mmc->f_min = clk_get_rate(host->clk_per) >> 16;
1103 mmc->f_max = clk_get_rate(host->clk_per) >> 1;
1104
1105 /* recommended in data sheet */
1106 mxcmci_writew(host, 0x2db4, MMC_REG_READ_TO);
1107
1108 mxcmci_writel(host, host->default_irq_mask, MMC_REG_INT_CNTR);
1109
1110 if (!host->pdata) {
1111 host->dma = dma_request_chan(&pdev->dev, "rx-tx");
1112 if (IS_ERR(host->dma)) {
1113 if (PTR_ERR(host->dma) == -EPROBE_DEFER) {
1114 ret = -EPROBE_DEFER;
1115 goto out_clk_put;
1116 }
1117
1118 /* Ignore errors to fall back to PIO mode */
1119 host->dma = NULL;
1120 }
1121 } else {
1122 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1123 if (res) {
1124 host->dmareq = res->start;
1125 host->dma_data.peripheral_type = IMX_DMATYPE_SDHC;
1126 host->dma_data.priority = DMA_PRIO_LOW;
1127 host->dma_data.dma_request = host->dmareq;
1128 dma_cap_zero(mask);
1129 dma_cap_set(DMA_SLAVE, mask);
1130 host->dma = dma_request_channel(mask, filter, host);
1131 }
1132 }
1133 if (host->dma)
1134 mmc->max_seg_size = dma_get_max_seg_size(
1135 host->dma->device->dev);
1136 else
1137 dev_info(mmc_dev(host->mmc), "dma not available. Using PIO\n");
1138
1139 INIT_WORK(&host->datawork, mxcmci_datawork);
1140
1141 ret = devm_request_irq(&pdev->dev, irq, mxcmci_irq, 0,
1142 dev_name(&pdev->dev), host);
1143 if (ret)
1144 goto out_free_dma;
1145
1146 platform_set_drvdata(pdev, mmc);
1147
1148 if (host->pdata && host->pdata->init) {
1149 ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq,
1150 host->mmc);
1151 if (ret)
1152 goto out_free_dma;
1153 }
1154
1155 timer_setup(&host->watchdog, mxcmci_watchdog, 0);
1156
1157 ret = mmc_add_host(mmc);
1158 if (ret)
1159 goto out_free_dma;
1160
1161 return 0;
1162
1163out_free_dma:
1164 if (host->dma)
1165 dma_release_channel(host->dma);
1166
1167out_clk_put:
1168 clk_disable_unprepare(host->clk_ipg);
1169out_clk_per_put:
1170 clk_disable_unprepare(host->clk_per);
1171
1172out_free:
1173 mmc_free_host(mmc);
1174
1175 return ret;
1176}
1177
1178static void mxcmci_remove(struct platform_device *pdev)
1179{
1180 struct mmc_host *mmc = platform_get_drvdata(pdev);
1181 struct mxcmci_host *host = mmc_priv(mmc);
1182
1183 mmc_remove_host(mmc);
1184
1185 if (host->pdata && host->pdata->exit)
1186 host->pdata->exit(&pdev->dev, mmc);
1187
1188 if (host->dma)
1189 dma_release_channel(host->dma);
1190
1191 clk_disable_unprepare(host->clk_per);
1192 clk_disable_unprepare(host->clk_ipg);
1193
1194 mmc_free_host(mmc);
1195}
1196
1197static int mxcmci_suspend(struct device *dev)
1198{
1199 struct mmc_host *mmc = dev_get_drvdata(dev);
1200 struct mxcmci_host *host = mmc_priv(mmc);
1201
1202 clk_disable_unprepare(host->clk_per);
1203 clk_disable_unprepare(host->clk_ipg);
1204 return 0;
1205}
1206
1207static int mxcmci_resume(struct device *dev)
1208{
1209 struct mmc_host *mmc = dev_get_drvdata(dev);
1210 struct mxcmci_host *host = mmc_priv(mmc);
1211 int ret;
1212
1213 ret = clk_prepare_enable(host->clk_per);
1214 if (ret)
1215 return ret;
1216
1217 ret = clk_prepare_enable(host->clk_ipg);
1218 if (ret)
1219 clk_disable_unprepare(host->clk_per);
1220
1221 return ret;
1222}
1223
1224static DEFINE_SIMPLE_DEV_PM_OPS(mxcmci_pm_ops, mxcmci_suspend, mxcmci_resume);
1225
1226static struct platform_driver mxcmci_driver = {
1227 .probe = mxcmci_probe,
1228 .remove = mxcmci_remove,
1229 .driver = {
1230 .name = DRIVER_NAME,
1231 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1232 .pm = pm_sleep_ptr(&mxcmci_pm_ops),
1233 .of_match_table = mxcmci_of_match,
1234 }
1235};
1236
1237module_platform_driver(mxcmci_driver);
1238
1239MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
1240MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1241MODULE_LICENSE("GPL");
1242MODULE_ALIAS("platform:mxc-mmc");