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1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __DAL_HW_SHARED_H__
27#define __DAL_HW_SHARED_H__
28
29#include "os_types.h"
30#include "fixed31_32.h"
31#include "dc_hw_types.h"
32
33/******************************************************************************
34 * Data types shared between different Virtual HW blocks
35 ******************************************************************************/
36
37#define MAX_AUDIOS 7
38
39/**
40 * @MAX_PIPES:
41 *
42 * Every ASIC support a fixed number of pipes; MAX_PIPES defines a large number
43 * to be used inside loops and for determining array sizes.
44 */
45#define MAX_PIPES 6
46#define MAX_DIG_LINK_ENCODERS 7
47#define MAX_DWB_PIPES 1
48#define MAX_HPO_DP2_ENCODERS 4
49#define MAX_HPO_DP2_LINK_ENCODERS 2
50
51struct gamma_curve {
52 uint32_t offset;
53 uint32_t segments_num;
54};
55
56struct curve_points {
57 struct fixed31_32 x;
58 struct fixed31_32 y;
59 struct fixed31_32 offset;
60 struct fixed31_32 slope;
61
62 uint32_t custom_float_x;
63 uint32_t custom_float_y;
64 uint32_t custom_float_offset;
65 uint32_t custom_float_slope;
66};
67
68struct curve_points3 {
69 struct curve_points red;
70 struct curve_points green;
71 struct curve_points blue;
72};
73
74struct pwl_result_data {
75 struct fixed31_32 red;
76 struct fixed31_32 green;
77 struct fixed31_32 blue;
78
79 struct fixed31_32 delta_red;
80 struct fixed31_32 delta_green;
81 struct fixed31_32 delta_blue;
82
83 uint32_t red_reg;
84 uint32_t green_reg;
85 uint32_t blue_reg;
86
87 uint32_t delta_red_reg;
88 uint32_t delta_green_reg;
89 uint32_t delta_blue_reg;
90};
91
92struct dc_rgb {
93 uint32_t red;
94 uint32_t green;
95 uint32_t blue;
96};
97
98struct tetrahedral_17x17x17 {
99 struct dc_rgb lut0[1229];
100 struct dc_rgb lut1[1228];
101 struct dc_rgb lut2[1228];
102 struct dc_rgb lut3[1228];
103};
104struct tetrahedral_9x9x9 {
105 struct dc_rgb lut0[183];
106 struct dc_rgb lut1[182];
107 struct dc_rgb lut2[182];
108 struct dc_rgb lut3[182];
109};
110
111struct tetrahedral_params {
112 union {
113 struct tetrahedral_17x17x17 tetrahedral_17;
114 struct tetrahedral_9x9x9 tetrahedral_9;
115 };
116 bool use_tetrahedral_9;
117 bool use_12bits;
118
119};
120
121/* arr_curve_points - regamma regions/segments specification
122 * arr_points - beginning and end point specified separately (only one on DCE)
123 * corner_points - beginning and end point for all 3 colors (DCN)
124 * rgb_resulted - final curve
125 */
126struct pwl_params {
127 struct gamma_curve arr_curve_points[34];
128 union {
129 struct curve_points arr_points[2];
130 struct curve_points3 corner_points[2];
131 };
132 struct pwl_result_data rgb_resulted[256 + 3];
133 uint32_t hw_points_num;
134};
135
136/* move to dpp
137 * while we are moving functionality out of opp to dpp to align
138 * HW programming to HW IP, we define these struct in hw_shared
139 * so we can still compile while refactoring
140 */
141
142enum lb_pixel_depth {
143 /* do not change the values because it is used as bit vector */
144 LB_PIXEL_DEPTH_18BPP = 1,
145 LB_PIXEL_DEPTH_24BPP = 2,
146 LB_PIXEL_DEPTH_30BPP = 4,
147 LB_PIXEL_DEPTH_36BPP = 8
148};
149
150enum graphics_csc_adjust_type {
151 GRAPHICS_CSC_ADJUST_TYPE_BYPASS = 0,
152 GRAPHICS_CSC_ADJUST_TYPE_HW, /* without adjustments */
153 GRAPHICS_CSC_ADJUST_TYPE_SW /*use adjustments */
154};
155
156enum ipp_degamma_mode {
157 IPP_DEGAMMA_MODE_BYPASS,
158 IPP_DEGAMMA_MODE_HW_sRGB,
159 IPP_DEGAMMA_MODE_HW_xvYCC,
160 IPP_DEGAMMA_MODE_USER_PWL
161};
162
163enum gamcor_mode {
164 GAMCOR_MODE_BYPASS,
165 GAMCOR_MODE_RESERVED_1,
166 GAMCOR_MODE_USER_PWL,
167 GAMCOR_MODE_RESERVED_3
168};
169
170enum ipp_output_format {
171 IPP_OUTPUT_FORMAT_12_BIT_FIX,
172 IPP_OUTPUT_FORMAT_16_BIT_BYPASS,
173 IPP_OUTPUT_FORMAT_FLOAT
174};
175
176enum expansion_mode {
177 EXPANSION_MODE_DYNAMIC,
178 EXPANSION_MODE_ZERO
179};
180
181struct default_adjustment {
182 enum lb_pixel_depth lb_color_depth;
183 enum dc_color_space out_color_space;
184 enum dc_color_space in_color_space;
185 enum dc_color_depth color_depth;
186 enum pixel_format surface_pixel_format;
187 enum graphics_csc_adjust_type csc_adjust_type;
188 bool force_hw_default;
189};
190
191
192struct out_csc_color_matrix {
193 enum dc_color_space color_space;
194 uint16_t regval[12];
195};
196
197enum gamut_remap_select {
198 GAMUT_REMAP_BYPASS = 0,
199 GAMUT_REMAP_COEFF,
200 GAMUT_REMAP_COMA_COEFF,
201 GAMUT_REMAP_COMB_COEFF
202};
203
204enum opp_regamma {
205 OPP_REGAMMA_BYPASS = 0,
206 OPP_REGAMMA_SRGB,
207 OPP_REGAMMA_XVYCC,
208 OPP_REGAMMA_USER
209};
210
211enum optc_dsc_mode {
212 OPTC_DSC_DISABLED = 0,
213 OPTC_DSC_ENABLED_444 = 1, /* 'RGB 444' or 'Simple YCbCr 4:2:2' (4:2:2 upsampled to 4:4:4) */
214 OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED = 2 /* Native 4:2:2 or 4:2:0 */
215};
216
217struct dc_bias_and_scale {
218 uint16_t scale_red;
219 uint16_t bias_red;
220 uint16_t scale_green;
221 uint16_t bias_green;
222 uint16_t scale_blue;
223 uint16_t bias_blue;
224};
225
226enum test_pattern_dyn_range {
227 TEST_PATTERN_DYN_RANGE_VESA = 0,
228 TEST_PATTERN_DYN_RANGE_CEA
229};
230
231enum test_pattern_mode {
232 TEST_PATTERN_MODE_COLORSQUARES_RGB = 0,
233 TEST_PATTERN_MODE_COLORSQUARES_YCBCR601,
234 TEST_PATTERN_MODE_COLORSQUARES_YCBCR709,
235 TEST_PATTERN_MODE_VERTICALBARS,
236 TEST_PATTERN_MODE_HORIZONTALBARS,
237 TEST_PATTERN_MODE_SINGLERAMP_RGB,
238 TEST_PATTERN_MODE_DUALRAMP_RGB,
239 TEST_PATTERN_MODE_XR_BIAS_RGB
240};
241
242enum test_pattern_color_format {
243 TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0,
244 TEST_PATTERN_COLOR_FORMAT_BPC_8,
245 TEST_PATTERN_COLOR_FORMAT_BPC_10,
246 TEST_PATTERN_COLOR_FORMAT_BPC_12
247};
248
249enum controller_dp_test_pattern {
250 CONTROLLER_DP_TEST_PATTERN_D102 = 0,
251 CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR,
252 CONTROLLER_DP_TEST_PATTERN_PRBS7,
253 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES,
254 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS,
255 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS,
256 CONTROLLER_DP_TEST_PATTERN_COLORRAMP,
257 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
258 CONTROLLER_DP_TEST_PATTERN_RESERVED_8,
259 CONTROLLER_DP_TEST_PATTERN_RESERVED_9,
260 CONTROLLER_DP_TEST_PATTERN_RESERVED_A,
261 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA,
262 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR
263};
264
265enum controller_dp_color_space {
266 CONTROLLER_DP_COLOR_SPACE_RGB,
267 CONTROLLER_DP_COLOR_SPACE_YCBCR601,
268 CONTROLLER_DP_COLOR_SPACE_YCBCR709,
269 CONTROLLER_DP_COLOR_SPACE_UDEFINED
270};
271
272enum dc_lut_mode {
273 LUT_BYPASS,
274 LUT_RAM_A,
275 LUT_RAM_B
276};
277
278enum symclk_state {
279 SYMCLK_OFF_TX_OFF,
280 SYMCLK_ON_TX_ON,
281 SYMCLK_ON_TX_OFF,
282};
283
284struct phy_state {
285 struct {
286 uint8_t otg : 1;
287 uint8_t reserved : 7;
288 } symclk_ref_cnts;
289 enum symclk_state symclk_state;
290};
291
292/**
293 * speakersToChannels
294 *
295 * @brief
296 * translate speakers to channels
297 *
298 * FL - Front Left
299 * FR - Front Right
300 * RL - Rear Left
301 * RR - Rear Right
302 * RC - Rear Center
303 * FC - Front Center
304 * FLC - Front Left Center
305 * FRC - Front Right Center
306 * RLC - Rear Left Center
307 * RRC - Rear Right Center
308 * LFE - Low Freq Effect
309 *
310 * FC
311 * FLC FRC
312 * FL FR
313 *
314 * LFE
315 * ()
316 *
317 *
318 * RL RR
319 * RLC RRC
320 * RC
321 *
322 * ch 8 7 6 5 4 3 2 1
323 * 0b00000011 - - - - - - FR FL
324 * 0b00000111 - - - - - LFE FR FL
325 * 0b00001011 - - - - FC - FR FL
326 * 0b00001111 - - - - FC LFE FR FL
327 * 0b00010011 - - - RC - - FR FL
328 * 0b00010111 - - - RC - LFE FR FL
329 * 0b00011011 - - - RC FC - FR FL
330 * 0b00011111 - - - RC FC LFE FR FL
331 * 0b00110011 - - RR RL - - FR FL
332 * 0b00110111 - - RR RL - LFE FR FL
333 * 0b00111011 - - RR RL FC - FR FL
334 * 0b00111111 - - RR RL FC LFE FR FL
335 * 0b01110011 - RC RR RL - - FR FL
336 * 0b01110111 - RC RR RL - LFE FR FL
337 * 0b01111011 - RC RR RL FC - FR FL
338 * 0b01111111 - RC RR RL FC LFE FR FL
339 * 0b11110011 RRC RLC RR RL - - FR FL
340 * 0b11110111 RRC RLC RR RL - LFE FR FL
341 * 0b11111011 RRC RLC RR RL FC - FR FL
342 * 0b11111111 RRC RLC RR RL FC LFE FR FL
343 * 0b11000011 FRC FLC - - - - FR FL
344 * 0b11000111 FRC FLC - - - LFE FR FL
345 * 0b11001011 FRC FLC - - FC - FR FL
346 * 0b11001111 FRC FLC - - FC LFE FR FL
347 * 0b11010011 FRC FLC - RC - - FR FL
348 * 0b11010111 FRC FLC - RC - LFE FR FL
349 * 0b11011011 FRC FLC - RC FC - FR FL
350 * 0b11011111 FRC FLC - RC FC LFE FR FL
351 * 0b11110011 FRC FLC RR RL - - FR FL
352 * 0b11110111 FRC FLC RR RL - LFE FR FL
353 * 0b11111011 FRC FLC RR RL FC - FR FL
354 * 0b11111111 FRC FLC RR RL FC LFE FR FL
355 *
356 * @param
357 * speakers - speaker information as it comes from CEA audio block
358 */
359/* translate speakers to channels */
360
361union audio_cea_channels {
362 uint8_t all;
363 struct audio_cea_channels_bits {
364 uint32_t FL:1;
365 uint32_t FR:1;
366 uint32_t LFE:1;
367 uint32_t FC:1;
368 uint32_t RL_RC:1;
369 uint32_t RR:1;
370 uint32_t RC_RLC_FLC:1;
371 uint32_t RRC_FRC:1;
372 } channels;
373};
374
375#endif /* __DAL_HW_SHARED_H__ */
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __DAL_HW_SHARED_H__
27#define __DAL_HW_SHARED_H__
28
29#include "os_types.h"
30#include "fixed31_32.h"
31#include "dc_hw_types.h"
32
33/******************************************************************************
34 * Data types shared between different Virtual HW blocks
35 ******************************************************************************/
36
37#define MAX_AUDIOS 7
38
39/**
40 * @MAX_PIPES:
41 *
42 * Every ASIC support a fixed number of pipes; MAX_PIPES defines a large number
43 * to be used inside loops and for determining array sizes.
44 */
45#define MAX_PIPES 6
46#define MAX_PHANTOM_PIPES (MAX_PIPES / 2)
47#define MAX_LINKS (MAX_PIPES * 2 +2)
48#define MAX_DIG_LINK_ENCODERS 7
49#define MAX_DWB_PIPES 1
50#define MAX_HPO_DP2_ENCODERS 4
51#define MAX_HPO_DP2_LINK_ENCODERS 4
52
53struct gamma_curve {
54 uint32_t offset;
55 uint32_t segments_num;
56};
57
58struct curve_points {
59 struct fixed31_32 x;
60 struct fixed31_32 y;
61 struct fixed31_32 offset;
62 struct fixed31_32 slope;
63
64 uint32_t custom_float_x;
65 uint32_t custom_float_y;
66 uint32_t custom_float_offset;
67 uint32_t custom_float_slope;
68};
69
70struct curve_points3 {
71 struct curve_points red;
72 struct curve_points green;
73 struct curve_points blue;
74};
75
76struct pwl_result_data {
77 struct fixed31_32 red;
78 struct fixed31_32 green;
79 struct fixed31_32 blue;
80
81 struct fixed31_32 delta_red;
82 struct fixed31_32 delta_green;
83 struct fixed31_32 delta_blue;
84
85 uint32_t red_reg;
86 uint32_t green_reg;
87 uint32_t blue_reg;
88
89 uint32_t delta_red_reg;
90 uint32_t delta_green_reg;
91 uint32_t delta_blue_reg;
92};
93
94struct dc_rgb {
95 uint32_t red;
96 uint32_t green;
97 uint32_t blue;
98};
99
100struct tetrahedral_17x17x17 {
101 struct dc_rgb lut0[1229];
102 struct dc_rgb lut1[1228];
103 struct dc_rgb lut2[1228];
104 struct dc_rgb lut3[1228];
105};
106struct tetrahedral_9x9x9 {
107 struct dc_rgb lut0[183];
108 struct dc_rgb lut1[182];
109 struct dc_rgb lut2[182];
110 struct dc_rgb lut3[182];
111};
112
113struct tetrahedral_params {
114 union {
115 struct tetrahedral_17x17x17 tetrahedral_17;
116 struct tetrahedral_9x9x9 tetrahedral_9;
117 };
118 bool use_tetrahedral_9;
119 bool use_12bits;
120
121};
122
123/* arr_curve_points - regamma regions/segments specification
124 * arr_points - beginning and end point specified separately (only one on DCE)
125 * corner_points - beginning and end point for all 3 colors (DCN)
126 * rgb_resulted - final curve
127 */
128struct pwl_params {
129 struct gamma_curve arr_curve_points[34];
130 union {
131 struct curve_points arr_points[2];
132 struct curve_points3 corner_points[2];
133 };
134 struct pwl_result_data rgb_resulted[256 + 3];
135 uint32_t hw_points_num;
136};
137
138/* move to dpp
139 * while we are moving functionality out of opp to dpp to align
140 * HW programming to HW IP, we define these struct in hw_shared
141 * so we can still compile while refactoring
142 */
143
144enum lb_pixel_depth {
145 /* do not change the values because it is used as bit vector */
146 LB_PIXEL_DEPTH_18BPP = 1,
147 LB_PIXEL_DEPTH_24BPP = 2,
148 LB_PIXEL_DEPTH_30BPP = 4,
149 LB_PIXEL_DEPTH_36BPP = 8
150};
151
152enum graphics_csc_adjust_type {
153 GRAPHICS_CSC_ADJUST_TYPE_BYPASS = 0,
154 GRAPHICS_CSC_ADJUST_TYPE_HW, /* without adjustments */
155 GRAPHICS_CSC_ADJUST_TYPE_SW /*use adjustments */
156};
157
158enum ipp_degamma_mode {
159 IPP_DEGAMMA_MODE_BYPASS,
160 IPP_DEGAMMA_MODE_HW_sRGB,
161 IPP_DEGAMMA_MODE_HW_xvYCC,
162 IPP_DEGAMMA_MODE_USER_PWL
163};
164
165enum gamcor_mode {
166 GAMCOR_MODE_BYPASS,
167 GAMCOR_MODE_RESERVED_1,
168 GAMCOR_MODE_USER_PWL,
169 GAMCOR_MODE_RESERVED_3
170};
171
172enum ipp_output_format {
173 IPP_OUTPUT_FORMAT_12_BIT_FIX,
174 IPP_OUTPUT_FORMAT_16_BIT_BYPASS,
175 IPP_OUTPUT_FORMAT_FLOAT
176};
177
178enum expansion_mode {
179 EXPANSION_MODE_DYNAMIC,
180 EXPANSION_MODE_ZERO
181};
182
183struct default_adjustment {
184 enum lb_pixel_depth lb_color_depth;
185 enum dc_color_space out_color_space;
186 enum dc_color_space in_color_space;
187 enum dc_color_depth color_depth;
188 enum pixel_format surface_pixel_format;
189 enum graphics_csc_adjust_type csc_adjust_type;
190 bool force_hw_default;
191};
192
193
194struct out_csc_color_matrix {
195 enum dc_color_space color_space;
196 uint16_t regval[12];
197};
198
199enum gamut_remap_select {
200 GAMUT_REMAP_BYPASS = 0,
201 GAMUT_REMAP_COEFF,
202 GAMUT_REMAP_COMA_COEFF,
203 GAMUT_REMAP_COMB_COEFF
204};
205
206enum opp_regamma {
207 OPP_REGAMMA_BYPASS = 0,
208 OPP_REGAMMA_SRGB,
209 OPP_REGAMMA_XVYCC,
210 OPP_REGAMMA_USER
211};
212
213enum optc_dsc_mode {
214 OPTC_DSC_DISABLED = 0,
215 OPTC_DSC_ENABLED_444 = 1, /* 'RGB 444' or 'Simple YCbCr 4:2:2' (4:2:2 upsampled to 4:4:4) */
216 OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED = 2 /* Native 4:2:2 or 4:2:0 */
217};
218
219struct dc_bias_and_scale {
220 uint32_t scale_red;
221 uint32_t bias_red;
222 uint32_t scale_green;
223 uint32_t bias_green;
224 uint32_t scale_blue;
225 uint32_t bias_blue;
226 bool bias_and_scale_valid;
227};
228
229enum test_pattern_dyn_range {
230 TEST_PATTERN_DYN_RANGE_VESA = 0,
231 TEST_PATTERN_DYN_RANGE_CEA
232};
233
234enum test_pattern_mode {
235 TEST_PATTERN_MODE_COLORSQUARES_RGB = 0,
236 TEST_PATTERN_MODE_COLORSQUARES_YCBCR601,
237 TEST_PATTERN_MODE_COLORSQUARES_YCBCR709,
238 TEST_PATTERN_MODE_VERTICALBARS,
239 TEST_PATTERN_MODE_HORIZONTALBARS,
240 TEST_PATTERN_MODE_SINGLERAMP_RGB,
241 TEST_PATTERN_MODE_DUALRAMP_RGB,
242 TEST_PATTERN_MODE_XR_BIAS_RGB
243};
244
245enum test_pattern_color_format {
246 TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0,
247 TEST_PATTERN_COLOR_FORMAT_BPC_8,
248 TEST_PATTERN_COLOR_FORMAT_BPC_10,
249 TEST_PATTERN_COLOR_FORMAT_BPC_12
250};
251
252enum controller_dp_test_pattern {
253 CONTROLLER_DP_TEST_PATTERN_D102 = 0,
254 CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR,
255 CONTROLLER_DP_TEST_PATTERN_PRBS7,
256 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES,
257 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS,
258 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS,
259 CONTROLLER_DP_TEST_PATTERN_COLORRAMP,
260 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
261 CONTROLLER_DP_TEST_PATTERN_RESERVED_8,
262 CONTROLLER_DP_TEST_PATTERN_RESERVED_9,
263 CONTROLLER_DP_TEST_PATTERN_RESERVED_A,
264 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA,
265 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR
266};
267
268enum controller_dp_color_space {
269 CONTROLLER_DP_COLOR_SPACE_RGB,
270 CONTROLLER_DP_COLOR_SPACE_YCBCR601,
271 CONTROLLER_DP_COLOR_SPACE_YCBCR709,
272 CONTROLLER_DP_COLOR_SPACE_UDEFINED
273};
274
275enum dc_lut_mode {
276 LUT_BYPASS,
277 LUT_RAM_A,
278 LUT_RAM_B
279};
280
281/**
282 * speakersToChannels
283 *
284 * @brief
285 * translate speakers to channels
286 *
287 * FL - Front Left
288 * FR - Front Right
289 * RL - Rear Left
290 * RR - Rear Right
291 * RC - Rear Center
292 * FC - Front Center
293 * FLC - Front Left Center
294 * FRC - Front Right Center
295 * RLC - Rear Left Center
296 * RRC - Rear Right Center
297 * LFE - Low Freq Effect
298 *
299 * FC
300 * FLC FRC
301 * FL FR
302 *
303 * LFE
304 * ()
305 *
306 *
307 * RL RR
308 * RLC RRC
309 * RC
310 *
311 * ch 8 7 6 5 4 3 2 1
312 * 0b00000011 - - - - - - FR FL
313 * 0b00000111 - - - - - LFE FR FL
314 * 0b00001011 - - - - FC - FR FL
315 * 0b00001111 - - - - FC LFE FR FL
316 * 0b00010011 - - - RC - - FR FL
317 * 0b00010111 - - - RC - LFE FR FL
318 * 0b00011011 - - - RC FC - FR FL
319 * 0b00011111 - - - RC FC LFE FR FL
320 * 0b00110011 - - RR RL - - FR FL
321 * 0b00110111 - - RR RL - LFE FR FL
322 * 0b00111011 - - RR RL FC - FR FL
323 * 0b00111111 - - RR RL FC LFE FR FL
324 * 0b01110011 - RC RR RL - - FR FL
325 * 0b01110111 - RC RR RL - LFE FR FL
326 * 0b01111011 - RC RR RL FC - FR FL
327 * 0b01111111 - RC RR RL FC LFE FR FL
328 * 0b11110011 RRC RLC RR RL - - FR FL
329 * 0b11110111 RRC RLC RR RL - LFE FR FL
330 * 0b11111011 RRC RLC RR RL FC - FR FL
331 * 0b11111111 RRC RLC RR RL FC LFE FR FL
332 * 0b11000011 FRC FLC - - - - FR FL
333 * 0b11000111 FRC FLC - - - LFE FR FL
334 * 0b11001011 FRC FLC - - FC - FR FL
335 * 0b11001111 FRC FLC - - FC LFE FR FL
336 * 0b11010011 FRC FLC - RC - - FR FL
337 * 0b11010111 FRC FLC - RC - LFE FR FL
338 * 0b11011011 FRC FLC - RC FC - FR FL
339 * 0b11011111 FRC FLC - RC FC LFE FR FL
340 * 0b11110011 FRC FLC RR RL - - FR FL
341 * 0b11110111 FRC FLC RR RL - LFE FR FL
342 * 0b11111011 FRC FLC RR RL FC - FR FL
343 * 0b11111111 FRC FLC RR RL FC LFE FR FL
344 *
345 * @param
346 * speakers - speaker information as it comes from CEA audio block
347 */
348/* translate speakers to channels */
349
350union audio_cea_channels {
351 uint8_t all;
352 struct audio_cea_channels_bits {
353 uint32_t FL:1;
354 uint32_t FR:1;
355 uint32_t LFE:1;
356 uint32_t FC:1;
357 uint32_t RL_RC:1;
358 uint32_t RR:1;
359 uint32_t RC_RLC_FLC:1;
360 uint32_t RRC_FRC:1;
361 } channels;
362};
363
364#endif /* __DAL_HW_SHARED_H__ */