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1/*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/pci.h>
25
26#include "amdgpu.h"
27#include "amdgpu_ih.h"
28#include "soc15.h"
29
30#include "oss/osssys_4_2_0_offset.h"
31#include "oss/osssys_4_2_0_sh_mask.h"
32
33#include "soc15_common.h"
34#include "vega20_ih.h"
35
36#define MAX_REARM_RETRY 10
37
38#define mmIH_CHICKEN_ALDEBARAN 0x18d
39#define mmIH_CHICKEN_ALDEBARAN_BASE_IDX 0
40
41static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev);
42
43/**
44 * vega20_ih_init_register_offset - Initialize register offset for ih rings
45 *
46 * @adev: amdgpu_device pointer
47 *
48 * Initialize register offset ih rings (VEGA20).
49 */
50static void vega20_ih_init_register_offset(struct amdgpu_device *adev)
51{
52 struct amdgpu_ih_regs *ih_regs;
53
54 if (adev->irq.ih.ring_size) {
55 ih_regs = &adev->irq.ih.ih_regs;
56 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE);
57 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI);
58 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);
59 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
60 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR);
61 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR);
62 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO);
63 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI);
64 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL;
65 }
66
67 if (adev->irq.ih1.ring_size) {
68 ih_regs = &adev->irq.ih1.ih_regs;
69 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1);
70 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1);
71 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);
72 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1);
73 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1);
74 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1);
75 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1;
76 }
77
78 if (adev->irq.ih2.ring_size) {
79 ih_regs = &adev->irq.ih2.ih_regs;
80 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2);
81 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2);
82 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);
83 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2);
84 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2);
85 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2);
86 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2;
87 }
88}
89
90/**
91 * vega20_ih_toggle_ring_interrupts - toggle the interrupt ring buffer
92 *
93 * @adev: amdgpu_device pointer
94 * @ih: amdgpu_ih_ring pointer
95 * @enable: true - enable the interrupts, false - disable the interrupts
96 *
97 * Toggle the interrupt ring buffer (VEGA20)
98 */
99static int vega20_ih_toggle_ring_interrupts(struct amdgpu_device *adev,
100 struct amdgpu_ih_ring *ih,
101 bool enable)
102{
103 struct amdgpu_ih_regs *ih_regs;
104 uint32_t tmp;
105
106 ih_regs = &ih->ih_regs;
107
108 tmp = RREG32(ih_regs->ih_rb_cntl);
109 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));
110 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1);
111
112 /* enable_intr field is only valid in ring0 */
113 if (ih == &adev->irq.ih)
114 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
115 if (amdgpu_sriov_vf(adev)) {
116 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
117 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n");
118 return -ETIMEDOUT;
119 }
120 } else {
121 WREG32(ih_regs->ih_rb_cntl, tmp);
122 }
123
124 if (enable) {
125 ih->enabled = true;
126 } else {
127 /* set rptr, wptr to 0 */
128 WREG32(ih_regs->ih_rb_rptr, 0);
129 WREG32(ih_regs->ih_rb_wptr, 0);
130 ih->enabled = false;
131 ih->rptr = 0;
132 }
133
134 return 0;
135}
136
137/**
138 * vega20_ih_toggle_interrupts - Toggle all the available interrupt ring buffers
139 *
140 * @adev: amdgpu_device pointer
141 * @enable: enable or disable interrupt ring buffers
142 *
143 * Toggle all the available interrupt ring buffers (VEGA20).
144 */
145static int vega20_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable)
146{
147 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
148 int i;
149 int r;
150
151 for (i = 0; i < ARRAY_SIZE(ih); i++) {
152 if (ih[i]->ring_size) {
153 r = vega20_ih_toggle_ring_interrupts(adev, ih[i], enable);
154 if (r)
155 return r;
156 }
157 }
158
159 return 0;
160}
161
162static uint32_t vega20_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)
163{
164 int rb_bufsz = order_base_2(ih->ring_size / 4);
165
166 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
167 MC_SPACE, ih->use_bus_addr ? 1 : 4);
168 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
169 WPTR_OVERFLOW_CLEAR, 1);
170 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
171 WPTR_OVERFLOW_ENABLE, 1);
172 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
173 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register
174 * value is written to memory
175 */
176 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
177 WPTR_WRITEBACK_ENABLE, 1);
178 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
179 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
180 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
181
182 return ih_rb_cntl;
183}
184
185static uint32_t vega20_ih_doorbell_rptr(struct amdgpu_ih_ring *ih)
186{
187 u32 ih_doorbell_rtpr = 0;
188
189 if (ih->use_doorbell) {
190 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
191 IH_DOORBELL_RPTR, OFFSET,
192 ih->doorbell_index);
193 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
194 IH_DOORBELL_RPTR,
195 ENABLE, 1);
196 } else {
197 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
198 IH_DOORBELL_RPTR,
199 ENABLE, 0);
200 }
201 return ih_doorbell_rtpr;
202}
203
204/**
205 * vega20_ih_enable_ring - enable an ih ring buffer
206 *
207 * @adev: amdgpu_device pointer
208 * @ih: amdgpu_ih_ring pointer
209 *
210 * Enable an ih ring buffer (VEGA20)
211 */
212static int vega20_ih_enable_ring(struct amdgpu_device *adev,
213 struct amdgpu_ih_ring *ih)
214{
215 struct amdgpu_ih_regs *ih_regs;
216 uint32_t tmp;
217
218 ih_regs = &ih->ih_regs;
219
220 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
221 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);
222 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);
223
224 tmp = RREG32(ih_regs->ih_rb_cntl);
225 tmp = vega20_ih_rb_cntl(ih, tmp);
226 if (ih == &adev->irq.ih)
227 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);
228 if (ih == &adev->irq.ih1)
229 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
230 if (amdgpu_sriov_vf(adev)) {
231 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
232 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n");
233 return -ETIMEDOUT;
234 }
235 } else {
236 WREG32(ih_regs->ih_rb_cntl, tmp);
237 }
238
239 if (ih == &adev->irq.ih) {
240 /* set the ih ring 0 writeback address whether it's enabled or not */
241 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
242 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);
243 }
244
245 /* set rptr, wptr to 0 */
246 WREG32(ih_regs->ih_rb_wptr, 0);
247 WREG32(ih_regs->ih_rb_rptr, 0);
248
249 WREG32(ih_regs->ih_doorbell_rptr, vega20_ih_doorbell_rptr(ih));
250
251 return 0;
252}
253
254/**
255 * vega20_ih_reroute_ih - reroute VMC/UTCL2 ih to an ih ring
256 *
257 * @adev: amdgpu_device pointer
258 *
259 * Reroute VMC and UMC interrupts on primary ih ring to
260 * ih ring 1 so they won't lose when bunches of page faults
261 * interrupts overwhelms the interrupt handler(VEGA20)
262 */
263static void vega20_ih_reroute_ih(struct amdgpu_device *adev)
264{
265 uint32_t tmp;
266
267 /* vega20 ih reroute will go through psp this
268 * function is used for newer asics starting arcturus
269 */
270 if (adev->ip_versions[OSSSYS_HWIP][0] >= IP_VERSION(4, 2, 1)) {
271 /* Reroute to IH ring 1 for VMC */
272 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x12);
273 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA);
274 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
275 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
276 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp);
277
278 /* Reroute IH ring 1 for UTCL2 */
279 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x1B);
280 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA);
281 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
282 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp);
283 }
284}
285
286/**
287 * vega20_ih_irq_init - init and enable the interrupt ring
288 *
289 * @adev: amdgpu_device pointer
290 *
291 * Allocate a ring buffer for the interrupt controller,
292 * enable the RLC, disable interrupts, enable the IH
293 * ring buffer and enable it (VI).
294 * Called at device load and reume.
295 * Returns 0 for success, errors for failure.
296 */
297static int vega20_ih_irq_init(struct amdgpu_device *adev)
298{
299 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
300 u32 ih_chicken;
301 int ret;
302 int i;
303
304 /* disable irqs */
305 ret = vega20_ih_toggle_interrupts(adev, false);
306 if (ret)
307 return ret;
308
309 adev->nbio.funcs->ih_control(adev);
310
311 if ((adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 2, 1)) &&
312 adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
313 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);
314 if (adev->irq.ih.use_bus_addr) {
315 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
316 MC_SPACE_GPA_ENABLE, 1);
317 }
318 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);
319 }
320
321 /* psp firmware won't program IH_CHICKEN for aldebaran
322 * driver needs to program it properly according to
323 * MC_SPACE type in IH_RB_CNTL */
324 if (adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 0)) {
325 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN);
326 if (adev->irq.ih.use_bus_addr) {
327 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
328 MC_SPACE_GPA_ENABLE, 1);
329 }
330 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN, ih_chicken);
331 }
332
333 for (i = 0; i < ARRAY_SIZE(ih); i++) {
334 if (ih[i]->ring_size) {
335 if (i == 1)
336 vega20_ih_reroute_ih(adev);
337 ret = vega20_ih_enable_ring(adev, ih[i]);
338 if (ret)
339 return ret;
340 }
341 }
342
343 if (!amdgpu_sriov_vf(adev))
344 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
345 adev->irq.ih.doorbell_index);
346
347 pci_set_master(adev->pdev);
348
349 /* enable interrupts */
350 ret = vega20_ih_toggle_interrupts(adev, true);
351 if (ret)
352 return ret;
353
354 if (adev->irq.ih_soft.ring_size)
355 adev->irq.ih_soft.enabled = true;
356
357 return 0;
358}
359
360/**
361 * vega20_ih_irq_disable - disable interrupts
362 *
363 * @adev: amdgpu_device pointer
364 *
365 * Disable interrupts on the hw (VEGA20).
366 */
367static void vega20_ih_irq_disable(struct amdgpu_device *adev)
368{
369 vega20_ih_toggle_interrupts(adev, false);
370
371 /* Wait and acknowledge irq */
372 mdelay(1);
373}
374
375/**
376 * vega20_ih_get_wptr - get the IH ring buffer wptr
377 *
378 * @adev: amdgpu_device pointer
379 * @ih: amdgpu_ih_ring pointer
380 *
381 * Get the IH ring buffer wptr from either the register
382 * or the writeback memory buffer (VEGA20). Also check for
383 * ring buffer overflow and deal with it.
384 * Returns the value of the wptr.
385 */
386static u32 vega20_ih_get_wptr(struct amdgpu_device *adev,
387 struct amdgpu_ih_ring *ih)
388{
389 u32 wptr, tmp;
390 struct amdgpu_ih_regs *ih_regs;
391
392 if (ih == &adev->irq.ih || ih == &adev->irq.ih_soft) {
393 /* Only ring0 supports writeback. On other rings fall back
394 * to register-based code with overflow checking below.
395 * ih_soft ring doesn't have any backing hardware registers,
396 * update wptr and return.
397 */
398 wptr = le32_to_cpu(*ih->wptr_cpu);
399
400 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
401 goto out;
402 }
403
404 ih_regs = &ih->ih_regs;
405
406 /* Double check that the overflow wasn't already cleared. */
407 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);
408 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
409 goto out;
410
411 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
412
413 /* When a ring buffer overflow happen start parsing interrupt
414 * from the last not overwritten vector (wptr + 32). Hopefully
415 * this should allow us to catchup.
416 */
417 tmp = (wptr + 32) & ih->ptr_mask;
418 dev_warn(adev->dev, "IH ring buffer overflow "
419 "(0x%08X, 0x%08X, 0x%08X)\n",
420 wptr, ih->rptr, tmp);
421 ih->rptr = tmp;
422
423 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
424 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
425 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
426
427out:
428 return (wptr & ih->ptr_mask);
429}
430
431/**
432 * vega20_ih_irq_rearm - rearm IRQ if lost
433 *
434 * @adev: amdgpu_device pointer
435 * @ih: amdgpu_ih_ring pointer
436 *
437 */
438static void vega20_ih_irq_rearm(struct amdgpu_device *adev,
439 struct amdgpu_ih_ring *ih)
440{
441 uint32_t v = 0;
442 uint32_t i = 0;
443 struct amdgpu_ih_regs *ih_regs;
444
445 ih_regs = &ih->ih_regs;
446
447 /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */
448 for (i = 0; i < MAX_REARM_RETRY; i++) {
449 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);
450 if ((v < ih->ring_size) && (v != ih->rptr))
451 WDOORBELL32(ih->doorbell_index, ih->rptr);
452 else
453 break;
454 }
455}
456
457/**
458 * vega20_ih_set_rptr - set the IH ring buffer rptr
459 *
460 * @adev: amdgpu_device pointer
461 * @ih: amdgpu_ih_ring pointer
462 *
463 * Set the IH ring buffer rptr.
464 */
465static void vega20_ih_set_rptr(struct amdgpu_device *adev,
466 struct amdgpu_ih_ring *ih)
467{
468 struct amdgpu_ih_regs *ih_regs;
469
470 if (ih == &adev->irq.ih_soft)
471 return;
472
473 if (ih->use_doorbell) {
474 /* XXX check if swapping is necessary on BE */
475 *ih->rptr_cpu = ih->rptr;
476 WDOORBELL32(ih->doorbell_index, ih->rptr);
477
478 if (amdgpu_sriov_vf(adev))
479 vega20_ih_irq_rearm(adev, ih);
480 } else {
481 ih_regs = &ih->ih_regs;
482 WREG32(ih_regs->ih_rb_rptr, ih->rptr);
483 }
484}
485
486/**
487 * vega20_ih_self_irq - dispatch work for ring 1 and 2
488 *
489 * @adev: amdgpu_device pointer
490 * @source: irq source
491 * @entry: IV with WPTR update
492 *
493 * Update the WPTR from the IV and schedule work to handle the entries.
494 */
495static int vega20_ih_self_irq(struct amdgpu_device *adev,
496 struct amdgpu_irq_src *source,
497 struct amdgpu_iv_entry *entry)
498{
499 switch (entry->ring_id) {
500 case 1:
501 schedule_work(&adev->irq.ih1_work);
502 break;
503 case 2:
504 schedule_work(&adev->irq.ih2_work);
505 break;
506 default: break;
507 }
508 return 0;
509}
510
511static const struct amdgpu_irq_src_funcs vega20_ih_self_irq_funcs = {
512 .process = vega20_ih_self_irq,
513};
514
515static void vega20_ih_set_self_irq_funcs(struct amdgpu_device *adev)
516{
517 adev->irq.self_irq.num_types = 0;
518 adev->irq.self_irq.funcs = &vega20_ih_self_irq_funcs;
519}
520
521static int vega20_ih_early_init(void *handle)
522{
523 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
524
525 vega20_ih_set_interrupt_funcs(adev);
526 vega20_ih_set_self_irq_funcs(adev);
527 return 0;
528}
529
530static int vega20_ih_sw_init(void *handle)
531{
532 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
533 int r;
534
535 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0,
536 &adev->irq.self_irq);
537 if (r)
538 return r;
539
540 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true);
541 if (r)
542 return r;
543
544 adev->irq.ih.use_doorbell = true;
545 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
546
547 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true);
548 if (r)
549 return r;
550
551 adev->irq.ih1.use_doorbell = true;
552 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1;
553
554 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true);
555 if (r)
556 return r;
557
558 adev->irq.ih2.use_doorbell = true;
559 adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1;
560
561 /* initialize ih control registers offset */
562 vega20_ih_init_register_offset(adev);
563
564 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true);
565 if (r)
566 return r;
567
568 r = amdgpu_irq_init(adev);
569
570 return r;
571}
572
573static int vega20_ih_sw_fini(void *handle)
574{
575 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
576
577 amdgpu_irq_fini_sw(adev);
578
579 return 0;
580}
581
582static int vega20_ih_hw_init(void *handle)
583{
584 int r;
585 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
586
587 r = vega20_ih_irq_init(adev);
588 if (r)
589 return r;
590
591 return 0;
592}
593
594static int vega20_ih_hw_fini(void *handle)
595{
596 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
597
598 vega20_ih_irq_disable(adev);
599
600 return 0;
601}
602
603static int vega20_ih_suspend(void *handle)
604{
605 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
606
607 return vega20_ih_hw_fini(adev);
608}
609
610static int vega20_ih_resume(void *handle)
611{
612 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
613
614 return vega20_ih_hw_init(adev);
615}
616
617static bool vega20_ih_is_idle(void *handle)
618{
619 /* todo */
620 return true;
621}
622
623static int vega20_ih_wait_for_idle(void *handle)
624{
625 /* todo */
626 return -ETIMEDOUT;
627}
628
629static int vega20_ih_soft_reset(void *handle)
630{
631 /* todo */
632
633 return 0;
634}
635
636static void vega20_ih_update_clockgating_state(struct amdgpu_device *adev,
637 bool enable)
638{
639 uint32_t data, def, field_val;
640
641 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) {
642 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL);
643 field_val = enable ? 0 : 1;
644 data = REG_SET_FIELD(data, IH_CLK_CTRL,
645 IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val);
646 data = REG_SET_FIELD(data, IH_CLK_CTRL,
647 IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val);
648 data = REG_SET_FIELD(data, IH_CLK_CTRL,
649 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val);
650 data = REG_SET_FIELD(data, IH_CLK_CTRL,
651 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val);
652 data = REG_SET_FIELD(data, IH_CLK_CTRL,
653 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val);
654 data = REG_SET_FIELD(data, IH_CLK_CTRL,
655 DYN_CLK_SOFT_OVERRIDE, field_val);
656 data = REG_SET_FIELD(data, IH_CLK_CTRL,
657 REG_CLK_SOFT_OVERRIDE, field_val);
658 if (def != data)
659 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data);
660 }
661}
662
663static int vega20_ih_set_clockgating_state(void *handle,
664 enum amd_clockgating_state state)
665{
666 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
667
668 vega20_ih_update_clockgating_state(adev,
669 state == AMD_CG_STATE_GATE);
670 return 0;
671
672}
673
674static int vega20_ih_set_powergating_state(void *handle,
675 enum amd_powergating_state state)
676{
677 return 0;
678}
679
680const struct amd_ip_funcs vega20_ih_ip_funcs = {
681 .name = "vega20_ih",
682 .early_init = vega20_ih_early_init,
683 .late_init = NULL,
684 .sw_init = vega20_ih_sw_init,
685 .sw_fini = vega20_ih_sw_fini,
686 .hw_init = vega20_ih_hw_init,
687 .hw_fini = vega20_ih_hw_fini,
688 .suspend = vega20_ih_suspend,
689 .resume = vega20_ih_resume,
690 .is_idle = vega20_ih_is_idle,
691 .wait_for_idle = vega20_ih_wait_for_idle,
692 .soft_reset = vega20_ih_soft_reset,
693 .set_clockgating_state = vega20_ih_set_clockgating_state,
694 .set_powergating_state = vega20_ih_set_powergating_state,
695};
696
697static const struct amdgpu_ih_funcs vega20_ih_funcs = {
698 .get_wptr = vega20_ih_get_wptr,
699 .decode_iv = amdgpu_ih_decode_iv_helper,
700 .decode_iv_ts = amdgpu_ih_decode_iv_ts_helper,
701 .set_rptr = vega20_ih_set_rptr
702};
703
704static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev)
705{
706 adev->irq.ih_funcs = &vega20_ih_funcs;
707}
708
709const struct amdgpu_ip_block_version vega20_ih_ip_block =
710{
711 .type = AMD_IP_BLOCK_TYPE_IH,
712 .major = 4,
713 .minor = 2,
714 .rev = 0,
715 .funcs = &vega20_ih_ip_funcs,
716};
1/*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/pci.h>
25
26#include "amdgpu.h"
27#include "amdgpu_ih.h"
28#include "soc15.h"
29
30#include "oss/osssys_4_2_0_offset.h"
31#include "oss/osssys_4_2_0_sh_mask.h"
32
33#include "soc15_common.h"
34#include "vega20_ih.h"
35
36#define MAX_REARM_RETRY 10
37
38#define mmIH_CHICKEN_ALDEBARAN 0x18d
39#define mmIH_CHICKEN_ALDEBARAN_BASE_IDX 0
40
41#define mmIH_RETRY_INT_CAM_CNTL_ALDEBARAN 0x00ea
42#define mmIH_RETRY_INT_CAM_CNTL_ALDEBARAN_BASE_IDX 0
43#define IH_RETRY_INT_CAM_CNTL_ALDEBARAN__ENABLE__SHIFT 0x10
44#define IH_RETRY_INT_CAM_CNTL_ALDEBARAN__ENABLE_MASK 0x00010000L
45
46static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev);
47
48/**
49 * vega20_ih_init_register_offset - Initialize register offset for ih rings
50 *
51 * @adev: amdgpu_device pointer
52 *
53 * Initialize register offset ih rings (VEGA20).
54 */
55static void vega20_ih_init_register_offset(struct amdgpu_device *adev)
56{
57 struct amdgpu_ih_regs *ih_regs;
58
59 if (adev->irq.ih.ring_size) {
60 ih_regs = &adev->irq.ih.ih_regs;
61 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE);
62 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI);
63 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);
64 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
65 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR);
66 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR);
67 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO);
68 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI);
69 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL;
70 }
71
72 if (adev->irq.ih1.ring_size) {
73 ih_regs = &adev->irq.ih1.ih_regs;
74 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1);
75 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1);
76 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);
77 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1);
78 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1);
79 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1);
80 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1;
81 }
82
83 if (adev->irq.ih2.ring_size) {
84 ih_regs = &adev->irq.ih2.ih_regs;
85 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2);
86 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2);
87 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);
88 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2);
89 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2);
90 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2);
91 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2;
92 }
93}
94
95/**
96 * vega20_ih_toggle_ring_interrupts - toggle the interrupt ring buffer
97 *
98 * @adev: amdgpu_device pointer
99 * @ih: amdgpu_ih_ring pointer
100 * @enable: true - enable the interrupts, false - disable the interrupts
101 *
102 * Toggle the interrupt ring buffer (VEGA20)
103 */
104static int vega20_ih_toggle_ring_interrupts(struct amdgpu_device *adev,
105 struct amdgpu_ih_ring *ih,
106 bool enable)
107{
108 struct amdgpu_ih_regs *ih_regs;
109 uint32_t tmp;
110
111 ih_regs = &ih->ih_regs;
112
113 tmp = RREG32(ih_regs->ih_rb_cntl);
114 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));
115 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1);
116
117 if (enable) {
118 /* Unset the CLEAR_OVERFLOW bit to make sure the next step
119 * is switching the bit from 0 to 1
120 */
121 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
122 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
123 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
124 return -ETIMEDOUT;
125 } else {
126 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
127 }
128
129 /* Clear RB_OVERFLOW bit */
130 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
131 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
132 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
133 return -ETIMEDOUT;
134 } else {
135 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
136 }
137
138 /* Unset the CLEAR_OVERFLOW bit immediately so new overflows
139 * can be detected.
140 */
141 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
142 }
143
144 /* enable_intr field is only valid in ring0 */
145 if (ih == &adev->irq.ih)
146 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
147 if (amdgpu_sriov_vf(adev)) {
148 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
149 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n");
150 return -ETIMEDOUT;
151 }
152 } else {
153 WREG32(ih_regs->ih_rb_cntl, tmp);
154 }
155
156 if (enable) {
157 ih->enabled = true;
158 } else {
159 /* set rptr, wptr to 0 */
160 WREG32(ih_regs->ih_rb_rptr, 0);
161 WREG32(ih_regs->ih_rb_wptr, 0);
162 ih->enabled = false;
163 ih->rptr = 0;
164 }
165
166 return 0;
167}
168
169/**
170 * vega20_ih_toggle_interrupts - Toggle all the available interrupt ring buffers
171 *
172 * @adev: amdgpu_device pointer
173 * @enable: enable or disable interrupt ring buffers
174 *
175 * Toggle all the available interrupt ring buffers (VEGA20).
176 */
177static int vega20_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable)
178{
179 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
180 int i;
181 int r;
182
183 for (i = 0; i < ARRAY_SIZE(ih); i++) {
184 if (ih[i]->ring_size) {
185 r = vega20_ih_toggle_ring_interrupts(adev, ih[i], enable);
186 if (r)
187 return r;
188 }
189 }
190
191 return 0;
192}
193
194static uint32_t vega20_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)
195{
196 int rb_bufsz = order_base_2(ih->ring_size / 4);
197
198 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
199 MC_SPACE, ih->use_bus_addr ? 1 : 4);
200 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
201 WPTR_OVERFLOW_CLEAR, 1);
202 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
203 WPTR_OVERFLOW_ENABLE, 1);
204 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
205 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register
206 * value is written to memory
207 */
208 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
209 WPTR_WRITEBACK_ENABLE, 1);
210 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
211 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
212 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
213
214 return ih_rb_cntl;
215}
216
217static uint32_t vega20_ih_doorbell_rptr(struct amdgpu_ih_ring *ih)
218{
219 u32 ih_doorbell_rtpr = 0;
220
221 if (ih->use_doorbell) {
222 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
223 IH_DOORBELL_RPTR, OFFSET,
224 ih->doorbell_index);
225 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
226 IH_DOORBELL_RPTR,
227 ENABLE, 1);
228 } else {
229 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
230 IH_DOORBELL_RPTR,
231 ENABLE, 0);
232 }
233 return ih_doorbell_rtpr;
234}
235
236/**
237 * vega20_ih_enable_ring - enable an ih ring buffer
238 *
239 * @adev: amdgpu_device pointer
240 * @ih: amdgpu_ih_ring pointer
241 *
242 * Enable an ih ring buffer (VEGA20)
243 */
244static int vega20_ih_enable_ring(struct amdgpu_device *adev,
245 struct amdgpu_ih_ring *ih)
246{
247 struct amdgpu_ih_regs *ih_regs;
248 uint32_t tmp;
249
250 ih_regs = &ih->ih_regs;
251
252 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
253 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);
254 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);
255
256 tmp = RREG32(ih_regs->ih_rb_cntl);
257 tmp = vega20_ih_rb_cntl(ih, tmp);
258 if (ih == &adev->irq.ih)
259 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);
260 if (ih == &adev->irq.ih1)
261 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
262 if (amdgpu_sriov_vf(adev)) {
263 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
264 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n");
265 return -ETIMEDOUT;
266 }
267 } else {
268 WREG32(ih_regs->ih_rb_cntl, tmp);
269 }
270
271 if (ih == &adev->irq.ih) {
272 /* set the ih ring 0 writeback address whether it's enabled or not */
273 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
274 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);
275 }
276
277 /* set rptr, wptr to 0 */
278 WREG32(ih_regs->ih_rb_wptr, 0);
279 WREG32(ih_regs->ih_rb_rptr, 0);
280
281 WREG32(ih_regs->ih_doorbell_rptr, vega20_ih_doorbell_rptr(ih));
282
283 return 0;
284}
285
286static uint32_t vega20_setup_retry_doorbell(u32 doorbell_index)
287{
288 u32 val = 0;
289
290 val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, OFFSET, doorbell_index);
291 val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, ENABLE, 1);
292
293 return val;
294}
295
296/**
297 * vega20_ih_irq_init - init and enable the interrupt ring
298 *
299 * @adev: amdgpu_device pointer
300 *
301 * Allocate a ring buffer for the interrupt controller,
302 * enable the RLC, disable interrupts, enable the IH
303 * ring buffer and enable it (VI).
304 * Called at device load and reume.
305 * Returns 0 for success, errors for failure.
306 */
307static int vega20_ih_irq_init(struct amdgpu_device *adev)
308{
309 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
310 u32 ih_chicken;
311 int ret;
312 int i;
313
314 /* disable irqs */
315 ret = vega20_ih_toggle_interrupts(adev, false);
316 if (ret)
317 return ret;
318
319 adev->nbio.funcs->ih_control(adev);
320
321 if (!amdgpu_sriov_vf(adev)) {
322 if ((amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 2, 1)) &&
323 adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
324 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);
325 if (adev->irq.ih.use_bus_addr) {
326 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
327 MC_SPACE_GPA_ENABLE, 1);
328 }
329 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);
330 }
331
332 /* psp firmware won't program IH_CHICKEN for aldebaran
333 * driver needs to program it properly according to
334 * MC_SPACE type in IH_RB_CNTL */
335 if ((amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 0)) ||
336 (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 2)) ||
337 (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 5))) {
338 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN);
339 if (adev->irq.ih.use_bus_addr) {
340 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
341 MC_SPACE_GPA_ENABLE, 1);
342 }
343 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN, ih_chicken);
344 }
345 }
346
347 for (i = 0; i < ARRAY_SIZE(ih); i++) {
348 if (ih[i]->ring_size) {
349 ret = vega20_ih_enable_ring(adev, ih[i]);
350 if (ret)
351 return ret;
352 }
353 }
354
355 if (!amdgpu_sriov_vf(adev))
356 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
357 adev->irq.ih.doorbell_index);
358
359 pci_set_master(adev->pdev);
360
361 /* Allocate the doorbell for IH Retry CAM */
362 adev->irq.retry_cam_doorbell_index = (adev->doorbell_index.ih + 3) << 1;
363 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RETRY_CAM,
364 vega20_setup_retry_doorbell(adev->irq.retry_cam_doorbell_index));
365
366 /* Enable IH Retry CAM */
367 if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 0) ||
368 amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 2) ||
369 amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 5))
370 WREG32_FIELD15(OSSSYS, 0, IH_RETRY_INT_CAM_CNTL_ALDEBARAN,
371 ENABLE, 1);
372 else
373 WREG32_FIELD15(OSSSYS, 0, IH_RETRY_INT_CAM_CNTL, ENABLE, 1);
374
375 adev->irq.retry_cam_enabled = true;
376
377 /* enable interrupts */
378 ret = vega20_ih_toggle_interrupts(adev, true);
379 if (ret)
380 return ret;
381
382 if (adev->irq.ih_soft.ring_size)
383 adev->irq.ih_soft.enabled = true;
384
385 return 0;
386}
387
388/**
389 * vega20_ih_irq_disable - disable interrupts
390 *
391 * @adev: amdgpu_device pointer
392 *
393 * Disable interrupts on the hw (VEGA20).
394 */
395static void vega20_ih_irq_disable(struct amdgpu_device *adev)
396{
397 vega20_ih_toggle_interrupts(adev, false);
398
399 /* Wait and acknowledge irq */
400 mdelay(1);
401}
402
403/**
404 * vega20_ih_get_wptr - get the IH ring buffer wptr
405 *
406 * @adev: amdgpu_device pointer
407 * @ih: amdgpu_ih_ring pointer
408 *
409 * Get the IH ring buffer wptr from either the register
410 * or the writeback memory buffer (VEGA20). Also check for
411 * ring buffer overflow and deal with it.
412 * Returns the value of the wptr.
413 */
414static u32 vega20_ih_get_wptr(struct amdgpu_device *adev,
415 struct amdgpu_ih_ring *ih)
416{
417 u32 wptr, tmp;
418 struct amdgpu_ih_regs *ih_regs;
419
420 if (ih == &adev->irq.ih || ih == &adev->irq.ih_soft) {
421 /* Only ring0 supports writeback. On other rings fall back
422 * to register-based code with overflow checking below.
423 * ih_soft ring doesn't have any backing hardware registers,
424 * update wptr and return.
425 */
426 wptr = le32_to_cpu(*ih->wptr_cpu);
427
428 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
429 goto out;
430 }
431
432 ih_regs = &ih->ih_regs;
433
434 /* Double check that the overflow wasn't already cleared. */
435 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);
436 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
437 goto out;
438
439 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
440
441 /* When a ring buffer overflow happen start parsing interrupt
442 * from the last not overwritten vector (wptr + 32). Hopefully
443 * this should allow us to catchup.
444 */
445 tmp = (wptr + 32) & ih->ptr_mask;
446 dev_warn(adev->dev, "IH ring buffer overflow "
447 "(0x%08X, 0x%08X, 0x%08X)\n",
448 wptr, ih->rptr, tmp);
449 ih->rptr = tmp;
450
451 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
452 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
453 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
454
455 /* Unset the CLEAR_OVERFLOW bit immediately so new overflows
456 * can be detected.
457 */
458 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
459 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
460
461out:
462 return (wptr & ih->ptr_mask);
463}
464
465/**
466 * vega20_ih_irq_rearm - rearm IRQ if lost
467 *
468 * @adev: amdgpu_device pointer
469 * @ih: amdgpu_ih_ring pointer
470 *
471 */
472static void vega20_ih_irq_rearm(struct amdgpu_device *adev,
473 struct amdgpu_ih_ring *ih)
474{
475 uint32_t v = 0;
476 uint32_t i = 0;
477 struct amdgpu_ih_regs *ih_regs;
478
479 ih_regs = &ih->ih_regs;
480
481 /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */
482 for (i = 0; i < MAX_REARM_RETRY; i++) {
483 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);
484 if ((v < ih->ring_size) && (v != ih->rptr))
485 WDOORBELL32(ih->doorbell_index, ih->rptr);
486 else
487 break;
488 }
489}
490
491/**
492 * vega20_ih_set_rptr - set the IH ring buffer rptr
493 *
494 * @adev: amdgpu_device pointer
495 * @ih: amdgpu_ih_ring pointer
496 *
497 * Set the IH ring buffer rptr.
498 */
499static void vega20_ih_set_rptr(struct amdgpu_device *adev,
500 struct amdgpu_ih_ring *ih)
501{
502 struct amdgpu_ih_regs *ih_regs;
503
504 if (ih == &adev->irq.ih_soft)
505 return;
506
507 if (ih->use_doorbell) {
508 /* XXX check if swapping is necessary on BE */
509 *ih->rptr_cpu = ih->rptr;
510 WDOORBELL32(ih->doorbell_index, ih->rptr);
511
512 if (amdgpu_sriov_vf(adev))
513 vega20_ih_irq_rearm(adev, ih);
514 } else {
515 ih_regs = &ih->ih_regs;
516 WREG32(ih_regs->ih_rb_rptr, ih->rptr);
517 }
518}
519
520/**
521 * vega20_ih_self_irq - dispatch work for ring 1 and 2
522 *
523 * @adev: amdgpu_device pointer
524 * @source: irq source
525 * @entry: IV with WPTR update
526 *
527 * Update the WPTR from the IV and schedule work to handle the entries.
528 */
529static int vega20_ih_self_irq(struct amdgpu_device *adev,
530 struct amdgpu_irq_src *source,
531 struct amdgpu_iv_entry *entry)
532{
533 switch (entry->ring_id) {
534 case 1:
535 schedule_work(&adev->irq.ih1_work);
536 break;
537 case 2:
538 schedule_work(&adev->irq.ih2_work);
539 break;
540 default:
541 break;
542 }
543 return 0;
544}
545
546static const struct amdgpu_irq_src_funcs vega20_ih_self_irq_funcs = {
547 .process = vega20_ih_self_irq,
548};
549
550static void vega20_ih_set_self_irq_funcs(struct amdgpu_device *adev)
551{
552 adev->irq.self_irq.num_types = 0;
553 adev->irq.self_irq.funcs = &vega20_ih_self_irq_funcs;
554}
555
556static int vega20_ih_early_init(struct amdgpu_ip_block *ip_block)
557{
558 struct amdgpu_device *adev = ip_block->adev;
559
560 vega20_ih_set_interrupt_funcs(adev);
561 vega20_ih_set_self_irq_funcs(adev);
562 return 0;
563}
564
565static int vega20_ih_sw_init(struct amdgpu_ip_block *ip_block)
566{
567 struct amdgpu_device *adev = ip_block->adev;
568 bool use_bus_addr = true;
569 int r;
570
571 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0,
572 &adev->irq.self_irq);
573 if (r)
574 return r;
575
576 if ((adev->flags & AMD_IS_APU) &&
577 (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 2)))
578 use_bus_addr = false;
579
580 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, use_bus_addr);
581 if (r)
582 return r;
583
584 adev->irq.ih.use_doorbell = true;
585 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
586
587 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, use_bus_addr);
588 if (r)
589 return r;
590
591 adev->irq.ih1.use_doorbell = true;
592 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1;
593
594 if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) != IP_VERSION(4, 4, 2) &&
595 amdgpu_ip_version(adev, OSSSYS_HWIP, 0) != IP_VERSION(4, 4, 5)) {
596 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true);
597 if (r)
598 return r;
599
600 adev->irq.ih2.use_doorbell = true;
601 adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1;
602 }
603
604 /* initialize ih control registers offset */
605 vega20_ih_init_register_offset(adev);
606
607 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, use_bus_addr);
608 if (r)
609 return r;
610
611 r = amdgpu_irq_init(adev);
612
613 return r;
614}
615
616static int vega20_ih_sw_fini(struct amdgpu_ip_block *ip_block)
617{
618 struct amdgpu_device *adev = ip_block->adev;
619
620 amdgpu_irq_fini_sw(adev);
621
622 return 0;
623}
624
625static int vega20_ih_hw_init(struct amdgpu_ip_block *ip_block)
626{
627 int r;
628 struct amdgpu_device *adev = ip_block->adev;
629
630 r = vega20_ih_irq_init(adev);
631 if (r)
632 return r;
633
634 return 0;
635}
636
637static int vega20_ih_hw_fini(struct amdgpu_ip_block *ip_block)
638{
639 vega20_ih_irq_disable(ip_block->adev);
640
641 return 0;
642}
643
644static int vega20_ih_suspend(struct amdgpu_ip_block *ip_block)
645{
646 return vega20_ih_hw_fini(ip_block);
647}
648
649static int vega20_ih_resume(struct amdgpu_ip_block *ip_block)
650{
651 return vega20_ih_hw_init(ip_block);
652}
653
654static bool vega20_ih_is_idle(void *handle)
655{
656 /* todo */
657 return true;
658}
659
660static int vega20_ih_wait_for_idle(struct amdgpu_ip_block *ip_block)
661{
662 /* todo */
663 return -ETIMEDOUT;
664}
665
666static int vega20_ih_soft_reset(struct amdgpu_ip_block *ip_block)
667{
668 /* todo */
669
670 return 0;
671}
672
673static void vega20_ih_update_clockgating_state(struct amdgpu_device *adev,
674 bool enable)
675{
676 uint32_t data, def, field_val;
677
678 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) {
679 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL);
680 field_val = enable ? 0 : 1;
681 data = REG_SET_FIELD(data, IH_CLK_CTRL,
682 IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val);
683 data = REG_SET_FIELD(data, IH_CLK_CTRL,
684 IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val);
685 data = REG_SET_FIELD(data, IH_CLK_CTRL,
686 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val);
687 data = REG_SET_FIELD(data, IH_CLK_CTRL,
688 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val);
689 data = REG_SET_FIELD(data, IH_CLK_CTRL,
690 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val);
691 data = REG_SET_FIELD(data, IH_CLK_CTRL,
692 DYN_CLK_SOFT_OVERRIDE, field_val);
693 data = REG_SET_FIELD(data, IH_CLK_CTRL,
694 REG_CLK_SOFT_OVERRIDE, field_val);
695 if (def != data)
696 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data);
697 }
698}
699
700static int vega20_ih_set_clockgating_state(void *handle,
701 enum amd_clockgating_state state)
702{
703 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
704
705 vega20_ih_update_clockgating_state(adev,
706 state == AMD_CG_STATE_GATE);
707 return 0;
708
709}
710
711static int vega20_ih_set_powergating_state(void *handle,
712 enum amd_powergating_state state)
713{
714 return 0;
715}
716
717const struct amd_ip_funcs vega20_ih_ip_funcs = {
718 .name = "vega20_ih",
719 .early_init = vega20_ih_early_init,
720 .sw_init = vega20_ih_sw_init,
721 .sw_fini = vega20_ih_sw_fini,
722 .hw_init = vega20_ih_hw_init,
723 .hw_fini = vega20_ih_hw_fini,
724 .suspend = vega20_ih_suspend,
725 .resume = vega20_ih_resume,
726 .is_idle = vega20_ih_is_idle,
727 .wait_for_idle = vega20_ih_wait_for_idle,
728 .soft_reset = vega20_ih_soft_reset,
729 .set_clockgating_state = vega20_ih_set_clockgating_state,
730 .set_powergating_state = vega20_ih_set_powergating_state,
731};
732
733static const struct amdgpu_ih_funcs vega20_ih_funcs = {
734 .get_wptr = vega20_ih_get_wptr,
735 .decode_iv = amdgpu_ih_decode_iv_helper,
736 .decode_iv_ts = amdgpu_ih_decode_iv_ts_helper,
737 .set_rptr = vega20_ih_set_rptr
738};
739
740static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev)
741{
742 adev->irq.ih_funcs = &vega20_ih_funcs;
743}
744
745const struct amdgpu_ip_block_version vega20_ih_ip_block = {
746 .type = AMD_IP_BLOCK_TYPE_IH,
747 .major = 4,
748 .minor = 2,
749 .rev = 0,
750 .funcs = &vega20_ih_ip_funcs,
751};