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1/*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/delay.h>
25#include <linux/firmware.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28
29#include "amdgpu.h"
30#include "amdgpu_xcp.h"
31#include "amdgpu_ucode.h"
32#include "amdgpu_trace.h"
33
34#include "sdma/sdma_4_4_2_offset.h"
35#include "sdma/sdma_4_4_2_sh_mask.h"
36
37#include "soc15_common.h"
38#include "soc15.h"
39#include "vega10_sdma_pkt_open.h"
40
41#include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h"
42#include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h"
43
44#include "amdgpu_ras.h"
45
46MODULE_FIRMWARE("amdgpu/sdma_4_4_2.bin");
47MODULE_FIRMWARE("amdgpu/sdma_4_4_5.bin");
48
49static const struct amdgpu_hwip_reg_entry sdma_reg_list_4_4_2[] = {
50 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS_REG),
51 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS1_REG),
52 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS2_REG),
53 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS3_REG),
54 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UCODE_CHECKSUM),
55 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RB_RPTR_FETCH_HI),
56 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RB_RPTR_FETCH),
57 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_STATUS),
58 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_STATUS),
59 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_XNACK0),
60 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_XNACK1),
61 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_XNACK0),
62 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_XNACK1),
63 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_CNTL),
64 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_RPTR),
65 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_RPTR_HI),
66 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_WPTR),
67 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_WPTR_HI),
68 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_OFFSET),
69 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_BASE_LO),
70 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_BASE_HI),
71 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_CNTL),
72 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_RPTR),
73 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_SUB_REMAIN),
74 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_DUMMY_REG),
75 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_CNTL),
76 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_RPTR),
77 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_RPTR_HI),
78 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_WPTR),
79 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_WPTR_HI),
80 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_OFFSET),
81 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_BASE_LO),
82 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_BASE_HI),
83 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_DUMMY_REG),
84 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_CNTL),
85 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_RPTR),
86 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_RPTR_HI),
87 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_WPTR),
88 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_WPTR_HI),
89 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_OFFSET),
90 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_BASE_LO),
91 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_BASE_HI),
92 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_DUMMY_REG),
93 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_VM_CNTL)
94};
95
96#define mmSMNAID_AID0_MCA_SMU 0x03b30400
97
98#define WREG32_SDMA(instance, offset, value) \
99 WREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)), value)
100#define RREG32_SDMA(instance, offset) \
101 RREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)))
102
103static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev);
104static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev);
105static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev);
106static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev);
107static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev);
108
109static u32 sdma_v4_4_2_get_reg_offset(struct amdgpu_device *adev,
110 u32 instance, u32 offset)
111{
112 u32 dev_inst = GET_INST(SDMA0, instance);
113
114 return (adev->reg_offset[SDMA0_HWIP][dev_inst][0] + offset);
115}
116
117static unsigned sdma_v4_4_2_seq_to_irq_id(int seq_num)
118{
119 switch (seq_num) {
120 case 0:
121 return SOC15_IH_CLIENTID_SDMA0;
122 case 1:
123 return SOC15_IH_CLIENTID_SDMA1;
124 case 2:
125 return SOC15_IH_CLIENTID_SDMA2;
126 case 3:
127 return SOC15_IH_CLIENTID_SDMA3;
128 default:
129 return -EINVAL;
130 }
131}
132
133static int sdma_v4_4_2_irq_id_to_seq(struct amdgpu_device *adev, unsigned client_id)
134{
135 switch (client_id) {
136 case SOC15_IH_CLIENTID_SDMA0:
137 return 0;
138 case SOC15_IH_CLIENTID_SDMA1:
139 return 1;
140 case SOC15_IH_CLIENTID_SDMA2:
141 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1))
142 return 0;
143 else
144 return 2;
145 case SOC15_IH_CLIENTID_SDMA3:
146 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1))
147 return 1;
148 else
149 return 3;
150 default:
151 return -EINVAL;
152 }
153}
154
155static void sdma_v4_4_2_inst_init_golden_registers(struct amdgpu_device *adev,
156 uint32_t inst_mask)
157{
158 u32 val;
159 int i;
160
161 for (i = 0; i < adev->sdma.num_instances; i++) {
162 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG);
163 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, NUM_BANKS, 4);
164 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG,
165 PIPE_INTERLEAVE_SIZE, 0);
166 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG, val);
167
168 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ);
169 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, NUM_BANKS,
170 4);
171 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ,
172 PIPE_INTERLEAVE_SIZE, 0);
173 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ, val);
174 }
175}
176
177/**
178 * sdma_v4_4_2_init_microcode - load ucode images from disk
179 *
180 * @adev: amdgpu_device pointer
181 *
182 * Use the firmware interface to load the ucode images into
183 * the driver (not loaded into hw).
184 * Returns 0 on success, error on failure.
185 */
186static int sdma_v4_4_2_init_microcode(struct amdgpu_device *adev)
187{
188 int ret, i;
189
190 for (i = 0; i < adev->sdma.num_instances; i++) {
191 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2) ||
192 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5)) {
193 ret = amdgpu_sdma_init_microcode(adev, 0, true);
194 break;
195 } else {
196 ret = amdgpu_sdma_init_microcode(adev, i, false);
197 if (ret)
198 return ret;
199 }
200 }
201
202 return ret;
203}
204
205/**
206 * sdma_v4_4_2_ring_get_rptr - get the current read pointer
207 *
208 * @ring: amdgpu ring pointer
209 *
210 * Get the current rptr from the hardware.
211 */
212static uint64_t sdma_v4_4_2_ring_get_rptr(struct amdgpu_ring *ring)
213{
214 u64 rptr;
215
216 /* XXX check if swapping is necessary on BE */
217 rptr = READ_ONCE(*((u64 *)&ring->adev->wb.wb[ring->rptr_offs]));
218
219 DRM_DEBUG("rptr before shift == 0x%016llx\n", rptr);
220 return rptr >> 2;
221}
222
223/**
224 * sdma_v4_4_2_ring_get_wptr - get the current write pointer
225 *
226 * @ring: amdgpu ring pointer
227 *
228 * Get the current wptr from the hardware.
229 */
230static uint64_t sdma_v4_4_2_ring_get_wptr(struct amdgpu_ring *ring)
231{
232 struct amdgpu_device *adev = ring->adev;
233 u64 wptr;
234
235 if (ring->use_doorbell) {
236 /* XXX check if swapping is necessary on BE */
237 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
238 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
239 } else {
240 wptr = RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI);
241 wptr = wptr << 32;
242 wptr |= RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR);
243 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n",
244 ring->me, wptr);
245 }
246
247 return wptr >> 2;
248}
249
250/**
251 * sdma_v4_4_2_ring_set_wptr - commit the write pointer
252 *
253 * @ring: amdgpu ring pointer
254 *
255 * Write the wptr back to the hardware.
256 */
257static void sdma_v4_4_2_ring_set_wptr(struct amdgpu_ring *ring)
258{
259 struct amdgpu_device *adev = ring->adev;
260
261 DRM_DEBUG("Setting write pointer\n");
262 if (ring->use_doorbell) {
263 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
264
265 DRM_DEBUG("Using doorbell -- "
266 "wptr_offs == 0x%08x "
267 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
268 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
269 ring->wptr_offs,
270 lower_32_bits(ring->wptr << 2),
271 upper_32_bits(ring->wptr << 2));
272 /* XXX check if swapping is necessary on BE */
273 WRITE_ONCE(*wb, (ring->wptr << 2));
274 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
275 ring->doorbell_index, ring->wptr << 2);
276 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
277 } else {
278 DRM_DEBUG("Not using doorbell -- "
279 "regSDMA%i_GFX_RB_WPTR == 0x%08x "
280 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
281 ring->me,
282 lower_32_bits(ring->wptr << 2),
283 ring->me,
284 upper_32_bits(ring->wptr << 2));
285 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR,
286 lower_32_bits(ring->wptr << 2));
287 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI,
288 upper_32_bits(ring->wptr << 2));
289 }
290}
291
292/**
293 * sdma_v4_4_2_page_ring_get_wptr - get the current write pointer
294 *
295 * @ring: amdgpu ring pointer
296 *
297 * Get the current wptr from the hardware.
298 */
299static uint64_t sdma_v4_4_2_page_ring_get_wptr(struct amdgpu_ring *ring)
300{
301 struct amdgpu_device *adev = ring->adev;
302 u64 wptr;
303
304 if (ring->use_doorbell) {
305 /* XXX check if swapping is necessary on BE */
306 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
307 } else {
308 wptr = RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI);
309 wptr = wptr << 32;
310 wptr |= RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR);
311 }
312
313 return wptr >> 2;
314}
315
316/**
317 * sdma_v4_4_2_page_ring_set_wptr - commit the write pointer
318 *
319 * @ring: amdgpu ring pointer
320 *
321 * Write the wptr back to the hardware.
322 */
323static void sdma_v4_4_2_page_ring_set_wptr(struct amdgpu_ring *ring)
324{
325 struct amdgpu_device *adev = ring->adev;
326
327 if (ring->use_doorbell) {
328 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
329
330 /* XXX check if swapping is necessary on BE */
331 WRITE_ONCE(*wb, (ring->wptr << 2));
332 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
333 } else {
334 uint64_t wptr = ring->wptr << 2;
335
336 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR,
337 lower_32_bits(wptr));
338 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI,
339 upper_32_bits(wptr));
340 }
341}
342
343static void sdma_v4_4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
344{
345 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
346 int i;
347
348 for (i = 0; i < count; i++)
349 if (sdma && sdma->burst_nop && (i == 0))
350 amdgpu_ring_write(ring, ring->funcs->nop |
351 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
352 else
353 amdgpu_ring_write(ring, ring->funcs->nop);
354}
355
356/**
357 * sdma_v4_4_2_ring_emit_ib - Schedule an IB on the DMA engine
358 *
359 * @ring: amdgpu ring pointer
360 * @job: job to retrieve vmid from
361 * @ib: IB object to schedule
362 * @flags: unused
363 *
364 * Schedule an IB in the DMA ring.
365 */
366static void sdma_v4_4_2_ring_emit_ib(struct amdgpu_ring *ring,
367 struct amdgpu_job *job,
368 struct amdgpu_ib *ib,
369 uint32_t flags)
370{
371 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
372
373 /* IB packet must end on a 8 DW boundary */
374 sdma_v4_4_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
375
376 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
377 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
378 /* base must be 32 byte aligned */
379 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
380 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
381 amdgpu_ring_write(ring, ib->length_dw);
382 amdgpu_ring_write(ring, 0);
383 amdgpu_ring_write(ring, 0);
384
385}
386
387static void sdma_v4_4_2_wait_reg_mem(struct amdgpu_ring *ring,
388 int mem_space, int hdp,
389 uint32_t addr0, uint32_t addr1,
390 uint32_t ref, uint32_t mask,
391 uint32_t inv)
392{
393 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
394 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) |
395 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) |
396 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
397 if (mem_space) {
398 /* memory */
399 amdgpu_ring_write(ring, addr0);
400 amdgpu_ring_write(ring, addr1);
401 } else {
402 /* registers */
403 amdgpu_ring_write(ring, addr0 << 2);
404 amdgpu_ring_write(ring, addr1 << 2);
405 }
406 amdgpu_ring_write(ring, ref); /* reference */
407 amdgpu_ring_write(ring, mask); /* mask */
408 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
409 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */
410}
411
412/**
413 * sdma_v4_4_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
414 *
415 * @ring: amdgpu ring pointer
416 *
417 * Emit an hdp flush packet on the requested DMA ring.
418 */
419static void sdma_v4_4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
420{
421 struct amdgpu_device *adev = ring->adev;
422 u32 ref_and_mask = 0;
423 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
424
425 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0
426 << (ring->me % adev->sdma.num_inst_per_aid);
427
428 sdma_v4_4_2_wait_reg_mem(ring, 0, 1,
429 adev->nbio.funcs->get_hdp_flush_done_offset(adev),
430 adev->nbio.funcs->get_hdp_flush_req_offset(adev),
431 ref_and_mask, ref_and_mask, 10);
432}
433
434/**
435 * sdma_v4_4_2_ring_emit_fence - emit a fence on the DMA ring
436 *
437 * @ring: amdgpu ring pointer
438 * @addr: address
439 * @seq: sequence number
440 * @flags: fence related flags
441 *
442 * Add a DMA fence packet to the ring to write
443 * the fence seq number and DMA trap packet to generate
444 * an interrupt if needed.
445 */
446static void sdma_v4_4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
447 unsigned flags)
448{
449 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
450 /* write the fence */
451 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
452 /* zero in first two bits */
453 BUG_ON(addr & 0x3);
454 amdgpu_ring_write(ring, lower_32_bits(addr));
455 amdgpu_ring_write(ring, upper_32_bits(addr));
456 amdgpu_ring_write(ring, lower_32_bits(seq));
457
458 /* optionally write high bits as well */
459 if (write64bit) {
460 addr += 4;
461 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
462 /* zero in first two bits */
463 BUG_ON(addr & 0x3);
464 amdgpu_ring_write(ring, lower_32_bits(addr));
465 amdgpu_ring_write(ring, upper_32_bits(addr));
466 amdgpu_ring_write(ring, upper_32_bits(seq));
467 }
468
469 /* generate an interrupt */
470 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
471 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
472}
473
474
475/**
476 * sdma_v4_4_2_inst_gfx_stop - stop the gfx async dma engines
477 *
478 * @adev: amdgpu_device pointer
479 * @inst_mask: mask of dma engine instances to be disabled
480 *
481 * Stop the gfx async dma ring buffers.
482 */
483static void sdma_v4_4_2_inst_gfx_stop(struct amdgpu_device *adev,
484 uint32_t inst_mask)
485{
486 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
487 u32 doorbell_offset, doorbell;
488 u32 rb_cntl, ib_cntl;
489 int i;
490
491 for_each_inst(i, inst_mask) {
492 sdma[i] = &adev->sdma.instance[i].ring;
493
494 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL);
495 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 0);
496 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl);
497 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL);
498 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 0);
499 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl);
500
501 if (sdma[i]->use_doorbell) {
502 doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL);
503 doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET);
504
505 doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 0);
506 doorbell_offset = REG_SET_FIELD(doorbell_offset,
507 SDMA_GFX_DOORBELL_OFFSET,
508 OFFSET, 0);
509 WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell);
510 WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset);
511 }
512 }
513}
514
515/**
516 * sdma_v4_4_2_inst_rlc_stop - stop the compute async dma engines
517 *
518 * @adev: amdgpu_device pointer
519 * @inst_mask: mask of dma engine instances to be disabled
520 *
521 * Stop the compute async dma queues.
522 */
523static void sdma_v4_4_2_inst_rlc_stop(struct amdgpu_device *adev,
524 uint32_t inst_mask)
525{
526 /* XXX todo */
527}
528
529/**
530 * sdma_v4_4_2_inst_page_stop - stop the page async dma engines
531 *
532 * @adev: amdgpu_device pointer
533 * @inst_mask: mask of dma engine instances to be disabled
534 *
535 * Stop the page async dma ring buffers.
536 */
537static void sdma_v4_4_2_inst_page_stop(struct amdgpu_device *adev,
538 uint32_t inst_mask)
539{
540 u32 rb_cntl, ib_cntl;
541 int i;
542
543 for_each_inst(i, inst_mask) {
544 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL);
545 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL,
546 RB_ENABLE, 0);
547 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl);
548 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL);
549 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL,
550 IB_ENABLE, 0);
551 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl);
552 }
553}
554
555/**
556 * sdma_v4_4_2_inst_ctx_switch_enable - stop the async dma engines context switch
557 *
558 * @adev: amdgpu_device pointer
559 * @enable: enable/disable the DMA MEs context switch.
560 * @inst_mask: mask of dma engine instances to be enabled
561 *
562 * Halt or unhalt the async dma engines context switch.
563 */
564static void sdma_v4_4_2_inst_ctx_switch_enable(struct amdgpu_device *adev,
565 bool enable, uint32_t inst_mask)
566{
567 u32 f32_cntl, phase_quantum = 0;
568 int i;
569
570 if (amdgpu_sdma_phase_quantum) {
571 unsigned value = amdgpu_sdma_phase_quantum;
572 unsigned unit = 0;
573
574 while (value > (SDMA_PHASE0_QUANTUM__VALUE_MASK >>
575 SDMA_PHASE0_QUANTUM__VALUE__SHIFT)) {
576 value = (value + 1) >> 1;
577 unit++;
578 }
579 if (unit > (SDMA_PHASE0_QUANTUM__UNIT_MASK >>
580 SDMA_PHASE0_QUANTUM__UNIT__SHIFT)) {
581 value = (SDMA_PHASE0_QUANTUM__VALUE_MASK >>
582 SDMA_PHASE0_QUANTUM__VALUE__SHIFT);
583 unit = (SDMA_PHASE0_QUANTUM__UNIT_MASK >>
584 SDMA_PHASE0_QUANTUM__UNIT__SHIFT);
585 WARN_ONCE(1,
586 "clamping sdma_phase_quantum to %uK clock cycles\n",
587 value << unit);
588 }
589 phase_quantum =
590 value << SDMA_PHASE0_QUANTUM__VALUE__SHIFT |
591 unit << SDMA_PHASE0_QUANTUM__UNIT__SHIFT;
592 }
593
594 for_each_inst(i, inst_mask) {
595 f32_cntl = RREG32_SDMA(i, regSDMA_CNTL);
596 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_CNTL,
597 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
598 if (enable && amdgpu_sdma_phase_quantum) {
599 WREG32_SDMA(i, regSDMA_PHASE0_QUANTUM, phase_quantum);
600 WREG32_SDMA(i, regSDMA_PHASE1_QUANTUM, phase_quantum);
601 WREG32_SDMA(i, regSDMA_PHASE2_QUANTUM, phase_quantum);
602 }
603 WREG32_SDMA(i, regSDMA_CNTL, f32_cntl);
604
605 /* Extend page fault timeout to avoid interrupt storm */
606 WREG32_SDMA(i, regSDMA_UTCL1_TIMEOUT, 0x00800080);
607 }
608}
609
610/**
611 * sdma_v4_4_2_inst_enable - stop the async dma engines
612 *
613 * @adev: amdgpu_device pointer
614 * @enable: enable/disable the DMA MEs.
615 * @inst_mask: mask of dma engine instances to be enabled
616 *
617 * Halt or unhalt the async dma engines.
618 */
619static void sdma_v4_4_2_inst_enable(struct amdgpu_device *adev, bool enable,
620 uint32_t inst_mask)
621{
622 u32 f32_cntl;
623 int i;
624
625 if (!enable) {
626 sdma_v4_4_2_inst_gfx_stop(adev, inst_mask);
627 sdma_v4_4_2_inst_rlc_stop(adev, inst_mask);
628 if (adev->sdma.has_page_queue)
629 sdma_v4_4_2_inst_page_stop(adev, inst_mask);
630
631 /* SDMA FW needs to respond to FREEZE requests during reset.
632 * Keep it running during reset */
633 if (!amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
634 return;
635 }
636
637 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
638 return;
639
640 for_each_inst(i, inst_mask) {
641 f32_cntl = RREG32_SDMA(i, regSDMA_F32_CNTL);
642 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_F32_CNTL, HALT, enable ? 0 : 1);
643 WREG32_SDMA(i, regSDMA_F32_CNTL, f32_cntl);
644 }
645}
646
647/*
648 * sdma_v4_4_2_rb_cntl - get parameters for rb_cntl
649 */
650static uint32_t sdma_v4_4_2_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl)
651{
652 /* Set ring buffer size in dwords */
653 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4);
654
655 barrier(); /* work around https://llvm.org/pr42576 */
656 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
657#ifdef __BIG_ENDIAN
658 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
659 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL,
660 RPTR_WRITEBACK_SWAP_ENABLE, 1);
661#endif
662 return rb_cntl;
663}
664
665/**
666 * sdma_v4_4_2_gfx_resume - setup and start the async dma engines
667 *
668 * @adev: amdgpu_device pointer
669 * @i: instance to resume
670 *
671 * Set up the gfx DMA ring buffers and enable them.
672 * Returns 0 for success, error for failure.
673 */
674static void sdma_v4_4_2_gfx_resume(struct amdgpu_device *adev, unsigned int i)
675{
676 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring;
677 u32 rb_cntl, ib_cntl, wptr_poll_cntl;
678 u32 wb_offset;
679 u32 doorbell;
680 u32 doorbell_offset;
681 u64 wptr_gpu_addr;
682
683 wb_offset = (ring->rptr_offs * 4);
684
685 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL);
686 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl);
687 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl);
688
689 /* set the wb address whether it's enabled or not */
690 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_HI,
691 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
692 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_LO,
693 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
694
695 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL,
696 RPTR_WRITEBACK_ENABLE, 1);
697
698 WREG32_SDMA(i, regSDMA_GFX_RB_BASE, ring->gpu_addr >> 8);
699 WREG32_SDMA(i, regSDMA_GFX_RB_BASE_HI, ring->gpu_addr >> 40);
700
701 ring->wptr = 0;
702
703 /* before programing wptr to a less value, need set minor_ptr_update first */
704 WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 1);
705
706 /* Initialize the ring buffer's read and write pointers */
707 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, 0);
708 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, 0);
709 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, 0);
710 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, 0);
711
712 doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL);
713 doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET);
714
715 doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE,
716 ring->use_doorbell);
717 doorbell_offset = REG_SET_FIELD(doorbell_offset,
718 SDMA_GFX_DOORBELL_OFFSET,
719 OFFSET, ring->doorbell_index);
720 WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell);
721 WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset);
722
723 sdma_v4_4_2_ring_set_wptr(ring);
724
725 /* set minor_ptr_update to 0 after wptr programed */
726 WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 0);
727
728 /* setup the wptr shadow polling */
729 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
730 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_LO,
731 lower_32_bits(wptr_gpu_addr));
732 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_HI,
733 upper_32_bits(wptr_gpu_addr));
734 wptr_poll_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL);
735 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
736 SDMA_GFX_RB_WPTR_POLL_CNTL,
737 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
738 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
739
740 /* enable DMA RB */
741 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 1);
742 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl);
743
744 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL);
745 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 1);
746#ifdef __BIG_ENDIAN
747 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
748#endif
749 /* enable DMA IBs */
750 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl);
751}
752
753/**
754 * sdma_v4_4_2_page_resume - setup and start the async dma engines
755 *
756 * @adev: amdgpu_device pointer
757 * @i: instance to resume
758 *
759 * Set up the page DMA ring buffers and enable them.
760 * Returns 0 for success, error for failure.
761 */
762static void sdma_v4_4_2_page_resume(struct amdgpu_device *adev, unsigned int i)
763{
764 struct amdgpu_ring *ring = &adev->sdma.instance[i].page;
765 u32 rb_cntl, ib_cntl, wptr_poll_cntl;
766 u32 wb_offset;
767 u32 doorbell;
768 u32 doorbell_offset;
769 u64 wptr_gpu_addr;
770
771 wb_offset = (ring->rptr_offs * 4);
772
773 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL);
774 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl);
775 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl);
776
777 /* Initialize the ring buffer's read and write pointers */
778 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, 0);
779 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, 0);
780 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, 0);
781 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, 0);
782
783 /* set the wb address whether it's enabled or not */
784 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_HI,
785 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
786 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_LO,
787 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
788
789 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL,
790 RPTR_WRITEBACK_ENABLE, 1);
791
792 WREG32_SDMA(i, regSDMA_PAGE_RB_BASE, ring->gpu_addr >> 8);
793 WREG32_SDMA(i, regSDMA_PAGE_RB_BASE_HI, ring->gpu_addr >> 40);
794
795 ring->wptr = 0;
796
797 /* before programing wptr to a less value, need set minor_ptr_update first */
798 WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 1);
799
800 doorbell = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL);
801 doorbell_offset = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET);
802
803 doorbell = REG_SET_FIELD(doorbell, SDMA_PAGE_DOORBELL, ENABLE,
804 ring->use_doorbell);
805 doorbell_offset = REG_SET_FIELD(doorbell_offset,
806 SDMA_PAGE_DOORBELL_OFFSET,
807 OFFSET, ring->doorbell_index);
808 WREG32_SDMA(i, regSDMA_PAGE_DOORBELL, doorbell);
809 WREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET, doorbell_offset);
810
811 /* paging queue doorbell range is setup at sdma_v4_4_2_gfx_resume */
812 sdma_v4_4_2_page_ring_set_wptr(ring);
813
814 /* set minor_ptr_update to 0 after wptr programed */
815 WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 0);
816
817 /* setup the wptr shadow polling */
818 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
819 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_LO,
820 lower_32_bits(wptr_gpu_addr));
821 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_HI,
822 upper_32_bits(wptr_gpu_addr));
823 wptr_poll_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL);
824 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
825 SDMA_PAGE_RB_WPTR_POLL_CNTL,
826 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
827 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
828
829 /* enable DMA RB */
830 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, RB_ENABLE, 1);
831 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl);
832
833 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL);
834 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_ENABLE, 1);
835#ifdef __BIG_ENDIAN
836 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1);
837#endif
838 /* enable DMA IBs */
839 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl);
840}
841
842static void sdma_v4_4_2_init_pg(struct amdgpu_device *adev)
843{
844
845}
846
847/**
848 * sdma_v4_4_2_inst_rlc_resume - setup and start the async dma engines
849 *
850 * @adev: amdgpu_device pointer
851 * @inst_mask: mask of dma engine instances to be enabled
852 *
853 * Set up the compute DMA queues and enable them.
854 * Returns 0 for success, error for failure.
855 */
856static int sdma_v4_4_2_inst_rlc_resume(struct amdgpu_device *adev,
857 uint32_t inst_mask)
858{
859 sdma_v4_4_2_init_pg(adev);
860
861 return 0;
862}
863
864/**
865 * sdma_v4_4_2_inst_load_microcode - load the sDMA ME ucode
866 *
867 * @adev: amdgpu_device pointer
868 * @inst_mask: mask of dma engine instances to be enabled
869 *
870 * Loads the sDMA0/1 ucode.
871 * Returns 0 for success, -EINVAL if the ucode is not available.
872 */
873static int sdma_v4_4_2_inst_load_microcode(struct amdgpu_device *adev,
874 uint32_t inst_mask)
875{
876 const struct sdma_firmware_header_v1_0 *hdr;
877 const __le32 *fw_data;
878 u32 fw_size;
879 int i, j;
880
881 /* halt the MEs */
882 sdma_v4_4_2_inst_enable(adev, false, inst_mask);
883
884 for_each_inst(i, inst_mask) {
885 if (!adev->sdma.instance[i].fw)
886 return -EINVAL;
887
888 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
889 amdgpu_ucode_print_sdma_hdr(&hdr->header);
890 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
891
892 fw_data = (const __le32 *)
893 (adev->sdma.instance[i].fw->data +
894 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
895
896 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 0);
897
898 for (j = 0; j < fw_size; j++)
899 WREG32_SDMA(i, regSDMA_UCODE_DATA,
900 le32_to_cpup(fw_data++));
901
902 WREG32_SDMA(i, regSDMA_UCODE_ADDR,
903 adev->sdma.instance[i].fw_version);
904 }
905
906 return 0;
907}
908
909/**
910 * sdma_v4_4_2_inst_start - setup and start the async dma engines
911 *
912 * @adev: amdgpu_device pointer
913 * @inst_mask: mask of dma engine instances to be enabled
914 *
915 * Set up the DMA engines and enable them.
916 * Returns 0 for success, error for failure.
917 */
918static int sdma_v4_4_2_inst_start(struct amdgpu_device *adev,
919 uint32_t inst_mask)
920{
921 struct amdgpu_ring *ring;
922 uint32_t tmp_mask;
923 int i, r = 0;
924
925 if (amdgpu_sriov_vf(adev)) {
926 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
927 sdma_v4_4_2_inst_enable(adev, false, inst_mask);
928 } else {
929 /* bypass sdma microcode loading on Gopher */
930 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP &&
931 adev->sdma.instance[0].fw) {
932 r = sdma_v4_4_2_inst_load_microcode(adev, inst_mask);
933 if (r)
934 return r;
935 }
936
937 /* unhalt the MEs */
938 sdma_v4_4_2_inst_enable(adev, true, inst_mask);
939 /* enable sdma ring preemption */
940 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask);
941 }
942
943 /* start the gfx rings and rlc compute queues */
944 tmp_mask = inst_mask;
945 for_each_inst(i, tmp_mask) {
946 uint32_t temp;
947
948 WREG32_SDMA(i, regSDMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);
949 sdma_v4_4_2_gfx_resume(adev, i);
950 if (adev->sdma.has_page_queue)
951 sdma_v4_4_2_page_resume(adev, i);
952
953 /* set utc l1 enable flag always to 1 */
954 temp = RREG32_SDMA(i, regSDMA_CNTL);
955 temp = REG_SET_FIELD(temp, SDMA_CNTL, UTC_L1_ENABLE, 1);
956
957 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) < IP_VERSION(4, 4, 5)) {
958 /* enable context empty interrupt during initialization */
959 temp = REG_SET_FIELD(temp, SDMA_CNTL, CTXEMPTY_INT_ENABLE, 1);
960 WREG32_SDMA(i, regSDMA_CNTL, temp);
961 }
962 if (!amdgpu_sriov_vf(adev)) {
963 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
964 /* unhalt engine */
965 temp = RREG32_SDMA(i, regSDMA_F32_CNTL);
966 temp = REG_SET_FIELD(temp, SDMA_F32_CNTL, HALT, 0);
967 WREG32_SDMA(i, regSDMA_F32_CNTL, temp);
968 }
969 }
970 }
971
972 if (amdgpu_sriov_vf(adev)) {
973 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask);
974 sdma_v4_4_2_inst_enable(adev, true, inst_mask);
975 } else {
976 r = sdma_v4_4_2_inst_rlc_resume(adev, inst_mask);
977 if (r)
978 return r;
979 }
980
981 tmp_mask = inst_mask;
982 for_each_inst(i, tmp_mask) {
983 ring = &adev->sdma.instance[i].ring;
984
985 r = amdgpu_ring_test_helper(ring);
986 if (r)
987 return r;
988
989 if (adev->sdma.has_page_queue) {
990 struct amdgpu_ring *page = &adev->sdma.instance[i].page;
991
992 r = amdgpu_ring_test_helper(page);
993 if (r)
994 return r;
995 }
996 }
997
998 return r;
999}
1000
1001/**
1002 * sdma_v4_4_2_ring_test_ring - simple async dma engine test
1003 *
1004 * @ring: amdgpu_ring structure holding ring information
1005 *
1006 * Test the DMA engine by writing using it to write an
1007 * value to memory.
1008 * Returns 0 for success, error for failure.
1009 */
1010static int sdma_v4_4_2_ring_test_ring(struct amdgpu_ring *ring)
1011{
1012 struct amdgpu_device *adev = ring->adev;
1013 unsigned i;
1014 unsigned index;
1015 int r;
1016 u32 tmp;
1017 u64 gpu_addr;
1018
1019 r = amdgpu_device_wb_get(adev, &index);
1020 if (r)
1021 return r;
1022
1023 gpu_addr = adev->wb.gpu_addr + (index * 4);
1024 tmp = 0xCAFEDEAD;
1025 adev->wb.wb[index] = cpu_to_le32(tmp);
1026
1027 r = amdgpu_ring_alloc(ring, 5);
1028 if (r)
1029 goto error_free_wb;
1030
1031 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1032 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
1033 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
1034 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
1035 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
1036 amdgpu_ring_write(ring, 0xDEADBEEF);
1037 amdgpu_ring_commit(ring);
1038
1039 for (i = 0; i < adev->usec_timeout; i++) {
1040 tmp = le32_to_cpu(adev->wb.wb[index]);
1041 if (tmp == 0xDEADBEEF)
1042 break;
1043 udelay(1);
1044 }
1045
1046 if (i >= adev->usec_timeout)
1047 r = -ETIMEDOUT;
1048
1049error_free_wb:
1050 amdgpu_device_wb_free(adev, index);
1051 return r;
1052}
1053
1054/**
1055 * sdma_v4_4_2_ring_test_ib - test an IB on the DMA engine
1056 *
1057 * @ring: amdgpu_ring structure holding ring information
1058 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1059 *
1060 * Test a simple IB in the DMA ring.
1061 * Returns 0 on success, error on failure.
1062 */
1063static int sdma_v4_4_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1064{
1065 struct amdgpu_device *adev = ring->adev;
1066 struct amdgpu_ib ib;
1067 struct dma_fence *f = NULL;
1068 unsigned index;
1069 long r;
1070 u32 tmp = 0;
1071 u64 gpu_addr;
1072
1073 r = amdgpu_device_wb_get(adev, &index);
1074 if (r)
1075 return r;
1076
1077 gpu_addr = adev->wb.gpu_addr + (index * 4);
1078 tmp = 0xCAFEDEAD;
1079 adev->wb.wb[index] = cpu_to_le32(tmp);
1080 memset(&ib, 0, sizeof(ib));
1081 r = amdgpu_ib_get(adev, NULL, 256,
1082 AMDGPU_IB_POOL_DIRECT, &ib);
1083 if (r)
1084 goto err0;
1085
1086 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1087 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1088 ib.ptr[1] = lower_32_bits(gpu_addr);
1089 ib.ptr[2] = upper_32_bits(gpu_addr);
1090 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1091 ib.ptr[4] = 0xDEADBEEF;
1092 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1093 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1094 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1095 ib.length_dw = 8;
1096
1097 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1098 if (r)
1099 goto err1;
1100
1101 r = dma_fence_wait_timeout(f, false, timeout);
1102 if (r == 0) {
1103 r = -ETIMEDOUT;
1104 goto err1;
1105 } else if (r < 0) {
1106 goto err1;
1107 }
1108 tmp = le32_to_cpu(adev->wb.wb[index]);
1109 if (tmp == 0xDEADBEEF)
1110 r = 0;
1111 else
1112 r = -EINVAL;
1113
1114err1:
1115 amdgpu_ib_free(adev, &ib, NULL);
1116 dma_fence_put(f);
1117err0:
1118 amdgpu_device_wb_free(adev, index);
1119 return r;
1120}
1121
1122
1123/**
1124 * sdma_v4_4_2_vm_copy_pte - update PTEs by copying them from the GART
1125 *
1126 * @ib: indirect buffer to fill with commands
1127 * @pe: addr of the page entry
1128 * @src: src addr to copy from
1129 * @count: number of page entries to update
1130 *
1131 * Update PTEs by copying them from the GART using sDMA.
1132 */
1133static void sdma_v4_4_2_vm_copy_pte(struct amdgpu_ib *ib,
1134 uint64_t pe, uint64_t src,
1135 unsigned count)
1136{
1137 unsigned bytes = count * 8;
1138
1139 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1140 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1141 ib->ptr[ib->length_dw++] = bytes - 1;
1142 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1143 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1144 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1145 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1146 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1147
1148}
1149
1150/**
1151 * sdma_v4_4_2_vm_write_pte - update PTEs by writing them manually
1152 *
1153 * @ib: indirect buffer to fill with commands
1154 * @pe: addr of the page entry
1155 * @value: dst addr to write into pe
1156 * @count: number of page entries to update
1157 * @incr: increase next addr by incr bytes
1158 *
1159 * Update PTEs by writing them manually using sDMA.
1160 */
1161static void sdma_v4_4_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1162 uint64_t value, unsigned count,
1163 uint32_t incr)
1164{
1165 unsigned ndw = count * 2;
1166
1167 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1168 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1169 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1170 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1171 ib->ptr[ib->length_dw++] = ndw - 1;
1172 for (; ndw > 0; ndw -= 2) {
1173 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1174 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1175 value += incr;
1176 }
1177}
1178
1179/**
1180 * sdma_v4_4_2_vm_set_pte_pde - update the page tables using sDMA
1181 *
1182 * @ib: indirect buffer to fill with commands
1183 * @pe: addr of the page entry
1184 * @addr: dst addr to write into pe
1185 * @count: number of page entries to update
1186 * @incr: increase next addr by incr bytes
1187 * @flags: access flags
1188 *
1189 * Update the page tables using sDMA.
1190 */
1191static void sdma_v4_4_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1192 uint64_t pe,
1193 uint64_t addr, unsigned count,
1194 uint32_t incr, uint64_t flags)
1195{
1196 /* for physically contiguous pages (vram) */
1197 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1198 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1199 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1200 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1201 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1202 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1203 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1204 ib->ptr[ib->length_dw++] = incr; /* increment size */
1205 ib->ptr[ib->length_dw++] = 0;
1206 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1207}
1208
1209/**
1210 * sdma_v4_4_2_ring_pad_ib - pad the IB to the required number of dw
1211 *
1212 * @ring: amdgpu_ring structure holding ring information
1213 * @ib: indirect buffer to fill with padding
1214 */
1215static void sdma_v4_4_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1216{
1217 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1218 u32 pad_count;
1219 int i;
1220
1221 pad_count = (-ib->length_dw) & 7;
1222 for (i = 0; i < pad_count; i++)
1223 if (sdma && sdma->burst_nop && (i == 0))
1224 ib->ptr[ib->length_dw++] =
1225 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1226 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1227 else
1228 ib->ptr[ib->length_dw++] =
1229 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1230}
1231
1232
1233/**
1234 * sdma_v4_4_2_ring_emit_pipeline_sync - sync the pipeline
1235 *
1236 * @ring: amdgpu_ring pointer
1237 *
1238 * Make sure all previous operations are completed (CIK).
1239 */
1240static void sdma_v4_4_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1241{
1242 uint32_t seq = ring->fence_drv.sync_seq;
1243 uint64_t addr = ring->fence_drv.gpu_addr;
1244
1245 /* wait for idle */
1246 sdma_v4_4_2_wait_reg_mem(ring, 1, 0,
1247 addr & 0xfffffffc,
1248 upper_32_bits(addr) & 0xffffffff,
1249 seq, 0xffffffff, 4);
1250}
1251
1252
1253/**
1254 * sdma_v4_4_2_ring_emit_vm_flush - vm flush using sDMA
1255 *
1256 * @ring: amdgpu_ring pointer
1257 * @vmid: vmid number to use
1258 * @pd_addr: address
1259 *
1260 * Update the page table base and flush the VM TLB
1261 * using sDMA.
1262 */
1263static void sdma_v4_4_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
1264 unsigned vmid, uint64_t pd_addr)
1265{
1266 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1267}
1268
1269static void sdma_v4_4_2_ring_emit_wreg(struct amdgpu_ring *ring,
1270 uint32_t reg, uint32_t val)
1271{
1272 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1273 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1274 amdgpu_ring_write(ring, reg);
1275 amdgpu_ring_write(ring, val);
1276}
1277
1278static void sdma_v4_4_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1279 uint32_t val, uint32_t mask)
1280{
1281 sdma_v4_4_2_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
1282}
1283
1284static bool sdma_v4_4_2_fw_support_paging_queue(struct amdgpu_device *adev)
1285{
1286 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
1287 case IP_VERSION(4, 4, 2):
1288 case IP_VERSION(4, 4, 5):
1289 return false;
1290 default:
1291 return false;
1292 }
1293}
1294
1295static int sdma_v4_4_2_early_init(struct amdgpu_ip_block *ip_block)
1296{
1297 struct amdgpu_device *adev = ip_block->adev;
1298 int r;
1299
1300 r = sdma_v4_4_2_init_microcode(adev);
1301 if (r)
1302 return r;
1303
1304 /* TODO: Page queue breaks driver reload under SRIOV */
1305 if (sdma_v4_4_2_fw_support_paging_queue(adev))
1306 adev->sdma.has_page_queue = true;
1307
1308 sdma_v4_4_2_set_ring_funcs(adev);
1309 sdma_v4_4_2_set_buffer_funcs(adev);
1310 sdma_v4_4_2_set_vm_pte_funcs(adev);
1311 sdma_v4_4_2_set_irq_funcs(adev);
1312 sdma_v4_4_2_set_ras_funcs(adev);
1313
1314 return 0;
1315}
1316
1317#if 0
1318static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev,
1319 void *err_data,
1320 struct amdgpu_iv_entry *entry);
1321#endif
1322
1323static int sdma_v4_4_2_late_init(struct amdgpu_ip_block *ip_block)
1324{
1325 struct amdgpu_device *adev = ip_block->adev;
1326#if 0
1327 struct ras_ih_if ih_info = {
1328 .cb = sdma_v4_4_2_process_ras_data_cb,
1329 };
1330#endif
1331 if (!amdgpu_persistent_edc_harvesting_supported(adev))
1332 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__SDMA);
1333
1334 return 0;
1335}
1336
1337static int sdma_v4_4_2_sw_init(struct amdgpu_ip_block *ip_block)
1338{
1339 struct amdgpu_ring *ring;
1340 int r, i;
1341 struct amdgpu_device *adev = ip_block->adev;
1342 u32 aid_id;
1343 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2);
1344 uint32_t *ptr;
1345
1346 /* SDMA trap event */
1347 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) {
1348 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1349 SDMA0_4_0__SRCID__SDMA_TRAP,
1350 &adev->sdma.trap_irq);
1351 if (r)
1352 return r;
1353 }
1354
1355 /* SDMA SRAM ECC event */
1356 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) {
1357 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1358 SDMA0_4_0__SRCID__SDMA_SRAM_ECC,
1359 &adev->sdma.ecc_irq);
1360 if (r)
1361 return r;
1362 }
1363
1364 /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/
1365 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) {
1366 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1367 SDMA0_4_0__SRCID__SDMA_VM_HOLE,
1368 &adev->sdma.vm_hole_irq);
1369 if (r)
1370 return r;
1371
1372 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1373 SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID,
1374 &adev->sdma.doorbell_invalid_irq);
1375 if (r)
1376 return r;
1377
1378 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1379 SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT,
1380 &adev->sdma.pool_timeout_irq);
1381 if (r)
1382 return r;
1383
1384 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1385 SDMA0_4_0__SRCID__SDMA_SRBMWRITE,
1386 &adev->sdma.srbm_write_irq);
1387 if (r)
1388 return r;
1389 }
1390
1391 for (i = 0; i < adev->sdma.num_instances; i++) {
1392 ring = &adev->sdma.instance[i].ring;
1393 ring->ring_obj = NULL;
1394 ring->use_doorbell = true;
1395 aid_id = adev->sdma.instance[i].aid_id;
1396
1397 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1398 ring->use_doorbell?"true":"false");
1399
1400 /* doorbell size is 2 dwords, get DWORD offset */
1401 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1402 ring->vm_hub = AMDGPU_MMHUB0(aid_id);
1403
1404 sprintf(ring->name, "sdma%d.%d", aid_id,
1405 i % adev->sdma.num_inst_per_aid);
1406 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1407 AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1408 AMDGPU_RING_PRIO_DEFAULT, NULL);
1409 if (r)
1410 return r;
1411
1412 if (adev->sdma.has_page_queue) {
1413 ring = &adev->sdma.instance[i].page;
1414 ring->ring_obj = NULL;
1415 ring->use_doorbell = true;
1416
1417 /* doorbell index of page queue is assigned right after
1418 * gfx queue on the same instance
1419 */
1420 ring->doorbell_index =
1421 (adev->doorbell_index.sdma_engine[i] + 1) << 1;
1422 ring->vm_hub = AMDGPU_MMHUB0(aid_id);
1423
1424 sprintf(ring->name, "page%d.%d", aid_id,
1425 i % adev->sdma.num_inst_per_aid);
1426 r = amdgpu_ring_init(adev, ring, 1024,
1427 &adev->sdma.trap_irq,
1428 AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1429 AMDGPU_RING_PRIO_DEFAULT, NULL);
1430 if (r)
1431 return r;
1432 }
1433 }
1434
1435 /* TODO: Add queue reset mask when FW fully supports it */
1436 adev->sdma.supported_reset =
1437 amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring);
1438
1439 if (amdgpu_sdma_ras_sw_init(adev)) {
1440 dev_err(adev->dev, "fail to initialize sdma ras block\n");
1441 return -EINVAL;
1442 }
1443
1444 /* Allocate memory for SDMA IP Dump buffer */
1445 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL);
1446 if (ptr)
1447 adev->sdma.ip_dump = ptr;
1448 else
1449 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");
1450
1451 r = amdgpu_sdma_sysfs_reset_mask_init(adev);
1452 if (r)
1453 return r;
1454
1455 return r;
1456}
1457
1458static int sdma_v4_4_2_sw_fini(struct amdgpu_ip_block *ip_block)
1459{
1460 struct amdgpu_device *adev = ip_block->adev;
1461 int i;
1462
1463 for (i = 0; i < adev->sdma.num_instances; i++) {
1464 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1465 if (adev->sdma.has_page_queue)
1466 amdgpu_ring_fini(&adev->sdma.instance[i].page);
1467 }
1468
1469 amdgpu_sdma_sysfs_reset_mask_fini(adev);
1470 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2) ||
1471 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5))
1472 amdgpu_sdma_destroy_inst_ctx(adev, true);
1473 else
1474 amdgpu_sdma_destroy_inst_ctx(adev, false);
1475
1476 kfree(adev->sdma.ip_dump);
1477
1478 return 0;
1479}
1480
1481static int sdma_v4_4_2_hw_init(struct amdgpu_ip_block *ip_block)
1482{
1483 int r;
1484 struct amdgpu_device *adev = ip_block->adev;
1485 uint32_t inst_mask;
1486
1487 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
1488 if (!amdgpu_sriov_vf(adev))
1489 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask);
1490
1491 r = sdma_v4_4_2_inst_start(adev, inst_mask);
1492
1493 return r;
1494}
1495
1496static int sdma_v4_4_2_hw_fini(struct amdgpu_ip_block *ip_block)
1497{
1498 struct amdgpu_device *adev = ip_block->adev;
1499 uint32_t inst_mask;
1500 int i;
1501
1502 if (amdgpu_sriov_vf(adev))
1503 return 0;
1504
1505 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
1506 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
1507 for (i = 0; i < adev->sdma.num_instances; i++) {
1508 amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
1509 AMDGPU_SDMA_IRQ_INSTANCE0 + i);
1510 }
1511 }
1512
1513 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
1514 sdma_v4_4_2_inst_enable(adev, false, inst_mask);
1515
1516 return 0;
1517}
1518
1519static int sdma_v4_4_2_set_clockgating_state(void *handle,
1520 enum amd_clockgating_state state);
1521
1522static int sdma_v4_4_2_suspend(struct amdgpu_ip_block *ip_block)
1523{
1524 struct amdgpu_device *adev = ip_block->adev;
1525
1526 if (amdgpu_in_reset(adev))
1527 sdma_v4_4_2_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
1528
1529 return sdma_v4_4_2_hw_fini(ip_block);
1530}
1531
1532static int sdma_v4_4_2_resume(struct amdgpu_ip_block *ip_block)
1533{
1534 return sdma_v4_4_2_hw_init(ip_block);
1535}
1536
1537static bool sdma_v4_4_2_is_idle(void *handle)
1538{
1539 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1540 u32 i;
1541
1542 for (i = 0; i < adev->sdma.num_instances; i++) {
1543 u32 tmp = RREG32_SDMA(i, regSDMA_STATUS_REG);
1544
1545 if (!(tmp & SDMA_STATUS_REG__IDLE_MASK))
1546 return false;
1547 }
1548
1549 return true;
1550}
1551
1552static int sdma_v4_4_2_wait_for_idle(struct amdgpu_ip_block *ip_block)
1553{
1554 unsigned i, j;
1555 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES];
1556 struct amdgpu_device *adev = ip_block->adev;
1557
1558 for (i = 0; i < adev->usec_timeout; i++) {
1559 for (j = 0; j < adev->sdma.num_instances; j++) {
1560 sdma[j] = RREG32_SDMA(j, regSDMA_STATUS_REG);
1561 if (!(sdma[j] & SDMA_STATUS_REG__IDLE_MASK))
1562 break;
1563 }
1564 if (j == adev->sdma.num_instances)
1565 return 0;
1566 udelay(1);
1567 }
1568 return -ETIMEDOUT;
1569}
1570
1571static int sdma_v4_4_2_soft_reset(struct amdgpu_ip_block *ip_block)
1572{
1573 /* todo */
1574
1575 return 0;
1576}
1577
1578static int sdma_v4_4_2_set_trap_irq_state(struct amdgpu_device *adev,
1579 struct amdgpu_irq_src *source,
1580 unsigned type,
1581 enum amdgpu_interrupt_state state)
1582{
1583 u32 sdma_cntl;
1584
1585 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL);
1586 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, TRAP_ENABLE,
1587 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1588 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);
1589
1590 return 0;
1591}
1592
1593static int sdma_v4_4_2_process_trap_irq(struct amdgpu_device *adev,
1594 struct amdgpu_irq_src *source,
1595 struct amdgpu_iv_entry *entry)
1596{
1597 uint32_t instance, i;
1598
1599 DRM_DEBUG("IH: SDMA trap\n");
1600 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id);
1601
1602 /* Client id gives the SDMA instance in AID. To know the exact SDMA
1603 * instance, interrupt entry gives the node id which corresponds to the AID instance.
1604 * Match node id with the AID id associated with the SDMA instance. */
1605 for (i = instance; i < adev->sdma.num_instances;
1606 i += adev->sdma.num_inst_per_aid) {
1607 if (adev->sdma.instance[i].aid_id ==
1608 node_id_to_phys_map[entry->node_id])
1609 break;
1610 }
1611
1612 if (i >= adev->sdma.num_instances) {
1613 dev_WARN_ONCE(
1614 adev->dev, 1,
1615 "Couldn't find the right sdma instance in trap handler");
1616 return 0;
1617 }
1618
1619 switch (entry->ring_id) {
1620 case 0:
1621 amdgpu_fence_process(&adev->sdma.instance[i].ring);
1622 break;
1623 default:
1624 break;
1625 }
1626 return 0;
1627}
1628
1629#if 0
1630static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev,
1631 void *err_data,
1632 struct amdgpu_iv_entry *entry)
1633{
1634 int instance;
1635
1636 /* When “Full RAS” is enabled, the per-IP interrupt sources should
1637 * be disabled and the driver should only look for the aggregated
1638 * interrupt via sync flood
1639 */
1640 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA))
1641 goto out;
1642
1643 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id);
1644 if (instance < 0)
1645 goto out;
1646
1647 amdgpu_sdma_process_ras_data_cb(adev, err_data, entry);
1648
1649out:
1650 return AMDGPU_RAS_SUCCESS;
1651}
1652#endif
1653
1654static int sdma_v4_4_2_process_illegal_inst_irq(struct amdgpu_device *adev,
1655 struct amdgpu_irq_src *source,
1656 struct amdgpu_iv_entry *entry)
1657{
1658 int instance;
1659
1660 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1661
1662 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id);
1663 if (instance < 0)
1664 return 0;
1665
1666 switch (entry->ring_id) {
1667 case 0:
1668 drm_sched_fault(&adev->sdma.instance[instance].ring.sched);
1669 break;
1670 }
1671 return 0;
1672}
1673
1674static int sdma_v4_4_2_set_ecc_irq_state(struct amdgpu_device *adev,
1675 struct amdgpu_irq_src *source,
1676 unsigned type,
1677 enum amdgpu_interrupt_state state)
1678{
1679 u32 sdma_cntl;
1680
1681 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL);
1682 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, DRAM_ECC_INT_ENABLE,
1683 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1684 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);
1685
1686 return 0;
1687}
1688
1689static int sdma_v4_4_2_print_iv_entry(struct amdgpu_device *adev,
1690 struct amdgpu_iv_entry *entry)
1691{
1692 int instance;
1693 struct amdgpu_task_info *task_info;
1694 u64 addr;
1695
1696 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id);
1697 if (instance < 0 || instance >= adev->sdma.num_instances) {
1698 dev_err(adev->dev, "sdma instance invalid %d\n", instance);
1699 return -EINVAL;
1700 }
1701
1702 addr = (u64)entry->src_data[0] << 12;
1703 addr |= ((u64)entry->src_data[1] & 0xf) << 44;
1704
1705 dev_dbg_ratelimited(adev->dev,
1706 "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u pasid:%u\n",
1707 instance, addr, entry->src_id, entry->ring_id, entry->vmid,
1708 entry->pasid);
1709
1710 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid);
1711 if (task_info) {
1712 dev_dbg_ratelimited(adev->dev, " for process %s pid %d thread %s pid %d\n",
1713 task_info->process_name, task_info->tgid,
1714 task_info->task_name, task_info->pid);
1715 amdgpu_vm_put_task_info(task_info);
1716 }
1717
1718 return 0;
1719}
1720
1721static int sdma_v4_4_2_process_vm_hole_irq(struct amdgpu_device *adev,
1722 struct amdgpu_irq_src *source,
1723 struct amdgpu_iv_entry *entry)
1724{
1725 dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n");
1726 sdma_v4_4_2_print_iv_entry(adev, entry);
1727 return 0;
1728}
1729
1730static int sdma_v4_4_2_process_doorbell_invalid_irq(struct amdgpu_device *adev,
1731 struct amdgpu_irq_src *source,
1732 struct amdgpu_iv_entry *entry)
1733{
1734
1735 dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n");
1736 sdma_v4_4_2_print_iv_entry(adev, entry);
1737 return 0;
1738}
1739
1740static int sdma_v4_4_2_process_pool_timeout_irq(struct amdgpu_device *adev,
1741 struct amdgpu_irq_src *source,
1742 struct amdgpu_iv_entry *entry)
1743{
1744 dev_dbg_ratelimited(adev->dev,
1745 "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n");
1746 sdma_v4_4_2_print_iv_entry(adev, entry);
1747 return 0;
1748}
1749
1750static int sdma_v4_4_2_process_srbm_write_irq(struct amdgpu_device *adev,
1751 struct amdgpu_irq_src *source,
1752 struct amdgpu_iv_entry *entry)
1753{
1754 dev_dbg_ratelimited(adev->dev,
1755 "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n");
1756 sdma_v4_4_2_print_iv_entry(adev, entry);
1757 return 0;
1758}
1759
1760static void sdma_v4_4_2_inst_update_medium_grain_light_sleep(
1761 struct amdgpu_device *adev, bool enable, uint32_t inst_mask)
1762{
1763 uint32_t data, def;
1764 int i;
1765
1766 /* leave as default if it is not driver controlled */
1767 if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS))
1768 return;
1769
1770 if (enable) {
1771 for_each_inst(i, inst_mask) {
1772 /* 1-not override: enable sdma mem light sleep */
1773 def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL);
1774 data |= SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1775 if (def != data)
1776 WREG32_SDMA(i, regSDMA_POWER_CNTL, data);
1777 }
1778 } else {
1779 for_each_inst(i, inst_mask) {
1780 /* 0-override:disable sdma mem light sleep */
1781 def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL);
1782 data &= ~SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1783 if (def != data)
1784 WREG32_SDMA(i, regSDMA_POWER_CNTL, data);
1785 }
1786 }
1787}
1788
1789static void sdma_v4_4_2_inst_update_medium_grain_clock_gating(
1790 struct amdgpu_device *adev, bool enable, uint32_t inst_mask)
1791{
1792 uint32_t data, def;
1793 int i;
1794
1795 /* leave as default if it is not driver controlled */
1796 if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG))
1797 return;
1798
1799 if (enable) {
1800 for_each_inst(i, inst_mask) {
1801 def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL);
1802 data &= ~(SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1803 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1804 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1805 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1806 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1807 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1808 if (def != data)
1809 WREG32_SDMA(i, regSDMA_CLK_CTRL, data);
1810 }
1811 } else {
1812 for_each_inst(i, inst_mask) {
1813 def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL);
1814 data |= (SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1815 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1816 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1817 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1818 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1819 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1820 if (def != data)
1821 WREG32_SDMA(i, regSDMA_CLK_CTRL, data);
1822 }
1823 }
1824}
1825
1826static int sdma_v4_4_2_set_clockgating_state(void *handle,
1827 enum amd_clockgating_state state)
1828{
1829 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1830 uint32_t inst_mask;
1831
1832 if (amdgpu_sriov_vf(adev))
1833 return 0;
1834
1835 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
1836
1837 sdma_v4_4_2_inst_update_medium_grain_clock_gating(
1838 adev, state == AMD_CG_STATE_GATE, inst_mask);
1839 sdma_v4_4_2_inst_update_medium_grain_light_sleep(
1840 adev, state == AMD_CG_STATE_GATE, inst_mask);
1841 return 0;
1842}
1843
1844static int sdma_v4_4_2_set_powergating_state(void *handle,
1845 enum amd_powergating_state state)
1846{
1847 return 0;
1848}
1849
1850static void sdma_v4_4_2_get_clockgating_state(void *handle, u64 *flags)
1851{
1852 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1853 int data;
1854
1855 if (amdgpu_sriov_vf(adev))
1856 *flags = 0;
1857
1858 /* AMD_CG_SUPPORT_SDMA_MGCG */
1859 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL));
1860 if (!(data & SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK))
1861 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1862
1863 /* AMD_CG_SUPPORT_SDMA_LS */
1864 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL));
1865 if (data & SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1866 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1867}
1868
1869static void sdma_v4_4_2_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
1870{
1871 struct amdgpu_device *adev = ip_block->adev;
1872 int i, j;
1873 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2);
1874 uint32_t instance_offset;
1875
1876 if (!adev->sdma.ip_dump)
1877 return;
1878
1879 drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances);
1880 for (i = 0; i < adev->sdma.num_instances; i++) {
1881 instance_offset = i * reg_count;
1882 drm_printf(p, "\nInstance:%d\n", i);
1883
1884 for (j = 0; j < reg_count; j++)
1885 drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_4_4_2[j].reg_name,
1886 adev->sdma.ip_dump[instance_offset + j]);
1887 }
1888}
1889
1890static void sdma_v4_4_2_dump_ip_state(struct amdgpu_ip_block *ip_block)
1891{
1892 struct amdgpu_device *adev = ip_block->adev;
1893 int i, j;
1894 uint32_t instance_offset;
1895 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2);
1896
1897 if (!adev->sdma.ip_dump)
1898 return;
1899
1900 amdgpu_gfx_off_ctrl(adev, false);
1901 for (i = 0; i < adev->sdma.num_instances; i++) {
1902 instance_offset = i * reg_count;
1903 for (j = 0; j < reg_count; j++)
1904 adev->sdma.ip_dump[instance_offset + j] =
1905 RREG32(sdma_v4_4_2_get_reg_offset(adev, i,
1906 sdma_reg_list_4_4_2[j].reg_offset));
1907 }
1908 amdgpu_gfx_off_ctrl(adev, true);
1909}
1910
1911const struct amd_ip_funcs sdma_v4_4_2_ip_funcs = {
1912 .name = "sdma_v4_4_2",
1913 .early_init = sdma_v4_4_2_early_init,
1914 .late_init = sdma_v4_4_2_late_init,
1915 .sw_init = sdma_v4_4_2_sw_init,
1916 .sw_fini = sdma_v4_4_2_sw_fini,
1917 .hw_init = sdma_v4_4_2_hw_init,
1918 .hw_fini = sdma_v4_4_2_hw_fini,
1919 .suspend = sdma_v4_4_2_suspend,
1920 .resume = sdma_v4_4_2_resume,
1921 .is_idle = sdma_v4_4_2_is_idle,
1922 .wait_for_idle = sdma_v4_4_2_wait_for_idle,
1923 .soft_reset = sdma_v4_4_2_soft_reset,
1924 .set_clockgating_state = sdma_v4_4_2_set_clockgating_state,
1925 .set_powergating_state = sdma_v4_4_2_set_powergating_state,
1926 .get_clockgating_state = sdma_v4_4_2_get_clockgating_state,
1927 .dump_ip_state = sdma_v4_4_2_dump_ip_state,
1928 .print_ip_state = sdma_v4_4_2_print_ip_state,
1929};
1930
1931static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = {
1932 .type = AMDGPU_RING_TYPE_SDMA,
1933 .align_mask = 0xff,
1934 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1935 .support_64bit_ptrs = true,
1936 .get_rptr = sdma_v4_4_2_ring_get_rptr,
1937 .get_wptr = sdma_v4_4_2_ring_get_wptr,
1938 .set_wptr = sdma_v4_4_2_ring_set_wptr,
1939 .emit_frame_size =
1940 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */
1941 3 + /* hdp invalidate */
1942 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */
1943 /* sdma_v4_4_2_ring_emit_vm_flush */
1944 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1945 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1946 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */
1947 .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */
1948 .emit_ib = sdma_v4_4_2_ring_emit_ib,
1949 .emit_fence = sdma_v4_4_2_ring_emit_fence,
1950 .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync,
1951 .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush,
1952 .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush,
1953 .test_ring = sdma_v4_4_2_ring_test_ring,
1954 .test_ib = sdma_v4_4_2_ring_test_ib,
1955 .insert_nop = sdma_v4_4_2_ring_insert_nop,
1956 .pad_ib = sdma_v4_4_2_ring_pad_ib,
1957 .emit_wreg = sdma_v4_4_2_ring_emit_wreg,
1958 .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait,
1959 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1960};
1961
1962static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs = {
1963 .type = AMDGPU_RING_TYPE_SDMA,
1964 .align_mask = 0xff,
1965 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1966 .support_64bit_ptrs = true,
1967 .get_rptr = sdma_v4_4_2_ring_get_rptr,
1968 .get_wptr = sdma_v4_4_2_page_ring_get_wptr,
1969 .set_wptr = sdma_v4_4_2_page_ring_set_wptr,
1970 .emit_frame_size =
1971 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */
1972 3 + /* hdp invalidate */
1973 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */
1974 /* sdma_v4_4_2_ring_emit_vm_flush */
1975 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1976 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1977 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */
1978 .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */
1979 .emit_ib = sdma_v4_4_2_ring_emit_ib,
1980 .emit_fence = sdma_v4_4_2_ring_emit_fence,
1981 .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync,
1982 .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush,
1983 .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush,
1984 .test_ring = sdma_v4_4_2_ring_test_ring,
1985 .test_ib = sdma_v4_4_2_ring_test_ib,
1986 .insert_nop = sdma_v4_4_2_ring_insert_nop,
1987 .pad_ib = sdma_v4_4_2_ring_pad_ib,
1988 .emit_wreg = sdma_v4_4_2_ring_emit_wreg,
1989 .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait,
1990 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1991};
1992
1993static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev)
1994{
1995 int i, dev_inst;
1996
1997 for (i = 0; i < adev->sdma.num_instances; i++) {
1998 adev->sdma.instance[i].ring.funcs = &sdma_v4_4_2_ring_funcs;
1999 adev->sdma.instance[i].ring.me = i;
2000 if (adev->sdma.has_page_queue) {
2001 adev->sdma.instance[i].page.funcs =
2002 &sdma_v4_4_2_page_ring_funcs;
2003 adev->sdma.instance[i].page.me = i;
2004 }
2005
2006 dev_inst = GET_INST(SDMA0, i);
2007 /* AID to which SDMA belongs depends on physical instance */
2008 adev->sdma.instance[i].aid_id =
2009 dev_inst / adev->sdma.num_inst_per_aid;
2010 }
2011}
2012
2013static const struct amdgpu_irq_src_funcs sdma_v4_4_2_trap_irq_funcs = {
2014 .set = sdma_v4_4_2_set_trap_irq_state,
2015 .process = sdma_v4_4_2_process_trap_irq,
2016};
2017
2018static const struct amdgpu_irq_src_funcs sdma_v4_4_2_illegal_inst_irq_funcs = {
2019 .process = sdma_v4_4_2_process_illegal_inst_irq,
2020};
2021
2022static const struct amdgpu_irq_src_funcs sdma_v4_4_2_ecc_irq_funcs = {
2023 .set = sdma_v4_4_2_set_ecc_irq_state,
2024 .process = amdgpu_sdma_process_ecc_irq,
2025};
2026
2027static const struct amdgpu_irq_src_funcs sdma_v4_4_2_vm_hole_irq_funcs = {
2028 .process = sdma_v4_4_2_process_vm_hole_irq,
2029};
2030
2031static const struct amdgpu_irq_src_funcs sdma_v4_4_2_doorbell_invalid_irq_funcs = {
2032 .process = sdma_v4_4_2_process_doorbell_invalid_irq,
2033};
2034
2035static const struct amdgpu_irq_src_funcs sdma_v4_4_2_pool_timeout_irq_funcs = {
2036 .process = sdma_v4_4_2_process_pool_timeout_irq,
2037};
2038
2039static const struct amdgpu_irq_src_funcs sdma_v4_4_2_srbm_write_irq_funcs = {
2040 .process = sdma_v4_4_2_process_srbm_write_irq,
2041};
2042
2043static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev)
2044{
2045 adev->sdma.trap_irq.num_types = adev->sdma.num_instances;
2046 adev->sdma.ecc_irq.num_types = adev->sdma.num_instances;
2047 adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances;
2048 adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances;
2049 adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances;
2050 adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances;
2051
2052 adev->sdma.trap_irq.funcs = &sdma_v4_4_2_trap_irq_funcs;
2053 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_4_2_illegal_inst_irq_funcs;
2054 adev->sdma.ecc_irq.funcs = &sdma_v4_4_2_ecc_irq_funcs;
2055 adev->sdma.vm_hole_irq.funcs = &sdma_v4_4_2_vm_hole_irq_funcs;
2056 adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_4_2_doorbell_invalid_irq_funcs;
2057 adev->sdma.pool_timeout_irq.funcs = &sdma_v4_4_2_pool_timeout_irq_funcs;
2058 adev->sdma.srbm_write_irq.funcs = &sdma_v4_4_2_srbm_write_irq_funcs;
2059}
2060
2061/**
2062 * sdma_v4_4_2_emit_copy_buffer - copy buffer using the sDMA engine
2063 *
2064 * @ib: indirect buffer to copy to
2065 * @src_offset: src GPU address
2066 * @dst_offset: dst GPU address
2067 * @byte_count: number of bytes to xfer
2068 * @copy_flags: copy flags for the buffers
2069 *
2070 * Copy GPU buffers using the DMA engine.
2071 * Used by the amdgpu ttm implementation to move pages if
2072 * registered as the asic copy callback.
2073 */
2074static void sdma_v4_4_2_emit_copy_buffer(struct amdgpu_ib *ib,
2075 uint64_t src_offset,
2076 uint64_t dst_offset,
2077 uint32_t byte_count,
2078 uint32_t copy_flags)
2079{
2080 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
2081 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
2082 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0);
2083 ib->ptr[ib->length_dw++] = byte_count - 1;
2084 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
2085 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
2086 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
2087 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2088 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2089}
2090
2091/**
2092 * sdma_v4_4_2_emit_fill_buffer - fill buffer using the sDMA engine
2093 *
2094 * @ib: indirect buffer to copy to
2095 * @src_data: value to write to buffer
2096 * @dst_offset: dst GPU address
2097 * @byte_count: number of bytes to xfer
2098 *
2099 * Fill GPU buffers using the DMA engine.
2100 */
2101static void sdma_v4_4_2_emit_fill_buffer(struct amdgpu_ib *ib,
2102 uint32_t src_data,
2103 uint64_t dst_offset,
2104 uint32_t byte_count)
2105{
2106 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
2107 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2108 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2109 ib->ptr[ib->length_dw++] = src_data;
2110 ib->ptr[ib->length_dw++] = byte_count - 1;
2111}
2112
2113static const struct amdgpu_buffer_funcs sdma_v4_4_2_buffer_funcs = {
2114 .copy_max_bytes = 0x400000,
2115 .copy_num_dw = 7,
2116 .emit_copy_buffer = sdma_v4_4_2_emit_copy_buffer,
2117
2118 .fill_max_bytes = 0x400000,
2119 .fill_num_dw = 5,
2120 .emit_fill_buffer = sdma_v4_4_2_emit_fill_buffer,
2121};
2122
2123static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev)
2124{
2125 adev->mman.buffer_funcs = &sdma_v4_4_2_buffer_funcs;
2126 if (adev->sdma.has_page_queue)
2127 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
2128 else
2129 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
2130}
2131
2132static const struct amdgpu_vm_pte_funcs sdma_v4_4_2_vm_pte_funcs = {
2133 .copy_pte_num_dw = 7,
2134 .copy_pte = sdma_v4_4_2_vm_copy_pte,
2135
2136 .write_pte = sdma_v4_4_2_vm_write_pte,
2137 .set_pte_pde = sdma_v4_4_2_vm_set_pte_pde,
2138};
2139
2140static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev)
2141{
2142 struct drm_gpu_scheduler *sched;
2143 unsigned i;
2144
2145 adev->vm_manager.vm_pte_funcs = &sdma_v4_4_2_vm_pte_funcs;
2146 for (i = 0; i < adev->sdma.num_instances; i++) {
2147 if (adev->sdma.has_page_queue)
2148 sched = &adev->sdma.instance[i].page.sched;
2149 else
2150 sched = &adev->sdma.instance[i].ring.sched;
2151 adev->vm_manager.vm_pte_scheds[i] = sched;
2152 }
2153 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
2154}
2155
2156const struct amdgpu_ip_block_version sdma_v4_4_2_ip_block = {
2157 .type = AMD_IP_BLOCK_TYPE_SDMA,
2158 .major = 4,
2159 .minor = 4,
2160 .rev = 2,
2161 .funcs = &sdma_v4_4_2_ip_funcs,
2162};
2163
2164static int sdma_v4_4_2_xcp_resume(void *handle, uint32_t inst_mask)
2165{
2166 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2167 int r;
2168
2169 if (!amdgpu_sriov_vf(adev))
2170 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask);
2171
2172 r = sdma_v4_4_2_inst_start(adev, inst_mask);
2173
2174 return r;
2175}
2176
2177static int sdma_v4_4_2_xcp_suspend(void *handle, uint32_t inst_mask)
2178{
2179 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2180 uint32_t tmp_mask = inst_mask;
2181 int i;
2182
2183 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2184 for_each_inst(i, tmp_mask) {
2185 amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
2186 AMDGPU_SDMA_IRQ_INSTANCE0 + i);
2187 }
2188 }
2189
2190 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
2191 sdma_v4_4_2_inst_enable(adev, false, inst_mask);
2192
2193 return 0;
2194}
2195
2196struct amdgpu_xcp_ip_funcs sdma_v4_4_2_xcp_funcs = {
2197 .suspend = &sdma_v4_4_2_xcp_suspend,
2198 .resume = &sdma_v4_4_2_xcp_resume
2199};
2200
2201static const struct amdgpu_ras_err_status_reg_entry sdma_v4_2_2_ue_reg_list[] = {
2202 {AMDGPU_RAS_REG_ENTRY(SDMA0, 0, regSDMA_UE_ERR_STATUS_LO, regSDMA_UE_ERR_STATUS_HI),
2203 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SDMA"},
2204};
2205
2206static const struct amdgpu_ras_memory_id_entry sdma_v4_4_2_ras_memory_list[] = {
2207 {AMDGPU_SDMA_MBANK_DATA_BUF0, "SDMA_MBANK_DATA_BUF0"},
2208 {AMDGPU_SDMA_MBANK_DATA_BUF1, "SDMA_MBANK_DATA_BUF1"},
2209 {AMDGPU_SDMA_MBANK_DATA_BUF2, "SDMA_MBANK_DATA_BUF2"},
2210 {AMDGPU_SDMA_MBANK_DATA_BUF3, "SDMA_MBANK_DATA_BUF3"},
2211 {AMDGPU_SDMA_MBANK_DATA_BUF4, "SDMA_MBANK_DATA_BUF4"},
2212 {AMDGPU_SDMA_MBANK_DATA_BUF5, "SDMA_MBANK_DATA_BUF5"},
2213 {AMDGPU_SDMA_MBANK_DATA_BUF6, "SDMA_MBANK_DATA_BUF6"},
2214 {AMDGPU_SDMA_MBANK_DATA_BUF7, "SDMA_MBANK_DATA_BUF7"},
2215 {AMDGPU_SDMA_MBANK_DATA_BUF8, "SDMA_MBANK_DATA_BUF8"},
2216 {AMDGPU_SDMA_MBANK_DATA_BUF9, "SDMA_MBANK_DATA_BUF9"},
2217 {AMDGPU_SDMA_MBANK_DATA_BUF10, "SDMA_MBANK_DATA_BUF10"},
2218 {AMDGPU_SDMA_MBANK_DATA_BUF11, "SDMA_MBANK_DATA_BUF11"},
2219 {AMDGPU_SDMA_MBANK_DATA_BUF12, "SDMA_MBANK_DATA_BUF12"},
2220 {AMDGPU_SDMA_MBANK_DATA_BUF13, "SDMA_MBANK_DATA_BUF13"},
2221 {AMDGPU_SDMA_MBANK_DATA_BUF14, "SDMA_MBANK_DATA_BUF14"},
2222 {AMDGPU_SDMA_MBANK_DATA_BUF15, "SDMA_MBANK_DATA_BUF15"},
2223 {AMDGPU_SDMA_UCODE_BUF, "SDMA_UCODE_BUF"},
2224 {AMDGPU_SDMA_RB_CMD_BUF, "SDMA_RB_CMD_BUF"},
2225 {AMDGPU_SDMA_IB_CMD_BUF, "SDMA_IB_CMD_BUF"},
2226 {AMDGPU_SDMA_UTCL1_RD_FIFO, "SDMA_UTCL1_RD_FIFO"},
2227 {AMDGPU_SDMA_UTCL1_RDBST_FIFO, "SDMA_UTCL1_RDBST_FIFO"},
2228 {AMDGPU_SDMA_UTCL1_WR_FIFO, "SDMA_UTCL1_WR_FIFO"},
2229 {AMDGPU_SDMA_DATA_LUT_FIFO, "SDMA_DATA_LUT_FIFO"},
2230 {AMDGPU_SDMA_SPLIT_DAT_BUF, "SDMA_SPLIT_DAT_BUF"},
2231};
2232
2233static void sdma_v4_4_2_inst_query_ras_error_count(struct amdgpu_device *adev,
2234 uint32_t sdma_inst,
2235 void *ras_err_status)
2236{
2237 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status;
2238 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst);
2239 unsigned long ue_count = 0;
2240 struct amdgpu_smuio_mcm_config_info mcm_info = {
2241 .socket_id = adev->smuio.funcs->get_socket_id(adev),
2242 .die_id = adev->sdma.instance[sdma_inst].aid_id,
2243 };
2244
2245 /* sdma v4_4_2 doesn't support query ce counts */
2246 amdgpu_ras_inst_query_ras_error_count(adev,
2247 sdma_v4_2_2_ue_reg_list,
2248 ARRAY_SIZE(sdma_v4_2_2_ue_reg_list),
2249 sdma_v4_4_2_ras_memory_list,
2250 ARRAY_SIZE(sdma_v4_4_2_ras_memory_list),
2251 sdma_dev_inst,
2252 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
2253 &ue_count);
2254
2255 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count);
2256}
2257
2258static void sdma_v4_4_2_query_ras_error_count(struct amdgpu_device *adev,
2259 void *ras_err_status)
2260{
2261 uint32_t inst_mask;
2262 int i = 0;
2263
2264 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
2265 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2266 for_each_inst(i, inst_mask)
2267 sdma_v4_4_2_inst_query_ras_error_count(adev, i, ras_err_status);
2268 } else {
2269 dev_warn(adev->dev, "SDMA RAS is not supported\n");
2270 }
2271}
2272
2273static void sdma_v4_4_2_inst_reset_ras_error_count(struct amdgpu_device *adev,
2274 uint32_t sdma_inst)
2275{
2276 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst);
2277
2278 amdgpu_ras_inst_reset_ras_error_count(adev,
2279 sdma_v4_2_2_ue_reg_list,
2280 ARRAY_SIZE(sdma_v4_2_2_ue_reg_list),
2281 sdma_dev_inst);
2282}
2283
2284static void sdma_v4_4_2_reset_ras_error_count(struct amdgpu_device *adev)
2285{
2286 uint32_t inst_mask;
2287 int i = 0;
2288
2289 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
2290 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2291 for_each_inst(i, inst_mask)
2292 sdma_v4_4_2_inst_reset_ras_error_count(adev, i);
2293 } else {
2294 dev_warn(adev->dev, "SDMA RAS is not supported\n");
2295 }
2296}
2297
2298static const struct amdgpu_ras_block_hw_ops sdma_v4_4_2_ras_hw_ops = {
2299 .query_ras_error_count = sdma_v4_4_2_query_ras_error_count,
2300 .reset_ras_error_count = sdma_v4_4_2_reset_ras_error_count,
2301};
2302
2303static int sdma_v4_4_2_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank,
2304 enum aca_smu_type type, void *data)
2305{
2306 struct aca_bank_info info;
2307 u64 misc0;
2308 int ret;
2309
2310 ret = aca_bank_info_decode(bank, &info);
2311 if (ret)
2312 return ret;
2313
2314 misc0 = bank->regs[ACA_REG_IDX_MISC0];
2315 switch (type) {
2316 case ACA_SMU_TYPE_UE:
2317 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_UE,
2318 1ULL);
2319 break;
2320 case ACA_SMU_TYPE_CE:
2321 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_CE,
2322 ACA_REG__MISC0__ERRCNT(misc0));
2323 break;
2324 default:
2325 return -EINVAL;
2326 }
2327
2328 return ret;
2329}
2330
2331/* CODE_SDMA0 - CODE_SDMA4, reference to smu driver if header file */
2332static int sdma_v4_4_2_err_codes[] = { 33, 34, 35, 36 };
2333
2334static bool sdma_v4_4_2_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,
2335 enum aca_smu_type type, void *data)
2336{
2337 u32 instlo;
2338
2339 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]);
2340 instlo &= GENMASK(31, 1);
2341
2342 if (instlo != mmSMNAID_AID0_MCA_SMU)
2343 return false;
2344
2345 if (aca_bank_check_error_codes(handle->adev, bank,
2346 sdma_v4_4_2_err_codes,
2347 ARRAY_SIZE(sdma_v4_4_2_err_codes)))
2348 return false;
2349
2350 return true;
2351}
2352
2353static const struct aca_bank_ops sdma_v4_4_2_aca_bank_ops = {
2354 .aca_bank_parser = sdma_v4_4_2_aca_bank_parser,
2355 .aca_bank_is_valid = sdma_v4_4_2_aca_bank_is_valid,
2356};
2357
2358static const struct aca_info sdma_v4_4_2_aca_info = {
2359 .hwip = ACA_HWIP_TYPE_SMU,
2360 .mask = ACA_ERROR_UE_MASK,
2361 .bank_ops = &sdma_v4_4_2_aca_bank_ops,
2362};
2363
2364static int sdma_v4_4_2_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
2365{
2366 int r;
2367
2368 r = amdgpu_sdma_ras_late_init(adev, ras_block);
2369 if (r)
2370 return r;
2371
2372 return amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__SDMA,
2373 &sdma_v4_4_2_aca_info, NULL);
2374}
2375
2376static struct amdgpu_sdma_ras sdma_v4_4_2_ras = {
2377 .ras_block = {
2378 .hw_ops = &sdma_v4_4_2_ras_hw_ops,
2379 .ras_late_init = sdma_v4_4_2_ras_late_init,
2380 },
2381};
2382
2383static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev)
2384{
2385 adev->sdma.ras = &sdma_v4_4_2_ras;
2386}