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1/*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "amdgpu.h"
24#include "amdgpu_atombios.h"
25#include "hdp_v4_0.h"
26#include "amdgpu_ras.h"
27
28#include "hdp/hdp_4_0_offset.h"
29#include "hdp/hdp_4_0_sh_mask.h"
30#include <uapi/linux/kfd_ioctl.h>
31
32/* for Vega20 register name change */
33#define mmHDP_MEM_POWER_CTRL 0x00d4
34#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L
35#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L
36#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L
37#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
38#define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
39
40static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev,
41 struct amdgpu_ring *ring)
42{
43 if (!ring || !ring->funcs->emit_wreg)
44 WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
45 else
46 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
47}
48
49static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev,
50 struct amdgpu_ring *ring)
51{
52 if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 4, 0))
53 return;
54
55 if (!ring || !ring->funcs->emit_wreg)
56 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
57 else
58 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
59 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
60}
61
62static void hdp_v4_0_query_ras_error_count(struct amdgpu_device *adev,
63 void *ras_error_status)
64{
65 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
66
67 err_data->ue_count = 0;
68 err_data->ce_count = 0;
69
70 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
71 return;
72
73 /* HDP SRAM errors are uncorrectable ones (i.e. fatal errors) */
74 err_data->ue_count += RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
75};
76
77static void hdp_v4_0_reset_ras_error_count(struct amdgpu_device *adev)
78{
79 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
80 return;
81
82 if (adev->ip_versions[HDP_HWIP][0] >= IP_VERSION(4, 4, 0))
83 WREG32_SOC15(HDP, 0, mmHDP_EDC_CNT, 0);
84 else
85 /*read back hdp ras counter to reset it to 0 */
86 RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
87}
88
89static void hdp_v4_0_update_clock_gating(struct amdgpu_device *adev,
90 bool enable)
91{
92 uint32_t def, data;
93
94 if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 0, 0) ||
95 adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 0, 1) ||
96 adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 1, 1) ||
97 adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 1, 0)) {
98 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
99
100 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
101 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
102 else
103 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
104
105 if (def != data)
106 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
107 } else {
108 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
109
110 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
111 data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
112 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
113 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
114 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
115 else
116 data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
117 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
118 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
119 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
120
121 if (def != data)
122 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
123 }
124}
125
126static void hdp_v4_0_get_clockgating_state(struct amdgpu_device *adev,
127 u64 *flags)
128{
129 int data;
130
131 /* AMD_CG_SUPPORT_HDP_LS */
132 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
133 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
134 *flags |= AMD_CG_SUPPORT_HDP_LS;
135}
136
137static void hdp_v4_0_init_registers(struct amdgpu_device *adev)
138{
139 switch (adev->ip_versions[HDP_HWIP][0]) {
140 case IP_VERSION(4, 2, 1):
141 WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1);
142 break;
143 default:
144 break;
145 }
146
147 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
148
149 if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 4, 0))
150 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, READ_BUFFER_WATERMARK, 2);
151
152 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
153 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40));
154}
155
156struct amdgpu_ras_block_hw_ops hdp_v4_0_ras_hw_ops = {
157 .query_ras_error_count = hdp_v4_0_query_ras_error_count,
158 .reset_ras_error_count = hdp_v4_0_reset_ras_error_count,
159};
160
161struct amdgpu_hdp_ras hdp_v4_0_ras = {
162 .ras_block = {
163 .ras_comm = {
164 .name = "hdp",
165 .block = AMDGPU_RAS_BLOCK__HDP,
166 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
167 },
168 .hw_ops = &hdp_v4_0_ras_hw_ops,
169 },
170};
171
172const struct amdgpu_hdp_funcs hdp_v4_0_funcs = {
173 .flush_hdp = hdp_v4_0_flush_hdp,
174 .invalidate_hdp = hdp_v4_0_invalidate_hdp,
175 .update_clock_gating = hdp_v4_0_update_clock_gating,
176 .get_clock_gating_state = hdp_v4_0_get_clockgating_state,
177 .init_registers = hdp_v4_0_init_registers,
178};
1/*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "amdgpu.h"
24#include "amdgpu_atombios.h"
25#include "hdp_v4_0.h"
26#include "amdgpu_ras.h"
27
28#include "hdp/hdp_4_0_offset.h"
29#include "hdp/hdp_4_0_sh_mask.h"
30#include <uapi/linux/kfd_ioctl.h>
31
32/* for Vega20 register name change */
33#define mmHDP_MEM_POWER_CTRL 0x00d4
34#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L
35#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L
36#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L
37#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
38#define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
39
40static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev,
41 struct amdgpu_ring *ring)
42{
43 if (!ring || !ring->funcs->emit_wreg) {
44 WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
45 RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);
46 } else {
47 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
48 }
49}
50
51static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev,
52 struct amdgpu_ring *ring)
53{
54 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 0) ||
55 amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 2) ||
56 amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 5))
57 return;
58
59 if (!ring || !ring->funcs->emit_wreg) {
60 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
61 RREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE);
62 } else {
63 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
64 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
65 }
66}
67
68static void hdp_v4_0_query_ras_error_count(struct amdgpu_device *adev,
69 void *ras_error_status)
70{
71 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
72
73 err_data->ue_count = 0;
74 err_data->ce_count = 0;
75
76 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
77 return;
78
79 /* HDP SRAM errors are uncorrectable ones (i.e. fatal errors) */
80 err_data->ue_count += RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
81};
82
83static void hdp_v4_0_reset_ras_error_count(struct amdgpu_device *adev)
84{
85 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
86 return;
87
88 if (amdgpu_ip_version(adev, HDP_HWIP, 0) >= IP_VERSION(4, 4, 0))
89 WREG32_SOC15(HDP, 0, mmHDP_EDC_CNT, 0);
90 else
91 /*read back hdp ras counter to reset it to 0 */
92 RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
93}
94
95static void hdp_v4_0_update_clock_gating(struct amdgpu_device *adev,
96 bool enable)
97{
98 uint32_t def, data;
99
100 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 0, 0) ||
101 amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 0, 1) ||
102 amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 1, 1) ||
103 amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 1, 0)) {
104 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
105
106 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
107 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
108 else
109 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
110
111 if (def != data)
112 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
113 } else {
114 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
115
116 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
117 data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
118 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
119 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
120 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
121 else
122 data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
123 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
124 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
125 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
126
127 if (def != data)
128 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
129 }
130}
131
132static void hdp_v4_0_get_clockgating_state(struct amdgpu_device *adev,
133 u64 *flags)
134{
135 int data;
136
137 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 2) ||
138 amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 5)) {
139 /* Default enabled */
140 *flags |= AMD_CG_SUPPORT_HDP_MGCG;
141 return;
142 }
143 /* AMD_CG_SUPPORT_HDP_LS */
144 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
145 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
146 *flags |= AMD_CG_SUPPORT_HDP_LS;
147}
148
149static void hdp_v4_0_init_registers(struct amdgpu_device *adev)
150{
151 switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) {
152 case IP_VERSION(4, 2, 1):
153 WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1);
154 break;
155 default:
156 break;
157 }
158
159 /* Do not program registers if VF */
160 if (amdgpu_sriov_vf(adev))
161 return;
162
163 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
164
165 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 0))
166 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, READ_BUFFER_WATERMARK, 2);
167
168 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
169 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40));
170}
171
172struct amdgpu_ras_block_hw_ops hdp_v4_0_ras_hw_ops = {
173 .query_ras_error_count = hdp_v4_0_query_ras_error_count,
174 .reset_ras_error_count = hdp_v4_0_reset_ras_error_count,
175};
176
177struct amdgpu_hdp_ras hdp_v4_0_ras = {
178 .ras_block = {
179 .hw_ops = &hdp_v4_0_ras_hw_ops,
180 },
181};
182
183const struct amdgpu_hdp_funcs hdp_v4_0_funcs = {
184 .flush_hdp = hdp_v4_0_flush_hdp,
185 .invalidate_hdp = hdp_v4_0_invalidate_hdp,
186 .update_clock_gating = hdp_v4_0_update_clock_gating,
187 .get_clock_gating_state = hdp_v4_0_get_clockgating_state,
188 .init_registers = hdp_v4_0_init_registers,
189};