Loading...
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/dma-fence-array.h>
30#include <linux/interval_tree_generic.h>
31#include <linux/idr.h>
32#include <linux/dma-buf.h>
33
34#include <drm/amdgpu_drm.h>
35#include <drm/drm_drv.h>
36#include "amdgpu.h"
37#include "amdgpu_trace.h"
38#include "amdgpu_amdkfd.h"
39#include "amdgpu_gmc.h"
40#include "amdgpu_xgmi.h"
41#include "amdgpu_dma_buf.h"
42#include "amdgpu_res_cursor.h"
43#include "kfd_svm.h"
44
45/**
46 * DOC: GPUVM
47 *
48 * GPUVM is the MMU functionality provided on the GPU.
49 * GPUVM is similar to the legacy GART on older asics, however
50 * rather than there being a single global GART table
51 * for the entire GPU, there can be multiple GPUVM page tables active
52 * at any given time. The GPUVM page tables can contain a mix
53 * VRAM pages and system pages (both memory and MMIO) and system pages
54 * can be mapped as snooped (cached system pages) or unsnooped
55 * (uncached system pages).
56 *
57 * Each active GPUVM has an ID associated with it and there is a page table
58 * linked with each VMID. When executing a command buffer,
59 * the kernel tells the engine what VMID to use for that command
60 * buffer. VMIDs are allocated dynamically as commands are submitted.
61 * The userspace drivers maintain their own address space and the kernel
62 * sets up their pages tables accordingly when they submit their
63 * command buffers and a VMID is assigned.
64 * The hardware supports up to 16 active GPUVMs at any given time.
65 *
66 * Each GPUVM is represented by a 1-2 or 1-5 level page table, depending
67 * on the ASIC family. GPUVM supports RWX attributes on each page as well
68 * as other features such as encryption and caching attributes.
69 *
70 * VMID 0 is special. It is the GPUVM used for the kernel driver. In
71 * addition to an aperture managed by a page table, VMID 0 also has
72 * several other apertures. There is an aperture for direct access to VRAM
73 * and there is a legacy AGP aperture which just forwards accesses directly
74 * to the matching system physical addresses (or IOVAs when an IOMMU is
75 * present). These apertures provide direct access to these memories without
76 * incurring the overhead of a page table. VMID 0 is used by the kernel
77 * driver for tasks like memory management.
78 *
79 * GPU clients (i.e., engines on the GPU) use GPUVM VMIDs to access memory.
80 * For user applications, each application can have their own unique GPUVM
81 * address space. The application manages the address space and the kernel
82 * driver manages the GPUVM page tables for each process. If an GPU client
83 * accesses an invalid page, it will generate a GPU page fault, similar to
84 * accessing an invalid page on a CPU.
85 */
86
87#define START(node) ((node)->start)
88#define LAST(node) ((node)->last)
89
90INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
91 START, LAST, static, amdgpu_vm_it)
92
93#undef START
94#undef LAST
95
96/**
97 * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback
98 */
99struct amdgpu_prt_cb {
100
101 /**
102 * @adev: amdgpu device
103 */
104 struct amdgpu_device *adev;
105
106 /**
107 * @cb: callback
108 */
109 struct dma_fence_cb cb;
110};
111
112/**
113 * struct amdgpu_vm_tlb_seq_cb - Helper to increment the TLB flush sequence
114 */
115struct amdgpu_vm_tlb_seq_cb {
116 /**
117 * @vm: pointer to the amdgpu_vm structure to set the fence sequence on
118 */
119 struct amdgpu_vm *vm;
120
121 /**
122 * @cb: callback
123 */
124 struct dma_fence_cb cb;
125};
126
127/**
128 * amdgpu_vm_set_pasid - manage pasid and vm ptr mapping
129 *
130 * @adev: amdgpu_device pointer
131 * @vm: amdgpu_vm pointer
132 * @pasid: the pasid the VM is using on this GPU
133 *
134 * Set the pasid this VM is using on this GPU, can also be used to remove the
135 * pasid by passing in zero.
136 *
137 */
138int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm,
139 u32 pasid)
140{
141 int r;
142
143 if (vm->pasid == pasid)
144 return 0;
145
146 if (vm->pasid) {
147 r = xa_err(xa_erase_irq(&adev->vm_manager.pasids, vm->pasid));
148 if (r < 0)
149 return r;
150
151 vm->pasid = 0;
152 }
153
154 if (pasid) {
155 r = xa_err(xa_store_irq(&adev->vm_manager.pasids, pasid, vm,
156 GFP_KERNEL));
157 if (r < 0)
158 return r;
159
160 vm->pasid = pasid;
161 }
162
163
164 return 0;
165}
166
167/**
168 * amdgpu_vm_bo_evicted - vm_bo is evicted
169 *
170 * @vm_bo: vm_bo which is evicted
171 *
172 * State for PDs/PTs and per VM BOs which are not at the location they should
173 * be.
174 */
175static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo)
176{
177 struct amdgpu_vm *vm = vm_bo->vm;
178 struct amdgpu_bo *bo = vm_bo->bo;
179
180 vm_bo->moved = true;
181 spin_lock(&vm_bo->vm->status_lock);
182 if (bo->tbo.type == ttm_bo_type_kernel)
183 list_move(&vm_bo->vm_status, &vm->evicted);
184 else
185 list_move_tail(&vm_bo->vm_status, &vm->evicted);
186 spin_unlock(&vm_bo->vm->status_lock);
187}
188/**
189 * amdgpu_vm_bo_moved - vm_bo is moved
190 *
191 * @vm_bo: vm_bo which is moved
192 *
193 * State for per VM BOs which are moved, but that change is not yet reflected
194 * in the page tables.
195 */
196static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo)
197{
198 spin_lock(&vm_bo->vm->status_lock);
199 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
200 spin_unlock(&vm_bo->vm->status_lock);
201}
202
203/**
204 * amdgpu_vm_bo_idle - vm_bo is idle
205 *
206 * @vm_bo: vm_bo which is now idle
207 *
208 * State for PDs/PTs and per VM BOs which have gone through the state machine
209 * and are now idle.
210 */
211static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo)
212{
213 spin_lock(&vm_bo->vm->status_lock);
214 list_move(&vm_bo->vm_status, &vm_bo->vm->idle);
215 spin_unlock(&vm_bo->vm->status_lock);
216 vm_bo->moved = false;
217}
218
219/**
220 * amdgpu_vm_bo_invalidated - vm_bo is invalidated
221 *
222 * @vm_bo: vm_bo which is now invalidated
223 *
224 * State for normal BOs which are invalidated and that change not yet reflected
225 * in the PTs.
226 */
227static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo)
228{
229 spin_lock(&vm_bo->vm->status_lock);
230 list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated);
231 spin_unlock(&vm_bo->vm->status_lock);
232}
233
234/**
235 * amdgpu_vm_bo_relocated - vm_bo is reloacted
236 *
237 * @vm_bo: vm_bo which is relocated
238 *
239 * State for PDs/PTs which needs to update their parent PD.
240 * For the root PD, just move to idle state.
241 */
242static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo)
243{
244 if (vm_bo->bo->parent) {
245 spin_lock(&vm_bo->vm->status_lock);
246 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
247 spin_unlock(&vm_bo->vm->status_lock);
248 } else {
249 amdgpu_vm_bo_idle(vm_bo);
250 }
251}
252
253/**
254 * amdgpu_vm_bo_done - vm_bo is done
255 *
256 * @vm_bo: vm_bo which is now done
257 *
258 * State for normal BOs which are invalidated and that change has been updated
259 * in the PTs.
260 */
261static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo)
262{
263 spin_lock(&vm_bo->vm->status_lock);
264 list_move(&vm_bo->vm_status, &vm_bo->vm->done);
265 spin_unlock(&vm_bo->vm->status_lock);
266}
267
268/**
269 * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm
270 *
271 * @base: base structure for tracking BO usage in a VM
272 * @vm: vm to which bo is to be added
273 * @bo: amdgpu buffer object
274 *
275 * Initialize a bo_va_base structure and add it to the appropriate lists
276 *
277 */
278void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
279 struct amdgpu_vm *vm, struct amdgpu_bo *bo)
280{
281 base->vm = vm;
282 base->bo = bo;
283 base->next = NULL;
284 INIT_LIST_HEAD(&base->vm_status);
285
286 if (!bo)
287 return;
288 base->next = bo->vm_bo;
289 bo->vm_bo = base;
290
291 if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv)
292 return;
293
294 dma_resv_assert_held(vm->root.bo->tbo.base.resv);
295
296 ttm_bo_set_bulk_move(&bo->tbo, &vm->lru_bulk_move);
297 if (bo->tbo.type == ttm_bo_type_kernel && bo->parent)
298 amdgpu_vm_bo_relocated(base);
299 else
300 amdgpu_vm_bo_idle(base);
301
302 if (bo->preferred_domains &
303 amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type))
304 return;
305
306 /*
307 * we checked all the prerequisites, but it looks like this per vm bo
308 * is currently evicted. add the bo to the evicted list to make sure it
309 * is validated on next vm use to avoid fault.
310 * */
311 amdgpu_vm_bo_evicted(base);
312}
313
314/**
315 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
316 *
317 * @vm: vm providing the BOs
318 * @validated: head of validation list
319 * @entry: entry to add
320 *
321 * Add the page directory to the list of BOs to
322 * validate for command submission.
323 */
324void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
325 struct list_head *validated,
326 struct amdgpu_bo_list_entry *entry)
327{
328 entry->priority = 0;
329 entry->tv.bo = &vm->root.bo->tbo;
330 /* Two for VM updates, one for TTM and one for the CS job */
331 entry->tv.num_shared = 4;
332 entry->user_pages = NULL;
333 list_add(&entry->tv.head, validated);
334}
335
336/**
337 * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU
338 *
339 * @adev: amdgpu device pointer
340 * @vm: vm providing the BOs
341 *
342 * Move all BOs to the end of LRU and remember their positions to put them
343 * together.
344 */
345void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
346 struct amdgpu_vm *vm)
347{
348 spin_lock(&adev->mman.bdev.lru_lock);
349 ttm_lru_bulk_move_tail(&vm->lru_bulk_move);
350 spin_unlock(&adev->mman.bdev.lru_lock);
351}
352
353/**
354 * amdgpu_vm_validate_pt_bos - validate the page table BOs
355 *
356 * @adev: amdgpu device pointer
357 * @vm: vm providing the BOs
358 * @validate: callback to do the validation
359 * @param: parameter for the validation callback
360 *
361 * Validate the page table BOs on command submission if neccessary.
362 *
363 * Returns:
364 * Validation result.
365 */
366int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
367 int (*validate)(void *p, struct amdgpu_bo *bo),
368 void *param)
369{
370 struct amdgpu_vm_bo_base *bo_base;
371 struct amdgpu_bo *shadow;
372 struct amdgpu_bo *bo;
373 int r;
374
375 spin_lock(&vm->status_lock);
376 while (!list_empty(&vm->evicted)) {
377 bo_base = list_first_entry(&vm->evicted,
378 struct amdgpu_vm_bo_base,
379 vm_status);
380 spin_unlock(&vm->status_lock);
381
382 bo = bo_base->bo;
383 shadow = amdgpu_bo_shadowed(bo);
384
385 r = validate(param, bo);
386 if (r)
387 return r;
388 if (shadow) {
389 r = validate(param, shadow);
390 if (r)
391 return r;
392 }
393
394 if (bo->tbo.type != ttm_bo_type_kernel) {
395 amdgpu_vm_bo_moved(bo_base);
396 } else {
397 vm->update_funcs->map_table(to_amdgpu_bo_vm(bo));
398 amdgpu_vm_bo_relocated(bo_base);
399 }
400 spin_lock(&vm->status_lock);
401 }
402 spin_unlock(&vm->status_lock);
403
404 amdgpu_vm_eviction_lock(vm);
405 vm->evicting = false;
406 amdgpu_vm_eviction_unlock(vm);
407
408 return 0;
409}
410
411/**
412 * amdgpu_vm_ready - check VM is ready for updates
413 *
414 * @vm: VM to check
415 *
416 * Check if all VM PDs/PTs are ready for updates
417 *
418 * Returns:
419 * True if VM is not evicting.
420 */
421bool amdgpu_vm_ready(struct amdgpu_vm *vm)
422{
423 bool empty;
424 bool ret;
425
426 amdgpu_vm_eviction_lock(vm);
427 ret = !vm->evicting;
428 amdgpu_vm_eviction_unlock(vm);
429
430 spin_lock(&vm->status_lock);
431 empty = list_empty(&vm->evicted);
432 spin_unlock(&vm->status_lock);
433
434 return ret && empty;
435}
436
437/**
438 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
439 *
440 * @adev: amdgpu_device pointer
441 */
442void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
443{
444 const struct amdgpu_ip_block *ip_block;
445 bool has_compute_vm_bug;
446 struct amdgpu_ring *ring;
447 int i;
448
449 has_compute_vm_bug = false;
450
451 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
452 if (ip_block) {
453 /* Compute has a VM bug for GFX version < 7.
454 Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
455 if (ip_block->version->major <= 7)
456 has_compute_vm_bug = true;
457 else if (ip_block->version->major == 8)
458 if (adev->gfx.mec_fw_version < 673)
459 has_compute_vm_bug = true;
460 }
461
462 for (i = 0; i < adev->num_rings; i++) {
463 ring = adev->rings[i];
464 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
465 /* only compute rings */
466 ring->has_compute_vm_bug = has_compute_vm_bug;
467 else
468 ring->has_compute_vm_bug = false;
469 }
470}
471
472/**
473 * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job.
474 *
475 * @ring: ring on which the job will be submitted
476 * @job: job to submit
477 *
478 * Returns:
479 * True if sync is needed.
480 */
481bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
482 struct amdgpu_job *job)
483{
484 struct amdgpu_device *adev = ring->adev;
485 unsigned vmhub = ring->funcs->vmhub;
486 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
487
488 if (job->vmid == 0)
489 return false;
490
491 if (job->vm_needs_flush || ring->has_compute_vm_bug)
492 return true;
493
494 if (ring->funcs->emit_gds_switch && job->gds_switch_needed)
495 return true;
496
497 if (amdgpu_vmid_had_gpu_reset(adev, &id_mgr->ids[job->vmid]))
498 return true;
499
500 return false;
501}
502
503/**
504 * amdgpu_vm_flush - hardware flush the vm
505 *
506 * @ring: ring to use for flush
507 * @job: related job
508 * @need_pipe_sync: is pipe sync needed
509 *
510 * Emit a VM flush when it is necessary.
511 *
512 * Returns:
513 * 0 on success, errno otherwise.
514 */
515int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
516 bool need_pipe_sync)
517{
518 struct amdgpu_device *adev = ring->adev;
519 unsigned vmhub = ring->funcs->vmhub;
520 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
521 struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
522 bool spm_update_needed = job->spm_update_needed;
523 bool gds_switch_needed = ring->funcs->emit_gds_switch &&
524 job->gds_switch_needed;
525 bool vm_flush_needed = job->vm_needs_flush;
526 struct dma_fence *fence = NULL;
527 bool pasid_mapping_needed = false;
528 unsigned patch_offset = 0;
529 int r;
530
531 if (amdgpu_vmid_had_gpu_reset(adev, id)) {
532 gds_switch_needed = true;
533 vm_flush_needed = true;
534 pasid_mapping_needed = true;
535 spm_update_needed = true;
536 }
537
538 mutex_lock(&id_mgr->lock);
539 if (id->pasid != job->pasid || !id->pasid_mapping ||
540 !dma_fence_is_signaled(id->pasid_mapping))
541 pasid_mapping_needed = true;
542 mutex_unlock(&id_mgr->lock);
543
544 gds_switch_needed &= !!ring->funcs->emit_gds_switch;
545 vm_flush_needed &= !!ring->funcs->emit_vm_flush &&
546 job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET;
547 pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping &&
548 ring->funcs->emit_wreg;
549
550 if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync)
551 return 0;
552
553 amdgpu_ring_ib_begin(ring);
554 if (ring->funcs->init_cond_exec)
555 patch_offset = amdgpu_ring_init_cond_exec(ring);
556
557 if (need_pipe_sync)
558 amdgpu_ring_emit_pipeline_sync(ring);
559
560 if (vm_flush_needed) {
561 trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
562 amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
563 }
564
565 if (pasid_mapping_needed)
566 amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
567
568 if (spm_update_needed && adev->gfx.rlc.funcs->update_spm_vmid)
569 adev->gfx.rlc.funcs->update_spm_vmid(adev, job->vmid);
570
571 if (!ring->is_mes_queue && ring->funcs->emit_gds_switch &&
572 gds_switch_needed) {
573 amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
574 job->gds_size, job->gws_base,
575 job->gws_size, job->oa_base,
576 job->oa_size);
577 }
578
579 if (vm_flush_needed || pasid_mapping_needed) {
580 r = amdgpu_fence_emit(ring, &fence, NULL, 0);
581 if (r)
582 return r;
583 }
584
585 if (vm_flush_needed) {
586 mutex_lock(&id_mgr->lock);
587 dma_fence_put(id->last_flush);
588 id->last_flush = dma_fence_get(fence);
589 id->current_gpu_reset_count =
590 atomic_read(&adev->gpu_reset_counter);
591 mutex_unlock(&id_mgr->lock);
592 }
593
594 if (pasid_mapping_needed) {
595 mutex_lock(&id_mgr->lock);
596 id->pasid = job->pasid;
597 dma_fence_put(id->pasid_mapping);
598 id->pasid_mapping = dma_fence_get(fence);
599 mutex_unlock(&id_mgr->lock);
600 }
601 dma_fence_put(fence);
602
603 if (ring->funcs->patch_cond_exec)
604 amdgpu_ring_patch_cond_exec(ring, patch_offset);
605
606 /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
607 if (ring->funcs->emit_switch_buffer) {
608 amdgpu_ring_emit_switch_buffer(ring);
609 amdgpu_ring_emit_switch_buffer(ring);
610 }
611 amdgpu_ring_ib_end(ring);
612 return 0;
613}
614
615/**
616 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
617 *
618 * @vm: requested vm
619 * @bo: requested buffer object
620 *
621 * Find @bo inside the requested vm.
622 * Search inside the @bos vm list for the requested vm
623 * Returns the found bo_va or NULL if none is found
624 *
625 * Object has to be reserved!
626 *
627 * Returns:
628 * Found bo_va or NULL.
629 */
630struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
631 struct amdgpu_bo *bo)
632{
633 struct amdgpu_vm_bo_base *base;
634
635 for (base = bo->vm_bo; base; base = base->next) {
636 if (base->vm != vm)
637 continue;
638
639 return container_of(base, struct amdgpu_bo_va, base);
640 }
641 return NULL;
642}
643
644/**
645 * amdgpu_vm_map_gart - Resolve gart mapping of addr
646 *
647 * @pages_addr: optional DMA address to use for lookup
648 * @addr: the unmapped addr
649 *
650 * Look up the physical address of the page that the pte resolves
651 * to.
652 *
653 * Returns:
654 * The pointer for the page table entry.
655 */
656uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
657{
658 uint64_t result;
659
660 /* page table offset */
661 result = pages_addr[addr >> PAGE_SHIFT];
662
663 /* in case cpu page size != gpu page size*/
664 result |= addr & (~PAGE_MASK);
665
666 result &= 0xFFFFFFFFFFFFF000ULL;
667
668 return result;
669}
670
671/**
672 * amdgpu_vm_update_pdes - make sure that all directories are valid
673 *
674 * @adev: amdgpu_device pointer
675 * @vm: requested vm
676 * @immediate: submit immediately to the paging queue
677 *
678 * Makes sure all directories are up to date.
679 *
680 * Returns:
681 * 0 for success, error for failure.
682 */
683int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
684 struct amdgpu_vm *vm, bool immediate)
685{
686 struct amdgpu_vm_update_params params;
687 struct amdgpu_vm_bo_base *entry;
688 bool flush_tlb_needed = false;
689 LIST_HEAD(relocated);
690 int r, idx;
691
692 spin_lock(&vm->status_lock);
693 list_splice_init(&vm->relocated, &relocated);
694 spin_unlock(&vm->status_lock);
695
696 if (list_empty(&relocated))
697 return 0;
698
699 if (!drm_dev_enter(adev_to_drm(adev), &idx))
700 return -ENODEV;
701
702 memset(¶ms, 0, sizeof(params));
703 params.adev = adev;
704 params.vm = vm;
705 params.immediate = immediate;
706
707 r = vm->update_funcs->prepare(¶ms, NULL, AMDGPU_SYNC_EXPLICIT);
708 if (r)
709 goto error;
710
711 list_for_each_entry(entry, &relocated, vm_status) {
712 /* vm_flush_needed after updating moved PDEs */
713 flush_tlb_needed |= entry->moved;
714
715 r = amdgpu_vm_pde_update(¶ms, entry);
716 if (r)
717 goto error;
718 }
719
720 r = vm->update_funcs->commit(¶ms, &vm->last_update);
721 if (r)
722 goto error;
723
724 if (flush_tlb_needed)
725 atomic64_inc(&vm->tlb_seq);
726
727 while (!list_empty(&relocated)) {
728 entry = list_first_entry(&relocated, struct amdgpu_vm_bo_base,
729 vm_status);
730 amdgpu_vm_bo_idle(entry);
731 }
732
733error:
734 drm_dev_exit(idx);
735 return r;
736}
737
738/**
739 * amdgpu_vm_tlb_seq_cb - make sure to increment tlb sequence
740 * @fence: unused
741 * @cb: the callback structure
742 *
743 * Increments the tlb sequence to make sure that future CS execute a VM flush.
744 */
745static void amdgpu_vm_tlb_seq_cb(struct dma_fence *fence,
746 struct dma_fence_cb *cb)
747{
748 struct amdgpu_vm_tlb_seq_cb *tlb_cb;
749
750 tlb_cb = container_of(cb, typeof(*tlb_cb), cb);
751 atomic64_inc(&tlb_cb->vm->tlb_seq);
752 kfree(tlb_cb);
753}
754
755/**
756 * amdgpu_vm_update_range - update a range in the vm page table
757 *
758 * @adev: amdgpu_device pointer to use for commands
759 * @vm: the VM to update the range
760 * @immediate: immediate submission in a page fault
761 * @unlocked: unlocked invalidation during MM callback
762 * @flush_tlb: trigger tlb invalidation after update completed
763 * @resv: fences we need to sync to
764 * @start: start of mapped range
765 * @last: last mapped entry
766 * @flags: flags for the entries
767 * @offset: offset into nodes and pages_addr
768 * @vram_base: base for vram mappings
769 * @res: ttm_resource to map
770 * @pages_addr: DMA addresses to use for mapping
771 * @fence: optional resulting fence
772 *
773 * Fill in the page table entries between @start and @last.
774 *
775 * Returns:
776 * 0 for success, negative erro code for failure.
777 */
778int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
779 bool immediate, bool unlocked, bool flush_tlb,
780 struct dma_resv *resv, uint64_t start, uint64_t last,
781 uint64_t flags, uint64_t offset, uint64_t vram_base,
782 struct ttm_resource *res, dma_addr_t *pages_addr,
783 struct dma_fence **fence)
784{
785 struct amdgpu_vm_update_params params;
786 struct amdgpu_vm_tlb_seq_cb *tlb_cb;
787 struct amdgpu_res_cursor cursor;
788 enum amdgpu_sync_mode sync_mode;
789 int r, idx;
790
791 if (!drm_dev_enter(adev_to_drm(adev), &idx))
792 return -ENODEV;
793
794 tlb_cb = kmalloc(sizeof(*tlb_cb), GFP_KERNEL);
795 if (!tlb_cb) {
796 r = -ENOMEM;
797 goto error_unlock;
798 }
799
800 /* Vega20+XGMI where PTEs get inadvertently cached in L2 texture cache,
801 * heavy-weight flush TLB unconditionally.
802 */
803 flush_tlb |= adev->gmc.xgmi.num_physical_nodes &&
804 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0);
805
806 /*
807 * On GFX8 and older any 8 PTE block with a valid bit set enters the TLB
808 */
809 flush_tlb |= adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 0, 0);
810
811 memset(¶ms, 0, sizeof(params));
812 params.adev = adev;
813 params.vm = vm;
814 params.immediate = immediate;
815 params.pages_addr = pages_addr;
816 params.unlocked = unlocked;
817
818 /* Implicitly sync to command submissions in the same VM before
819 * unmapping. Sync to moving fences before mapping.
820 */
821 if (!(flags & AMDGPU_PTE_VALID))
822 sync_mode = AMDGPU_SYNC_EQ_OWNER;
823 else
824 sync_mode = AMDGPU_SYNC_EXPLICIT;
825
826 amdgpu_vm_eviction_lock(vm);
827 if (vm->evicting) {
828 r = -EBUSY;
829 goto error_free;
830 }
831
832 if (!unlocked && !dma_fence_is_signaled(vm->last_unlocked)) {
833 struct dma_fence *tmp = dma_fence_get_stub();
834
835 amdgpu_bo_fence(vm->root.bo, vm->last_unlocked, true);
836 swap(vm->last_unlocked, tmp);
837 dma_fence_put(tmp);
838 }
839
840 r = vm->update_funcs->prepare(¶ms, resv, sync_mode);
841 if (r)
842 goto error_free;
843
844 amdgpu_res_first(pages_addr ? NULL : res, offset,
845 (last - start + 1) * AMDGPU_GPU_PAGE_SIZE, &cursor);
846 while (cursor.remaining) {
847 uint64_t tmp, num_entries, addr;
848
849 num_entries = cursor.size >> AMDGPU_GPU_PAGE_SHIFT;
850 if (pages_addr) {
851 bool contiguous = true;
852
853 if (num_entries > AMDGPU_GPU_PAGES_IN_CPU_PAGE) {
854 uint64_t pfn = cursor.start >> PAGE_SHIFT;
855 uint64_t count;
856
857 contiguous = pages_addr[pfn + 1] ==
858 pages_addr[pfn] + PAGE_SIZE;
859
860 tmp = num_entries /
861 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
862 for (count = 2; count < tmp; ++count) {
863 uint64_t idx = pfn + count;
864
865 if (contiguous != (pages_addr[idx] ==
866 pages_addr[idx - 1] + PAGE_SIZE))
867 break;
868 }
869 num_entries = count *
870 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
871 }
872
873 if (!contiguous) {
874 addr = cursor.start;
875 params.pages_addr = pages_addr;
876 } else {
877 addr = pages_addr[cursor.start >> PAGE_SHIFT];
878 params.pages_addr = NULL;
879 }
880
881 } else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT)) {
882 addr = vram_base + cursor.start;
883 } else {
884 addr = 0;
885 }
886
887 tmp = start + num_entries;
888 r = amdgpu_vm_ptes_update(¶ms, start, tmp, addr, flags);
889 if (r)
890 goto error_free;
891
892 amdgpu_res_next(&cursor, num_entries * AMDGPU_GPU_PAGE_SIZE);
893 start = tmp;
894 }
895
896 r = vm->update_funcs->commit(¶ms, fence);
897
898 if (flush_tlb || params.table_freed) {
899 tlb_cb->vm = vm;
900 if (fence && *fence &&
901 !dma_fence_add_callback(*fence, &tlb_cb->cb,
902 amdgpu_vm_tlb_seq_cb)) {
903 dma_fence_put(vm->last_tlb_flush);
904 vm->last_tlb_flush = dma_fence_get(*fence);
905 } else {
906 amdgpu_vm_tlb_seq_cb(NULL, &tlb_cb->cb);
907 }
908 tlb_cb = NULL;
909 }
910
911error_free:
912 kfree(tlb_cb);
913
914error_unlock:
915 amdgpu_vm_eviction_unlock(vm);
916 drm_dev_exit(idx);
917 return r;
918}
919
920void amdgpu_vm_get_memory(struct amdgpu_vm *vm, uint64_t *vram_mem,
921 uint64_t *gtt_mem, uint64_t *cpu_mem)
922{
923 struct amdgpu_bo_va *bo_va, *tmp;
924
925 spin_lock(&vm->status_lock);
926 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
927 if (!bo_va->base.bo)
928 continue;
929 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
930 gtt_mem, cpu_mem);
931 }
932 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
933 if (!bo_va->base.bo)
934 continue;
935 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
936 gtt_mem, cpu_mem);
937 }
938 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
939 if (!bo_va->base.bo)
940 continue;
941 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
942 gtt_mem, cpu_mem);
943 }
944 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
945 if (!bo_va->base.bo)
946 continue;
947 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
948 gtt_mem, cpu_mem);
949 }
950 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
951 if (!bo_va->base.bo)
952 continue;
953 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
954 gtt_mem, cpu_mem);
955 }
956 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
957 if (!bo_va->base.bo)
958 continue;
959 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
960 gtt_mem, cpu_mem);
961 }
962 spin_unlock(&vm->status_lock);
963}
964/**
965 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
966 *
967 * @adev: amdgpu_device pointer
968 * @bo_va: requested BO and VM object
969 * @clear: if true clear the entries
970 *
971 * Fill in the page table entries for @bo_va.
972 *
973 * Returns:
974 * 0 for success, -EINVAL for failure.
975 */
976int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
977 bool clear)
978{
979 struct amdgpu_bo *bo = bo_va->base.bo;
980 struct amdgpu_vm *vm = bo_va->base.vm;
981 struct amdgpu_bo_va_mapping *mapping;
982 dma_addr_t *pages_addr = NULL;
983 struct ttm_resource *mem;
984 struct dma_fence **last_update;
985 bool flush_tlb = clear;
986 struct dma_resv *resv;
987 uint64_t vram_base;
988 uint64_t flags;
989 int r;
990
991 if (clear || !bo) {
992 mem = NULL;
993 resv = vm->root.bo->tbo.base.resv;
994 } else {
995 struct drm_gem_object *obj = &bo->tbo.base;
996
997 resv = bo->tbo.base.resv;
998 if (obj->import_attach && bo_va->is_xgmi) {
999 struct dma_buf *dma_buf = obj->import_attach->dmabuf;
1000 struct drm_gem_object *gobj = dma_buf->priv;
1001 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
1002
1003 if (abo->tbo.resource->mem_type == TTM_PL_VRAM)
1004 bo = gem_to_amdgpu_bo(gobj);
1005 }
1006 mem = bo->tbo.resource;
1007 if (mem->mem_type == TTM_PL_TT ||
1008 mem->mem_type == AMDGPU_PL_PREEMPT)
1009 pages_addr = bo->tbo.ttm->dma_address;
1010 }
1011
1012 if (bo) {
1013 struct amdgpu_device *bo_adev;
1014
1015 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
1016
1017 if (amdgpu_bo_encrypted(bo))
1018 flags |= AMDGPU_PTE_TMZ;
1019
1020 bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
1021 vram_base = bo_adev->vm_manager.vram_base_offset;
1022 } else {
1023 flags = 0x0;
1024 vram_base = 0;
1025 }
1026
1027 if (clear || (bo && bo->tbo.base.resv ==
1028 vm->root.bo->tbo.base.resv))
1029 last_update = &vm->last_update;
1030 else
1031 last_update = &bo_va->last_pt_update;
1032
1033 if (!clear && bo_va->base.moved) {
1034 flush_tlb = true;
1035 list_splice_init(&bo_va->valids, &bo_va->invalids);
1036
1037 } else if (bo_va->cleared != clear) {
1038 list_splice_init(&bo_va->valids, &bo_va->invalids);
1039 }
1040
1041 list_for_each_entry(mapping, &bo_va->invalids, list) {
1042 uint64_t update_flags = flags;
1043
1044 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1045 * but in case of something, we filter the flags in first place
1046 */
1047 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1048 update_flags &= ~AMDGPU_PTE_READABLE;
1049 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1050 update_flags &= ~AMDGPU_PTE_WRITEABLE;
1051
1052 /* Apply ASIC specific mapping flags */
1053 amdgpu_gmc_get_vm_pte(adev, mapping, &update_flags);
1054
1055 trace_amdgpu_vm_bo_update(mapping);
1056
1057 r = amdgpu_vm_update_range(adev, vm, false, false, flush_tlb,
1058 resv, mapping->start, mapping->last,
1059 update_flags, mapping->offset,
1060 vram_base, mem, pages_addr,
1061 last_update);
1062 if (r)
1063 return r;
1064 }
1065
1066 /* If the BO is not in its preferred location add it back to
1067 * the evicted list so that it gets validated again on the
1068 * next command submission.
1069 */
1070 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
1071 uint32_t mem_type = bo->tbo.resource->mem_type;
1072
1073 if (!(bo->preferred_domains &
1074 amdgpu_mem_type_to_domain(mem_type)))
1075 amdgpu_vm_bo_evicted(&bo_va->base);
1076 else
1077 amdgpu_vm_bo_idle(&bo_va->base);
1078 } else {
1079 amdgpu_vm_bo_done(&bo_va->base);
1080 }
1081
1082 list_splice_init(&bo_va->invalids, &bo_va->valids);
1083 bo_va->cleared = clear;
1084 bo_va->base.moved = false;
1085
1086 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1087 list_for_each_entry(mapping, &bo_va->valids, list)
1088 trace_amdgpu_vm_bo_mapping(mapping);
1089 }
1090
1091 return 0;
1092}
1093
1094/**
1095 * amdgpu_vm_update_prt_state - update the global PRT state
1096 *
1097 * @adev: amdgpu_device pointer
1098 */
1099static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
1100{
1101 unsigned long flags;
1102 bool enable;
1103
1104 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
1105 enable = !!atomic_read(&adev->vm_manager.num_prt_users);
1106 adev->gmc.gmc_funcs->set_prt(adev, enable);
1107 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
1108}
1109
1110/**
1111 * amdgpu_vm_prt_get - add a PRT user
1112 *
1113 * @adev: amdgpu_device pointer
1114 */
1115static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
1116{
1117 if (!adev->gmc.gmc_funcs->set_prt)
1118 return;
1119
1120 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
1121 amdgpu_vm_update_prt_state(adev);
1122}
1123
1124/**
1125 * amdgpu_vm_prt_put - drop a PRT user
1126 *
1127 * @adev: amdgpu_device pointer
1128 */
1129static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
1130{
1131 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
1132 amdgpu_vm_update_prt_state(adev);
1133}
1134
1135/**
1136 * amdgpu_vm_prt_cb - callback for updating the PRT status
1137 *
1138 * @fence: fence for the callback
1139 * @_cb: the callback function
1140 */
1141static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
1142{
1143 struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
1144
1145 amdgpu_vm_prt_put(cb->adev);
1146 kfree(cb);
1147}
1148
1149/**
1150 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1151 *
1152 * @adev: amdgpu_device pointer
1153 * @fence: fence for the callback
1154 */
1155static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
1156 struct dma_fence *fence)
1157{
1158 struct amdgpu_prt_cb *cb;
1159
1160 if (!adev->gmc.gmc_funcs->set_prt)
1161 return;
1162
1163 cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
1164 if (!cb) {
1165 /* Last resort when we are OOM */
1166 if (fence)
1167 dma_fence_wait(fence, false);
1168
1169 amdgpu_vm_prt_put(adev);
1170 } else {
1171 cb->adev = adev;
1172 if (!fence || dma_fence_add_callback(fence, &cb->cb,
1173 amdgpu_vm_prt_cb))
1174 amdgpu_vm_prt_cb(fence, &cb->cb);
1175 }
1176}
1177
1178/**
1179 * amdgpu_vm_free_mapping - free a mapping
1180 *
1181 * @adev: amdgpu_device pointer
1182 * @vm: requested vm
1183 * @mapping: mapping to be freed
1184 * @fence: fence of the unmap operation
1185 *
1186 * Free a mapping and make sure we decrease the PRT usage count if applicable.
1187 */
1188static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
1189 struct amdgpu_vm *vm,
1190 struct amdgpu_bo_va_mapping *mapping,
1191 struct dma_fence *fence)
1192{
1193 if (mapping->flags & AMDGPU_PTE_PRT)
1194 amdgpu_vm_add_prt_cb(adev, fence);
1195 kfree(mapping);
1196}
1197
1198/**
1199 * amdgpu_vm_prt_fini - finish all prt mappings
1200 *
1201 * @adev: amdgpu_device pointer
1202 * @vm: requested vm
1203 *
1204 * Register a cleanup callback to disable PRT support after VM dies.
1205 */
1206static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1207{
1208 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
1209 struct dma_resv_iter cursor;
1210 struct dma_fence *fence;
1211
1212 dma_resv_for_each_fence(&cursor, resv, DMA_RESV_USAGE_BOOKKEEP, fence) {
1213 /* Add a callback for each fence in the reservation object */
1214 amdgpu_vm_prt_get(adev);
1215 amdgpu_vm_add_prt_cb(adev, fence);
1216 }
1217}
1218
1219/**
1220 * amdgpu_vm_clear_freed - clear freed BOs in the PT
1221 *
1222 * @adev: amdgpu_device pointer
1223 * @vm: requested vm
1224 * @fence: optional resulting fence (unchanged if no work needed to be done
1225 * or if an error occurred)
1226 *
1227 * Make sure all freed BOs are cleared in the PT.
1228 * PTs have to be reserved and mutex must be locked!
1229 *
1230 * Returns:
1231 * 0 for success.
1232 *
1233 */
1234int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
1235 struct amdgpu_vm *vm,
1236 struct dma_fence **fence)
1237{
1238 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
1239 struct amdgpu_bo_va_mapping *mapping;
1240 uint64_t init_pte_value = 0;
1241 struct dma_fence *f = NULL;
1242 int r;
1243
1244 while (!list_empty(&vm->freed)) {
1245 mapping = list_first_entry(&vm->freed,
1246 struct amdgpu_bo_va_mapping, list);
1247 list_del(&mapping->list);
1248
1249 if (vm->pte_support_ats &&
1250 mapping->start < AMDGPU_GMC_HOLE_START)
1251 init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
1252
1253 r = amdgpu_vm_update_range(adev, vm, false, false, true, resv,
1254 mapping->start, mapping->last,
1255 init_pte_value, 0, 0, NULL, NULL,
1256 &f);
1257 amdgpu_vm_free_mapping(adev, vm, mapping, f);
1258 if (r) {
1259 dma_fence_put(f);
1260 return r;
1261 }
1262 }
1263
1264 if (fence && f) {
1265 dma_fence_put(*fence);
1266 *fence = f;
1267 } else {
1268 dma_fence_put(f);
1269 }
1270
1271 return 0;
1272
1273}
1274
1275/**
1276 * amdgpu_vm_handle_moved - handle moved BOs in the PT
1277 *
1278 * @adev: amdgpu_device pointer
1279 * @vm: requested vm
1280 *
1281 * Make sure all BOs which are moved are updated in the PTs.
1282 *
1283 * Returns:
1284 * 0 for success.
1285 *
1286 * PTs have to be reserved!
1287 */
1288int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
1289 struct amdgpu_vm *vm)
1290{
1291 struct amdgpu_bo_va *bo_va;
1292 struct dma_resv *resv;
1293 bool clear;
1294 int r;
1295
1296 spin_lock(&vm->status_lock);
1297 while (!list_empty(&vm->moved)) {
1298 bo_va = list_first_entry(&vm->moved, struct amdgpu_bo_va,
1299 base.vm_status);
1300 spin_unlock(&vm->status_lock);
1301
1302 /* Per VM BOs never need to bo cleared in the page tables */
1303 r = amdgpu_vm_bo_update(adev, bo_va, false);
1304 if (r)
1305 return r;
1306 spin_lock(&vm->status_lock);
1307 }
1308
1309 while (!list_empty(&vm->invalidated)) {
1310 bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va,
1311 base.vm_status);
1312 resv = bo_va->base.bo->tbo.base.resv;
1313 spin_unlock(&vm->status_lock);
1314
1315 /* Try to reserve the BO to avoid clearing its ptes */
1316 if (!amdgpu_vm_debug && dma_resv_trylock(resv))
1317 clear = false;
1318 /* Somebody else is using the BO right now */
1319 else
1320 clear = true;
1321
1322 r = amdgpu_vm_bo_update(adev, bo_va, clear);
1323 if (r)
1324 return r;
1325
1326 if (!clear)
1327 dma_resv_unlock(resv);
1328 spin_lock(&vm->status_lock);
1329 }
1330 spin_unlock(&vm->status_lock);
1331
1332 return 0;
1333}
1334
1335/**
1336 * amdgpu_vm_bo_add - add a bo to a specific vm
1337 *
1338 * @adev: amdgpu_device pointer
1339 * @vm: requested vm
1340 * @bo: amdgpu buffer object
1341 *
1342 * Add @bo into the requested vm.
1343 * Add @bo to the list of bos associated with the vm
1344 *
1345 * Returns:
1346 * Newly added bo_va or NULL for failure
1347 *
1348 * Object has to be reserved!
1349 */
1350struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
1351 struct amdgpu_vm *vm,
1352 struct amdgpu_bo *bo)
1353{
1354 struct amdgpu_bo_va *bo_va;
1355
1356 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
1357 if (bo_va == NULL) {
1358 return NULL;
1359 }
1360 amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
1361
1362 bo_va->ref_count = 1;
1363 INIT_LIST_HEAD(&bo_va->valids);
1364 INIT_LIST_HEAD(&bo_va->invalids);
1365
1366 if (!bo)
1367 return bo_va;
1368
1369 dma_resv_assert_held(bo->tbo.base.resv);
1370 if (amdgpu_dmabuf_is_xgmi_accessible(adev, bo)) {
1371 bo_va->is_xgmi = true;
1372 /* Power up XGMI if it can be potentially used */
1373 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MAX_VEGA20);
1374 }
1375
1376 return bo_va;
1377}
1378
1379
1380/**
1381 * amdgpu_vm_bo_insert_map - insert a new mapping
1382 *
1383 * @adev: amdgpu_device pointer
1384 * @bo_va: bo_va to store the address
1385 * @mapping: the mapping to insert
1386 *
1387 * Insert a new mapping into all structures.
1388 */
1389static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
1390 struct amdgpu_bo_va *bo_va,
1391 struct amdgpu_bo_va_mapping *mapping)
1392{
1393 struct amdgpu_vm *vm = bo_va->base.vm;
1394 struct amdgpu_bo *bo = bo_va->base.bo;
1395
1396 mapping->bo_va = bo_va;
1397 list_add(&mapping->list, &bo_va->invalids);
1398 amdgpu_vm_it_insert(mapping, &vm->va);
1399
1400 if (mapping->flags & AMDGPU_PTE_PRT)
1401 amdgpu_vm_prt_get(adev);
1402
1403 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
1404 !bo_va->base.moved) {
1405 amdgpu_vm_bo_moved(&bo_va->base);
1406 }
1407 trace_amdgpu_vm_bo_map(bo_va, mapping);
1408}
1409
1410/**
1411 * amdgpu_vm_bo_map - map bo inside a vm
1412 *
1413 * @adev: amdgpu_device pointer
1414 * @bo_va: bo_va to store the address
1415 * @saddr: where to map the BO
1416 * @offset: requested offset in the BO
1417 * @size: BO size in bytes
1418 * @flags: attributes of pages (read/write/valid/etc.)
1419 *
1420 * Add a mapping of the BO at the specefied addr into the VM.
1421 *
1422 * Returns:
1423 * 0 for success, error for failure.
1424 *
1425 * Object has to be reserved and unreserved outside!
1426 */
1427int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1428 struct amdgpu_bo_va *bo_va,
1429 uint64_t saddr, uint64_t offset,
1430 uint64_t size, uint64_t flags)
1431{
1432 struct amdgpu_bo_va_mapping *mapping, *tmp;
1433 struct amdgpu_bo *bo = bo_va->base.bo;
1434 struct amdgpu_vm *vm = bo_va->base.vm;
1435 uint64_t eaddr;
1436
1437 /* validate the parameters */
1438 if (saddr & ~PAGE_MASK || offset & ~PAGE_MASK ||
1439 size == 0 || size & ~PAGE_MASK)
1440 return -EINVAL;
1441
1442 /* make sure object fit at this offset */
1443 eaddr = saddr + size - 1;
1444 if (saddr >= eaddr ||
1445 (bo && offset + size > amdgpu_bo_size(bo)) ||
1446 (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
1447 return -EINVAL;
1448
1449 saddr /= AMDGPU_GPU_PAGE_SIZE;
1450 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1451
1452 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
1453 if (tmp) {
1454 /* bo and tmp overlap, invalid addr */
1455 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
1456 "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr,
1457 tmp->start, tmp->last + 1);
1458 return -EINVAL;
1459 }
1460
1461 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1462 if (!mapping)
1463 return -ENOMEM;
1464
1465 mapping->start = saddr;
1466 mapping->last = eaddr;
1467 mapping->offset = offset;
1468 mapping->flags = flags;
1469
1470 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
1471
1472 return 0;
1473}
1474
1475/**
1476 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
1477 *
1478 * @adev: amdgpu_device pointer
1479 * @bo_va: bo_va to store the address
1480 * @saddr: where to map the BO
1481 * @offset: requested offset in the BO
1482 * @size: BO size in bytes
1483 * @flags: attributes of pages (read/write/valid/etc.)
1484 *
1485 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
1486 * mappings as we do so.
1487 *
1488 * Returns:
1489 * 0 for success, error for failure.
1490 *
1491 * Object has to be reserved and unreserved outside!
1492 */
1493int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
1494 struct amdgpu_bo_va *bo_va,
1495 uint64_t saddr, uint64_t offset,
1496 uint64_t size, uint64_t flags)
1497{
1498 struct amdgpu_bo_va_mapping *mapping;
1499 struct amdgpu_bo *bo = bo_va->base.bo;
1500 uint64_t eaddr;
1501 int r;
1502
1503 /* validate the parameters */
1504 if (saddr & ~PAGE_MASK || offset & ~PAGE_MASK ||
1505 size == 0 || size & ~PAGE_MASK)
1506 return -EINVAL;
1507
1508 /* make sure object fit at this offset */
1509 eaddr = saddr + size - 1;
1510 if (saddr >= eaddr ||
1511 (bo && offset + size > amdgpu_bo_size(bo)) ||
1512 (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
1513 return -EINVAL;
1514
1515 /* Allocate all the needed memory */
1516 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1517 if (!mapping)
1518 return -ENOMEM;
1519
1520 r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size);
1521 if (r) {
1522 kfree(mapping);
1523 return r;
1524 }
1525
1526 saddr /= AMDGPU_GPU_PAGE_SIZE;
1527 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1528
1529 mapping->start = saddr;
1530 mapping->last = eaddr;
1531 mapping->offset = offset;
1532 mapping->flags = flags;
1533
1534 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
1535
1536 return 0;
1537}
1538
1539/**
1540 * amdgpu_vm_bo_unmap - remove bo mapping from vm
1541 *
1542 * @adev: amdgpu_device pointer
1543 * @bo_va: bo_va to remove the address from
1544 * @saddr: where to the BO is mapped
1545 *
1546 * Remove a mapping of the BO at the specefied addr from the VM.
1547 *
1548 * Returns:
1549 * 0 for success, error for failure.
1550 *
1551 * Object has to be reserved and unreserved outside!
1552 */
1553int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
1554 struct amdgpu_bo_va *bo_va,
1555 uint64_t saddr)
1556{
1557 struct amdgpu_bo_va_mapping *mapping;
1558 struct amdgpu_vm *vm = bo_va->base.vm;
1559 bool valid = true;
1560
1561 saddr /= AMDGPU_GPU_PAGE_SIZE;
1562
1563 list_for_each_entry(mapping, &bo_va->valids, list) {
1564 if (mapping->start == saddr)
1565 break;
1566 }
1567
1568 if (&mapping->list == &bo_va->valids) {
1569 valid = false;
1570
1571 list_for_each_entry(mapping, &bo_va->invalids, list) {
1572 if (mapping->start == saddr)
1573 break;
1574 }
1575
1576 if (&mapping->list == &bo_va->invalids)
1577 return -ENOENT;
1578 }
1579
1580 list_del(&mapping->list);
1581 amdgpu_vm_it_remove(mapping, &vm->va);
1582 mapping->bo_va = NULL;
1583 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1584
1585 if (valid)
1586 list_add(&mapping->list, &vm->freed);
1587 else
1588 amdgpu_vm_free_mapping(adev, vm, mapping,
1589 bo_va->last_pt_update);
1590
1591 return 0;
1592}
1593
1594/**
1595 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
1596 *
1597 * @adev: amdgpu_device pointer
1598 * @vm: VM structure to use
1599 * @saddr: start of the range
1600 * @size: size of the range
1601 *
1602 * Remove all mappings in a range, split them as appropriate.
1603 *
1604 * Returns:
1605 * 0 for success, error for failure.
1606 */
1607int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
1608 struct amdgpu_vm *vm,
1609 uint64_t saddr, uint64_t size)
1610{
1611 struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
1612 LIST_HEAD(removed);
1613 uint64_t eaddr;
1614
1615 eaddr = saddr + size - 1;
1616 saddr /= AMDGPU_GPU_PAGE_SIZE;
1617 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1618
1619 /* Allocate all the needed memory */
1620 before = kzalloc(sizeof(*before), GFP_KERNEL);
1621 if (!before)
1622 return -ENOMEM;
1623 INIT_LIST_HEAD(&before->list);
1624
1625 after = kzalloc(sizeof(*after), GFP_KERNEL);
1626 if (!after) {
1627 kfree(before);
1628 return -ENOMEM;
1629 }
1630 INIT_LIST_HEAD(&after->list);
1631
1632 /* Now gather all removed mappings */
1633 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
1634 while (tmp) {
1635 /* Remember mapping split at the start */
1636 if (tmp->start < saddr) {
1637 before->start = tmp->start;
1638 before->last = saddr - 1;
1639 before->offset = tmp->offset;
1640 before->flags = tmp->flags;
1641 before->bo_va = tmp->bo_va;
1642 list_add(&before->list, &tmp->bo_va->invalids);
1643 }
1644
1645 /* Remember mapping split at the end */
1646 if (tmp->last > eaddr) {
1647 after->start = eaddr + 1;
1648 after->last = tmp->last;
1649 after->offset = tmp->offset;
1650 after->offset += (after->start - tmp->start) << PAGE_SHIFT;
1651 after->flags = tmp->flags;
1652 after->bo_va = tmp->bo_va;
1653 list_add(&after->list, &tmp->bo_va->invalids);
1654 }
1655
1656 list_del(&tmp->list);
1657 list_add(&tmp->list, &removed);
1658
1659 tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
1660 }
1661
1662 /* And free them up */
1663 list_for_each_entry_safe(tmp, next, &removed, list) {
1664 amdgpu_vm_it_remove(tmp, &vm->va);
1665 list_del(&tmp->list);
1666
1667 if (tmp->start < saddr)
1668 tmp->start = saddr;
1669 if (tmp->last > eaddr)
1670 tmp->last = eaddr;
1671
1672 tmp->bo_va = NULL;
1673 list_add(&tmp->list, &vm->freed);
1674 trace_amdgpu_vm_bo_unmap(NULL, tmp);
1675 }
1676
1677 /* Insert partial mapping before the range */
1678 if (!list_empty(&before->list)) {
1679 amdgpu_vm_it_insert(before, &vm->va);
1680 if (before->flags & AMDGPU_PTE_PRT)
1681 amdgpu_vm_prt_get(adev);
1682 } else {
1683 kfree(before);
1684 }
1685
1686 /* Insert partial mapping after the range */
1687 if (!list_empty(&after->list)) {
1688 amdgpu_vm_it_insert(after, &vm->va);
1689 if (after->flags & AMDGPU_PTE_PRT)
1690 amdgpu_vm_prt_get(adev);
1691 } else {
1692 kfree(after);
1693 }
1694
1695 return 0;
1696}
1697
1698/**
1699 * amdgpu_vm_bo_lookup_mapping - find mapping by address
1700 *
1701 * @vm: the requested VM
1702 * @addr: the address
1703 *
1704 * Find a mapping by it's address.
1705 *
1706 * Returns:
1707 * The amdgpu_bo_va_mapping matching for addr or NULL
1708 *
1709 */
1710struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
1711 uint64_t addr)
1712{
1713 return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
1714}
1715
1716/**
1717 * amdgpu_vm_bo_trace_cs - trace all reserved mappings
1718 *
1719 * @vm: the requested vm
1720 * @ticket: CS ticket
1721 *
1722 * Trace all mappings of BOs reserved during a command submission.
1723 */
1724void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket)
1725{
1726 struct amdgpu_bo_va_mapping *mapping;
1727
1728 if (!trace_amdgpu_vm_bo_cs_enabled())
1729 return;
1730
1731 for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping;
1732 mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) {
1733 if (mapping->bo_va && mapping->bo_va->base.bo) {
1734 struct amdgpu_bo *bo;
1735
1736 bo = mapping->bo_va->base.bo;
1737 if (dma_resv_locking_ctx(bo->tbo.base.resv) !=
1738 ticket)
1739 continue;
1740 }
1741
1742 trace_amdgpu_vm_bo_cs(mapping);
1743 }
1744}
1745
1746/**
1747 * amdgpu_vm_bo_del - remove a bo from a specific vm
1748 *
1749 * @adev: amdgpu_device pointer
1750 * @bo_va: requested bo_va
1751 *
1752 * Remove @bo_va->bo from the requested vm.
1753 *
1754 * Object have to be reserved!
1755 */
1756void amdgpu_vm_bo_del(struct amdgpu_device *adev,
1757 struct amdgpu_bo_va *bo_va)
1758{
1759 struct amdgpu_bo_va_mapping *mapping, *next;
1760 struct amdgpu_bo *bo = bo_va->base.bo;
1761 struct amdgpu_vm *vm = bo_va->base.vm;
1762 struct amdgpu_vm_bo_base **base;
1763
1764 dma_resv_assert_held(vm->root.bo->tbo.base.resv);
1765
1766 if (bo) {
1767 dma_resv_assert_held(bo->tbo.base.resv);
1768 if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
1769 ttm_bo_set_bulk_move(&bo->tbo, NULL);
1770
1771 for (base = &bo_va->base.bo->vm_bo; *base;
1772 base = &(*base)->next) {
1773 if (*base != &bo_va->base)
1774 continue;
1775
1776 *base = bo_va->base.next;
1777 break;
1778 }
1779 }
1780
1781 spin_lock(&vm->status_lock);
1782 list_del(&bo_va->base.vm_status);
1783 spin_unlock(&vm->status_lock);
1784
1785 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
1786 list_del(&mapping->list);
1787 amdgpu_vm_it_remove(mapping, &vm->va);
1788 mapping->bo_va = NULL;
1789 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1790 list_add(&mapping->list, &vm->freed);
1791 }
1792 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
1793 list_del(&mapping->list);
1794 amdgpu_vm_it_remove(mapping, &vm->va);
1795 amdgpu_vm_free_mapping(adev, vm, mapping,
1796 bo_va->last_pt_update);
1797 }
1798
1799 dma_fence_put(bo_va->last_pt_update);
1800
1801 if (bo && bo_va->is_xgmi)
1802 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MIN);
1803
1804 kfree(bo_va);
1805}
1806
1807/**
1808 * amdgpu_vm_evictable - check if we can evict a VM
1809 *
1810 * @bo: A page table of the VM.
1811 *
1812 * Check if it is possible to evict a VM.
1813 */
1814bool amdgpu_vm_evictable(struct amdgpu_bo *bo)
1815{
1816 struct amdgpu_vm_bo_base *bo_base = bo->vm_bo;
1817
1818 /* Page tables of a destroyed VM can go away immediately */
1819 if (!bo_base || !bo_base->vm)
1820 return true;
1821
1822 /* Don't evict VM page tables while they are busy */
1823 if (!dma_resv_test_signaled(bo->tbo.base.resv, DMA_RESV_USAGE_BOOKKEEP))
1824 return false;
1825
1826 /* Try to block ongoing updates */
1827 if (!amdgpu_vm_eviction_trylock(bo_base->vm))
1828 return false;
1829
1830 /* Don't evict VM page tables while they are updated */
1831 if (!dma_fence_is_signaled(bo_base->vm->last_unlocked)) {
1832 amdgpu_vm_eviction_unlock(bo_base->vm);
1833 return false;
1834 }
1835
1836 bo_base->vm->evicting = true;
1837 amdgpu_vm_eviction_unlock(bo_base->vm);
1838 return true;
1839}
1840
1841/**
1842 * amdgpu_vm_bo_invalidate - mark the bo as invalid
1843 *
1844 * @adev: amdgpu_device pointer
1845 * @bo: amdgpu buffer object
1846 * @evicted: is the BO evicted
1847 *
1848 * Mark @bo as invalid.
1849 */
1850void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
1851 struct amdgpu_bo *bo, bool evicted)
1852{
1853 struct amdgpu_vm_bo_base *bo_base;
1854
1855 /* shadow bo doesn't have bo base, its validation needs its parent */
1856 if (bo->parent && (amdgpu_bo_shadowed(bo->parent) == bo))
1857 bo = bo->parent;
1858
1859 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
1860 struct amdgpu_vm *vm = bo_base->vm;
1861
1862 if (evicted && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
1863 amdgpu_vm_bo_evicted(bo_base);
1864 continue;
1865 }
1866
1867 if (bo_base->moved)
1868 continue;
1869 bo_base->moved = true;
1870
1871 if (bo->tbo.type == ttm_bo_type_kernel)
1872 amdgpu_vm_bo_relocated(bo_base);
1873 else if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
1874 amdgpu_vm_bo_moved(bo_base);
1875 else
1876 amdgpu_vm_bo_invalidated(bo_base);
1877 }
1878}
1879
1880/**
1881 * amdgpu_vm_get_block_size - calculate VM page table size as power of two
1882 *
1883 * @vm_size: VM size
1884 *
1885 * Returns:
1886 * VM page table as power of two
1887 */
1888static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
1889{
1890 /* Total bits covered by PD + PTs */
1891 unsigned bits = ilog2(vm_size) + 18;
1892
1893 /* Make sure the PD is 4K in size up to 8GB address space.
1894 Above that split equal between PD and PTs */
1895 if (vm_size <= 8)
1896 return (bits - 9);
1897 else
1898 return ((bits + 3) / 2);
1899}
1900
1901/**
1902 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
1903 *
1904 * @adev: amdgpu_device pointer
1905 * @min_vm_size: the minimum vm size in GB if it's set auto
1906 * @fragment_size_default: Default PTE fragment size
1907 * @max_level: max VMPT level
1908 * @max_bits: max address space size in bits
1909 *
1910 */
1911void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
1912 uint32_t fragment_size_default, unsigned max_level,
1913 unsigned max_bits)
1914{
1915 unsigned int max_size = 1 << (max_bits - 30);
1916 unsigned int vm_size;
1917 uint64_t tmp;
1918
1919 /* adjust vm size first */
1920 if (amdgpu_vm_size != -1) {
1921 vm_size = amdgpu_vm_size;
1922 if (vm_size > max_size) {
1923 dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
1924 amdgpu_vm_size, max_size);
1925 vm_size = max_size;
1926 }
1927 } else {
1928 struct sysinfo si;
1929 unsigned int phys_ram_gb;
1930
1931 /* Optimal VM size depends on the amount of physical
1932 * RAM available. Underlying requirements and
1933 * assumptions:
1934 *
1935 * - Need to map system memory and VRAM from all GPUs
1936 * - VRAM from other GPUs not known here
1937 * - Assume VRAM <= system memory
1938 * - On GFX8 and older, VM space can be segmented for
1939 * different MTYPEs
1940 * - Need to allow room for fragmentation, guard pages etc.
1941 *
1942 * This adds up to a rough guess of system memory x3.
1943 * Round up to power of two to maximize the available
1944 * VM size with the given page table size.
1945 */
1946 si_meminfo(&si);
1947 phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit +
1948 (1 << 30) - 1) >> 30;
1949 vm_size = roundup_pow_of_two(
1950 min(max(phys_ram_gb * 3, min_vm_size), max_size));
1951 }
1952
1953 adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
1954
1955 tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
1956 if (amdgpu_vm_block_size != -1)
1957 tmp >>= amdgpu_vm_block_size - 9;
1958 tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
1959 adev->vm_manager.num_level = min(max_level, (unsigned)tmp);
1960 switch (adev->vm_manager.num_level) {
1961 case 3:
1962 adev->vm_manager.root_level = AMDGPU_VM_PDB2;
1963 break;
1964 case 2:
1965 adev->vm_manager.root_level = AMDGPU_VM_PDB1;
1966 break;
1967 case 1:
1968 adev->vm_manager.root_level = AMDGPU_VM_PDB0;
1969 break;
1970 default:
1971 dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
1972 }
1973 /* block size depends on vm size and hw setup*/
1974 if (amdgpu_vm_block_size != -1)
1975 adev->vm_manager.block_size =
1976 min((unsigned)amdgpu_vm_block_size, max_bits
1977 - AMDGPU_GPU_PAGE_SHIFT
1978 - 9 * adev->vm_manager.num_level);
1979 else if (adev->vm_manager.num_level > 1)
1980 adev->vm_manager.block_size = 9;
1981 else
1982 adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
1983
1984 if (amdgpu_vm_fragment_size == -1)
1985 adev->vm_manager.fragment_size = fragment_size_default;
1986 else
1987 adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
1988
1989 DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
1990 vm_size, adev->vm_manager.num_level + 1,
1991 adev->vm_manager.block_size,
1992 adev->vm_manager.fragment_size);
1993}
1994
1995/**
1996 * amdgpu_vm_wait_idle - wait for the VM to become idle
1997 *
1998 * @vm: VM object to wait for
1999 * @timeout: timeout to wait for VM to become idle
2000 */
2001long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
2002{
2003 timeout = dma_resv_wait_timeout(vm->root.bo->tbo.base.resv,
2004 DMA_RESV_USAGE_BOOKKEEP,
2005 true, timeout);
2006 if (timeout <= 0)
2007 return timeout;
2008
2009 return dma_fence_wait_timeout(vm->last_unlocked, true, timeout);
2010}
2011
2012/**
2013 * amdgpu_vm_init - initialize a vm instance
2014 *
2015 * @adev: amdgpu_device pointer
2016 * @vm: requested vm
2017 *
2018 * Init @vm fields.
2019 *
2020 * Returns:
2021 * 0 for success, error for failure.
2022 */
2023int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2024{
2025 struct amdgpu_bo *root_bo;
2026 struct amdgpu_bo_vm *root;
2027 int r, i;
2028
2029 vm->va = RB_ROOT_CACHED;
2030 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2031 vm->reserved_vmid[i] = NULL;
2032 INIT_LIST_HEAD(&vm->evicted);
2033 INIT_LIST_HEAD(&vm->relocated);
2034 INIT_LIST_HEAD(&vm->moved);
2035 INIT_LIST_HEAD(&vm->idle);
2036 INIT_LIST_HEAD(&vm->invalidated);
2037 spin_lock_init(&vm->status_lock);
2038 INIT_LIST_HEAD(&vm->freed);
2039 INIT_LIST_HEAD(&vm->done);
2040 INIT_LIST_HEAD(&vm->pt_freed);
2041 INIT_WORK(&vm->pt_free_work, amdgpu_vm_pt_free_work);
2042
2043 /* create scheduler entities for page table updates */
2044 r = drm_sched_entity_init(&vm->immediate, DRM_SCHED_PRIORITY_NORMAL,
2045 adev->vm_manager.vm_pte_scheds,
2046 adev->vm_manager.vm_pte_num_scheds, NULL);
2047 if (r)
2048 return r;
2049
2050 r = drm_sched_entity_init(&vm->delayed, DRM_SCHED_PRIORITY_NORMAL,
2051 adev->vm_manager.vm_pte_scheds,
2052 adev->vm_manager.vm_pte_num_scheds, NULL);
2053 if (r)
2054 goto error_free_immediate;
2055
2056 vm->pte_support_ats = false;
2057 vm->is_compute_context = false;
2058
2059 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2060 AMDGPU_VM_USE_CPU_FOR_GFX);
2061
2062 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2063 vm->use_cpu_for_update ? "CPU" : "SDMA");
2064 WARN_ONCE((vm->use_cpu_for_update &&
2065 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2066 "CPU update of VM recommended only for large BAR system\n");
2067
2068 if (vm->use_cpu_for_update)
2069 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2070 else
2071 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2072 vm->last_update = NULL;
2073 vm->last_unlocked = dma_fence_get_stub();
2074 vm->last_tlb_flush = dma_fence_get_stub();
2075
2076 mutex_init(&vm->eviction_lock);
2077 vm->evicting = false;
2078
2079 r = amdgpu_vm_pt_create(adev, vm, adev->vm_manager.root_level,
2080 false, &root);
2081 if (r)
2082 goto error_free_delayed;
2083 root_bo = &root->bo;
2084 r = amdgpu_bo_reserve(root_bo, true);
2085 if (r)
2086 goto error_free_root;
2087
2088 r = dma_resv_reserve_fences(root_bo->tbo.base.resv, 1);
2089 if (r)
2090 goto error_unreserve;
2091
2092 amdgpu_vm_bo_base_init(&vm->root, vm, root_bo);
2093
2094 r = amdgpu_vm_pt_clear(adev, vm, root, false);
2095 if (r)
2096 goto error_unreserve;
2097
2098 amdgpu_bo_unreserve(vm->root.bo);
2099
2100 INIT_KFIFO(vm->faults);
2101
2102 return 0;
2103
2104error_unreserve:
2105 amdgpu_bo_unreserve(vm->root.bo);
2106
2107error_free_root:
2108 amdgpu_bo_unref(&root->shadow);
2109 amdgpu_bo_unref(&root_bo);
2110 vm->root.bo = NULL;
2111
2112error_free_delayed:
2113 dma_fence_put(vm->last_tlb_flush);
2114 dma_fence_put(vm->last_unlocked);
2115 drm_sched_entity_destroy(&vm->delayed);
2116
2117error_free_immediate:
2118 drm_sched_entity_destroy(&vm->immediate);
2119
2120 return r;
2121}
2122
2123/**
2124 * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
2125 *
2126 * @adev: amdgpu_device pointer
2127 * @vm: requested vm
2128 *
2129 * This only works on GFX VMs that don't have any BOs added and no
2130 * page tables allocated yet.
2131 *
2132 * Changes the following VM parameters:
2133 * - use_cpu_for_update
2134 * - pte_supports_ats
2135 *
2136 * Reinitializes the page directory to reflect the changed ATS
2137 * setting.
2138 *
2139 * Returns:
2140 * 0 for success, -errno for errors.
2141 */
2142int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2143{
2144 bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
2145 int r;
2146
2147 r = amdgpu_bo_reserve(vm->root.bo, true);
2148 if (r)
2149 return r;
2150
2151 /* Sanity checks */
2152 if (!amdgpu_vm_pt_is_root_clean(adev, vm)) {
2153 r = -EINVAL;
2154 goto unreserve_bo;
2155 }
2156
2157 /* Check if PD needs to be reinitialized and do it before
2158 * changing any other state, in case it fails.
2159 */
2160 if (pte_support_ats != vm->pte_support_ats) {
2161 vm->pte_support_ats = pte_support_ats;
2162 r = amdgpu_vm_pt_clear(adev, vm, to_amdgpu_bo_vm(vm->root.bo),
2163 false);
2164 if (r)
2165 goto unreserve_bo;
2166 }
2167
2168 /* Update VM state */
2169 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2170 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
2171 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2172 vm->use_cpu_for_update ? "CPU" : "SDMA");
2173 WARN_ONCE((vm->use_cpu_for_update &&
2174 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2175 "CPU update of VM recommended only for large BAR system\n");
2176
2177 if (vm->use_cpu_for_update) {
2178 /* Sync with last SDMA update/clear before switching to CPU */
2179 r = amdgpu_bo_sync_wait(vm->root.bo,
2180 AMDGPU_FENCE_OWNER_UNDEFINED, true);
2181 if (r)
2182 goto unreserve_bo;
2183
2184 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2185 } else {
2186 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2187 }
2188 /*
2189 * Make sure root PD gets mapped. As vm_update_mode could be changed
2190 * when turning a GFX VM into a compute VM.
2191 */
2192 r = vm->update_funcs->map_table(to_amdgpu_bo_vm(vm->root.bo));
2193 if (r)
2194 goto unreserve_bo;
2195
2196 dma_fence_put(vm->last_update);
2197 vm->last_update = NULL;
2198 vm->is_compute_context = true;
2199
2200 /* Free the shadow bo for compute VM */
2201 amdgpu_bo_unref(&to_amdgpu_bo_vm(vm->root.bo)->shadow);
2202
2203 goto unreserve_bo;
2204
2205unreserve_bo:
2206 amdgpu_bo_unreserve(vm->root.bo);
2207 return r;
2208}
2209
2210/**
2211 * amdgpu_vm_release_compute - release a compute vm
2212 * @adev: amdgpu_device pointer
2213 * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute
2214 *
2215 * This is a correspondant of amdgpu_vm_make_compute. It decouples compute
2216 * pasid from vm. Compute should stop use of vm after this call.
2217 */
2218void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2219{
2220 amdgpu_vm_set_pasid(adev, vm, 0);
2221 vm->is_compute_context = false;
2222}
2223
2224/**
2225 * amdgpu_vm_fini - tear down a vm instance
2226 *
2227 * @adev: amdgpu_device pointer
2228 * @vm: requested vm
2229 *
2230 * Tear down @vm.
2231 * Unbind the VM and remove all bos from the vm bo list
2232 */
2233void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2234{
2235 struct amdgpu_bo_va_mapping *mapping, *tmp;
2236 bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
2237 struct amdgpu_bo *root;
2238 unsigned long flags;
2239 int i;
2240
2241 amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
2242
2243 flush_work(&vm->pt_free_work);
2244
2245 root = amdgpu_bo_ref(vm->root.bo);
2246 amdgpu_bo_reserve(root, true);
2247 amdgpu_vm_set_pasid(adev, vm, 0);
2248 dma_fence_wait(vm->last_unlocked, false);
2249 dma_fence_put(vm->last_unlocked);
2250 dma_fence_wait(vm->last_tlb_flush, false);
2251 /* Make sure that all fence callbacks have completed */
2252 spin_lock_irqsave(vm->last_tlb_flush->lock, flags);
2253 spin_unlock_irqrestore(vm->last_tlb_flush->lock, flags);
2254 dma_fence_put(vm->last_tlb_flush);
2255
2256 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
2257 if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
2258 amdgpu_vm_prt_fini(adev, vm);
2259 prt_fini_needed = false;
2260 }
2261
2262 list_del(&mapping->list);
2263 amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
2264 }
2265
2266 amdgpu_vm_pt_free_root(adev, vm);
2267 amdgpu_bo_unreserve(root);
2268 amdgpu_bo_unref(&root);
2269 WARN_ON(vm->root.bo);
2270
2271 drm_sched_entity_destroy(&vm->immediate);
2272 drm_sched_entity_destroy(&vm->delayed);
2273
2274 if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
2275 dev_err(adev->dev, "still active bo inside vm\n");
2276 }
2277 rbtree_postorder_for_each_entry_safe(mapping, tmp,
2278 &vm->va.rb_root, rb) {
2279 /* Don't remove the mapping here, we don't want to trigger a
2280 * rebalance and the tree is about to be destroyed anyway.
2281 */
2282 list_del(&mapping->list);
2283 kfree(mapping);
2284 }
2285
2286 dma_fence_put(vm->last_update);
2287 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2288 amdgpu_vmid_free_reserved(adev, vm, i);
2289}
2290
2291/**
2292 * amdgpu_vm_manager_init - init the VM manager
2293 *
2294 * @adev: amdgpu_device pointer
2295 *
2296 * Initialize the VM manager structures
2297 */
2298void amdgpu_vm_manager_init(struct amdgpu_device *adev)
2299{
2300 unsigned i;
2301
2302 /* Concurrent flushes are only possible starting with Vega10 and
2303 * are broken on Navi10 and Navi14.
2304 */
2305 adev->vm_manager.concurrent_flush = !(adev->asic_type < CHIP_VEGA10 ||
2306 adev->asic_type == CHIP_NAVI10 ||
2307 adev->asic_type == CHIP_NAVI14);
2308 amdgpu_vmid_mgr_init(adev);
2309
2310 adev->vm_manager.fence_context =
2311 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2312 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
2313 adev->vm_manager.seqno[i] = 0;
2314
2315 spin_lock_init(&adev->vm_manager.prt_lock);
2316 atomic_set(&adev->vm_manager.num_prt_users, 0);
2317
2318 /* If not overridden by the user, by default, only in large BAR systems
2319 * Compute VM tables will be updated by CPU
2320 */
2321#ifdef CONFIG_X86_64
2322 if (amdgpu_vm_update_mode == -1) {
2323 /* For asic with VF MMIO access protection
2324 * avoid using CPU for VM table updates
2325 */
2326 if (amdgpu_gmc_vram_full_visible(&adev->gmc) &&
2327 !amdgpu_sriov_vf_mmio_access_protection(adev))
2328 adev->vm_manager.vm_update_mode =
2329 AMDGPU_VM_USE_CPU_FOR_COMPUTE;
2330 else
2331 adev->vm_manager.vm_update_mode = 0;
2332 } else
2333 adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
2334#else
2335 adev->vm_manager.vm_update_mode = 0;
2336#endif
2337
2338 xa_init_flags(&adev->vm_manager.pasids, XA_FLAGS_LOCK_IRQ);
2339}
2340
2341/**
2342 * amdgpu_vm_manager_fini - cleanup VM manager
2343 *
2344 * @adev: amdgpu_device pointer
2345 *
2346 * Cleanup the VM manager and free resources.
2347 */
2348void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
2349{
2350 WARN_ON(!xa_empty(&adev->vm_manager.pasids));
2351 xa_destroy(&adev->vm_manager.pasids);
2352
2353 amdgpu_vmid_mgr_fini(adev);
2354}
2355
2356/**
2357 * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs.
2358 *
2359 * @dev: drm device pointer
2360 * @data: drm_amdgpu_vm
2361 * @filp: drm file pointer
2362 *
2363 * Returns:
2364 * 0 for success, -errno for errors.
2365 */
2366int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
2367{
2368 union drm_amdgpu_vm *args = data;
2369 struct amdgpu_device *adev = drm_to_adev(dev);
2370 struct amdgpu_fpriv *fpriv = filp->driver_priv;
2371 int r;
2372
2373 switch (args->in.op) {
2374 case AMDGPU_VM_OP_RESERVE_VMID:
2375 /* We only have requirement to reserve vmid from gfxhub */
2376 r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm,
2377 AMDGPU_GFXHUB_0);
2378 if (r)
2379 return r;
2380 break;
2381 case AMDGPU_VM_OP_UNRESERVE_VMID:
2382 amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0);
2383 break;
2384 default:
2385 return -EINVAL;
2386 }
2387
2388 return 0;
2389}
2390
2391/**
2392 * amdgpu_vm_get_task_info - Extracts task info for a PASID.
2393 *
2394 * @adev: drm device pointer
2395 * @pasid: PASID identifier for VM
2396 * @task_info: task_info to fill.
2397 */
2398void amdgpu_vm_get_task_info(struct amdgpu_device *adev, u32 pasid,
2399 struct amdgpu_task_info *task_info)
2400{
2401 struct amdgpu_vm *vm;
2402 unsigned long flags;
2403
2404 xa_lock_irqsave(&adev->vm_manager.pasids, flags);
2405
2406 vm = xa_load(&adev->vm_manager.pasids, pasid);
2407 if (vm)
2408 *task_info = vm->task_info;
2409
2410 xa_unlock_irqrestore(&adev->vm_manager.pasids, flags);
2411}
2412
2413/**
2414 * amdgpu_vm_set_task_info - Sets VMs task info.
2415 *
2416 * @vm: vm for which to set the info
2417 */
2418void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
2419{
2420 if (vm->task_info.pid)
2421 return;
2422
2423 vm->task_info.pid = current->pid;
2424 get_task_comm(vm->task_info.task_name, current);
2425
2426 if (current->group_leader->mm != current->mm)
2427 return;
2428
2429 vm->task_info.tgid = current->group_leader->pid;
2430 get_task_comm(vm->task_info.process_name, current->group_leader);
2431}
2432
2433/**
2434 * amdgpu_vm_handle_fault - graceful handling of VM faults.
2435 * @adev: amdgpu device pointer
2436 * @pasid: PASID of the VM
2437 * @addr: Address of the fault
2438 * @write_fault: true is write fault, false is read fault
2439 *
2440 * Try to gracefully handle a VM fault. Return true if the fault was handled and
2441 * shouldn't be reported any more.
2442 */
2443bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
2444 uint64_t addr, bool write_fault)
2445{
2446 bool is_compute_context = false;
2447 struct amdgpu_bo *root;
2448 unsigned long irqflags;
2449 uint64_t value, flags;
2450 struct amdgpu_vm *vm;
2451 int r;
2452
2453 xa_lock_irqsave(&adev->vm_manager.pasids, irqflags);
2454 vm = xa_load(&adev->vm_manager.pasids, pasid);
2455 if (vm) {
2456 root = amdgpu_bo_ref(vm->root.bo);
2457 is_compute_context = vm->is_compute_context;
2458 } else {
2459 root = NULL;
2460 }
2461 xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags);
2462
2463 if (!root)
2464 return false;
2465
2466 addr /= AMDGPU_GPU_PAGE_SIZE;
2467
2468 if (is_compute_context &&
2469 !svm_range_restore_pages(adev, pasid, addr, write_fault)) {
2470 amdgpu_bo_unref(&root);
2471 return true;
2472 }
2473
2474 r = amdgpu_bo_reserve(root, true);
2475 if (r)
2476 goto error_unref;
2477
2478 /* Double check that the VM still exists */
2479 xa_lock_irqsave(&adev->vm_manager.pasids, irqflags);
2480 vm = xa_load(&adev->vm_manager.pasids, pasid);
2481 if (vm && vm->root.bo != root)
2482 vm = NULL;
2483 xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags);
2484 if (!vm)
2485 goto error_unlock;
2486
2487 flags = AMDGPU_PTE_VALID | AMDGPU_PTE_SNOOPED |
2488 AMDGPU_PTE_SYSTEM;
2489
2490 if (is_compute_context) {
2491 /* Intentionally setting invalid PTE flag
2492 * combination to force a no-retry-fault
2493 */
2494 flags = AMDGPU_PTE_SNOOPED | AMDGPU_PTE_PRT;
2495 value = 0;
2496 } else if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) {
2497 /* Redirect the access to the dummy page */
2498 value = adev->dummy_page_addr;
2499 flags |= AMDGPU_PTE_EXECUTABLE | AMDGPU_PTE_READABLE |
2500 AMDGPU_PTE_WRITEABLE;
2501
2502 } else {
2503 /* Let the hw retry silently on the PTE */
2504 value = 0;
2505 }
2506
2507 r = dma_resv_reserve_fences(root->tbo.base.resv, 1);
2508 if (r) {
2509 pr_debug("failed %d to reserve fence slot\n", r);
2510 goto error_unlock;
2511 }
2512
2513 r = amdgpu_vm_update_range(adev, vm, true, false, false, NULL, addr,
2514 addr, flags, value, 0, NULL, NULL, NULL);
2515 if (r)
2516 goto error_unlock;
2517
2518 r = amdgpu_vm_update_pdes(adev, vm, true);
2519
2520error_unlock:
2521 amdgpu_bo_unreserve(root);
2522 if (r < 0)
2523 DRM_ERROR("Can't handle page fault (%d)\n", r);
2524
2525error_unref:
2526 amdgpu_bo_unref(&root);
2527
2528 return false;
2529}
2530
2531#if defined(CONFIG_DEBUG_FS)
2532/**
2533 * amdgpu_debugfs_vm_bo_info - print BO info for the VM
2534 *
2535 * @vm: Requested VM for printing BO info
2536 * @m: debugfs file
2537 *
2538 * Print BO information in debugfs file for the VM
2539 */
2540void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m)
2541{
2542 struct amdgpu_bo_va *bo_va, *tmp;
2543 u64 total_idle = 0;
2544 u64 total_evicted = 0;
2545 u64 total_relocated = 0;
2546 u64 total_moved = 0;
2547 u64 total_invalidated = 0;
2548 u64 total_done = 0;
2549 unsigned int total_idle_objs = 0;
2550 unsigned int total_evicted_objs = 0;
2551 unsigned int total_relocated_objs = 0;
2552 unsigned int total_moved_objs = 0;
2553 unsigned int total_invalidated_objs = 0;
2554 unsigned int total_done_objs = 0;
2555 unsigned int id = 0;
2556
2557 spin_lock(&vm->status_lock);
2558 seq_puts(m, "\tIdle BOs:\n");
2559 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
2560 if (!bo_va->base.bo)
2561 continue;
2562 total_idle += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2563 }
2564 total_idle_objs = id;
2565 id = 0;
2566
2567 seq_puts(m, "\tEvicted BOs:\n");
2568 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
2569 if (!bo_va->base.bo)
2570 continue;
2571 total_evicted += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2572 }
2573 total_evicted_objs = id;
2574 id = 0;
2575
2576 seq_puts(m, "\tRelocated BOs:\n");
2577 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
2578 if (!bo_va->base.bo)
2579 continue;
2580 total_relocated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2581 }
2582 total_relocated_objs = id;
2583 id = 0;
2584
2585 seq_puts(m, "\tMoved BOs:\n");
2586 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
2587 if (!bo_va->base.bo)
2588 continue;
2589 total_moved += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2590 }
2591 total_moved_objs = id;
2592 id = 0;
2593
2594 seq_puts(m, "\tInvalidated BOs:\n");
2595 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
2596 if (!bo_va->base.bo)
2597 continue;
2598 total_invalidated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2599 }
2600 total_invalidated_objs = id;
2601 id = 0;
2602
2603 seq_puts(m, "\tDone BOs:\n");
2604 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
2605 if (!bo_va->base.bo)
2606 continue;
2607 total_done += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2608 }
2609 spin_unlock(&vm->status_lock);
2610 total_done_objs = id;
2611
2612 seq_printf(m, "\tTotal idle size: %12lld\tobjs:\t%d\n", total_idle,
2613 total_idle_objs);
2614 seq_printf(m, "\tTotal evicted size: %12lld\tobjs:\t%d\n", total_evicted,
2615 total_evicted_objs);
2616 seq_printf(m, "\tTotal relocated size: %12lld\tobjs:\t%d\n", total_relocated,
2617 total_relocated_objs);
2618 seq_printf(m, "\tTotal moved size: %12lld\tobjs:\t%d\n", total_moved,
2619 total_moved_objs);
2620 seq_printf(m, "\tTotal invalidated size: %12lld\tobjs:\t%d\n", total_invalidated,
2621 total_invalidated_objs);
2622 seq_printf(m, "\tTotal done size: %12lld\tobjs:\t%d\n", total_done,
2623 total_done_objs);
2624}
2625#endif
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/dma-fence-array.h>
30#include <linux/interval_tree_generic.h>
31#include <linux/idr.h>
32#include <linux/dma-buf.h>
33
34#include <drm/amdgpu_drm.h>
35#include <drm/drm_drv.h>
36#include <drm/ttm/ttm_tt.h>
37#include <drm/drm_exec.h>
38#include "amdgpu.h"
39#include "amdgpu_trace.h"
40#include "amdgpu_amdkfd.h"
41#include "amdgpu_gmc.h"
42#include "amdgpu_xgmi.h"
43#include "amdgpu_dma_buf.h"
44#include "amdgpu_res_cursor.h"
45#include "kfd_svm.h"
46
47/**
48 * DOC: GPUVM
49 *
50 * GPUVM is the MMU functionality provided on the GPU.
51 * GPUVM is similar to the legacy GART on older asics, however
52 * rather than there being a single global GART table
53 * for the entire GPU, there can be multiple GPUVM page tables active
54 * at any given time. The GPUVM page tables can contain a mix
55 * VRAM pages and system pages (both memory and MMIO) and system pages
56 * can be mapped as snooped (cached system pages) or unsnooped
57 * (uncached system pages).
58 *
59 * Each active GPUVM has an ID associated with it and there is a page table
60 * linked with each VMID. When executing a command buffer,
61 * the kernel tells the engine what VMID to use for that command
62 * buffer. VMIDs are allocated dynamically as commands are submitted.
63 * The userspace drivers maintain their own address space and the kernel
64 * sets up their pages tables accordingly when they submit their
65 * command buffers and a VMID is assigned.
66 * The hardware supports up to 16 active GPUVMs at any given time.
67 *
68 * Each GPUVM is represented by a 1-2 or 1-5 level page table, depending
69 * on the ASIC family. GPUVM supports RWX attributes on each page as well
70 * as other features such as encryption and caching attributes.
71 *
72 * VMID 0 is special. It is the GPUVM used for the kernel driver. In
73 * addition to an aperture managed by a page table, VMID 0 also has
74 * several other apertures. There is an aperture for direct access to VRAM
75 * and there is a legacy AGP aperture which just forwards accesses directly
76 * to the matching system physical addresses (or IOVAs when an IOMMU is
77 * present). These apertures provide direct access to these memories without
78 * incurring the overhead of a page table. VMID 0 is used by the kernel
79 * driver for tasks like memory management.
80 *
81 * GPU clients (i.e., engines on the GPU) use GPUVM VMIDs to access memory.
82 * For user applications, each application can have their own unique GPUVM
83 * address space. The application manages the address space and the kernel
84 * driver manages the GPUVM page tables for each process. If an GPU client
85 * accesses an invalid page, it will generate a GPU page fault, similar to
86 * accessing an invalid page on a CPU.
87 */
88
89#define START(node) ((node)->start)
90#define LAST(node) ((node)->last)
91
92INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
93 START, LAST, static, amdgpu_vm_it)
94
95#undef START
96#undef LAST
97
98/**
99 * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback
100 */
101struct amdgpu_prt_cb {
102
103 /**
104 * @adev: amdgpu device
105 */
106 struct amdgpu_device *adev;
107
108 /**
109 * @cb: callback
110 */
111 struct dma_fence_cb cb;
112};
113
114/**
115 * struct amdgpu_vm_tlb_seq_struct - Helper to increment the TLB flush sequence
116 */
117struct amdgpu_vm_tlb_seq_struct {
118 /**
119 * @vm: pointer to the amdgpu_vm structure to set the fence sequence on
120 */
121 struct amdgpu_vm *vm;
122
123 /**
124 * @cb: callback
125 */
126 struct dma_fence_cb cb;
127};
128
129/**
130 * amdgpu_vm_set_pasid - manage pasid and vm ptr mapping
131 *
132 * @adev: amdgpu_device pointer
133 * @vm: amdgpu_vm pointer
134 * @pasid: the pasid the VM is using on this GPU
135 *
136 * Set the pasid this VM is using on this GPU, can also be used to remove the
137 * pasid by passing in zero.
138 *
139 */
140int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm,
141 u32 pasid)
142{
143 int r;
144
145 if (vm->pasid == pasid)
146 return 0;
147
148 if (vm->pasid) {
149 r = xa_err(xa_erase_irq(&adev->vm_manager.pasids, vm->pasid));
150 if (r < 0)
151 return r;
152
153 vm->pasid = 0;
154 }
155
156 if (pasid) {
157 r = xa_err(xa_store_irq(&adev->vm_manager.pasids, pasid, vm,
158 GFP_KERNEL));
159 if (r < 0)
160 return r;
161
162 vm->pasid = pasid;
163 }
164
165
166 return 0;
167}
168
169/**
170 * amdgpu_vm_bo_evicted - vm_bo is evicted
171 *
172 * @vm_bo: vm_bo which is evicted
173 *
174 * State for PDs/PTs and per VM BOs which are not at the location they should
175 * be.
176 */
177static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo)
178{
179 struct amdgpu_vm *vm = vm_bo->vm;
180 struct amdgpu_bo *bo = vm_bo->bo;
181
182 vm_bo->moved = true;
183 spin_lock(&vm_bo->vm->status_lock);
184 if (bo->tbo.type == ttm_bo_type_kernel)
185 list_move(&vm_bo->vm_status, &vm->evicted);
186 else
187 list_move_tail(&vm_bo->vm_status, &vm->evicted);
188 spin_unlock(&vm_bo->vm->status_lock);
189}
190/**
191 * amdgpu_vm_bo_moved - vm_bo is moved
192 *
193 * @vm_bo: vm_bo which is moved
194 *
195 * State for per VM BOs which are moved, but that change is not yet reflected
196 * in the page tables.
197 */
198static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo)
199{
200 spin_lock(&vm_bo->vm->status_lock);
201 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
202 spin_unlock(&vm_bo->vm->status_lock);
203}
204
205/**
206 * amdgpu_vm_bo_idle - vm_bo is idle
207 *
208 * @vm_bo: vm_bo which is now idle
209 *
210 * State for PDs/PTs and per VM BOs which have gone through the state machine
211 * and are now idle.
212 */
213static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo)
214{
215 spin_lock(&vm_bo->vm->status_lock);
216 list_move(&vm_bo->vm_status, &vm_bo->vm->idle);
217 spin_unlock(&vm_bo->vm->status_lock);
218 vm_bo->moved = false;
219}
220
221/**
222 * amdgpu_vm_bo_invalidated - vm_bo is invalidated
223 *
224 * @vm_bo: vm_bo which is now invalidated
225 *
226 * State for normal BOs which are invalidated and that change not yet reflected
227 * in the PTs.
228 */
229static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo)
230{
231 spin_lock(&vm_bo->vm->status_lock);
232 list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated);
233 spin_unlock(&vm_bo->vm->status_lock);
234}
235
236/**
237 * amdgpu_vm_bo_evicted_user - vm_bo is evicted
238 *
239 * @vm_bo: vm_bo which is evicted
240 *
241 * State for BOs used by user mode queues which are not at the location they
242 * should be.
243 */
244static void amdgpu_vm_bo_evicted_user(struct amdgpu_vm_bo_base *vm_bo)
245{
246 vm_bo->moved = true;
247 spin_lock(&vm_bo->vm->status_lock);
248 list_move(&vm_bo->vm_status, &vm_bo->vm->evicted_user);
249 spin_unlock(&vm_bo->vm->status_lock);
250}
251
252/**
253 * amdgpu_vm_bo_relocated - vm_bo is reloacted
254 *
255 * @vm_bo: vm_bo which is relocated
256 *
257 * State for PDs/PTs which needs to update their parent PD.
258 * For the root PD, just move to idle state.
259 */
260static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo)
261{
262 if (vm_bo->bo->parent) {
263 spin_lock(&vm_bo->vm->status_lock);
264 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
265 spin_unlock(&vm_bo->vm->status_lock);
266 } else {
267 amdgpu_vm_bo_idle(vm_bo);
268 }
269}
270
271/**
272 * amdgpu_vm_bo_done - vm_bo is done
273 *
274 * @vm_bo: vm_bo which is now done
275 *
276 * State for normal BOs which are invalidated and that change has been updated
277 * in the PTs.
278 */
279static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo)
280{
281 spin_lock(&vm_bo->vm->status_lock);
282 list_move(&vm_bo->vm_status, &vm_bo->vm->done);
283 spin_unlock(&vm_bo->vm->status_lock);
284}
285
286/**
287 * amdgpu_vm_bo_reset_state_machine - reset the vm_bo state machine
288 * @vm: the VM which state machine to reset
289 *
290 * Move all vm_bo object in the VM into a state where they will be updated
291 * again during validation.
292 */
293static void amdgpu_vm_bo_reset_state_machine(struct amdgpu_vm *vm)
294{
295 struct amdgpu_vm_bo_base *vm_bo, *tmp;
296
297 spin_lock(&vm->status_lock);
298 list_splice_init(&vm->done, &vm->invalidated);
299 list_for_each_entry(vm_bo, &vm->invalidated, vm_status)
300 vm_bo->moved = true;
301 list_for_each_entry_safe(vm_bo, tmp, &vm->idle, vm_status) {
302 struct amdgpu_bo *bo = vm_bo->bo;
303
304 vm_bo->moved = true;
305 if (!bo || bo->tbo.type != ttm_bo_type_kernel)
306 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
307 else if (bo->parent)
308 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
309 }
310 spin_unlock(&vm->status_lock);
311}
312
313/**
314 * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm
315 *
316 * @base: base structure for tracking BO usage in a VM
317 * @vm: vm to which bo is to be added
318 * @bo: amdgpu buffer object
319 *
320 * Initialize a bo_va_base structure and add it to the appropriate lists
321 *
322 */
323void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
324 struct amdgpu_vm *vm, struct amdgpu_bo *bo)
325{
326 base->vm = vm;
327 base->bo = bo;
328 base->next = NULL;
329 INIT_LIST_HEAD(&base->vm_status);
330
331 if (!bo)
332 return;
333 base->next = bo->vm_bo;
334 bo->vm_bo = base;
335
336 if (!amdgpu_vm_is_bo_always_valid(vm, bo))
337 return;
338
339 dma_resv_assert_held(vm->root.bo->tbo.base.resv);
340
341 ttm_bo_set_bulk_move(&bo->tbo, &vm->lru_bulk_move);
342 if (bo->tbo.type == ttm_bo_type_kernel && bo->parent)
343 amdgpu_vm_bo_relocated(base);
344 else
345 amdgpu_vm_bo_idle(base);
346
347 if (bo->preferred_domains &
348 amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type))
349 return;
350
351 /*
352 * we checked all the prerequisites, but it looks like this per vm bo
353 * is currently evicted. add the bo to the evicted list to make sure it
354 * is validated on next vm use to avoid fault.
355 * */
356 amdgpu_vm_bo_evicted(base);
357}
358
359/**
360 * amdgpu_vm_lock_pd - lock PD in drm_exec
361 *
362 * @vm: vm providing the BOs
363 * @exec: drm execution context
364 * @num_fences: number of extra fences to reserve
365 *
366 * Lock the VM root PD in the DRM execution context.
367 */
368int amdgpu_vm_lock_pd(struct amdgpu_vm *vm, struct drm_exec *exec,
369 unsigned int num_fences)
370{
371 /* We need at least two fences for the VM PD/PT updates */
372 return drm_exec_prepare_obj(exec, &vm->root.bo->tbo.base,
373 2 + num_fences);
374}
375
376/**
377 * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU
378 *
379 * @adev: amdgpu device pointer
380 * @vm: vm providing the BOs
381 *
382 * Move all BOs to the end of LRU and remember their positions to put them
383 * together.
384 */
385void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
386 struct amdgpu_vm *vm)
387{
388 spin_lock(&adev->mman.bdev.lru_lock);
389 ttm_lru_bulk_move_tail(&vm->lru_bulk_move);
390 spin_unlock(&adev->mman.bdev.lru_lock);
391}
392
393/* Create scheduler entities for page table updates */
394static int amdgpu_vm_init_entities(struct amdgpu_device *adev,
395 struct amdgpu_vm *vm)
396{
397 int r;
398
399 r = drm_sched_entity_init(&vm->immediate, DRM_SCHED_PRIORITY_NORMAL,
400 adev->vm_manager.vm_pte_scheds,
401 adev->vm_manager.vm_pte_num_scheds, NULL);
402 if (r)
403 goto error;
404
405 return drm_sched_entity_init(&vm->delayed, DRM_SCHED_PRIORITY_NORMAL,
406 adev->vm_manager.vm_pte_scheds,
407 adev->vm_manager.vm_pte_num_scheds, NULL);
408
409error:
410 drm_sched_entity_destroy(&vm->immediate);
411 return r;
412}
413
414/* Destroy the entities for page table updates again */
415static void amdgpu_vm_fini_entities(struct amdgpu_vm *vm)
416{
417 drm_sched_entity_destroy(&vm->immediate);
418 drm_sched_entity_destroy(&vm->delayed);
419}
420
421/**
422 * amdgpu_vm_generation - return the page table re-generation counter
423 * @adev: the amdgpu_device
424 * @vm: optional VM to check, might be NULL
425 *
426 * Returns a page table re-generation token to allow checking if submissions
427 * are still valid to use this VM. The VM parameter might be NULL in which case
428 * just the VRAM lost counter will be used.
429 */
430uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm)
431{
432 uint64_t result = (u64)atomic_read(&adev->vram_lost_counter) << 32;
433
434 if (!vm)
435 return result;
436
437 result += lower_32_bits(vm->generation);
438 /* Add one if the page tables will be re-generated on next CS */
439 if (drm_sched_entity_error(&vm->delayed))
440 ++result;
441
442 return result;
443}
444
445/**
446 * amdgpu_vm_validate - validate evicted BOs tracked in the VM
447 *
448 * @adev: amdgpu device pointer
449 * @vm: vm providing the BOs
450 * @ticket: optional reservation ticket used to reserve the VM
451 * @validate: callback to do the validation
452 * @param: parameter for the validation callback
453 *
454 * Validate the page table BOs and per-VM BOs on command submission if
455 * necessary. If a ticket is given, also try to validate evicted user queue
456 * BOs. They must already be reserved with the given ticket.
457 *
458 * Returns:
459 * Validation result.
460 */
461int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm,
462 struct ww_acquire_ctx *ticket,
463 int (*validate)(void *p, struct amdgpu_bo *bo),
464 void *param)
465{
466 uint64_t new_vm_generation = amdgpu_vm_generation(adev, vm);
467 struct amdgpu_vm_bo_base *bo_base;
468 struct amdgpu_bo *bo;
469 int r;
470
471 if (vm->generation != new_vm_generation) {
472 vm->generation = new_vm_generation;
473 amdgpu_vm_bo_reset_state_machine(vm);
474 amdgpu_vm_fini_entities(vm);
475 r = amdgpu_vm_init_entities(adev, vm);
476 if (r)
477 return r;
478 }
479
480 spin_lock(&vm->status_lock);
481 while (!list_empty(&vm->evicted)) {
482 bo_base = list_first_entry(&vm->evicted,
483 struct amdgpu_vm_bo_base,
484 vm_status);
485 spin_unlock(&vm->status_lock);
486
487 bo = bo_base->bo;
488
489 r = validate(param, bo);
490 if (r)
491 return r;
492
493 if (bo->tbo.type != ttm_bo_type_kernel) {
494 amdgpu_vm_bo_moved(bo_base);
495 } else {
496 vm->update_funcs->map_table(to_amdgpu_bo_vm(bo));
497 amdgpu_vm_bo_relocated(bo_base);
498 }
499 spin_lock(&vm->status_lock);
500 }
501 while (ticket && !list_empty(&vm->evicted_user)) {
502 bo_base = list_first_entry(&vm->evicted_user,
503 struct amdgpu_vm_bo_base,
504 vm_status);
505 spin_unlock(&vm->status_lock);
506
507 bo = bo_base->bo;
508
509 if (dma_resv_locking_ctx(bo->tbo.base.resv) != ticket) {
510 struct amdgpu_task_info *ti = amdgpu_vm_get_task_info_vm(vm);
511
512 pr_warn_ratelimited("Evicted user BO is not reserved\n");
513 if (ti) {
514 pr_warn_ratelimited("pid %d\n", ti->pid);
515 amdgpu_vm_put_task_info(ti);
516 }
517
518 return -EINVAL;
519 }
520
521 r = validate(param, bo);
522 if (r)
523 return r;
524
525 amdgpu_vm_bo_invalidated(bo_base);
526
527 spin_lock(&vm->status_lock);
528 }
529 spin_unlock(&vm->status_lock);
530
531 amdgpu_vm_eviction_lock(vm);
532 vm->evicting = false;
533 amdgpu_vm_eviction_unlock(vm);
534
535 return 0;
536}
537
538/**
539 * amdgpu_vm_ready - check VM is ready for updates
540 *
541 * @vm: VM to check
542 *
543 * Check if all VM PDs/PTs are ready for updates
544 *
545 * Returns:
546 * True if VM is not evicting.
547 */
548bool amdgpu_vm_ready(struct amdgpu_vm *vm)
549{
550 bool empty;
551 bool ret;
552
553 amdgpu_vm_eviction_lock(vm);
554 ret = !vm->evicting;
555 amdgpu_vm_eviction_unlock(vm);
556
557 spin_lock(&vm->status_lock);
558 empty = list_empty(&vm->evicted);
559 spin_unlock(&vm->status_lock);
560
561 return ret && empty;
562}
563
564/**
565 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
566 *
567 * @adev: amdgpu_device pointer
568 */
569void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
570{
571 const struct amdgpu_ip_block *ip_block;
572 bool has_compute_vm_bug;
573 struct amdgpu_ring *ring;
574 int i;
575
576 has_compute_vm_bug = false;
577
578 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
579 if (ip_block) {
580 /* Compute has a VM bug for GFX version < 7.
581 Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
582 if (ip_block->version->major <= 7)
583 has_compute_vm_bug = true;
584 else if (ip_block->version->major == 8)
585 if (adev->gfx.mec_fw_version < 673)
586 has_compute_vm_bug = true;
587 }
588
589 for (i = 0; i < adev->num_rings; i++) {
590 ring = adev->rings[i];
591 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
592 /* only compute rings */
593 ring->has_compute_vm_bug = has_compute_vm_bug;
594 else
595 ring->has_compute_vm_bug = false;
596 }
597}
598
599/**
600 * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job.
601 *
602 * @ring: ring on which the job will be submitted
603 * @job: job to submit
604 *
605 * Returns:
606 * True if sync is needed.
607 */
608bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
609 struct amdgpu_job *job)
610{
611 struct amdgpu_device *adev = ring->adev;
612 unsigned vmhub = ring->vm_hub;
613 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
614
615 if (job->vmid == 0)
616 return false;
617
618 if (job->vm_needs_flush || ring->has_compute_vm_bug)
619 return true;
620
621 if (ring->funcs->emit_gds_switch && job->gds_switch_needed)
622 return true;
623
624 if (amdgpu_vmid_had_gpu_reset(adev, &id_mgr->ids[job->vmid]))
625 return true;
626
627 return false;
628}
629
630/**
631 * amdgpu_vm_flush - hardware flush the vm
632 *
633 * @ring: ring to use for flush
634 * @job: related job
635 * @need_pipe_sync: is pipe sync needed
636 *
637 * Emit a VM flush when it is necessary.
638 *
639 * Returns:
640 * 0 on success, errno otherwise.
641 */
642int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
643 bool need_pipe_sync)
644{
645 struct amdgpu_device *adev = ring->adev;
646 unsigned vmhub = ring->vm_hub;
647 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
648 struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
649 bool spm_update_needed = job->spm_update_needed;
650 bool gds_switch_needed = ring->funcs->emit_gds_switch &&
651 job->gds_switch_needed;
652 bool vm_flush_needed = job->vm_needs_flush;
653 struct dma_fence *fence = NULL;
654 bool pasid_mapping_needed = false;
655 unsigned int patch;
656 int r;
657
658 if (amdgpu_vmid_had_gpu_reset(adev, id)) {
659 gds_switch_needed = true;
660 vm_flush_needed = true;
661 pasid_mapping_needed = true;
662 spm_update_needed = true;
663 }
664
665 mutex_lock(&id_mgr->lock);
666 if (id->pasid != job->pasid || !id->pasid_mapping ||
667 !dma_fence_is_signaled(id->pasid_mapping))
668 pasid_mapping_needed = true;
669 mutex_unlock(&id_mgr->lock);
670
671 gds_switch_needed &= !!ring->funcs->emit_gds_switch;
672 vm_flush_needed &= !!ring->funcs->emit_vm_flush &&
673 job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET;
674 pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping &&
675 ring->funcs->emit_wreg;
676
677 if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync &&
678 !(job->enforce_isolation && !job->vmid))
679 return 0;
680
681 amdgpu_ring_ib_begin(ring);
682 if (ring->funcs->init_cond_exec)
683 patch = amdgpu_ring_init_cond_exec(ring,
684 ring->cond_exe_gpu_addr);
685
686 if (need_pipe_sync)
687 amdgpu_ring_emit_pipeline_sync(ring);
688
689 if (adev->gfx.enable_cleaner_shader &&
690 ring->funcs->emit_cleaner_shader &&
691 job->enforce_isolation)
692 ring->funcs->emit_cleaner_shader(ring);
693
694 if (vm_flush_needed) {
695 trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
696 amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
697 }
698
699 if (pasid_mapping_needed)
700 amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
701
702 if (spm_update_needed && adev->gfx.rlc.funcs->update_spm_vmid)
703 adev->gfx.rlc.funcs->update_spm_vmid(adev, ring, job->vmid);
704
705 if (!ring->is_mes_queue && ring->funcs->emit_gds_switch &&
706 gds_switch_needed) {
707 amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
708 job->gds_size, job->gws_base,
709 job->gws_size, job->oa_base,
710 job->oa_size);
711 }
712
713 if (vm_flush_needed || pasid_mapping_needed) {
714 r = amdgpu_fence_emit(ring, &fence, NULL, 0);
715 if (r)
716 return r;
717 }
718
719 if (vm_flush_needed) {
720 mutex_lock(&id_mgr->lock);
721 dma_fence_put(id->last_flush);
722 id->last_flush = dma_fence_get(fence);
723 id->current_gpu_reset_count =
724 atomic_read(&adev->gpu_reset_counter);
725 mutex_unlock(&id_mgr->lock);
726 }
727
728 if (pasid_mapping_needed) {
729 mutex_lock(&id_mgr->lock);
730 id->pasid = job->pasid;
731 dma_fence_put(id->pasid_mapping);
732 id->pasid_mapping = dma_fence_get(fence);
733 mutex_unlock(&id_mgr->lock);
734 }
735 dma_fence_put(fence);
736
737 amdgpu_ring_patch_cond_exec(ring, patch);
738
739 /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
740 if (ring->funcs->emit_switch_buffer) {
741 amdgpu_ring_emit_switch_buffer(ring);
742 amdgpu_ring_emit_switch_buffer(ring);
743 }
744
745 amdgpu_ring_ib_end(ring);
746 return 0;
747}
748
749/**
750 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
751 *
752 * @vm: requested vm
753 * @bo: requested buffer object
754 *
755 * Find @bo inside the requested vm.
756 * Search inside the @bos vm list for the requested vm
757 * Returns the found bo_va or NULL if none is found
758 *
759 * Object has to be reserved!
760 *
761 * Returns:
762 * Found bo_va or NULL.
763 */
764struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
765 struct amdgpu_bo *bo)
766{
767 struct amdgpu_vm_bo_base *base;
768
769 for (base = bo->vm_bo; base; base = base->next) {
770 if (base->vm != vm)
771 continue;
772
773 return container_of(base, struct amdgpu_bo_va, base);
774 }
775 return NULL;
776}
777
778/**
779 * amdgpu_vm_map_gart - Resolve gart mapping of addr
780 *
781 * @pages_addr: optional DMA address to use for lookup
782 * @addr: the unmapped addr
783 *
784 * Look up the physical address of the page that the pte resolves
785 * to.
786 *
787 * Returns:
788 * The pointer for the page table entry.
789 */
790uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
791{
792 uint64_t result;
793
794 /* page table offset */
795 result = pages_addr[addr >> PAGE_SHIFT];
796
797 /* in case cpu page size != gpu page size*/
798 result |= addr & (~PAGE_MASK);
799
800 result &= 0xFFFFFFFFFFFFF000ULL;
801
802 return result;
803}
804
805/**
806 * amdgpu_vm_update_pdes - make sure that all directories are valid
807 *
808 * @adev: amdgpu_device pointer
809 * @vm: requested vm
810 * @immediate: submit immediately to the paging queue
811 *
812 * Makes sure all directories are up to date.
813 *
814 * Returns:
815 * 0 for success, error for failure.
816 */
817int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
818 struct amdgpu_vm *vm, bool immediate)
819{
820 struct amdgpu_vm_update_params params;
821 struct amdgpu_vm_bo_base *entry;
822 bool flush_tlb_needed = false;
823 LIST_HEAD(relocated);
824 int r, idx;
825
826 spin_lock(&vm->status_lock);
827 list_splice_init(&vm->relocated, &relocated);
828 spin_unlock(&vm->status_lock);
829
830 if (list_empty(&relocated))
831 return 0;
832
833 if (!drm_dev_enter(adev_to_drm(adev), &idx))
834 return -ENODEV;
835
836 memset(¶ms, 0, sizeof(params));
837 params.adev = adev;
838 params.vm = vm;
839 params.immediate = immediate;
840
841 r = vm->update_funcs->prepare(¶ms, NULL);
842 if (r)
843 goto error;
844
845 list_for_each_entry(entry, &relocated, vm_status) {
846 /* vm_flush_needed after updating moved PDEs */
847 flush_tlb_needed |= entry->moved;
848
849 r = amdgpu_vm_pde_update(¶ms, entry);
850 if (r)
851 goto error;
852 }
853
854 r = vm->update_funcs->commit(¶ms, &vm->last_update);
855 if (r)
856 goto error;
857
858 if (flush_tlb_needed)
859 atomic64_inc(&vm->tlb_seq);
860
861 while (!list_empty(&relocated)) {
862 entry = list_first_entry(&relocated, struct amdgpu_vm_bo_base,
863 vm_status);
864 amdgpu_vm_bo_idle(entry);
865 }
866
867error:
868 drm_dev_exit(idx);
869 return r;
870}
871
872/**
873 * amdgpu_vm_tlb_seq_cb - make sure to increment tlb sequence
874 * @fence: unused
875 * @cb: the callback structure
876 *
877 * Increments the tlb sequence to make sure that future CS execute a VM flush.
878 */
879static void amdgpu_vm_tlb_seq_cb(struct dma_fence *fence,
880 struct dma_fence_cb *cb)
881{
882 struct amdgpu_vm_tlb_seq_struct *tlb_cb;
883
884 tlb_cb = container_of(cb, typeof(*tlb_cb), cb);
885 atomic64_inc(&tlb_cb->vm->tlb_seq);
886 kfree(tlb_cb);
887}
888
889/**
890 * amdgpu_vm_tlb_flush - prepare TLB flush
891 *
892 * @params: parameters for update
893 * @fence: input fence to sync TLB flush with
894 * @tlb_cb: the callback structure
895 *
896 * Increments the tlb sequence to make sure that future CS execute a VM flush.
897 */
898static void
899amdgpu_vm_tlb_flush(struct amdgpu_vm_update_params *params,
900 struct dma_fence **fence,
901 struct amdgpu_vm_tlb_seq_struct *tlb_cb)
902{
903 struct amdgpu_vm *vm = params->vm;
904
905 tlb_cb->vm = vm;
906 if (!fence || !*fence) {
907 amdgpu_vm_tlb_seq_cb(NULL, &tlb_cb->cb);
908 return;
909 }
910
911 if (!dma_fence_add_callback(*fence, &tlb_cb->cb,
912 amdgpu_vm_tlb_seq_cb)) {
913 dma_fence_put(vm->last_tlb_flush);
914 vm->last_tlb_flush = dma_fence_get(*fence);
915 } else {
916 amdgpu_vm_tlb_seq_cb(NULL, &tlb_cb->cb);
917 }
918
919 /* Prepare a TLB flush fence to be attached to PTs */
920 if (!params->unlocked && vm->is_compute_context) {
921 amdgpu_vm_tlb_fence_create(params->adev, vm, fence);
922
923 /* Makes sure no PD/PT is freed before the flush */
924 dma_resv_add_fence(vm->root.bo->tbo.base.resv, *fence,
925 DMA_RESV_USAGE_BOOKKEEP);
926 }
927}
928
929/**
930 * amdgpu_vm_update_range - update a range in the vm page table
931 *
932 * @adev: amdgpu_device pointer to use for commands
933 * @vm: the VM to update the range
934 * @immediate: immediate submission in a page fault
935 * @unlocked: unlocked invalidation during MM callback
936 * @flush_tlb: trigger tlb invalidation after update completed
937 * @allow_override: change MTYPE for local NUMA nodes
938 * @sync: fences we need to sync to
939 * @start: start of mapped range
940 * @last: last mapped entry
941 * @flags: flags for the entries
942 * @offset: offset into nodes and pages_addr
943 * @vram_base: base for vram mappings
944 * @res: ttm_resource to map
945 * @pages_addr: DMA addresses to use for mapping
946 * @fence: optional resulting fence
947 *
948 * Fill in the page table entries between @start and @last.
949 *
950 * Returns:
951 * 0 for success, negative erro code for failure.
952 */
953int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
954 bool immediate, bool unlocked, bool flush_tlb,
955 bool allow_override, struct amdgpu_sync *sync,
956 uint64_t start, uint64_t last, uint64_t flags,
957 uint64_t offset, uint64_t vram_base,
958 struct ttm_resource *res, dma_addr_t *pages_addr,
959 struct dma_fence **fence)
960{
961 struct amdgpu_vm_tlb_seq_struct *tlb_cb;
962 struct amdgpu_vm_update_params params;
963 struct amdgpu_res_cursor cursor;
964 int r, idx;
965
966 if (!drm_dev_enter(adev_to_drm(adev), &idx))
967 return -ENODEV;
968
969 tlb_cb = kmalloc(sizeof(*tlb_cb), GFP_KERNEL);
970 if (!tlb_cb) {
971 drm_dev_exit(idx);
972 return -ENOMEM;
973 }
974
975 /* Vega20+XGMI where PTEs get inadvertently cached in L2 texture cache,
976 * heavy-weight flush TLB unconditionally.
977 */
978 flush_tlb |= adev->gmc.xgmi.num_physical_nodes &&
979 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0);
980
981 /*
982 * On GFX8 and older any 8 PTE block with a valid bit set enters the TLB
983 */
984 flush_tlb |= amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 0, 0);
985
986 memset(¶ms, 0, sizeof(params));
987 params.adev = adev;
988 params.vm = vm;
989 params.immediate = immediate;
990 params.pages_addr = pages_addr;
991 params.unlocked = unlocked;
992 params.needs_flush = flush_tlb;
993 params.allow_override = allow_override;
994 INIT_LIST_HEAD(¶ms.tlb_flush_waitlist);
995
996 amdgpu_vm_eviction_lock(vm);
997 if (vm->evicting) {
998 r = -EBUSY;
999 goto error_free;
1000 }
1001
1002 if (!unlocked && !dma_fence_is_signaled(vm->last_unlocked)) {
1003 struct dma_fence *tmp = dma_fence_get_stub();
1004
1005 amdgpu_bo_fence(vm->root.bo, vm->last_unlocked, true);
1006 swap(vm->last_unlocked, tmp);
1007 dma_fence_put(tmp);
1008 }
1009
1010 r = vm->update_funcs->prepare(¶ms, sync);
1011 if (r)
1012 goto error_free;
1013
1014 amdgpu_res_first(pages_addr ? NULL : res, offset,
1015 (last - start + 1) * AMDGPU_GPU_PAGE_SIZE, &cursor);
1016 while (cursor.remaining) {
1017 uint64_t tmp, num_entries, addr;
1018
1019 num_entries = cursor.size >> AMDGPU_GPU_PAGE_SHIFT;
1020 if (pages_addr) {
1021 bool contiguous = true;
1022
1023 if (num_entries > AMDGPU_GPU_PAGES_IN_CPU_PAGE) {
1024 uint64_t pfn = cursor.start >> PAGE_SHIFT;
1025 uint64_t count;
1026
1027 contiguous = pages_addr[pfn + 1] ==
1028 pages_addr[pfn] + PAGE_SIZE;
1029
1030 tmp = num_entries /
1031 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1032 for (count = 2; count < tmp; ++count) {
1033 uint64_t idx = pfn + count;
1034
1035 if (contiguous != (pages_addr[idx] ==
1036 pages_addr[idx - 1] + PAGE_SIZE))
1037 break;
1038 }
1039 if (!contiguous)
1040 count--;
1041 num_entries = count *
1042 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1043 }
1044
1045 if (!contiguous) {
1046 addr = cursor.start;
1047 params.pages_addr = pages_addr;
1048 } else {
1049 addr = pages_addr[cursor.start >> PAGE_SHIFT];
1050 params.pages_addr = NULL;
1051 }
1052
1053 } else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT_FLAG(adev))) {
1054 addr = vram_base + cursor.start;
1055 } else {
1056 addr = 0;
1057 }
1058
1059 tmp = start + num_entries;
1060 r = amdgpu_vm_ptes_update(¶ms, start, tmp, addr, flags);
1061 if (r)
1062 goto error_free;
1063
1064 amdgpu_res_next(&cursor, num_entries * AMDGPU_GPU_PAGE_SIZE);
1065 start = tmp;
1066 }
1067
1068 r = vm->update_funcs->commit(¶ms, fence);
1069 if (r)
1070 goto error_free;
1071
1072 if (params.needs_flush) {
1073 amdgpu_vm_tlb_flush(¶ms, fence, tlb_cb);
1074 tlb_cb = NULL;
1075 }
1076
1077 amdgpu_vm_pt_free_list(adev, ¶ms);
1078
1079error_free:
1080 kfree(tlb_cb);
1081 amdgpu_vm_eviction_unlock(vm);
1082 drm_dev_exit(idx);
1083 return r;
1084}
1085
1086static void amdgpu_vm_bo_get_memory(struct amdgpu_bo_va *bo_va,
1087 struct amdgpu_mem_stats *stats,
1088 unsigned int size)
1089{
1090 struct amdgpu_vm *vm = bo_va->base.vm;
1091 struct amdgpu_bo *bo = bo_va->base.bo;
1092
1093 if (!bo)
1094 return;
1095
1096 /*
1097 * For now ignore BOs which are currently locked and potentially
1098 * changing their location.
1099 */
1100 if (!amdgpu_vm_is_bo_always_valid(vm, bo) &&
1101 !dma_resv_trylock(bo->tbo.base.resv))
1102 return;
1103
1104 amdgpu_bo_get_memory(bo, stats, size);
1105 if (!amdgpu_vm_is_bo_always_valid(vm, bo))
1106 dma_resv_unlock(bo->tbo.base.resv);
1107}
1108
1109void amdgpu_vm_get_memory(struct amdgpu_vm *vm,
1110 struct amdgpu_mem_stats *stats,
1111 unsigned int size)
1112{
1113 struct amdgpu_bo_va *bo_va, *tmp;
1114
1115 spin_lock(&vm->status_lock);
1116 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status)
1117 amdgpu_vm_bo_get_memory(bo_va, stats, size);
1118
1119 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status)
1120 amdgpu_vm_bo_get_memory(bo_va, stats, size);
1121
1122 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status)
1123 amdgpu_vm_bo_get_memory(bo_va, stats, size);
1124
1125 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status)
1126 amdgpu_vm_bo_get_memory(bo_va, stats, size);
1127
1128 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status)
1129 amdgpu_vm_bo_get_memory(bo_va, stats, size);
1130
1131 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status)
1132 amdgpu_vm_bo_get_memory(bo_va, stats, size);
1133 spin_unlock(&vm->status_lock);
1134}
1135
1136/**
1137 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1138 *
1139 * @adev: amdgpu_device pointer
1140 * @bo_va: requested BO and VM object
1141 * @clear: if true clear the entries
1142 *
1143 * Fill in the page table entries for @bo_va.
1144 *
1145 * Returns:
1146 * 0 for success, -EINVAL for failure.
1147 */
1148int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
1149 bool clear)
1150{
1151 struct amdgpu_bo *bo = bo_va->base.bo;
1152 struct amdgpu_vm *vm = bo_va->base.vm;
1153 struct amdgpu_bo_va_mapping *mapping;
1154 struct dma_fence **last_update;
1155 dma_addr_t *pages_addr = NULL;
1156 struct ttm_resource *mem;
1157 struct amdgpu_sync sync;
1158 bool flush_tlb = clear;
1159 uint64_t vram_base;
1160 uint64_t flags;
1161 bool uncached;
1162 int r;
1163
1164 amdgpu_sync_create(&sync);
1165 if (clear) {
1166 mem = NULL;
1167
1168 /* Implicitly sync to command submissions in the same VM before
1169 * unmapping.
1170 */
1171 r = amdgpu_sync_resv(adev, &sync, vm->root.bo->tbo.base.resv,
1172 AMDGPU_SYNC_EQ_OWNER, vm);
1173 if (r)
1174 goto error_free;
1175 if (bo) {
1176 r = amdgpu_sync_kfd(&sync, bo->tbo.base.resv);
1177 if (r)
1178 goto error_free;
1179 }
1180 } else if (!bo) {
1181 mem = NULL;
1182
1183 /* PRT map operations don't need to sync to anything. */
1184
1185 } else {
1186 struct drm_gem_object *obj = &bo->tbo.base;
1187
1188 if (obj->import_attach && bo_va->is_xgmi) {
1189 struct dma_buf *dma_buf = obj->import_attach->dmabuf;
1190 struct drm_gem_object *gobj = dma_buf->priv;
1191 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
1192
1193 if (abo->tbo.resource &&
1194 abo->tbo.resource->mem_type == TTM_PL_VRAM)
1195 bo = gem_to_amdgpu_bo(gobj);
1196 }
1197 mem = bo->tbo.resource;
1198 if (mem && (mem->mem_type == TTM_PL_TT ||
1199 mem->mem_type == AMDGPU_PL_PREEMPT))
1200 pages_addr = bo->tbo.ttm->dma_address;
1201
1202 /* Implicitly sync to moving fences before mapping anything */
1203 r = amdgpu_sync_resv(adev, &sync, bo->tbo.base.resv,
1204 AMDGPU_SYNC_EXPLICIT, vm);
1205 if (r)
1206 goto error_free;
1207 }
1208
1209 if (bo) {
1210 struct amdgpu_device *bo_adev;
1211
1212 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
1213
1214 if (amdgpu_bo_encrypted(bo))
1215 flags |= AMDGPU_PTE_TMZ;
1216
1217 bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
1218 vram_base = bo_adev->vm_manager.vram_base_offset;
1219 uncached = (bo->flags & AMDGPU_GEM_CREATE_UNCACHED) != 0;
1220 } else {
1221 flags = 0x0;
1222 vram_base = 0;
1223 uncached = false;
1224 }
1225
1226 if (clear || amdgpu_vm_is_bo_always_valid(vm, bo))
1227 last_update = &vm->last_update;
1228 else
1229 last_update = &bo_va->last_pt_update;
1230
1231 if (!clear && bo_va->base.moved) {
1232 flush_tlb = true;
1233 list_splice_init(&bo_va->valids, &bo_va->invalids);
1234
1235 } else if (bo_va->cleared != clear) {
1236 list_splice_init(&bo_va->valids, &bo_va->invalids);
1237 }
1238
1239 list_for_each_entry(mapping, &bo_va->invalids, list) {
1240 uint64_t update_flags = flags;
1241
1242 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1243 * but in case of something, we filter the flags in first place
1244 */
1245 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1246 update_flags &= ~AMDGPU_PTE_READABLE;
1247 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1248 update_flags &= ~AMDGPU_PTE_WRITEABLE;
1249
1250 /* Apply ASIC specific mapping flags */
1251 amdgpu_gmc_get_vm_pte(adev, mapping, &update_flags);
1252
1253 trace_amdgpu_vm_bo_update(mapping);
1254
1255 r = amdgpu_vm_update_range(adev, vm, false, false, flush_tlb,
1256 !uncached, &sync, mapping->start,
1257 mapping->last, update_flags,
1258 mapping->offset, vram_base, mem,
1259 pages_addr, last_update);
1260 if (r)
1261 goto error_free;
1262 }
1263
1264 /* If the BO is not in its preferred location add it back to
1265 * the evicted list so that it gets validated again on the
1266 * next command submission.
1267 */
1268 if (amdgpu_vm_is_bo_always_valid(vm, bo)) {
1269 if (bo->tbo.resource &&
1270 !(bo->preferred_domains &
1271 amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type)))
1272 amdgpu_vm_bo_evicted(&bo_va->base);
1273 else
1274 amdgpu_vm_bo_idle(&bo_va->base);
1275 } else {
1276 amdgpu_vm_bo_done(&bo_va->base);
1277 }
1278
1279 list_splice_init(&bo_va->invalids, &bo_va->valids);
1280 bo_va->cleared = clear;
1281 bo_va->base.moved = false;
1282
1283 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1284 list_for_each_entry(mapping, &bo_va->valids, list)
1285 trace_amdgpu_vm_bo_mapping(mapping);
1286 }
1287
1288error_free:
1289 amdgpu_sync_free(&sync);
1290 return r;
1291}
1292
1293/**
1294 * amdgpu_vm_update_prt_state - update the global PRT state
1295 *
1296 * @adev: amdgpu_device pointer
1297 */
1298static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
1299{
1300 unsigned long flags;
1301 bool enable;
1302
1303 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
1304 enable = !!atomic_read(&adev->vm_manager.num_prt_users);
1305 adev->gmc.gmc_funcs->set_prt(adev, enable);
1306 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
1307}
1308
1309/**
1310 * amdgpu_vm_prt_get - add a PRT user
1311 *
1312 * @adev: amdgpu_device pointer
1313 */
1314static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
1315{
1316 if (!adev->gmc.gmc_funcs->set_prt)
1317 return;
1318
1319 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
1320 amdgpu_vm_update_prt_state(adev);
1321}
1322
1323/**
1324 * amdgpu_vm_prt_put - drop a PRT user
1325 *
1326 * @adev: amdgpu_device pointer
1327 */
1328static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
1329{
1330 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
1331 amdgpu_vm_update_prt_state(adev);
1332}
1333
1334/**
1335 * amdgpu_vm_prt_cb - callback for updating the PRT status
1336 *
1337 * @fence: fence for the callback
1338 * @_cb: the callback function
1339 */
1340static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
1341{
1342 struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
1343
1344 amdgpu_vm_prt_put(cb->adev);
1345 kfree(cb);
1346}
1347
1348/**
1349 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1350 *
1351 * @adev: amdgpu_device pointer
1352 * @fence: fence for the callback
1353 */
1354static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
1355 struct dma_fence *fence)
1356{
1357 struct amdgpu_prt_cb *cb;
1358
1359 if (!adev->gmc.gmc_funcs->set_prt)
1360 return;
1361
1362 cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
1363 if (!cb) {
1364 /* Last resort when we are OOM */
1365 if (fence)
1366 dma_fence_wait(fence, false);
1367
1368 amdgpu_vm_prt_put(adev);
1369 } else {
1370 cb->adev = adev;
1371 if (!fence || dma_fence_add_callback(fence, &cb->cb,
1372 amdgpu_vm_prt_cb))
1373 amdgpu_vm_prt_cb(fence, &cb->cb);
1374 }
1375}
1376
1377/**
1378 * amdgpu_vm_free_mapping - free a mapping
1379 *
1380 * @adev: amdgpu_device pointer
1381 * @vm: requested vm
1382 * @mapping: mapping to be freed
1383 * @fence: fence of the unmap operation
1384 *
1385 * Free a mapping and make sure we decrease the PRT usage count if applicable.
1386 */
1387static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
1388 struct amdgpu_vm *vm,
1389 struct amdgpu_bo_va_mapping *mapping,
1390 struct dma_fence *fence)
1391{
1392 if (mapping->flags & AMDGPU_PTE_PRT_FLAG(adev))
1393 amdgpu_vm_add_prt_cb(adev, fence);
1394 kfree(mapping);
1395}
1396
1397/**
1398 * amdgpu_vm_prt_fini - finish all prt mappings
1399 *
1400 * @adev: amdgpu_device pointer
1401 * @vm: requested vm
1402 *
1403 * Register a cleanup callback to disable PRT support after VM dies.
1404 */
1405static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1406{
1407 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
1408 struct dma_resv_iter cursor;
1409 struct dma_fence *fence;
1410
1411 dma_resv_for_each_fence(&cursor, resv, DMA_RESV_USAGE_BOOKKEEP, fence) {
1412 /* Add a callback for each fence in the reservation object */
1413 amdgpu_vm_prt_get(adev);
1414 amdgpu_vm_add_prt_cb(adev, fence);
1415 }
1416}
1417
1418/**
1419 * amdgpu_vm_clear_freed - clear freed BOs in the PT
1420 *
1421 * @adev: amdgpu_device pointer
1422 * @vm: requested vm
1423 * @fence: optional resulting fence (unchanged if no work needed to be done
1424 * or if an error occurred)
1425 *
1426 * Make sure all freed BOs are cleared in the PT.
1427 * PTs have to be reserved and mutex must be locked!
1428 *
1429 * Returns:
1430 * 0 for success.
1431 *
1432 */
1433int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
1434 struct amdgpu_vm *vm,
1435 struct dma_fence **fence)
1436{
1437 struct amdgpu_bo_va_mapping *mapping;
1438 struct dma_fence *f = NULL;
1439 struct amdgpu_sync sync;
1440 int r;
1441
1442
1443 /*
1444 * Implicitly sync to command submissions in the same VM before
1445 * unmapping.
1446 */
1447 amdgpu_sync_create(&sync);
1448 r = amdgpu_sync_resv(adev, &sync, vm->root.bo->tbo.base.resv,
1449 AMDGPU_SYNC_EQ_OWNER, vm);
1450 if (r)
1451 goto error_free;
1452
1453 while (!list_empty(&vm->freed)) {
1454 mapping = list_first_entry(&vm->freed,
1455 struct amdgpu_bo_va_mapping, list);
1456 list_del(&mapping->list);
1457
1458 r = amdgpu_vm_update_range(adev, vm, false, false, true, false,
1459 &sync, mapping->start, mapping->last,
1460 0, 0, 0, NULL, NULL, &f);
1461 amdgpu_vm_free_mapping(adev, vm, mapping, f);
1462 if (r) {
1463 dma_fence_put(f);
1464 goto error_free;
1465 }
1466 }
1467
1468 if (fence && f) {
1469 dma_fence_put(*fence);
1470 *fence = f;
1471 } else {
1472 dma_fence_put(f);
1473 }
1474
1475error_free:
1476 amdgpu_sync_free(&sync);
1477 return r;
1478
1479}
1480
1481/**
1482 * amdgpu_vm_handle_moved - handle moved BOs in the PT
1483 *
1484 * @adev: amdgpu_device pointer
1485 * @vm: requested vm
1486 * @ticket: optional reservation ticket used to reserve the VM
1487 *
1488 * Make sure all BOs which are moved are updated in the PTs.
1489 *
1490 * Returns:
1491 * 0 for success.
1492 *
1493 * PTs have to be reserved!
1494 */
1495int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
1496 struct amdgpu_vm *vm,
1497 struct ww_acquire_ctx *ticket)
1498{
1499 struct amdgpu_bo_va *bo_va;
1500 struct dma_resv *resv;
1501 bool clear, unlock;
1502 int r;
1503
1504 spin_lock(&vm->status_lock);
1505 while (!list_empty(&vm->moved)) {
1506 bo_va = list_first_entry(&vm->moved, struct amdgpu_bo_va,
1507 base.vm_status);
1508 spin_unlock(&vm->status_lock);
1509
1510 /* Per VM BOs never need to bo cleared in the page tables */
1511 r = amdgpu_vm_bo_update(adev, bo_va, false);
1512 if (r)
1513 return r;
1514 spin_lock(&vm->status_lock);
1515 }
1516
1517 while (!list_empty(&vm->invalidated)) {
1518 bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va,
1519 base.vm_status);
1520 resv = bo_va->base.bo->tbo.base.resv;
1521 spin_unlock(&vm->status_lock);
1522
1523 /* Try to reserve the BO to avoid clearing its ptes */
1524 if (!adev->debug_vm && dma_resv_trylock(resv)) {
1525 clear = false;
1526 unlock = true;
1527 /* The caller is already holding the reservation lock */
1528 } else if (ticket && dma_resv_locking_ctx(resv) == ticket) {
1529 clear = false;
1530 unlock = false;
1531 /* Somebody else is using the BO right now */
1532 } else {
1533 clear = true;
1534 unlock = false;
1535 }
1536
1537 r = amdgpu_vm_bo_update(adev, bo_va, clear);
1538
1539 if (unlock)
1540 dma_resv_unlock(resv);
1541 if (r)
1542 return r;
1543
1544 /* Remember evicted DMABuf imports in compute VMs for later
1545 * validation
1546 */
1547 if (vm->is_compute_context &&
1548 bo_va->base.bo->tbo.base.import_attach &&
1549 (!bo_va->base.bo->tbo.resource ||
1550 bo_va->base.bo->tbo.resource->mem_type == TTM_PL_SYSTEM))
1551 amdgpu_vm_bo_evicted_user(&bo_va->base);
1552
1553 spin_lock(&vm->status_lock);
1554 }
1555 spin_unlock(&vm->status_lock);
1556
1557 return 0;
1558}
1559
1560/**
1561 * amdgpu_vm_flush_compute_tlb - Flush TLB on compute VM
1562 *
1563 * @adev: amdgpu_device pointer
1564 * @vm: requested vm
1565 * @flush_type: flush type
1566 * @xcc_mask: mask of XCCs that belong to the compute partition in need of a TLB flush.
1567 *
1568 * Flush TLB if needed for a compute VM.
1569 *
1570 * Returns:
1571 * 0 for success.
1572 */
1573int amdgpu_vm_flush_compute_tlb(struct amdgpu_device *adev,
1574 struct amdgpu_vm *vm,
1575 uint32_t flush_type,
1576 uint32_t xcc_mask)
1577{
1578 uint64_t tlb_seq = amdgpu_vm_tlb_seq(vm);
1579 bool all_hub = false;
1580 int xcc = 0, r = 0;
1581
1582 WARN_ON_ONCE(!vm->is_compute_context);
1583
1584 /*
1585 * It can be that we race and lose here, but that is extremely unlikely
1586 * and the worst thing which could happen is that we flush the changes
1587 * into the TLB once more which is harmless.
1588 */
1589 if (atomic64_xchg(&vm->kfd_last_flushed_seq, tlb_seq) == tlb_seq)
1590 return 0;
1591
1592 if (adev->family == AMDGPU_FAMILY_AI ||
1593 adev->family == AMDGPU_FAMILY_RV)
1594 all_hub = true;
1595
1596 for_each_inst(xcc, xcc_mask) {
1597 r = amdgpu_gmc_flush_gpu_tlb_pasid(adev, vm->pasid, flush_type,
1598 all_hub, xcc);
1599 if (r)
1600 break;
1601 }
1602 return r;
1603}
1604
1605/**
1606 * amdgpu_vm_bo_add - add a bo to a specific vm
1607 *
1608 * @adev: amdgpu_device pointer
1609 * @vm: requested vm
1610 * @bo: amdgpu buffer object
1611 *
1612 * Add @bo into the requested vm.
1613 * Add @bo to the list of bos associated with the vm
1614 *
1615 * Returns:
1616 * Newly added bo_va or NULL for failure
1617 *
1618 * Object has to be reserved!
1619 */
1620struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
1621 struct amdgpu_vm *vm,
1622 struct amdgpu_bo *bo)
1623{
1624 struct amdgpu_bo_va *bo_va;
1625
1626 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
1627 if (bo_va == NULL) {
1628 return NULL;
1629 }
1630 amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
1631
1632 bo_va->ref_count = 1;
1633 bo_va->last_pt_update = dma_fence_get_stub();
1634 INIT_LIST_HEAD(&bo_va->valids);
1635 INIT_LIST_HEAD(&bo_va->invalids);
1636
1637 if (!bo)
1638 return bo_va;
1639
1640 dma_resv_assert_held(bo->tbo.base.resv);
1641 if (amdgpu_dmabuf_is_xgmi_accessible(adev, bo)) {
1642 bo_va->is_xgmi = true;
1643 /* Power up XGMI if it can be potentially used */
1644 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MAX_VEGA20);
1645 }
1646
1647 return bo_va;
1648}
1649
1650
1651/**
1652 * amdgpu_vm_bo_insert_map - insert a new mapping
1653 *
1654 * @adev: amdgpu_device pointer
1655 * @bo_va: bo_va to store the address
1656 * @mapping: the mapping to insert
1657 *
1658 * Insert a new mapping into all structures.
1659 */
1660static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
1661 struct amdgpu_bo_va *bo_va,
1662 struct amdgpu_bo_va_mapping *mapping)
1663{
1664 struct amdgpu_vm *vm = bo_va->base.vm;
1665 struct amdgpu_bo *bo = bo_va->base.bo;
1666
1667 mapping->bo_va = bo_va;
1668 list_add(&mapping->list, &bo_va->invalids);
1669 amdgpu_vm_it_insert(mapping, &vm->va);
1670
1671 if (mapping->flags & AMDGPU_PTE_PRT_FLAG(adev))
1672 amdgpu_vm_prt_get(adev);
1673
1674 if (amdgpu_vm_is_bo_always_valid(vm, bo) && !bo_va->base.moved)
1675 amdgpu_vm_bo_moved(&bo_va->base);
1676
1677 trace_amdgpu_vm_bo_map(bo_va, mapping);
1678}
1679
1680/* Validate operation parameters to prevent potential abuse */
1681static int amdgpu_vm_verify_parameters(struct amdgpu_device *adev,
1682 struct amdgpu_bo *bo,
1683 uint64_t saddr,
1684 uint64_t offset,
1685 uint64_t size)
1686{
1687 uint64_t tmp, lpfn;
1688
1689 if (saddr & AMDGPU_GPU_PAGE_MASK
1690 || offset & AMDGPU_GPU_PAGE_MASK
1691 || size & AMDGPU_GPU_PAGE_MASK)
1692 return -EINVAL;
1693
1694 if (check_add_overflow(saddr, size, &tmp)
1695 || check_add_overflow(offset, size, &tmp)
1696 || size == 0 /* which also leads to end < begin */)
1697 return -EINVAL;
1698
1699 /* make sure object fit at this offset */
1700 if (bo && offset + size > amdgpu_bo_size(bo))
1701 return -EINVAL;
1702
1703 /* Ensure last pfn not exceed max_pfn */
1704 lpfn = (saddr + size - 1) >> AMDGPU_GPU_PAGE_SHIFT;
1705 if (lpfn >= adev->vm_manager.max_pfn)
1706 return -EINVAL;
1707
1708 return 0;
1709}
1710
1711/**
1712 * amdgpu_vm_bo_map - map bo inside a vm
1713 *
1714 * @adev: amdgpu_device pointer
1715 * @bo_va: bo_va to store the address
1716 * @saddr: where to map the BO
1717 * @offset: requested offset in the BO
1718 * @size: BO size in bytes
1719 * @flags: attributes of pages (read/write/valid/etc.)
1720 *
1721 * Add a mapping of the BO at the specefied addr into the VM.
1722 *
1723 * Returns:
1724 * 0 for success, error for failure.
1725 *
1726 * Object has to be reserved and unreserved outside!
1727 */
1728int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1729 struct amdgpu_bo_va *bo_va,
1730 uint64_t saddr, uint64_t offset,
1731 uint64_t size, uint64_t flags)
1732{
1733 struct amdgpu_bo_va_mapping *mapping, *tmp;
1734 struct amdgpu_bo *bo = bo_va->base.bo;
1735 struct amdgpu_vm *vm = bo_va->base.vm;
1736 uint64_t eaddr;
1737 int r;
1738
1739 r = amdgpu_vm_verify_parameters(adev, bo, saddr, offset, size);
1740 if (r)
1741 return r;
1742
1743 saddr /= AMDGPU_GPU_PAGE_SIZE;
1744 eaddr = saddr + (size - 1) / AMDGPU_GPU_PAGE_SIZE;
1745
1746 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
1747 if (tmp) {
1748 /* bo and tmp overlap, invalid addr */
1749 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
1750 "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr,
1751 tmp->start, tmp->last + 1);
1752 return -EINVAL;
1753 }
1754
1755 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1756 if (!mapping)
1757 return -ENOMEM;
1758
1759 mapping->start = saddr;
1760 mapping->last = eaddr;
1761 mapping->offset = offset;
1762 mapping->flags = flags;
1763
1764 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
1765
1766 return 0;
1767}
1768
1769/**
1770 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
1771 *
1772 * @adev: amdgpu_device pointer
1773 * @bo_va: bo_va to store the address
1774 * @saddr: where to map the BO
1775 * @offset: requested offset in the BO
1776 * @size: BO size in bytes
1777 * @flags: attributes of pages (read/write/valid/etc.)
1778 *
1779 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
1780 * mappings as we do so.
1781 *
1782 * Returns:
1783 * 0 for success, error for failure.
1784 *
1785 * Object has to be reserved and unreserved outside!
1786 */
1787int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
1788 struct amdgpu_bo_va *bo_va,
1789 uint64_t saddr, uint64_t offset,
1790 uint64_t size, uint64_t flags)
1791{
1792 struct amdgpu_bo_va_mapping *mapping;
1793 struct amdgpu_bo *bo = bo_va->base.bo;
1794 uint64_t eaddr;
1795 int r;
1796
1797 r = amdgpu_vm_verify_parameters(adev, bo, saddr, offset, size);
1798 if (r)
1799 return r;
1800
1801 /* Allocate all the needed memory */
1802 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1803 if (!mapping)
1804 return -ENOMEM;
1805
1806 r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size);
1807 if (r) {
1808 kfree(mapping);
1809 return r;
1810 }
1811
1812 saddr /= AMDGPU_GPU_PAGE_SIZE;
1813 eaddr = saddr + (size - 1) / AMDGPU_GPU_PAGE_SIZE;
1814
1815 mapping->start = saddr;
1816 mapping->last = eaddr;
1817 mapping->offset = offset;
1818 mapping->flags = flags;
1819
1820 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
1821
1822 return 0;
1823}
1824
1825/**
1826 * amdgpu_vm_bo_unmap - remove bo mapping from vm
1827 *
1828 * @adev: amdgpu_device pointer
1829 * @bo_va: bo_va to remove the address from
1830 * @saddr: where to the BO is mapped
1831 *
1832 * Remove a mapping of the BO at the specefied addr from the VM.
1833 *
1834 * Returns:
1835 * 0 for success, error for failure.
1836 *
1837 * Object has to be reserved and unreserved outside!
1838 */
1839int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
1840 struct amdgpu_bo_va *bo_va,
1841 uint64_t saddr)
1842{
1843 struct amdgpu_bo_va_mapping *mapping;
1844 struct amdgpu_vm *vm = bo_va->base.vm;
1845 bool valid = true;
1846
1847 saddr /= AMDGPU_GPU_PAGE_SIZE;
1848
1849 list_for_each_entry(mapping, &bo_va->valids, list) {
1850 if (mapping->start == saddr)
1851 break;
1852 }
1853
1854 if (&mapping->list == &bo_va->valids) {
1855 valid = false;
1856
1857 list_for_each_entry(mapping, &bo_va->invalids, list) {
1858 if (mapping->start == saddr)
1859 break;
1860 }
1861
1862 if (&mapping->list == &bo_va->invalids)
1863 return -ENOENT;
1864 }
1865
1866 list_del(&mapping->list);
1867 amdgpu_vm_it_remove(mapping, &vm->va);
1868 mapping->bo_va = NULL;
1869 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1870
1871 if (valid)
1872 list_add(&mapping->list, &vm->freed);
1873 else
1874 amdgpu_vm_free_mapping(adev, vm, mapping,
1875 bo_va->last_pt_update);
1876
1877 return 0;
1878}
1879
1880/**
1881 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
1882 *
1883 * @adev: amdgpu_device pointer
1884 * @vm: VM structure to use
1885 * @saddr: start of the range
1886 * @size: size of the range
1887 *
1888 * Remove all mappings in a range, split them as appropriate.
1889 *
1890 * Returns:
1891 * 0 for success, error for failure.
1892 */
1893int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
1894 struct amdgpu_vm *vm,
1895 uint64_t saddr, uint64_t size)
1896{
1897 struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
1898 LIST_HEAD(removed);
1899 uint64_t eaddr;
1900 int r;
1901
1902 r = amdgpu_vm_verify_parameters(adev, NULL, saddr, 0, size);
1903 if (r)
1904 return r;
1905
1906 saddr /= AMDGPU_GPU_PAGE_SIZE;
1907 eaddr = saddr + (size - 1) / AMDGPU_GPU_PAGE_SIZE;
1908
1909 /* Allocate all the needed memory */
1910 before = kzalloc(sizeof(*before), GFP_KERNEL);
1911 if (!before)
1912 return -ENOMEM;
1913 INIT_LIST_HEAD(&before->list);
1914
1915 after = kzalloc(sizeof(*after), GFP_KERNEL);
1916 if (!after) {
1917 kfree(before);
1918 return -ENOMEM;
1919 }
1920 INIT_LIST_HEAD(&after->list);
1921
1922 /* Now gather all removed mappings */
1923 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
1924 while (tmp) {
1925 /* Remember mapping split at the start */
1926 if (tmp->start < saddr) {
1927 before->start = tmp->start;
1928 before->last = saddr - 1;
1929 before->offset = tmp->offset;
1930 before->flags = tmp->flags;
1931 before->bo_va = tmp->bo_va;
1932 list_add(&before->list, &tmp->bo_va->invalids);
1933 }
1934
1935 /* Remember mapping split at the end */
1936 if (tmp->last > eaddr) {
1937 after->start = eaddr + 1;
1938 after->last = tmp->last;
1939 after->offset = tmp->offset;
1940 after->offset += (after->start - tmp->start) << PAGE_SHIFT;
1941 after->flags = tmp->flags;
1942 after->bo_va = tmp->bo_va;
1943 list_add(&after->list, &tmp->bo_va->invalids);
1944 }
1945
1946 list_del(&tmp->list);
1947 list_add(&tmp->list, &removed);
1948
1949 tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
1950 }
1951
1952 /* And free them up */
1953 list_for_each_entry_safe(tmp, next, &removed, list) {
1954 amdgpu_vm_it_remove(tmp, &vm->va);
1955 list_del(&tmp->list);
1956
1957 if (tmp->start < saddr)
1958 tmp->start = saddr;
1959 if (tmp->last > eaddr)
1960 tmp->last = eaddr;
1961
1962 tmp->bo_va = NULL;
1963 list_add(&tmp->list, &vm->freed);
1964 trace_amdgpu_vm_bo_unmap(NULL, tmp);
1965 }
1966
1967 /* Insert partial mapping before the range */
1968 if (!list_empty(&before->list)) {
1969 struct amdgpu_bo *bo = before->bo_va->base.bo;
1970
1971 amdgpu_vm_it_insert(before, &vm->va);
1972 if (before->flags & AMDGPU_PTE_PRT_FLAG(adev))
1973 amdgpu_vm_prt_get(adev);
1974
1975 if (amdgpu_vm_is_bo_always_valid(vm, bo) &&
1976 !before->bo_va->base.moved)
1977 amdgpu_vm_bo_moved(&before->bo_va->base);
1978 } else {
1979 kfree(before);
1980 }
1981
1982 /* Insert partial mapping after the range */
1983 if (!list_empty(&after->list)) {
1984 struct amdgpu_bo *bo = after->bo_va->base.bo;
1985
1986 amdgpu_vm_it_insert(after, &vm->va);
1987 if (after->flags & AMDGPU_PTE_PRT_FLAG(adev))
1988 amdgpu_vm_prt_get(adev);
1989
1990 if (amdgpu_vm_is_bo_always_valid(vm, bo) &&
1991 !after->bo_va->base.moved)
1992 amdgpu_vm_bo_moved(&after->bo_va->base);
1993 } else {
1994 kfree(after);
1995 }
1996
1997 return 0;
1998}
1999
2000/**
2001 * amdgpu_vm_bo_lookup_mapping - find mapping by address
2002 *
2003 * @vm: the requested VM
2004 * @addr: the address
2005 *
2006 * Find a mapping by it's address.
2007 *
2008 * Returns:
2009 * The amdgpu_bo_va_mapping matching for addr or NULL
2010 *
2011 */
2012struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
2013 uint64_t addr)
2014{
2015 return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
2016}
2017
2018/**
2019 * amdgpu_vm_bo_trace_cs - trace all reserved mappings
2020 *
2021 * @vm: the requested vm
2022 * @ticket: CS ticket
2023 *
2024 * Trace all mappings of BOs reserved during a command submission.
2025 */
2026void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket)
2027{
2028 struct amdgpu_bo_va_mapping *mapping;
2029
2030 if (!trace_amdgpu_vm_bo_cs_enabled())
2031 return;
2032
2033 for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping;
2034 mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) {
2035 if (mapping->bo_va && mapping->bo_va->base.bo) {
2036 struct amdgpu_bo *bo;
2037
2038 bo = mapping->bo_va->base.bo;
2039 if (dma_resv_locking_ctx(bo->tbo.base.resv) !=
2040 ticket)
2041 continue;
2042 }
2043
2044 trace_amdgpu_vm_bo_cs(mapping);
2045 }
2046}
2047
2048/**
2049 * amdgpu_vm_bo_del - remove a bo from a specific vm
2050 *
2051 * @adev: amdgpu_device pointer
2052 * @bo_va: requested bo_va
2053 *
2054 * Remove @bo_va->bo from the requested vm.
2055 *
2056 * Object have to be reserved!
2057 */
2058void amdgpu_vm_bo_del(struct amdgpu_device *adev,
2059 struct amdgpu_bo_va *bo_va)
2060{
2061 struct amdgpu_bo_va_mapping *mapping, *next;
2062 struct amdgpu_bo *bo = bo_va->base.bo;
2063 struct amdgpu_vm *vm = bo_va->base.vm;
2064 struct amdgpu_vm_bo_base **base;
2065
2066 dma_resv_assert_held(vm->root.bo->tbo.base.resv);
2067
2068 if (bo) {
2069 dma_resv_assert_held(bo->tbo.base.resv);
2070 if (amdgpu_vm_is_bo_always_valid(vm, bo))
2071 ttm_bo_set_bulk_move(&bo->tbo, NULL);
2072
2073 for (base = &bo_va->base.bo->vm_bo; *base;
2074 base = &(*base)->next) {
2075 if (*base != &bo_va->base)
2076 continue;
2077
2078 *base = bo_va->base.next;
2079 break;
2080 }
2081 }
2082
2083 spin_lock(&vm->status_lock);
2084 list_del(&bo_va->base.vm_status);
2085 spin_unlock(&vm->status_lock);
2086
2087 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
2088 list_del(&mapping->list);
2089 amdgpu_vm_it_remove(mapping, &vm->va);
2090 mapping->bo_va = NULL;
2091 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2092 list_add(&mapping->list, &vm->freed);
2093 }
2094 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
2095 list_del(&mapping->list);
2096 amdgpu_vm_it_remove(mapping, &vm->va);
2097 amdgpu_vm_free_mapping(adev, vm, mapping,
2098 bo_va->last_pt_update);
2099 }
2100
2101 dma_fence_put(bo_va->last_pt_update);
2102
2103 if (bo && bo_va->is_xgmi)
2104 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MIN);
2105
2106 kfree(bo_va);
2107}
2108
2109/**
2110 * amdgpu_vm_evictable - check if we can evict a VM
2111 *
2112 * @bo: A page table of the VM.
2113 *
2114 * Check if it is possible to evict a VM.
2115 */
2116bool amdgpu_vm_evictable(struct amdgpu_bo *bo)
2117{
2118 struct amdgpu_vm_bo_base *bo_base = bo->vm_bo;
2119
2120 /* Page tables of a destroyed VM can go away immediately */
2121 if (!bo_base || !bo_base->vm)
2122 return true;
2123
2124 /* Don't evict VM page tables while they are busy */
2125 if (!dma_resv_test_signaled(bo->tbo.base.resv, DMA_RESV_USAGE_BOOKKEEP))
2126 return false;
2127
2128 /* Try to block ongoing updates */
2129 if (!amdgpu_vm_eviction_trylock(bo_base->vm))
2130 return false;
2131
2132 /* Don't evict VM page tables while they are updated */
2133 if (!dma_fence_is_signaled(bo_base->vm->last_unlocked)) {
2134 amdgpu_vm_eviction_unlock(bo_base->vm);
2135 return false;
2136 }
2137
2138 bo_base->vm->evicting = true;
2139 amdgpu_vm_eviction_unlock(bo_base->vm);
2140 return true;
2141}
2142
2143/**
2144 * amdgpu_vm_bo_invalidate - mark the bo as invalid
2145 *
2146 * @adev: amdgpu_device pointer
2147 * @bo: amdgpu buffer object
2148 * @evicted: is the BO evicted
2149 *
2150 * Mark @bo as invalid.
2151 */
2152void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2153 struct amdgpu_bo *bo, bool evicted)
2154{
2155 struct amdgpu_vm_bo_base *bo_base;
2156
2157 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
2158 struct amdgpu_vm *vm = bo_base->vm;
2159
2160 if (evicted && amdgpu_vm_is_bo_always_valid(vm, bo)) {
2161 amdgpu_vm_bo_evicted(bo_base);
2162 continue;
2163 }
2164
2165 if (bo_base->moved)
2166 continue;
2167 bo_base->moved = true;
2168
2169 if (bo->tbo.type == ttm_bo_type_kernel)
2170 amdgpu_vm_bo_relocated(bo_base);
2171 else if (amdgpu_vm_is_bo_always_valid(vm, bo))
2172 amdgpu_vm_bo_moved(bo_base);
2173 else
2174 amdgpu_vm_bo_invalidated(bo_base);
2175 }
2176}
2177
2178/**
2179 * amdgpu_vm_get_block_size - calculate VM page table size as power of two
2180 *
2181 * @vm_size: VM size
2182 *
2183 * Returns:
2184 * VM page table as power of two
2185 */
2186static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
2187{
2188 /* Total bits covered by PD + PTs */
2189 unsigned bits = ilog2(vm_size) + 18;
2190
2191 /* Make sure the PD is 4K in size up to 8GB address space.
2192 Above that split equal between PD and PTs */
2193 if (vm_size <= 8)
2194 return (bits - 9);
2195 else
2196 return ((bits + 3) / 2);
2197}
2198
2199/**
2200 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
2201 *
2202 * @adev: amdgpu_device pointer
2203 * @min_vm_size: the minimum vm size in GB if it's set auto
2204 * @fragment_size_default: Default PTE fragment size
2205 * @max_level: max VMPT level
2206 * @max_bits: max address space size in bits
2207 *
2208 */
2209void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
2210 uint32_t fragment_size_default, unsigned max_level,
2211 unsigned max_bits)
2212{
2213 unsigned int max_size = 1 << (max_bits - 30);
2214 unsigned int vm_size;
2215 uint64_t tmp;
2216
2217 /* adjust vm size first */
2218 if (amdgpu_vm_size != -1) {
2219 vm_size = amdgpu_vm_size;
2220 if (vm_size > max_size) {
2221 dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
2222 amdgpu_vm_size, max_size);
2223 vm_size = max_size;
2224 }
2225 } else {
2226 struct sysinfo si;
2227 unsigned int phys_ram_gb;
2228
2229 /* Optimal VM size depends on the amount of physical
2230 * RAM available. Underlying requirements and
2231 * assumptions:
2232 *
2233 * - Need to map system memory and VRAM from all GPUs
2234 * - VRAM from other GPUs not known here
2235 * - Assume VRAM <= system memory
2236 * - On GFX8 and older, VM space can be segmented for
2237 * different MTYPEs
2238 * - Need to allow room for fragmentation, guard pages etc.
2239 *
2240 * This adds up to a rough guess of system memory x3.
2241 * Round up to power of two to maximize the available
2242 * VM size with the given page table size.
2243 */
2244 si_meminfo(&si);
2245 phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit +
2246 (1 << 30) - 1) >> 30;
2247 vm_size = roundup_pow_of_two(
2248 clamp(phys_ram_gb * 3, min_vm_size, max_size));
2249 }
2250
2251 adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
2252
2253 tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
2254 if (amdgpu_vm_block_size != -1)
2255 tmp >>= amdgpu_vm_block_size - 9;
2256 tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
2257 adev->vm_manager.num_level = min_t(unsigned int, max_level, tmp);
2258 switch (adev->vm_manager.num_level) {
2259 case 3:
2260 adev->vm_manager.root_level = AMDGPU_VM_PDB2;
2261 break;
2262 case 2:
2263 adev->vm_manager.root_level = AMDGPU_VM_PDB1;
2264 break;
2265 case 1:
2266 adev->vm_manager.root_level = AMDGPU_VM_PDB0;
2267 break;
2268 default:
2269 dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
2270 }
2271 /* block size depends on vm size and hw setup*/
2272 if (amdgpu_vm_block_size != -1)
2273 adev->vm_manager.block_size =
2274 min((unsigned)amdgpu_vm_block_size, max_bits
2275 - AMDGPU_GPU_PAGE_SHIFT
2276 - 9 * adev->vm_manager.num_level);
2277 else if (adev->vm_manager.num_level > 1)
2278 adev->vm_manager.block_size = 9;
2279 else
2280 adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
2281
2282 if (amdgpu_vm_fragment_size == -1)
2283 adev->vm_manager.fragment_size = fragment_size_default;
2284 else
2285 adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
2286
2287 DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
2288 vm_size, adev->vm_manager.num_level + 1,
2289 adev->vm_manager.block_size,
2290 adev->vm_manager.fragment_size);
2291}
2292
2293/**
2294 * amdgpu_vm_wait_idle - wait for the VM to become idle
2295 *
2296 * @vm: VM object to wait for
2297 * @timeout: timeout to wait for VM to become idle
2298 */
2299long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
2300{
2301 timeout = dma_resv_wait_timeout(vm->root.bo->tbo.base.resv,
2302 DMA_RESV_USAGE_BOOKKEEP,
2303 true, timeout);
2304 if (timeout <= 0)
2305 return timeout;
2306
2307 return dma_fence_wait_timeout(vm->last_unlocked, true, timeout);
2308}
2309
2310static void amdgpu_vm_destroy_task_info(struct kref *kref)
2311{
2312 struct amdgpu_task_info *ti = container_of(kref, struct amdgpu_task_info, refcount);
2313
2314 kfree(ti);
2315}
2316
2317static inline struct amdgpu_vm *
2318amdgpu_vm_get_vm_from_pasid(struct amdgpu_device *adev, u32 pasid)
2319{
2320 struct amdgpu_vm *vm;
2321 unsigned long flags;
2322
2323 xa_lock_irqsave(&adev->vm_manager.pasids, flags);
2324 vm = xa_load(&adev->vm_manager.pasids, pasid);
2325 xa_unlock_irqrestore(&adev->vm_manager.pasids, flags);
2326
2327 return vm;
2328}
2329
2330/**
2331 * amdgpu_vm_put_task_info - reference down the vm task_info ptr
2332 *
2333 * @task_info: task_info struct under discussion.
2334 *
2335 * frees the vm task_info ptr at the last put
2336 */
2337void amdgpu_vm_put_task_info(struct amdgpu_task_info *task_info)
2338{
2339 kref_put(&task_info->refcount, amdgpu_vm_destroy_task_info);
2340}
2341
2342/**
2343 * amdgpu_vm_get_task_info_vm - Extracts task info for a vm.
2344 *
2345 * @vm: VM to get info from
2346 *
2347 * Returns the reference counted task_info structure, which must be
2348 * referenced down with amdgpu_vm_put_task_info.
2349 */
2350struct amdgpu_task_info *
2351amdgpu_vm_get_task_info_vm(struct amdgpu_vm *vm)
2352{
2353 struct amdgpu_task_info *ti = NULL;
2354
2355 if (vm) {
2356 ti = vm->task_info;
2357 kref_get(&vm->task_info->refcount);
2358 }
2359
2360 return ti;
2361}
2362
2363/**
2364 * amdgpu_vm_get_task_info_pasid - Extracts task info for a PASID.
2365 *
2366 * @adev: drm device pointer
2367 * @pasid: PASID identifier for VM
2368 *
2369 * Returns the reference counted task_info structure, which must be
2370 * referenced down with amdgpu_vm_put_task_info.
2371 */
2372struct amdgpu_task_info *
2373amdgpu_vm_get_task_info_pasid(struct amdgpu_device *adev, u32 pasid)
2374{
2375 return amdgpu_vm_get_task_info_vm(
2376 amdgpu_vm_get_vm_from_pasid(adev, pasid));
2377}
2378
2379static int amdgpu_vm_create_task_info(struct amdgpu_vm *vm)
2380{
2381 vm->task_info = kzalloc(sizeof(struct amdgpu_task_info), GFP_KERNEL);
2382 if (!vm->task_info)
2383 return -ENOMEM;
2384
2385 kref_init(&vm->task_info->refcount);
2386 return 0;
2387}
2388
2389/**
2390 * amdgpu_vm_set_task_info - Sets VMs task info.
2391 *
2392 * @vm: vm for which to set the info
2393 */
2394void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
2395{
2396 if (!vm->task_info)
2397 return;
2398
2399 if (vm->task_info->pid == current->pid)
2400 return;
2401
2402 vm->task_info->pid = current->pid;
2403 get_task_comm(vm->task_info->task_name, current);
2404
2405 if (current->group_leader->mm != current->mm)
2406 return;
2407
2408 vm->task_info->tgid = current->group_leader->pid;
2409 get_task_comm(vm->task_info->process_name, current->group_leader);
2410}
2411
2412/**
2413 * amdgpu_vm_init - initialize a vm instance
2414 *
2415 * @adev: amdgpu_device pointer
2416 * @vm: requested vm
2417 * @xcp_id: GPU partition selection id
2418 *
2419 * Init @vm fields.
2420 *
2421 * Returns:
2422 * 0 for success, error for failure.
2423 */
2424int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
2425 int32_t xcp_id)
2426{
2427 struct amdgpu_bo *root_bo;
2428 struct amdgpu_bo_vm *root;
2429 int r, i;
2430
2431 vm->va = RB_ROOT_CACHED;
2432 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2433 vm->reserved_vmid[i] = NULL;
2434 INIT_LIST_HEAD(&vm->evicted);
2435 INIT_LIST_HEAD(&vm->evicted_user);
2436 INIT_LIST_HEAD(&vm->relocated);
2437 INIT_LIST_HEAD(&vm->moved);
2438 INIT_LIST_HEAD(&vm->idle);
2439 INIT_LIST_HEAD(&vm->invalidated);
2440 spin_lock_init(&vm->status_lock);
2441 INIT_LIST_HEAD(&vm->freed);
2442 INIT_LIST_HEAD(&vm->done);
2443 INIT_LIST_HEAD(&vm->pt_freed);
2444 INIT_WORK(&vm->pt_free_work, amdgpu_vm_pt_free_work);
2445 INIT_KFIFO(vm->faults);
2446
2447 r = amdgpu_vm_init_entities(adev, vm);
2448 if (r)
2449 return r;
2450
2451 ttm_lru_bulk_move_init(&vm->lru_bulk_move);
2452
2453 vm->is_compute_context = false;
2454
2455 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2456 AMDGPU_VM_USE_CPU_FOR_GFX);
2457
2458 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2459 vm->use_cpu_for_update ? "CPU" : "SDMA");
2460 WARN_ONCE((vm->use_cpu_for_update &&
2461 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2462 "CPU update of VM recommended only for large BAR system\n");
2463
2464 if (vm->use_cpu_for_update)
2465 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2466 else
2467 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2468
2469 vm->last_update = dma_fence_get_stub();
2470 vm->last_unlocked = dma_fence_get_stub();
2471 vm->last_tlb_flush = dma_fence_get_stub();
2472 vm->generation = amdgpu_vm_generation(adev, NULL);
2473
2474 mutex_init(&vm->eviction_lock);
2475 vm->evicting = false;
2476 vm->tlb_fence_context = dma_fence_context_alloc(1);
2477
2478 r = amdgpu_vm_pt_create(adev, vm, adev->vm_manager.root_level,
2479 false, &root, xcp_id);
2480 if (r)
2481 goto error_free_delayed;
2482
2483 root_bo = amdgpu_bo_ref(&root->bo);
2484 r = amdgpu_bo_reserve(root_bo, true);
2485 if (r) {
2486 amdgpu_bo_unref(&root_bo);
2487 goto error_free_delayed;
2488 }
2489
2490 amdgpu_vm_bo_base_init(&vm->root, vm, root_bo);
2491 r = dma_resv_reserve_fences(root_bo->tbo.base.resv, 1);
2492 if (r)
2493 goto error_free_root;
2494
2495 r = amdgpu_vm_pt_clear(adev, vm, root, false);
2496 if (r)
2497 goto error_free_root;
2498
2499 r = amdgpu_vm_create_task_info(vm);
2500 if (r)
2501 DRM_DEBUG("Failed to create task info for VM\n");
2502
2503 amdgpu_bo_unreserve(vm->root.bo);
2504 amdgpu_bo_unref(&root_bo);
2505
2506 return 0;
2507
2508error_free_root:
2509 amdgpu_vm_pt_free_root(adev, vm);
2510 amdgpu_bo_unreserve(vm->root.bo);
2511 amdgpu_bo_unref(&root_bo);
2512
2513error_free_delayed:
2514 dma_fence_put(vm->last_tlb_flush);
2515 dma_fence_put(vm->last_unlocked);
2516 ttm_lru_bulk_move_fini(&adev->mman.bdev, &vm->lru_bulk_move);
2517 amdgpu_vm_fini_entities(vm);
2518
2519 return r;
2520}
2521
2522/**
2523 * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
2524 *
2525 * @adev: amdgpu_device pointer
2526 * @vm: requested vm
2527 *
2528 * This only works on GFX VMs that don't have any BOs added and no
2529 * page tables allocated yet.
2530 *
2531 * Changes the following VM parameters:
2532 * - use_cpu_for_update
2533 * - pte_supports_ats
2534 *
2535 * Reinitializes the page directory to reflect the changed ATS
2536 * setting.
2537 *
2538 * Returns:
2539 * 0 for success, -errno for errors.
2540 */
2541int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2542{
2543 int r;
2544
2545 r = amdgpu_bo_reserve(vm->root.bo, true);
2546 if (r)
2547 return r;
2548
2549 /* Update VM state */
2550 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2551 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
2552 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2553 vm->use_cpu_for_update ? "CPU" : "SDMA");
2554 WARN_ONCE((vm->use_cpu_for_update &&
2555 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2556 "CPU update of VM recommended only for large BAR system\n");
2557
2558 if (vm->use_cpu_for_update) {
2559 /* Sync with last SDMA update/clear before switching to CPU */
2560 r = amdgpu_bo_sync_wait(vm->root.bo,
2561 AMDGPU_FENCE_OWNER_UNDEFINED, true);
2562 if (r)
2563 goto unreserve_bo;
2564
2565 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2566 r = amdgpu_vm_pt_map_tables(adev, vm);
2567 if (r)
2568 goto unreserve_bo;
2569
2570 } else {
2571 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2572 }
2573
2574 dma_fence_put(vm->last_update);
2575 vm->last_update = dma_fence_get_stub();
2576 vm->is_compute_context = true;
2577
2578unreserve_bo:
2579 amdgpu_bo_unreserve(vm->root.bo);
2580 return r;
2581}
2582
2583/**
2584 * amdgpu_vm_release_compute - release a compute vm
2585 * @adev: amdgpu_device pointer
2586 * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute
2587 *
2588 * This is a correspondant of amdgpu_vm_make_compute. It decouples compute
2589 * pasid from vm. Compute should stop use of vm after this call.
2590 */
2591void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2592{
2593 amdgpu_vm_set_pasid(adev, vm, 0);
2594 vm->is_compute_context = false;
2595}
2596
2597/**
2598 * amdgpu_vm_fini - tear down a vm instance
2599 *
2600 * @adev: amdgpu_device pointer
2601 * @vm: requested vm
2602 *
2603 * Tear down @vm.
2604 * Unbind the VM and remove all bos from the vm bo list
2605 */
2606void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2607{
2608 struct amdgpu_bo_va_mapping *mapping, *tmp;
2609 bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
2610 struct amdgpu_bo *root;
2611 unsigned long flags;
2612 int i;
2613
2614 amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
2615
2616 flush_work(&vm->pt_free_work);
2617
2618 root = amdgpu_bo_ref(vm->root.bo);
2619 amdgpu_bo_reserve(root, true);
2620 amdgpu_vm_put_task_info(vm->task_info);
2621 amdgpu_vm_set_pasid(adev, vm, 0);
2622 dma_fence_wait(vm->last_unlocked, false);
2623 dma_fence_put(vm->last_unlocked);
2624 dma_fence_wait(vm->last_tlb_flush, false);
2625 /* Make sure that all fence callbacks have completed */
2626 spin_lock_irqsave(vm->last_tlb_flush->lock, flags);
2627 spin_unlock_irqrestore(vm->last_tlb_flush->lock, flags);
2628 dma_fence_put(vm->last_tlb_flush);
2629
2630 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
2631 if (mapping->flags & AMDGPU_PTE_PRT_FLAG(adev) && prt_fini_needed) {
2632 amdgpu_vm_prt_fini(adev, vm);
2633 prt_fini_needed = false;
2634 }
2635
2636 list_del(&mapping->list);
2637 amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
2638 }
2639
2640 amdgpu_vm_pt_free_root(adev, vm);
2641 amdgpu_bo_unreserve(root);
2642 amdgpu_bo_unref(&root);
2643 WARN_ON(vm->root.bo);
2644
2645 amdgpu_vm_fini_entities(vm);
2646
2647 if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
2648 dev_err(adev->dev, "still active bo inside vm\n");
2649 }
2650 rbtree_postorder_for_each_entry_safe(mapping, tmp,
2651 &vm->va.rb_root, rb) {
2652 /* Don't remove the mapping here, we don't want to trigger a
2653 * rebalance and the tree is about to be destroyed anyway.
2654 */
2655 list_del(&mapping->list);
2656 kfree(mapping);
2657 }
2658
2659 dma_fence_put(vm->last_update);
2660
2661 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) {
2662 if (vm->reserved_vmid[i]) {
2663 amdgpu_vmid_free_reserved(adev, i);
2664 vm->reserved_vmid[i] = false;
2665 }
2666 }
2667
2668 ttm_lru_bulk_move_fini(&adev->mman.bdev, &vm->lru_bulk_move);
2669}
2670
2671/**
2672 * amdgpu_vm_manager_init - init the VM manager
2673 *
2674 * @adev: amdgpu_device pointer
2675 *
2676 * Initialize the VM manager structures
2677 */
2678void amdgpu_vm_manager_init(struct amdgpu_device *adev)
2679{
2680 unsigned i;
2681
2682 /* Concurrent flushes are only possible starting with Vega10 and
2683 * are broken on Navi10 and Navi14.
2684 */
2685 adev->vm_manager.concurrent_flush = !(adev->asic_type < CHIP_VEGA10 ||
2686 adev->asic_type == CHIP_NAVI10 ||
2687 adev->asic_type == CHIP_NAVI14);
2688 amdgpu_vmid_mgr_init(adev);
2689
2690 adev->vm_manager.fence_context =
2691 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2692 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
2693 adev->vm_manager.seqno[i] = 0;
2694
2695 spin_lock_init(&adev->vm_manager.prt_lock);
2696 atomic_set(&adev->vm_manager.num_prt_users, 0);
2697
2698 /* If not overridden by the user, by default, only in large BAR systems
2699 * Compute VM tables will be updated by CPU
2700 */
2701#ifdef CONFIG_X86_64
2702 if (amdgpu_vm_update_mode == -1) {
2703 /* For asic with VF MMIO access protection
2704 * avoid using CPU for VM table updates
2705 */
2706 if (amdgpu_gmc_vram_full_visible(&adev->gmc) &&
2707 !amdgpu_sriov_vf_mmio_access_protection(adev))
2708 adev->vm_manager.vm_update_mode =
2709 AMDGPU_VM_USE_CPU_FOR_COMPUTE;
2710 else
2711 adev->vm_manager.vm_update_mode = 0;
2712 } else
2713 adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
2714#else
2715 adev->vm_manager.vm_update_mode = 0;
2716#endif
2717
2718 xa_init_flags(&adev->vm_manager.pasids, XA_FLAGS_LOCK_IRQ);
2719}
2720
2721/**
2722 * amdgpu_vm_manager_fini - cleanup VM manager
2723 *
2724 * @adev: amdgpu_device pointer
2725 *
2726 * Cleanup the VM manager and free resources.
2727 */
2728void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
2729{
2730 WARN_ON(!xa_empty(&adev->vm_manager.pasids));
2731 xa_destroy(&adev->vm_manager.pasids);
2732
2733 amdgpu_vmid_mgr_fini(adev);
2734}
2735
2736/**
2737 * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs.
2738 *
2739 * @dev: drm device pointer
2740 * @data: drm_amdgpu_vm
2741 * @filp: drm file pointer
2742 *
2743 * Returns:
2744 * 0 for success, -errno for errors.
2745 */
2746int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
2747{
2748 union drm_amdgpu_vm *args = data;
2749 struct amdgpu_device *adev = drm_to_adev(dev);
2750 struct amdgpu_fpriv *fpriv = filp->driver_priv;
2751
2752 /* No valid flags defined yet */
2753 if (args->in.flags)
2754 return -EINVAL;
2755
2756 switch (args->in.op) {
2757 case AMDGPU_VM_OP_RESERVE_VMID:
2758 /* We only have requirement to reserve vmid from gfxhub */
2759 if (!fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)]) {
2760 amdgpu_vmid_alloc_reserved(adev, AMDGPU_GFXHUB(0));
2761 fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)] = true;
2762 }
2763
2764 break;
2765 case AMDGPU_VM_OP_UNRESERVE_VMID:
2766 if (fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)]) {
2767 amdgpu_vmid_free_reserved(adev, AMDGPU_GFXHUB(0));
2768 fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)] = false;
2769 }
2770 break;
2771 default:
2772 return -EINVAL;
2773 }
2774
2775 return 0;
2776}
2777
2778/**
2779 * amdgpu_vm_handle_fault - graceful handling of VM faults.
2780 * @adev: amdgpu device pointer
2781 * @pasid: PASID of the VM
2782 * @ts: Timestamp of the fault
2783 * @vmid: VMID, only used for GFX 9.4.3.
2784 * @node_id: Node_id received in IH cookie. Only applicable for
2785 * GFX 9.4.3.
2786 * @addr: Address of the fault
2787 * @write_fault: true is write fault, false is read fault
2788 *
2789 * Try to gracefully handle a VM fault. Return true if the fault was handled and
2790 * shouldn't be reported any more.
2791 */
2792bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
2793 u32 vmid, u32 node_id, uint64_t addr, uint64_t ts,
2794 bool write_fault)
2795{
2796 bool is_compute_context = false;
2797 struct amdgpu_bo *root;
2798 unsigned long irqflags;
2799 uint64_t value, flags;
2800 struct amdgpu_vm *vm;
2801 int r;
2802
2803 xa_lock_irqsave(&adev->vm_manager.pasids, irqflags);
2804 vm = xa_load(&adev->vm_manager.pasids, pasid);
2805 if (vm) {
2806 root = amdgpu_bo_ref(vm->root.bo);
2807 is_compute_context = vm->is_compute_context;
2808 } else {
2809 root = NULL;
2810 }
2811 xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags);
2812
2813 if (!root)
2814 return false;
2815
2816 addr /= AMDGPU_GPU_PAGE_SIZE;
2817
2818 if (is_compute_context && !svm_range_restore_pages(adev, pasid, vmid,
2819 node_id, addr, ts, write_fault)) {
2820 amdgpu_bo_unref(&root);
2821 return true;
2822 }
2823
2824 r = amdgpu_bo_reserve(root, true);
2825 if (r)
2826 goto error_unref;
2827
2828 /* Double check that the VM still exists */
2829 xa_lock_irqsave(&adev->vm_manager.pasids, irqflags);
2830 vm = xa_load(&adev->vm_manager.pasids, pasid);
2831 if (vm && vm->root.bo != root)
2832 vm = NULL;
2833 xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags);
2834 if (!vm)
2835 goto error_unlock;
2836
2837 flags = AMDGPU_PTE_VALID | AMDGPU_PTE_SNOOPED |
2838 AMDGPU_PTE_SYSTEM;
2839
2840 if (is_compute_context) {
2841 /* Intentionally setting invalid PTE flag
2842 * combination to force a no-retry-fault
2843 */
2844 flags = AMDGPU_VM_NORETRY_FLAGS;
2845 value = 0;
2846 } else if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) {
2847 /* Redirect the access to the dummy page */
2848 value = adev->dummy_page_addr;
2849 flags |= AMDGPU_PTE_EXECUTABLE | AMDGPU_PTE_READABLE |
2850 AMDGPU_PTE_WRITEABLE;
2851
2852 } else {
2853 /* Let the hw retry silently on the PTE */
2854 value = 0;
2855 }
2856
2857 r = dma_resv_reserve_fences(root->tbo.base.resv, 1);
2858 if (r) {
2859 pr_debug("failed %d to reserve fence slot\n", r);
2860 goto error_unlock;
2861 }
2862
2863 r = amdgpu_vm_update_range(adev, vm, true, false, false, false,
2864 NULL, addr, addr, flags, value, 0, NULL, NULL, NULL);
2865 if (r)
2866 goto error_unlock;
2867
2868 r = amdgpu_vm_update_pdes(adev, vm, true);
2869
2870error_unlock:
2871 amdgpu_bo_unreserve(root);
2872 if (r < 0)
2873 DRM_ERROR("Can't handle page fault (%d)\n", r);
2874
2875error_unref:
2876 amdgpu_bo_unref(&root);
2877
2878 return false;
2879}
2880
2881#if defined(CONFIG_DEBUG_FS)
2882/**
2883 * amdgpu_debugfs_vm_bo_info - print BO info for the VM
2884 *
2885 * @vm: Requested VM for printing BO info
2886 * @m: debugfs file
2887 *
2888 * Print BO information in debugfs file for the VM
2889 */
2890void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m)
2891{
2892 struct amdgpu_bo_va *bo_va, *tmp;
2893 u64 total_idle = 0;
2894 u64 total_evicted = 0;
2895 u64 total_relocated = 0;
2896 u64 total_moved = 0;
2897 u64 total_invalidated = 0;
2898 u64 total_done = 0;
2899 unsigned int total_idle_objs = 0;
2900 unsigned int total_evicted_objs = 0;
2901 unsigned int total_relocated_objs = 0;
2902 unsigned int total_moved_objs = 0;
2903 unsigned int total_invalidated_objs = 0;
2904 unsigned int total_done_objs = 0;
2905 unsigned int id = 0;
2906
2907 spin_lock(&vm->status_lock);
2908 seq_puts(m, "\tIdle BOs:\n");
2909 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
2910 if (!bo_va->base.bo)
2911 continue;
2912 total_idle += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2913 }
2914 total_idle_objs = id;
2915 id = 0;
2916
2917 seq_puts(m, "\tEvicted BOs:\n");
2918 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
2919 if (!bo_va->base.bo)
2920 continue;
2921 total_evicted += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2922 }
2923 total_evicted_objs = id;
2924 id = 0;
2925
2926 seq_puts(m, "\tRelocated BOs:\n");
2927 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
2928 if (!bo_va->base.bo)
2929 continue;
2930 total_relocated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2931 }
2932 total_relocated_objs = id;
2933 id = 0;
2934
2935 seq_puts(m, "\tMoved BOs:\n");
2936 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
2937 if (!bo_va->base.bo)
2938 continue;
2939 total_moved += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2940 }
2941 total_moved_objs = id;
2942 id = 0;
2943
2944 seq_puts(m, "\tInvalidated BOs:\n");
2945 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
2946 if (!bo_va->base.bo)
2947 continue;
2948 total_invalidated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2949 }
2950 total_invalidated_objs = id;
2951 id = 0;
2952
2953 seq_puts(m, "\tDone BOs:\n");
2954 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
2955 if (!bo_va->base.bo)
2956 continue;
2957 total_done += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2958 }
2959 spin_unlock(&vm->status_lock);
2960 total_done_objs = id;
2961
2962 seq_printf(m, "\tTotal idle size: %12lld\tobjs:\t%d\n", total_idle,
2963 total_idle_objs);
2964 seq_printf(m, "\tTotal evicted size: %12lld\tobjs:\t%d\n", total_evicted,
2965 total_evicted_objs);
2966 seq_printf(m, "\tTotal relocated size: %12lld\tobjs:\t%d\n", total_relocated,
2967 total_relocated_objs);
2968 seq_printf(m, "\tTotal moved size: %12lld\tobjs:\t%d\n", total_moved,
2969 total_moved_objs);
2970 seq_printf(m, "\tTotal invalidated size: %12lld\tobjs:\t%d\n", total_invalidated,
2971 total_invalidated_objs);
2972 seq_printf(m, "\tTotal done size: %12lld\tobjs:\t%d\n", total_done,
2973 total_done_objs);
2974}
2975#endif
2976
2977/**
2978 * amdgpu_vm_update_fault_cache - update cached fault into.
2979 * @adev: amdgpu device pointer
2980 * @pasid: PASID of the VM
2981 * @addr: Address of the fault
2982 * @status: GPUVM fault status register
2983 * @vmhub: which vmhub got the fault
2984 *
2985 * Cache the fault info for later use by userspace in debugging.
2986 */
2987void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev,
2988 unsigned int pasid,
2989 uint64_t addr,
2990 uint32_t status,
2991 unsigned int vmhub)
2992{
2993 struct amdgpu_vm *vm;
2994 unsigned long flags;
2995
2996 xa_lock_irqsave(&adev->vm_manager.pasids, flags);
2997
2998 vm = xa_load(&adev->vm_manager.pasids, pasid);
2999 /* Don't update the fault cache if status is 0. In the multiple
3000 * fault case, subsequent faults will return a 0 status which is
3001 * useless for userspace and replaces the useful fault status, so
3002 * only update if status is non-0.
3003 */
3004 if (vm && status) {
3005 vm->fault_info.addr = addr;
3006 vm->fault_info.status = status;
3007 /*
3008 * Update the fault information globally for later usage
3009 * when vm could be stale or freed.
3010 */
3011 adev->vm_manager.fault_info.addr = addr;
3012 adev->vm_manager.fault_info.vmhub = vmhub;
3013 adev->vm_manager.fault_info.status = status;
3014
3015 if (AMDGPU_IS_GFXHUB(vmhub)) {
3016 vm->fault_info.vmhub = AMDGPU_VMHUB_TYPE_GFX;
3017 vm->fault_info.vmhub |=
3018 (vmhub - AMDGPU_GFXHUB_START) << AMDGPU_VMHUB_IDX_SHIFT;
3019 } else if (AMDGPU_IS_MMHUB0(vmhub)) {
3020 vm->fault_info.vmhub = AMDGPU_VMHUB_TYPE_MM0;
3021 vm->fault_info.vmhub |=
3022 (vmhub - AMDGPU_MMHUB0_START) << AMDGPU_VMHUB_IDX_SHIFT;
3023 } else if (AMDGPU_IS_MMHUB1(vmhub)) {
3024 vm->fault_info.vmhub = AMDGPU_VMHUB_TYPE_MM1;
3025 vm->fault_info.vmhub |=
3026 (vmhub - AMDGPU_MMHUB1_START) << AMDGPU_VMHUB_IDX_SHIFT;
3027 } else {
3028 WARN_ONCE(1, "Invalid vmhub %u\n", vmhub);
3029 }
3030 }
3031 xa_unlock_irqrestore(&adev->vm_manager.pasids, flags);
3032}
3033
3034/**
3035 * amdgpu_vm_is_bo_always_valid - check if the BO is VM always valid
3036 *
3037 * @vm: VM to test against.
3038 * @bo: BO to be tested.
3039 *
3040 * Returns true if the BO shares the dma_resv object with the root PD and is
3041 * always guaranteed to be valid inside the VM.
3042 */
3043bool amdgpu_vm_is_bo_always_valid(struct amdgpu_vm *vm, struct amdgpu_bo *bo)
3044{
3045 return bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv;
3046}