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1// SPDX-License-Identifier: GPL-2.0+
2//
3// MXS GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
4// Copyright 2008 Juergen Beisert, kernel@pengutronix.de
5//
6// Based on code from Freescale,
7// Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
8
9#include <linux/err.h>
10#include <linux/init.h>
11#include <linux/interrupt.h>
12#include <linux/io.h>
13#include <linux/irq.h>
14#include <linux/irqdomain.h>
15#include <linux/of.h>
16#include <linux/of_address.h>
17#include <linux/of_device.h>
18#include <linux/platform_device.h>
19#include <linux/slab.h>
20#include <linux/gpio/driver.h>
21#include <linux/module.h>
22
23#define MXS_SET 0x4
24#define MXS_CLR 0x8
25
26#define PINCTRL_DOUT(p) ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
27#define PINCTRL_DIN(p) ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
28#define PINCTRL_DOE(p) ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
29#define PINCTRL_PIN2IRQ(p) ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
30#define PINCTRL_IRQEN(p) ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
31#define PINCTRL_IRQLEV(p) ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
32#define PINCTRL_IRQPOL(p) ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
33#define PINCTRL_IRQSTAT(p) ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
34
35#define GPIO_INT_FALL_EDGE 0x0
36#define GPIO_INT_LOW_LEV 0x1
37#define GPIO_INT_RISE_EDGE 0x2
38#define GPIO_INT_HIGH_LEV 0x3
39#define GPIO_INT_LEV_MASK (1 << 0)
40#define GPIO_INT_POL_MASK (1 << 1)
41
42enum mxs_gpio_id {
43 IMX23_GPIO,
44 IMX28_GPIO,
45};
46
47struct mxs_gpio_port {
48 void __iomem *base;
49 int id;
50 int irq;
51 struct irq_domain *domain;
52 struct gpio_chip gc;
53 struct device *dev;
54 enum mxs_gpio_id devid;
55 u32 both_edges;
56};
57
58static inline int is_imx23_gpio(struct mxs_gpio_port *port)
59{
60 return port->devid == IMX23_GPIO;
61}
62
63/* Note: This driver assumes 32 GPIOs are handled in one register */
64
65static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
66{
67 u32 val;
68 u32 pin_mask = 1 << d->hwirq;
69 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
70 struct irq_chip_type *ct = irq_data_get_chip_type(d);
71 struct mxs_gpio_port *port = gc->private;
72 void __iomem *pin_addr;
73 int edge;
74
75 if (!(ct->type & type))
76 if (irq_setup_alt_chip(d, type))
77 return -EINVAL;
78
79 port->both_edges &= ~pin_mask;
80 switch (type) {
81 case IRQ_TYPE_EDGE_BOTH:
82 val = readl(port->base + PINCTRL_DIN(port)) & pin_mask;
83 if (val)
84 edge = GPIO_INT_FALL_EDGE;
85 else
86 edge = GPIO_INT_RISE_EDGE;
87 port->both_edges |= pin_mask;
88 break;
89 case IRQ_TYPE_EDGE_RISING:
90 edge = GPIO_INT_RISE_EDGE;
91 break;
92 case IRQ_TYPE_EDGE_FALLING:
93 edge = GPIO_INT_FALL_EDGE;
94 break;
95 case IRQ_TYPE_LEVEL_LOW:
96 edge = GPIO_INT_LOW_LEV;
97 break;
98 case IRQ_TYPE_LEVEL_HIGH:
99 edge = GPIO_INT_HIGH_LEV;
100 break;
101 default:
102 return -EINVAL;
103 }
104
105 /* set level or edge */
106 pin_addr = port->base + PINCTRL_IRQLEV(port);
107 if (edge & GPIO_INT_LEV_MASK) {
108 writel(pin_mask, pin_addr + MXS_SET);
109 writel(pin_mask, port->base + PINCTRL_IRQEN(port) + MXS_SET);
110 } else {
111 writel(pin_mask, pin_addr + MXS_CLR);
112 writel(pin_mask, port->base + PINCTRL_PIN2IRQ(port) + MXS_SET);
113 }
114
115 /* set polarity */
116 pin_addr = port->base + PINCTRL_IRQPOL(port);
117 if (edge & GPIO_INT_POL_MASK)
118 writel(pin_mask, pin_addr + MXS_SET);
119 else
120 writel(pin_mask, pin_addr + MXS_CLR);
121
122 writel(pin_mask, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
123
124 return 0;
125}
126
127static void mxs_flip_edge(struct mxs_gpio_port *port, u32 gpio)
128{
129 u32 bit, val, edge;
130 void __iomem *pin_addr;
131
132 bit = 1 << gpio;
133
134 pin_addr = port->base + PINCTRL_IRQPOL(port);
135 val = readl(pin_addr);
136 edge = val & bit;
137
138 if (edge)
139 writel(bit, pin_addr + MXS_CLR);
140 else
141 writel(bit, pin_addr + MXS_SET);
142}
143
144/* MXS has one interrupt *per* gpio port */
145static void mxs_gpio_irq_handler(struct irq_desc *desc)
146{
147 u32 irq_stat;
148 struct mxs_gpio_port *port = irq_desc_get_handler_data(desc);
149
150 desc->irq_data.chip->irq_ack(&desc->irq_data);
151
152 irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
153 readl(port->base + PINCTRL_IRQEN(port));
154
155 while (irq_stat != 0) {
156 int irqoffset = fls(irq_stat) - 1;
157 if (port->both_edges & (1 << irqoffset))
158 mxs_flip_edge(port, irqoffset);
159
160 generic_handle_domain_irq(port->domain, irqoffset);
161 irq_stat &= ~(1 << irqoffset);
162 }
163}
164
165/*
166 * Set interrupt number "irq" in the GPIO as a wake-up source.
167 * While system is running, all registered GPIO interrupts need to have
168 * wake-up enabled. When system is suspended, only selected GPIO interrupts
169 * need to have wake-up enabled.
170 * @param irq interrupt source number
171 * @param enable enable as wake-up if equal to non-zero
172 * @return This function returns 0 on success.
173 */
174static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
175{
176 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
177 struct mxs_gpio_port *port = gc->private;
178
179 if (enable)
180 enable_irq_wake(port->irq);
181 else
182 disable_irq_wake(port->irq);
183
184 return 0;
185}
186
187static int mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
188{
189 struct irq_chip_generic *gc;
190 struct irq_chip_type *ct;
191 int rv;
192
193 gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxs", 2, irq_base,
194 port->base, handle_level_irq);
195 if (!gc)
196 return -ENOMEM;
197
198 gc->private = port;
199
200 ct = &gc->chip_types[0];
201 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
202 ct->chip.irq_ack = irq_gc_ack_set_bit;
203 ct->chip.irq_mask = irq_gc_mask_disable_reg;
204 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
205 ct->chip.irq_set_type = mxs_gpio_set_irq_type;
206 ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
207 ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
208 ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
209 ct->regs.enable = PINCTRL_PIN2IRQ(port) + MXS_SET;
210 ct->regs.disable = PINCTRL_PIN2IRQ(port) + MXS_CLR;
211
212 ct = &gc->chip_types[1];
213 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
214 ct->chip.irq_ack = irq_gc_ack_set_bit;
215 ct->chip.irq_mask = irq_gc_mask_disable_reg;
216 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
217 ct->chip.irq_set_type = mxs_gpio_set_irq_type;
218 ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
219 ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
220 ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
221 ct->regs.enable = PINCTRL_IRQEN(port) + MXS_SET;
222 ct->regs.disable = PINCTRL_IRQEN(port) + MXS_CLR;
223 ct->handler = handle_level_irq;
224
225 rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
226 IRQ_GC_INIT_NESTED_LOCK,
227 IRQ_NOREQUEST, 0);
228
229 return rv;
230}
231
232static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
233{
234 struct mxs_gpio_port *port = gpiochip_get_data(gc);
235
236 return irq_find_mapping(port->domain, offset);
237}
238
239static int mxs_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
240{
241 struct mxs_gpio_port *port = gpiochip_get_data(gc);
242 u32 mask = 1 << offset;
243 u32 dir;
244
245 dir = readl(port->base + PINCTRL_DOE(port));
246 if (dir & mask)
247 return GPIO_LINE_DIRECTION_OUT;
248
249 return GPIO_LINE_DIRECTION_IN;
250}
251
252static const struct of_device_id mxs_gpio_dt_ids[] = {
253 { .compatible = "fsl,imx23-gpio", .data = (void *) IMX23_GPIO, },
254 { .compatible = "fsl,imx28-gpio", .data = (void *) IMX28_GPIO, },
255 { /* sentinel */ }
256};
257MODULE_DEVICE_TABLE(of, mxs_gpio_dt_ids);
258
259static int mxs_gpio_probe(struct platform_device *pdev)
260{
261 struct device_node *np = pdev->dev.of_node;
262 struct device_node *parent;
263 static void __iomem *base;
264 struct mxs_gpio_port *port;
265 int irq_base;
266 int err;
267
268 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
269 if (!port)
270 return -ENOMEM;
271
272 port->id = of_alias_get_id(np, "gpio");
273 if (port->id < 0)
274 return port->id;
275 port->devid = (enum mxs_gpio_id)of_device_get_match_data(&pdev->dev);
276 port->dev = &pdev->dev;
277 port->irq = platform_get_irq(pdev, 0);
278 if (port->irq < 0)
279 return port->irq;
280
281 /*
282 * map memory region only once, as all the gpio ports
283 * share the same one
284 */
285 if (!base) {
286 parent = of_get_parent(np);
287 base = of_iomap(parent, 0);
288 of_node_put(parent);
289 if (!base)
290 return -EADDRNOTAVAIL;
291 }
292 port->base = base;
293
294 /* initially disable the interrupts */
295 writel(0, port->base + PINCTRL_PIN2IRQ(port));
296 writel(0, port->base + PINCTRL_IRQEN(port));
297
298 /* clear address has to be used to clear IRQSTAT bits */
299 writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
300
301 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
302 if (irq_base < 0) {
303 err = irq_base;
304 goto out_iounmap;
305 }
306
307 port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
308 &irq_domain_simple_ops, NULL);
309 if (!port->domain) {
310 err = -ENODEV;
311 goto out_iounmap;
312 }
313
314 /* gpio-mxs can be a generic irq chip */
315 err = mxs_gpio_init_gc(port, irq_base);
316 if (err < 0)
317 goto out_irqdomain_remove;
318
319 /* setup one handler for each entry */
320 irq_set_chained_handler_and_data(port->irq, mxs_gpio_irq_handler,
321 port);
322
323 err = bgpio_init(&port->gc, &pdev->dev, 4,
324 port->base + PINCTRL_DIN(port),
325 port->base + PINCTRL_DOUT(port) + MXS_SET,
326 port->base + PINCTRL_DOUT(port) + MXS_CLR,
327 port->base + PINCTRL_DOE(port), NULL, 0);
328 if (err)
329 goto out_irqdomain_remove;
330
331 port->gc.to_irq = mxs_gpio_to_irq;
332 port->gc.get_direction = mxs_gpio_get_direction;
333 port->gc.base = port->id * 32;
334
335 err = gpiochip_add_data(&port->gc, port);
336 if (err)
337 goto out_irqdomain_remove;
338
339 return 0;
340
341out_irqdomain_remove:
342 irq_domain_remove(port->domain);
343out_iounmap:
344 iounmap(port->base);
345 return err;
346}
347
348static struct platform_driver mxs_gpio_driver = {
349 .driver = {
350 .name = "gpio-mxs",
351 .of_match_table = mxs_gpio_dt_ids,
352 .suppress_bind_attrs = true,
353 },
354 .probe = mxs_gpio_probe,
355};
356
357static int __init mxs_gpio_init(void)
358{
359 return platform_driver_register(&mxs_gpio_driver);
360}
361postcore_initcall(mxs_gpio_init);
362
363MODULE_AUTHOR("Freescale Semiconductor, "
364 "Daniel Mack <danielncaiaq.de>, "
365 "Juergen Beisert <kernel@pengutronix.de>");
366MODULE_DESCRIPTION("Freescale MXS GPIO");
367MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0+
2//
3// MXS GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
4// Copyright 2008 Juergen Beisert, kernel@pengutronix.de
5//
6// Based on code from Freescale,
7// Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
8
9#include <linux/err.h>
10#include <linux/init.h>
11#include <linux/interrupt.h>
12#include <linux/io.h>
13#include <linux/irq.h>
14#include <linux/irqdomain.h>
15#include <linux/of.h>
16#include <linux/of_address.h>
17#include <linux/platform_device.h>
18#include <linux/slab.h>
19#include <linux/gpio/driver.h>
20#include <linux/module.h>
21
22#define MXS_SET 0x4
23#define MXS_CLR 0x8
24
25#define PINCTRL_DOUT(p) ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
26#define PINCTRL_DIN(p) ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
27#define PINCTRL_DOE(p) ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
28#define PINCTRL_PIN2IRQ(p) ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
29#define PINCTRL_IRQEN(p) ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
30#define PINCTRL_IRQLEV(p) ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
31#define PINCTRL_IRQPOL(p) ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
32#define PINCTRL_IRQSTAT(p) ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
33
34#define GPIO_INT_FALL_EDGE 0x0
35#define GPIO_INT_LOW_LEV 0x1
36#define GPIO_INT_RISE_EDGE 0x2
37#define GPIO_INT_HIGH_LEV 0x3
38#define GPIO_INT_LEV_MASK (1 << 0)
39#define GPIO_INT_POL_MASK (1 << 1)
40
41enum mxs_gpio_id {
42 IMX23_GPIO,
43 IMX28_GPIO,
44};
45
46struct mxs_gpio_port {
47 void __iomem *base;
48 int id;
49 int irq;
50 struct irq_domain *domain;
51 struct gpio_chip gc;
52 struct device *dev;
53 enum mxs_gpio_id devid;
54 u32 both_edges;
55};
56
57static inline int is_imx23_gpio(struct mxs_gpio_port *port)
58{
59 return port->devid == IMX23_GPIO;
60}
61
62/* Note: This driver assumes 32 GPIOs are handled in one register */
63
64static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
65{
66 u32 val;
67 u32 pin_mask = 1 << d->hwirq;
68 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
69 struct irq_chip_type *ct = irq_data_get_chip_type(d);
70 struct mxs_gpio_port *port = gc->private;
71 void __iomem *pin_addr;
72 int edge;
73
74 if (!(ct->type & type))
75 if (irq_setup_alt_chip(d, type))
76 return -EINVAL;
77
78 port->both_edges &= ~pin_mask;
79 switch (type) {
80 case IRQ_TYPE_EDGE_BOTH:
81 val = readl(port->base + PINCTRL_DIN(port)) & pin_mask;
82 if (val)
83 edge = GPIO_INT_FALL_EDGE;
84 else
85 edge = GPIO_INT_RISE_EDGE;
86 port->both_edges |= pin_mask;
87 break;
88 case IRQ_TYPE_EDGE_RISING:
89 edge = GPIO_INT_RISE_EDGE;
90 break;
91 case IRQ_TYPE_EDGE_FALLING:
92 edge = GPIO_INT_FALL_EDGE;
93 break;
94 case IRQ_TYPE_LEVEL_LOW:
95 edge = GPIO_INT_LOW_LEV;
96 break;
97 case IRQ_TYPE_LEVEL_HIGH:
98 edge = GPIO_INT_HIGH_LEV;
99 break;
100 default:
101 return -EINVAL;
102 }
103
104 /* set level or edge */
105 pin_addr = port->base + PINCTRL_IRQLEV(port);
106 if (edge & GPIO_INT_LEV_MASK) {
107 writel(pin_mask, pin_addr + MXS_SET);
108 writel(pin_mask, port->base + PINCTRL_IRQEN(port) + MXS_SET);
109 } else {
110 writel(pin_mask, pin_addr + MXS_CLR);
111 writel(pin_mask, port->base + PINCTRL_PIN2IRQ(port) + MXS_SET);
112 }
113
114 /* set polarity */
115 pin_addr = port->base + PINCTRL_IRQPOL(port);
116 if (edge & GPIO_INT_POL_MASK)
117 writel(pin_mask, pin_addr + MXS_SET);
118 else
119 writel(pin_mask, pin_addr + MXS_CLR);
120
121 writel(pin_mask, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
122
123 return 0;
124}
125
126static void mxs_flip_edge(struct mxs_gpio_port *port, u32 gpio)
127{
128 u32 bit, val, edge;
129 void __iomem *pin_addr;
130
131 bit = 1 << gpio;
132
133 pin_addr = port->base + PINCTRL_IRQPOL(port);
134 val = readl(pin_addr);
135 edge = val & bit;
136
137 if (edge)
138 writel(bit, pin_addr + MXS_CLR);
139 else
140 writel(bit, pin_addr + MXS_SET);
141}
142
143/* MXS has one interrupt *per* gpio port */
144static void mxs_gpio_irq_handler(struct irq_desc *desc)
145{
146 u32 irq_stat;
147 struct mxs_gpio_port *port = irq_desc_get_handler_data(desc);
148
149 desc->irq_data.chip->irq_ack(&desc->irq_data);
150
151 irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
152 readl(port->base + PINCTRL_IRQEN(port));
153
154 while (irq_stat != 0) {
155 int irqoffset = fls(irq_stat) - 1;
156 if (port->both_edges & (1 << irqoffset))
157 mxs_flip_edge(port, irqoffset);
158
159 generic_handle_domain_irq(port->domain, irqoffset);
160 irq_stat &= ~(1 << irqoffset);
161 }
162}
163
164/*
165 * Set interrupt number "irq" in the GPIO as a wake-up source.
166 * While system is running, all registered GPIO interrupts need to have
167 * wake-up enabled. When system is suspended, only selected GPIO interrupts
168 * need to have wake-up enabled.
169 * @param irq interrupt source number
170 * @param enable enable as wake-up if equal to non-zero
171 * @return This function returns 0 on success.
172 */
173static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
174{
175 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
176 struct mxs_gpio_port *port = gc->private;
177
178 if (enable)
179 enable_irq_wake(port->irq);
180 else
181 disable_irq_wake(port->irq);
182
183 return 0;
184}
185
186static int mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
187{
188 struct irq_chip_generic *gc;
189 struct irq_chip_type *ct;
190 int rv;
191
192 gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxs", 2, irq_base,
193 port->base, handle_level_irq);
194 if (!gc)
195 return -ENOMEM;
196
197 gc->private = port;
198
199 ct = &gc->chip_types[0];
200 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
201 ct->chip.irq_ack = irq_gc_ack_set_bit;
202 ct->chip.irq_mask = irq_gc_mask_disable_reg;
203 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
204 ct->chip.irq_set_type = mxs_gpio_set_irq_type;
205 ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
206 ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
207 ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
208 ct->regs.enable = PINCTRL_PIN2IRQ(port) + MXS_SET;
209 ct->regs.disable = PINCTRL_PIN2IRQ(port) + MXS_CLR;
210
211 ct = &gc->chip_types[1];
212 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
213 ct->chip.irq_ack = irq_gc_ack_set_bit;
214 ct->chip.irq_mask = irq_gc_mask_disable_reg;
215 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
216 ct->chip.irq_set_type = mxs_gpio_set_irq_type;
217 ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
218 ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
219 ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
220 ct->regs.enable = PINCTRL_IRQEN(port) + MXS_SET;
221 ct->regs.disable = PINCTRL_IRQEN(port) + MXS_CLR;
222 ct->handler = handle_level_irq;
223
224 rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
225 IRQ_GC_INIT_NESTED_LOCK,
226 IRQ_NOREQUEST, 0);
227
228 return rv;
229}
230
231static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
232{
233 struct mxs_gpio_port *port = gpiochip_get_data(gc);
234
235 return irq_find_mapping(port->domain, offset);
236}
237
238static int mxs_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
239{
240 struct mxs_gpio_port *port = gpiochip_get_data(gc);
241 u32 mask = 1 << offset;
242 u32 dir;
243
244 dir = readl(port->base + PINCTRL_DOE(port));
245 if (dir & mask)
246 return GPIO_LINE_DIRECTION_OUT;
247
248 return GPIO_LINE_DIRECTION_IN;
249}
250
251static const struct of_device_id mxs_gpio_dt_ids[] = {
252 { .compatible = "fsl,imx23-gpio", .data = (void *) IMX23_GPIO, },
253 { .compatible = "fsl,imx28-gpio", .data = (void *) IMX28_GPIO, },
254 { /* sentinel */ }
255};
256MODULE_DEVICE_TABLE(of, mxs_gpio_dt_ids);
257
258static int mxs_gpio_probe(struct platform_device *pdev)
259{
260 struct device_node *np = pdev->dev.of_node;
261 struct device_node *parent;
262 static void __iomem *base;
263 struct mxs_gpio_port *port;
264 int irq_base;
265 int err;
266
267 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
268 if (!port)
269 return -ENOMEM;
270
271 port->id = of_alias_get_id(np, "gpio");
272 if (port->id < 0)
273 return port->id;
274 port->devid = (uintptr_t)of_device_get_match_data(&pdev->dev);
275 port->dev = &pdev->dev;
276 port->irq = platform_get_irq(pdev, 0);
277 if (port->irq < 0)
278 return port->irq;
279
280 /*
281 * map memory region only once, as all the gpio ports
282 * share the same one
283 */
284 if (!base) {
285 parent = of_get_parent(np);
286 base = of_iomap(parent, 0);
287 of_node_put(parent);
288 if (!base)
289 return -EADDRNOTAVAIL;
290 }
291 port->base = base;
292
293 /* initially disable the interrupts */
294 writel(0, port->base + PINCTRL_PIN2IRQ(port));
295 writel(0, port->base + PINCTRL_IRQEN(port));
296
297 /* clear address has to be used to clear IRQSTAT bits */
298 writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
299
300 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
301 if (irq_base < 0) {
302 err = irq_base;
303 goto out_iounmap;
304 }
305
306 port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
307 &irq_domain_simple_ops, NULL);
308 if (!port->domain) {
309 err = -ENODEV;
310 goto out_iounmap;
311 }
312
313 /* gpio-mxs can be a generic irq chip */
314 err = mxs_gpio_init_gc(port, irq_base);
315 if (err < 0)
316 goto out_irqdomain_remove;
317
318 /* setup one handler for each entry */
319 irq_set_chained_handler_and_data(port->irq, mxs_gpio_irq_handler,
320 port);
321
322 err = bgpio_init(&port->gc, &pdev->dev, 4,
323 port->base + PINCTRL_DIN(port),
324 port->base + PINCTRL_DOUT(port) + MXS_SET,
325 port->base + PINCTRL_DOUT(port) + MXS_CLR,
326 port->base + PINCTRL_DOE(port), NULL, 0);
327 if (err)
328 goto out_irqdomain_remove;
329
330 port->gc.to_irq = mxs_gpio_to_irq;
331 port->gc.get_direction = mxs_gpio_get_direction;
332 port->gc.base = port->id * 32;
333
334 err = gpiochip_add_data(&port->gc, port);
335 if (err)
336 goto out_irqdomain_remove;
337
338 return 0;
339
340out_irqdomain_remove:
341 irq_domain_remove(port->domain);
342out_iounmap:
343 iounmap(port->base);
344 return err;
345}
346
347static struct platform_driver mxs_gpio_driver = {
348 .driver = {
349 .name = "gpio-mxs",
350 .of_match_table = mxs_gpio_dt_ids,
351 .suppress_bind_attrs = true,
352 },
353 .probe = mxs_gpio_probe,
354};
355
356static int __init mxs_gpio_init(void)
357{
358 return platform_driver_register(&mxs_gpio_driver);
359}
360postcore_initcall(mxs_gpio_init);
361
362MODULE_AUTHOR("Freescale Semiconductor, "
363 "Daniel Mack <danielncaiaq.de>, "
364 "Juergen Beisert <kernel@pengutronix.de>");
365MODULE_DESCRIPTION("Freescale MXS GPIO");