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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * AMD Platform Security Processor (PSP) interface driver
4 *
5 * Copyright (C) 2017-2019 Advanced Micro Devices, Inc.
6 *
7 * Author: Brijesh Singh <brijesh.singh@amd.com>
8 */
9
10#ifndef __PSP_DEV_H__
11#define __PSP_DEV_H__
12
13#include <linux/device.h>
14#include <linux/list.h>
15#include <linux/bits.h>
16#include <linux/interrupt.h>
17
18#include "sp-dev.h"
19
20#define PSP_CMDRESP_RESP BIT(31)
21#define PSP_CMDRESP_ERR_MASK 0xffff
22
23#define MAX_PSP_NAME_LEN 16
24
25extern struct psp_device *psp_master;
26
27typedef void (*psp_irq_handler_t)(int, void *, unsigned int);
28
29struct psp_device {
30 struct list_head entry;
31
32 struct psp_vdata *vdata;
33 char name[MAX_PSP_NAME_LEN];
34
35 struct device *dev;
36 struct sp_device *sp;
37
38 void __iomem *io_regs;
39
40 psp_irq_handler_t sev_irq_handler;
41 void *sev_irq_data;
42
43 psp_irq_handler_t tee_irq_handler;
44 void *tee_irq_data;
45
46 void *sev_data;
47 void *tee_data;
48
49 unsigned int capability;
50};
51
52void psp_set_sev_irq_handler(struct psp_device *psp, psp_irq_handler_t handler,
53 void *data);
54void psp_clear_sev_irq_handler(struct psp_device *psp);
55
56void psp_set_tee_irq_handler(struct psp_device *psp, psp_irq_handler_t handler,
57 void *data);
58void psp_clear_tee_irq_handler(struct psp_device *psp);
59
60struct psp_device *psp_get_master_device(void);
61
62#define PSP_CAPABILITY_SEV BIT(0)
63#define PSP_CAPABILITY_TEE BIT(1)
64#define PSP_CAPABILITY_PSP_SECURITY_REPORTING BIT(7)
65
66#define PSP_CAPABILITY_PSP_SECURITY_OFFSET 8
67/*
68 * The PSP doesn't directly store these bits in the capability register
69 * but instead copies them from the results of query command.
70 *
71 * The offsets from the query command are below, and shifted when used.
72 */
73#define PSP_SECURITY_FUSED_PART BIT(0)
74#define PSP_SECURITY_DEBUG_LOCK_ON BIT(2)
75#define PSP_SECURITY_TSME_STATUS BIT(5)
76#define PSP_SECURITY_ANTI_ROLLBACK_STATUS BIT(7)
77#define PSP_SECURITY_RPMC_PRODUCTION_ENABLED BIT(8)
78#define PSP_SECURITY_RPMC_SPIROM_AVAILABLE BIT(9)
79#define PSP_SECURITY_HSP_TPM_AVAILABLE BIT(10)
80#define PSP_SECURITY_ROM_ARMOR_ENFORCED BIT(11)
81
82#endif /* __PSP_DEV_H */
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * AMD Platform Security Processor (PSP) interface driver
4 *
5 * Copyright (C) 2017-2019 Advanced Micro Devices, Inc.
6 *
7 * Author: Brijesh Singh <brijesh.singh@amd.com>
8 */
9
10#ifndef __PSP_DEV_H__
11#define __PSP_DEV_H__
12
13#include <linux/device.h>
14#include <linux/list.h>
15#include <linux/bits.h>
16#include <linux/interrupt.h>
17#include <linux/mutex.h>
18#include <linux/psp.h>
19#include <linux/psp-platform-access.h>
20
21#include "sp-dev.h"
22
23#define MAX_PSP_NAME_LEN 16
24
25extern struct psp_device *psp_master;
26
27typedef void (*psp_irq_handler_t)(int, void *, unsigned int);
28
29union psp_cap_register {
30 unsigned int raw;
31 struct {
32 unsigned int sev :1,
33 tee :1,
34 dbc_thru_ext :1,
35 rsvd1 :4,
36 security_reporting :1,
37 fused_part :1,
38 rsvd2 :1,
39 debug_lock_on :1,
40 rsvd3 :2,
41 tsme_status :1,
42 rsvd4 :1,
43 anti_rollback_status :1,
44 rpmc_production_enabled :1,
45 rpmc_spirom_available :1,
46 hsp_tpm_available :1,
47 rom_armor_enforced :1,
48 rsvd5 :12;
49 };
50};
51
52struct psp_device {
53 struct list_head entry;
54
55 struct psp_vdata *vdata;
56 char name[MAX_PSP_NAME_LEN];
57
58 struct device *dev;
59 struct sp_device *sp;
60
61 void __iomem *io_regs;
62 struct mutex mailbox_mutex;
63
64 psp_irq_handler_t sev_irq_handler;
65 void *sev_irq_data;
66
67 void *sev_data;
68 void *tee_data;
69 void *platform_access_data;
70 void *dbc_data;
71
72 union psp_cap_register capability;
73};
74
75void psp_set_sev_irq_handler(struct psp_device *psp, psp_irq_handler_t handler,
76 void *data);
77void psp_clear_sev_irq_handler(struct psp_device *psp);
78
79struct psp_device *psp_get_master_device(void);
80
81/**
82 * enum psp_cmd - PSP mailbox commands
83 * @PSP_CMD_TEE_RING_INIT: Initialize TEE ring buffer
84 * @PSP_CMD_TEE_RING_DESTROY: Destroy TEE ring buffer
85 * @PSP_CMD_TEE_EXTENDED_CMD: Extended command
86 * @PSP_CMD_MAX: Maximum command id
87 */
88enum psp_cmd {
89 PSP_CMD_TEE_RING_INIT = 1,
90 PSP_CMD_TEE_RING_DESTROY = 2,
91 PSP_CMD_TEE_EXTENDED_CMD = 14,
92 PSP_CMD_MAX = 15,
93};
94
95int psp_mailbox_command(struct psp_device *psp, enum psp_cmd cmd, void *cmdbuff,
96 unsigned int timeout_msecs, unsigned int *cmdresp);
97
98/**
99 * struct psp_ext_req_buffer_hdr - Structure of the extended command header
100 * @payload_size: total payload size
101 * @sub_cmd_id: extended command ID
102 * @status: status of command execution (out)
103 */
104struct psp_ext_req_buffer_hdr {
105 u32 payload_size;
106 u32 sub_cmd_id;
107 u32 status;
108} __packed;
109
110struct psp_ext_request {
111 struct psp_ext_req_buffer_hdr header;
112 void *buf;
113} __packed;
114
115/**
116 * enum psp_sub_cmd - PSP mailbox sub commands
117 * @PSP_SUB_CMD_DBC_GET_NONCE: Get nonce from DBC
118 * @PSP_SUB_CMD_DBC_SET_UID: Set UID for DBC
119 * @PSP_SUB_CMD_DBC_GET_PARAMETER: Get parameter from DBC
120 * @PSP_SUB_CMD_DBC_SET_PARAMETER: Set parameter for DBC
121 */
122enum psp_sub_cmd {
123 PSP_SUB_CMD_DBC_GET_NONCE = PSP_DYNAMIC_BOOST_GET_NONCE,
124 PSP_SUB_CMD_DBC_SET_UID = PSP_DYNAMIC_BOOST_SET_UID,
125 PSP_SUB_CMD_DBC_GET_PARAMETER = PSP_DYNAMIC_BOOST_GET_PARAMETER,
126 PSP_SUB_CMD_DBC_SET_PARAMETER = PSP_DYNAMIC_BOOST_SET_PARAMETER,
127};
128
129int psp_extended_mailbox_cmd(struct psp_device *psp, unsigned int timeout_msecs,
130 struct psp_ext_request *req);
131#endif /* __PSP_DEV_H */