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1/******************************************************************************
2 iphase.c: Device driver for Interphase ATM PCI adapter cards
3 Author: Peter Wang <pwang@iphase.com>
4 Some fixes: Arnaldo Carvalho de Melo <acme@conectiva.com.br>
5 Interphase Corporation <www.iphase.com>
6 Version: 1.0
7*******************************************************************************
8
9 This software may be used and distributed according to the terms
10 of the GNU General Public License (GPL), incorporated herein by reference.
11 Drivers based on this skeleton fall under the GPL and must retain
12 the authorship (implicit copyright) notice.
13
14 This program is distributed in the hope that it will be useful, but
15 WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 General Public License for more details.
18
19 Modified from an incomplete driver for Interphase 5575 1KVC 1M card which
20 was originally written by Monalisa Agrawal at UNH. Now this driver
21 supports a variety of varients of Interphase ATM PCI (i)Chip adapter
22 card family (See www.iphase.com/products/ClassSheet.cfm?ClassID=ATM)
23 in terms of PHY type, the size of control memory and the size of
24 packet memory. The following are the change log and history:
25
26 Bugfix the Mona's UBR driver.
27 Modify the basic memory allocation and dma logic.
28 Port the driver to the latest kernel from 2.0.46.
29 Complete the ABR logic of the driver, and added the ABR work-
30 around for the hardware anormalies.
31 Add the CBR support.
32 Add the flow control logic to the driver to allow rate-limit VC.
33 Add 4K VC support to the board with 512K control memory.
34 Add the support of all the variants of the Interphase ATM PCI
35 (i)Chip adapter cards including x575 (155M OC3 and UTP155), x525
36 (25M UTP25) and x531 (DS3 and E3).
37 Add SMP support.
38
39 Support and updates available at: ftp://ftp.iphase.com/pub/atm
40
41*******************************************************************************/
42
43#include <linux/module.h>
44#include <linux/kernel.h>
45#include <linux/mm.h>
46#include <linux/pci.h>
47#include <linux/errno.h>
48#include <linux/atm.h>
49#include <linux/atmdev.h>
50#include <linux/ctype.h>
51#include <linux/sonet.h>
52#include <linux/skbuff.h>
53#include <linux/time.h>
54#include <linux/delay.h>
55#include <linux/uio.h>
56#include <linux/init.h>
57#include <linux/interrupt.h>
58#include <linux/wait.h>
59#include <linux/slab.h>
60#include <asm/io.h>
61#include <linux/atomic.h>
62#include <linux/uaccess.h>
63#include <asm/string.h>
64#include <asm/byteorder.h>
65#include <linux/vmalloc.h>
66#include <linux/jiffies.h>
67#include <linux/nospec.h>
68#include "iphase.h"
69#include "suni.h"
70#define swap_byte_order(x) (((x & 0xff) << 8) | ((x & 0xff00) >> 8))
71
72#define PRIV(dev) ((struct suni_priv *) dev->phy_data)
73
74static unsigned char ia_phy_get(struct atm_dev *dev, unsigned long addr);
75static void desc_dbg(IADEV *iadev);
76
77static IADEV *ia_dev[8];
78static struct atm_dev *_ia_dev[8];
79static int iadev_count;
80static void ia_led_timer(struct timer_list *unused);
81static DEFINE_TIMER(ia_timer, ia_led_timer);
82static int IA_TX_BUF = DFL_TX_BUFFERS, IA_TX_BUF_SZ = DFL_TX_BUF_SZ;
83static int IA_RX_BUF = DFL_RX_BUFFERS, IA_RX_BUF_SZ = DFL_RX_BUF_SZ;
84static uint IADebugFlag = /* IF_IADBG_ERR | IF_IADBG_CBR| IF_IADBG_INIT_ADAPTER
85 |IF_IADBG_ABR | IF_IADBG_EVENT*/ 0;
86
87module_param(IA_TX_BUF, int, 0);
88module_param(IA_TX_BUF_SZ, int, 0);
89module_param(IA_RX_BUF, int, 0);
90module_param(IA_RX_BUF_SZ, int, 0);
91module_param(IADebugFlag, uint, 0644);
92
93MODULE_LICENSE("GPL");
94
95/**************************** IA_LIB **********************************/
96
97static void ia_init_rtn_q (IARTN_Q *que)
98{
99 que->next = NULL;
100 que->tail = NULL;
101}
102
103static void ia_enque_head_rtn_q (IARTN_Q *que, IARTN_Q * data)
104{
105 data->next = NULL;
106 if (que->next == NULL)
107 que->next = que->tail = data;
108 else {
109 data->next = que->next;
110 que->next = data;
111 }
112 return;
113}
114
115static int ia_enque_rtn_q (IARTN_Q *que, struct desc_tbl_t data) {
116 IARTN_Q *entry = kmalloc(sizeof(*entry), GFP_ATOMIC);
117 if (!entry)
118 return -ENOMEM;
119 entry->data = data;
120 entry->next = NULL;
121 if (que->next == NULL)
122 que->next = que->tail = entry;
123 else {
124 que->tail->next = entry;
125 que->tail = que->tail->next;
126 }
127 return 1;
128}
129
130static IARTN_Q * ia_deque_rtn_q (IARTN_Q *que) {
131 IARTN_Q *tmpdata;
132 if (que->next == NULL)
133 return NULL;
134 tmpdata = que->next;
135 if ( que->next == que->tail)
136 que->next = que->tail = NULL;
137 else
138 que->next = que->next->next;
139 return tmpdata;
140}
141
142static void ia_hack_tcq(IADEV *dev) {
143
144 u_short desc1;
145 u_short tcq_wr;
146 struct ia_vcc *iavcc_r = NULL;
147
148 tcq_wr = readl(dev->seg_reg+TCQ_WR_PTR) & 0xffff;
149 while (dev->host_tcq_wr != tcq_wr) {
150 desc1 = *(u_short *)(dev->seg_ram + dev->host_tcq_wr);
151 if (!desc1) ;
152 else if (!dev->desc_tbl[desc1 -1].timestamp) {
153 IF_ABR(printk(" Desc %d is reset at %ld\n", desc1 -1, jiffies);)
154 *(u_short *) (dev->seg_ram + dev->host_tcq_wr) = 0;
155 }
156 else if (dev->desc_tbl[desc1 -1].timestamp) {
157 if (!(iavcc_r = dev->desc_tbl[desc1 -1].iavcc)) {
158 printk("IA: Fatal err in get_desc\n");
159 continue;
160 }
161 iavcc_r->vc_desc_cnt--;
162 dev->desc_tbl[desc1 -1].timestamp = 0;
163 IF_EVENT(printk("ia_hack: return_q skb = 0x%p desc = %d\n",
164 dev->desc_tbl[desc1 -1].txskb, desc1);)
165 if (iavcc_r->pcr < dev->rate_limit) {
166 IA_SKB_STATE (dev->desc_tbl[desc1-1].txskb) |= IA_TX_DONE;
167 if (ia_enque_rtn_q(&dev->tx_return_q, dev->desc_tbl[desc1 -1]) < 0)
168 printk("ia_hack_tcq: No memory available\n");
169 }
170 dev->desc_tbl[desc1 -1].iavcc = NULL;
171 dev->desc_tbl[desc1 -1].txskb = NULL;
172 }
173 dev->host_tcq_wr += 2;
174 if (dev->host_tcq_wr > dev->ffL.tcq_ed)
175 dev->host_tcq_wr = dev->ffL.tcq_st;
176 }
177} /* ia_hack_tcq */
178
179static u16 get_desc (IADEV *dev, struct ia_vcc *iavcc) {
180 u_short desc_num, i;
181 struct ia_vcc *iavcc_r = NULL;
182 unsigned long delta;
183 static unsigned long timer = 0;
184 int ltimeout;
185
186 ia_hack_tcq (dev);
187 if((time_after(jiffies,timer+50)) || ((dev->ffL.tcq_rd==dev->host_tcq_wr))) {
188 timer = jiffies;
189 i=0;
190 while (i < dev->num_tx_desc) {
191 if (!dev->desc_tbl[i].timestamp) {
192 i++;
193 continue;
194 }
195 ltimeout = dev->desc_tbl[i].iavcc->ltimeout;
196 delta = jiffies - dev->desc_tbl[i].timestamp;
197 if (delta >= ltimeout) {
198 IF_ABR(printk("RECOVER run!! desc_tbl %d = %d delta = %ld, time = %ld\n", i,dev->desc_tbl[i].timestamp, delta, jiffies);)
199 if (dev->ffL.tcq_rd == dev->ffL.tcq_st)
200 dev->ffL.tcq_rd = dev->ffL.tcq_ed;
201 else
202 dev->ffL.tcq_rd -= 2;
203 *(u_short *)(dev->seg_ram + dev->ffL.tcq_rd) = i+1;
204 if (!dev->desc_tbl[i].txskb || !(iavcc_r = dev->desc_tbl[i].iavcc))
205 printk("Fatal err, desc table vcc or skb is NULL\n");
206 else
207 iavcc_r->vc_desc_cnt--;
208 dev->desc_tbl[i].timestamp = 0;
209 dev->desc_tbl[i].iavcc = NULL;
210 dev->desc_tbl[i].txskb = NULL;
211 }
212 i++;
213 } /* while */
214 }
215 if (dev->ffL.tcq_rd == dev->host_tcq_wr)
216 return 0xFFFF;
217
218 /* Get the next available descriptor number from TCQ */
219 desc_num = *(u_short *)(dev->seg_ram + dev->ffL.tcq_rd);
220
221 while (!desc_num || (dev->desc_tbl[desc_num -1]).timestamp) {
222 dev->ffL.tcq_rd += 2;
223 if (dev->ffL.tcq_rd > dev->ffL.tcq_ed)
224 dev->ffL.tcq_rd = dev->ffL.tcq_st;
225 if (dev->ffL.tcq_rd == dev->host_tcq_wr)
226 return 0xFFFF;
227 desc_num = *(u_short *)(dev->seg_ram + dev->ffL.tcq_rd);
228 }
229
230 /* get system time */
231 dev->desc_tbl[desc_num -1].timestamp = jiffies;
232 return desc_num;
233}
234
235static void clear_lockup (struct atm_vcc *vcc, IADEV *dev) {
236 u_char foundLockUp;
237 vcstatus_t *vcstatus;
238 u_short *shd_tbl;
239 u_short tempCellSlot, tempFract;
240 struct main_vc *abr_vc = (struct main_vc *)dev->MAIN_VC_TABLE_ADDR;
241 struct ext_vc *eabr_vc = (struct ext_vc *)dev->EXT_VC_TABLE_ADDR;
242 u_int i;
243
244 if (vcc->qos.txtp.traffic_class == ATM_ABR) {
245 vcstatus = (vcstatus_t *) &(dev->testTable[vcc->vci]->vc_status);
246 vcstatus->cnt++;
247 foundLockUp = 0;
248 if( vcstatus->cnt == 0x05 ) {
249 abr_vc += vcc->vci;
250 eabr_vc += vcc->vci;
251 if( eabr_vc->last_desc ) {
252 if( (abr_vc->status & 0x07) == ABR_STATE /* 0x2 */ ) {
253 /* Wait for 10 Micro sec */
254 udelay(10);
255 if ((eabr_vc->last_desc)&&((abr_vc->status & 0x07)==ABR_STATE))
256 foundLockUp = 1;
257 }
258 else {
259 tempCellSlot = abr_vc->last_cell_slot;
260 tempFract = abr_vc->fraction;
261 if((tempCellSlot == dev->testTable[vcc->vci]->lastTime)
262 && (tempFract == dev->testTable[vcc->vci]->fract))
263 foundLockUp = 1;
264 dev->testTable[vcc->vci]->lastTime = tempCellSlot;
265 dev->testTable[vcc->vci]->fract = tempFract;
266 }
267 } /* last descriptor */
268 vcstatus->cnt = 0;
269 } /* vcstatus->cnt */
270
271 if (foundLockUp) {
272 IF_ABR(printk("LOCK UP found\n");)
273 writew(0xFFFD, dev->seg_reg+MODE_REG_0);
274 /* Wait for 10 Micro sec */
275 udelay(10);
276 abr_vc->status &= 0xFFF8;
277 abr_vc->status |= 0x0001; /* state is idle */
278 shd_tbl = (u_short *)dev->ABR_SCHED_TABLE_ADDR;
279 for( i = 0; ((i < dev->num_vc) && (shd_tbl[i])); i++ );
280 if (i < dev->num_vc)
281 shd_tbl[i] = vcc->vci;
282 else
283 IF_ERR(printk("ABR Seg. may not continue on VC %x\n",vcc->vci);)
284 writew(T_ONLINE, dev->seg_reg+MODE_REG_0);
285 writew(~(TRANSMIT_DONE|TCQ_NOT_EMPTY), dev->seg_reg+SEG_MASK_REG);
286 writew(TRANSMIT_DONE, dev->seg_reg+SEG_INTR_STATUS_REG);
287 vcstatus->cnt = 0;
288 } /* foundLockUp */
289
290 } /* if an ABR VC */
291
292
293}
294
295/*
296** Conversion of 24-bit cellrate (cells/sec) to 16-bit floating point format.
297**
298** +----+----+------------------+-------------------------------+
299** | R | NZ | 5-bit exponent | 9-bit mantissa |
300** +----+----+------------------+-------------------------------+
301**
302** R = reserved (written as 0)
303** NZ = 0 if 0 cells/sec; 1 otherwise
304**
305** if NZ = 1, rate = 1.mmmmmmmmm x 2^(eeeee) cells/sec
306*/
307static u16
308cellrate_to_float(u32 cr)
309{
310
311#define NZ 0x4000
312#define M_BITS 9 /* Number of bits in mantissa */
313#define E_BITS 5 /* Number of bits in exponent */
314#define M_MASK 0x1ff
315#define E_MASK 0x1f
316 u16 flot;
317 u32 tmp = cr & 0x00ffffff;
318 int i = 0;
319 if (cr == 0)
320 return 0;
321 while (tmp != 1) {
322 tmp >>= 1;
323 i++;
324 }
325 if (i == M_BITS)
326 flot = NZ | (i << M_BITS) | (cr & M_MASK);
327 else if (i < M_BITS)
328 flot = NZ | (i << M_BITS) | ((cr << (M_BITS - i)) & M_MASK);
329 else
330 flot = NZ | (i << M_BITS) | ((cr >> (i - M_BITS)) & M_MASK);
331 return flot;
332}
333
334#if 0
335/*
336** Conversion of 16-bit floating point format to 24-bit cellrate (cells/sec).
337*/
338static u32
339float_to_cellrate(u16 rate)
340{
341 u32 exp, mantissa, cps;
342 if ((rate & NZ) == 0)
343 return 0;
344 exp = (rate >> M_BITS) & E_MASK;
345 mantissa = rate & M_MASK;
346 if (exp == 0)
347 return 1;
348 cps = (1 << M_BITS) | mantissa;
349 if (exp == M_BITS)
350 cps = cps;
351 else if (exp > M_BITS)
352 cps <<= (exp - M_BITS);
353 else
354 cps >>= (M_BITS - exp);
355 return cps;
356}
357#endif
358
359static void init_abr_vc (IADEV *dev, srv_cls_param_t *srv_p) {
360 srv_p->class_type = ATM_ABR;
361 srv_p->pcr = dev->LineRate;
362 srv_p->mcr = 0;
363 srv_p->icr = 0x055cb7;
364 srv_p->tbe = 0xffffff;
365 srv_p->frtt = 0x3a;
366 srv_p->rif = 0xf;
367 srv_p->rdf = 0xb;
368 srv_p->nrm = 0x4;
369 srv_p->trm = 0x7;
370 srv_p->cdf = 0x3;
371 srv_p->adtf = 50;
372}
373
374static int
375ia_open_abr_vc(IADEV *dev, srv_cls_param_t *srv_p,
376 struct atm_vcc *vcc, u8 flag)
377{
378 f_vc_abr_entry *f_abr_vc;
379 r_vc_abr_entry *r_abr_vc;
380 u32 icr;
381 u8 trm, nrm, crm;
382 u16 adtf, air, *ptr16;
383 f_abr_vc =(f_vc_abr_entry *)dev->MAIN_VC_TABLE_ADDR;
384 f_abr_vc += vcc->vci;
385 switch (flag) {
386 case 1: /* FFRED initialization */
387#if 0 /* sanity check */
388 if (srv_p->pcr == 0)
389 return INVALID_PCR;
390 if (srv_p->pcr > dev->LineRate)
391 srv_p->pcr = dev->LineRate;
392 if ((srv_p->mcr + dev->sum_mcr) > dev->LineRate)
393 return MCR_UNAVAILABLE;
394 if (srv_p->mcr > srv_p->pcr)
395 return INVALID_MCR;
396 if (!(srv_p->icr))
397 srv_p->icr = srv_p->pcr;
398 if ((srv_p->icr < srv_p->mcr) || (srv_p->icr > srv_p->pcr))
399 return INVALID_ICR;
400 if ((srv_p->tbe < MIN_TBE) || (srv_p->tbe > MAX_TBE))
401 return INVALID_TBE;
402 if ((srv_p->frtt < MIN_FRTT) || (srv_p->frtt > MAX_FRTT))
403 return INVALID_FRTT;
404 if (srv_p->nrm > MAX_NRM)
405 return INVALID_NRM;
406 if (srv_p->trm > MAX_TRM)
407 return INVALID_TRM;
408 if (srv_p->adtf > MAX_ADTF)
409 return INVALID_ADTF;
410 else if (srv_p->adtf == 0)
411 srv_p->adtf = 1;
412 if (srv_p->cdf > MAX_CDF)
413 return INVALID_CDF;
414 if (srv_p->rif > MAX_RIF)
415 return INVALID_RIF;
416 if (srv_p->rdf > MAX_RDF)
417 return INVALID_RDF;
418#endif
419 memset ((caddr_t)f_abr_vc, 0, sizeof(*f_abr_vc));
420 f_abr_vc->f_vc_type = ABR;
421 nrm = 2 << srv_p->nrm; /* (2 ** (srv_p->nrm +1)) */
422 /* i.e 2**n = 2 << (n-1) */
423 f_abr_vc->f_nrm = nrm << 8 | nrm;
424 trm = 100000/(2 << (16 - srv_p->trm));
425 if ( trm == 0) trm = 1;
426 f_abr_vc->f_nrmexp =(((srv_p->nrm +1) & 0x0f) << 12)|(MRM << 8) | trm;
427 crm = srv_p->tbe / nrm;
428 if (crm == 0) crm = 1;
429 f_abr_vc->f_crm = crm & 0xff;
430 f_abr_vc->f_pcr = cellrate_to_float(srv_p->pcr);
431 icr = min( srv_p->icr, (srv_p->tbe > srv_p->frtt) ?
432 ((srv_p->tbe/srv_p->frtt)*1000000) :
433 (1000000/(srv_p->frtt/srv_p->tbe)));
434 f_abr_vc->f_icr = cellrate_to_float(icr);
435 adtf = (10000 * srv_p->adtf)/8192;
436 if (adtf == 0) adtf = 1;
437 f_abr_vc->f_cdf = ((7 - srv_p->cdf) << 12 | adtf) & 0xfff;
438 f_abr_vc->f_mcr = cellrate_to_float(srv_p->mcr);
439 f_abr_vc->f_acr = f_abr_vc->f_icr;
440 f_abr_vc->f_status = 0x0042;
441 break;
442 case 0: /* RFRED initialization */
443 ptr16 = (u_short *)(dev->reass_ram + REASS_TABLE*dev->memSize);
444 *(ptr16 + vcc->vci) = NO_AAL5_PKT | REASS_ABR;
445 r_abr_vc = (r_vc_abr_entry*)(dev->reass_ram+ABR_VC_TABLE*dev->memSize);
446 r_abr_vc += vcc->vci;
447 r_abr_vc->r_status_rdf = (15 - srv_p->rdf) & 0x000f;
448 air = srv_p->pcr << (15 - srv_p->rif);
449 if (air == 0) air = 1;
450 r_abr_vc->r_air = cellrate_to_float(air);
451 dev->testTable[vcc->vci]->vc_status = VC_ACTIVE | VC_ABR;
452 dev->sum_mcr += srv_p->mcr;
453 dev->n_abr++;
454 break;
455 default:
456 break;
457 }
458 return 0;
459}
460static int ia_cbr_setup (IADEV *dev, struct atm_vcc *vcc) {
461 u32 rateLow=0, rateHigh, rate;
462 int entries;
463 struct ia_vcc *ia_vcc;
464
465 int idealSlot =0, testSlot, toBeAssigned, inc;
466 u32 spacing;
467 u16 *SchedTbl, *TstSchedTbl;
468 u16 cbrVC, vcIndex;
469 u32 fracSlot = 0;
470 u32 sp_mod = 0;
471 u32 sp_mod2 = 0;
472
473 /* IpAdjustTrafficParams */
474 if (vcc->qos.txtp.max_pcr <= 0) {
475 IF_ERR(printk("PCR for CBR not defined\n");)
476 return -1;
477 }
478 rate = vcc->qos.txtp.max_pcr;
479 entries = rate / dev->Granularity;
480 IF_CBR(printk("CBR: CBR entries=0x%x for rate=0x%x & Gran=0x%x\n",
481 entries, rate, dev->Granularity);)
482 if (entries < 1)
483 IF_CBR(printk("CBR: Bandwidth smaller than granularity of CBR table\n");)
484 rateLow = entries * dev->Granularity;
485 rateHigh = (entries + 1) * dev->Granularity;
486 if (3*(rate - rateLow) > (rateHigh - rate))
487 entries++;
488 if (entries > dev->CbrRemEntries) {
489 IF_CBR(printk("CBR: Not enough bandwidth to support this PCR.\n");)
490 IF_CBR(printk("Entries = 0x%x, CbrRemEntries = 0x%x.\n",
491 entries, dev->CbrRemEntries);)
492 return -EBUSY;
493 }
494
495 ia_vcc = INPH_IA_VCC(vcc);
496 ia_vcc->NumCbrEntry = entries;
497 dev->sum_mcr += entries * dev->Granularity;
498 /* IaFFrednInsertCbrSched */
499 // Starting at an arbitrary location, place the entries into the table
500 // as smoothly as possible
501 cbrVC = 0;
502 spacing = dev->CbrTotEntries / entries;
503 sp_mod = dev->CbrTotEntries % entries; // get modulo
504 toBeAssigned = entries;
505 fracSlot = 0;
506 vcIndex = vcc->vci;
507 IF_CBR(printk("Vci=0x%x,Spacing=0x%x,Sp_mod=0x%x\n",vcIndex,spacing,sp_mod);)
508 while (toBeAssigned)
509 {
510 // If this is the first time, start the table loading for this connection
511 // as close to entryPoint as possible.
512 if (toBeAssigned == entries)
513 {
514 idealSlot = dev->CbrEntryPt;
515 dev->CbrEntryPt += 2; // Adding 2 helps to prevent clumping
516 if (dev->CbrEntryPt >= dev->CbrTotEntries)
517 dev->CbrEntryPt -= dev->CbrTotEntries;// Wrap if necessary
518 } else {
519 idealSlot += (u32)(spacing + fracSlot); // Point to the next location
520 // in the table that would be smoothest
521 fracSlot = ((sp_mod + sp_mod2) / entries); // get new integer part
522 sp_mod2 = ((sp_mod + sp_mod2) % entries); // calc new fractional part
523 }
524 if (idealSlot >= (int)dev->CbrTotEntries)
525 idealSlot -= dev->CbrTotEntries;
526 // Continuously check around this ideal value until a null
527 // location is encountered.
528 SchedTbl = (u16*)(dev->seg_ram+CBR_SCHED_TABLE*dev->memSize);
529 inc = 0;
530 testSlot = idealSlot;
531 TstSchedTbl = (u16*)(SchedTbl+testSlot); //set index and read in value
532 IF_CBR(printk("CBR Testslot 0x%x AT Location 0x%p, NumToAssign=%d\n",
533 testSlot, TstSchedTbl,toBeAssigned);)
534 memcpy((caddr_t)&cbrVC,(caddr_t)TstSchedTbl,sizeof(cbrVC));
535 while (cbrVC) // If another VC at this location, we have to keep looking
536 {
537 inc++;
538 testSlot = idealSlot - inc;
539 if (testSlot < 0) { // Wrap if necessary
540 testSlot += dev->CbrTotEntries;
541 IF_CBR(printk("Testslot Wrap. STable Start=0x%p,Testslot=%d\n",
542 SchedTbl,testSlot);)
543 }
544 TstSchedTbl = (u16 *)(SchedTbl + testSlot); // set table index
545 memcpy((caddr_t)&cbrVC,(caddr_t)TstSchedTbl,sizeof(cbrVC));
546 if (!cbrVC)
547 break;
548 testSlot = idealSlot + inc;
549 if (testSlot >= (int)dev->CbrTotEntries) { // Wrap if necessary
550 testSlot -= dev->CbrTotEntries;
551 IF_CBR(printk("TotCbrEntries=%d",dev->CbrTotEntries);)
552 IF_CBR(printk(" Testslot=0x%x ToBeAssgned=%d\n",
553 testSlot, toBeAssigned);)
554 }
555 // set table index and read in value
556 TstSchedTbl = (u16*)(SchedTbl + testSlot);
557 IF_CBR(printk("Reading CBR Tbl from 0x%p, CbrVal=0x%x Iteration %d\n",
558 TstSchedTbl,cbrVC,inc);)
559 memcpy((caddr_t)&cbrVC,(caddr_t)TstSchedTbl,sizeof(cbrVC));
560 } /* while */
561 // Move this VCI number into this location of the CBR Sched table.
562 memcpy((caddr_t)TstSchedTbl, (caddr_t)&vcIndex, sizeof(*TstSchedTbl));
563 dev->CbrRemEntries--;
564 toBeAssigned--;
565 } /* while */
566
567 /* IaFFrednCbrEnable */
568 dev->NumEnabledCBR++;
569 if (dev->NumEnabledCBR == 1) {
570 writew((CBR_EN | UBR_EN | ABR_EN | (0x23 << 2)), dev->seg_reg+STPARMS);
571 IF_CBR(printk("CBR is enabled\n");)
572 }
573 return 0;
574}
575static void ia_cbrVc_close (struct atm_vcc *vcc) {
576 IADEV *iadev;
577 u16 *SchedTbl, NullVci = 0;
578 u32 i, NumFound;
579
580 iadev = INPH_IA_DEV(vcc->dev);
581 iadev->NumEnabledCBR--;
582 SchedTbl = (u16*)(iadev->seg_ram+CBR_SCHED_TABLE*iadev->memSize);
583 if (iadev->NumEnabledCBR == 0) {
584 writew((UBR_EN | ABR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS);
585 IF_CBR (printk("CBR support disabled\n");)
586 }
587 NumFound = 0;
588 for (i=0; i < iadev->CbrTotEntries; i++)
589 {
590 if (*SchedTbl == vcc->vci) {
591 iadev->CbrRemEntries++;
592 *SchedTbl = NullVci;
593 IF_CBR(NumFound++;)
594 }
595 SchedTbl++;
596 }
597 IF_CBR(printk("Exit ia_cbrVc_close, NumRemoved=%d\n",NumFound);)
598}
599
600static int ia_avail_descs(IADEV *iadev) {
601 int tmp = 0;
602 ia_hack_tcq(iadev);
603 if (iadev->host_tcq_wr >= iadev->ffL.tcq_rd)
604 tmp = (iadev->host_tcq_wr - iadev->ffL.tcq_rd) / 2;
605 else
606 tmp = (iadev->ffL.tcq_ed - iadev->ffL.tcq_rd + 2 + iadev->host_tcq_wr -
607 iadev->ffL.tcq_st) / 2;
608 return tmp;
609}
610
611static int ia_pkt_tx (struct atm_vcc *vcc, struct sk_buff *skb);
612
613static int ia_que_tx (IADEV *iadev) {
614 struct sk_buff *skb;
615 int num_desc;
616 struct atm_vcc *vcc;
617 num_desc = ia_avail_descs(iadev);
618
619 while (num_desc && (skb = skb_dequeue(&iadev->tx_backlog))) {
620 if (!(vcc = ATM_SKB(skb)->vcc)) {
621 dev_kfree_skb_any(skb);
622 printk("ia_que_tx: Null vcc\n");
623 break;
624 }
625 if (!test_bit(ATM_VF_READY,&vcc->flags)) {
626 dev_kfree_skb_any(skb);
627 printk("Free the SKB on closed vci %d \n", vcc->vci);
628 break;
629 }
630 if (ia_pkt_tx (vcc, skb)) {
631 skb_queue_head(&iadev->tx_backlog, skb);
632 }
633 num_desc--;
634 }
635 return 0;
636}
637
638static void ia_tx_poll (IADEV *iadev) {
639 struct atm_vcc *vcc = NULL;
640 struct sk_buff *skb = NULL, *skb1 = NULL;
641 struct ia_vcc *iavcc;
642 IARTN_Q * rtne;
643
644 ia_hack_tcq(iadev);
645 while ( (rtne = ia_deque_rtn_q(&iadev->tx_return_q))) {
646 skb = rtne->data.txskb;
647 if (!skb) {
648 printk("ia_tx_poll: skb is null\n");
649 goto out;
650 }
651 vcc = ATM_SKB(skb)->vcc;
652 if (!vcc) {
653 printk("ia_tx_poll: vcc is null\n");
654 dev_kfree_skb_any(skb);
655 goto out;
656 }
657
658 iavcc = INPH_IA_VCC(vcc);
659 if (!iavcc) {
660 printk("ia_tx_poll: iavcc is null\n");
661 dev_kfree_skb_any(skb);
662 goto out;
663 }
664
665 skb1 = skb_dequeue(&iavcc->txing_skb);
666 while (skb1 && (skb1 != skb)) {
667 if (!(IA_SKB_STATE(skb1) & IA_TX_DONE)) {
668 printk("IA_tx_intr: Vci %d lost pkt!!!\n", vcc->vci);
669 }
670 IF_ERR(printk("Release the SKB not match\n");)
671 if ((vcc->pop) && (skb1->len != 0))
672 {
673 vcc->pop(vcc, skb1);
674 IF_EVENT(printk("Transmit Done - skb 0x%lx return\n",
675 (long)skb1);)
676 }
677 else
678 dev_kfree_skb_any(skb1);
679 skb1 = skb_dequeue(&iavcc->txing_skb);
680 }
681 if (!skb1) {
682 IF_EVENT(printk("IA: Vci %d - skb not found requeued\n",vcc->vci);)
683 ia_enque_head_rtn_q (&iadev->tx_return_q, rtne);
684 break;
685 }
686 if ((vcc->pop) && (skb->len != 0))
687 {
688 vcc->pop(vcc, skb);
689 IF_EVENT(printk("Tx Done - skb 0x%lx return\n",(long)skb);)
690 }
691 else
692 dev_kfree_skb_any(skb);
693 kfree(rtne);
694 }
695 ia_que_tx(iadev);
696out:
697 return;
698}
699#if 0
700static void ia_eeprom_put (IADEV *iadev, u32 addr, u_short val)
701{
702 u32 t;
703 int i;
704 /*
705 * Issue a command to enable writes to the NOVRAM
706 */
707 NVRAM_CMD (EXTEND + EWEN);
708 NVRAM_CLR_CE;
709 /*
710 * issue the write command
711 */
712 NVRAM_CMD(IAWRITE + addr);
713 /*
714 * Send the data, starting with D15, then D14, and so on for 16 bits
715 */
716 for (i=15; i>=0; i--) {
717 NVRAM_CLKOUT (val & 0x8000);
718 val <<= 1;
719 }
720 NVRAM_CLR_CE;
721 CFG_OR(NVCE);
722 t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS);
723 while (!(t & NVDO))
724 t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS);
725
726 NVRAM_CLR_CE;
727 /*
728 * disable writes again
729 */
730 NVRAM_CMD(EXTEND + EWDS)
731 NVRAM_CLR_CE;
732 CFG_AND(~NVDI);
733}
734#endif
735
736static u16 ia_eeprom_get (IADEV *iadev, u32 addr)
737{
738 u_short val;
739 u32 t;
740 int i;
741 /*
742 * Read the first bit that was clocked with the falling edge of
743 * the last command data clock
744 */
745 NVRAM_CMD(IAREAD + addr);
746 /*
747 * Now read the rest of the bits, the next bit read is D14, then D13,
748 * and so on.
749 */
750 val = 0;
751 for (i=15; i>=0; i--) {
752 NVRAM_CLKIN(t);
753 val |= (t << i);
754 }
755 NVRAM_CLR_CE;
756 CFG_AND(~NVDI);
757 return val;
758}
759
760static void ia_hw_type(IADEV *iadev) {
761 u_short memType = ia_eeprom_get(iadev, 25);
762 iadev->memType = memType;
763 if ((memType & MEM_SIZE_MASK) == MEM_SIZE_1M) {
764 iadev->num_tx_desc = IA_TX_BUF;
765 iadev->tx_buf_sz = IA_TX_BUF_SZ;
766 iadev->num_rx_desc = IA_RX_BUF;
767 iadev->rx_buf_sz = IA_RX_BUF_SZ;
768 } else if ((memType & MEM_SIZE_MASK) == MEM_SIZE_512K) {
769 if (IA_TX_BUF == DFL_TX_BUFFERS)
770 iadev->num_tx_desc = IA_TX_BUF / 2;
771 else
772 iadev->num_tx_desc = IA_TX_BUF;
773 iadev->tx_buf_sz = IA_TX_BUF_SZ;
774 if (IA_RX_BUF == DFL_RX_BUFFERS)
775 iadev->num_rx_desc = IA_RX_BUF / 2;
776 else
777 iadev->num_rx_desc = IA_RX_BUF;
778 iadev->rx_buf_sz = IA_RX_BUF_SZ;
779 }
780 else {
781 if (IA_TX_BUF == DFL_TX_BUFFERS)
782 iadev->num_tx_desc = IA_TX_BUF / 8;
783 else
784 iadev->num_tx_desc = IA_TX_BUF;
785 iadev->tx_buf_sz = IA_TX_BUF_SZ;
786 if (IA_RX_BUF == DFL_RX_BUFFERS)
787 iadev->num_rx_desc = IA_RX_BUF / 8;
788 else
789 iadev->num_rx_desc = IA_RX_BUF;
790 iadev->rx_buf_sz = IA_RX_BUF_SZ;
791 }
792 iadev->rx_pkt_ram = TX_PACKET_RAM + (iadev->num_tx_desc * iadev->tx_buf_sz);
793 IF_INIT(printk("BUF: tx=%d,sz=%d rx=%d sz= %d rx_pkt_ram=%d\n",
794 iadev->num_tx_desc, iadev->tx_buf_sz, iadev->num_rx_desc,
795 iadev->rx_buf_sz, iadev->rx_pkt_ram);)
796
797#if 0
798 if ((memType & FE_MASK) == FE_SINGLE_MODE) {
799 iadev->phy_type = PHY_OC3C_S;
800 else if ((memType & FE_MASK) == FE_UTP_OPTION)
801 iadev->phy_type = PHY_UTP155;
802 else
803 iadev->phy_type = PHY_OC3C_M;
804#endif
805
806 iadev->phy_type = memType & FE_MASK;
807 IF_INIT(printk("memType = 0x%x iadev->phy_type = 0x%x\n",
808 memType,iadev->phy_type);)
809 if (iadev->phy_type == FE_25MBIT_PHY)
810 iadev->LineRate = (u32)(((25600000/8)*26)/(27*53));
811 else if (iadev->phy_type == FE_DS3_PHY)
812 iadev->LineRate = (u32)(((44736000/8)*26)/(27*53));
813 else if (iadev->phy_type == FE_E3_PHY)
814 iadev->LineRate = (u32)(((34368000/8)*26)/(27*53));
815 else
816 iadev->LineRate = (u32)(ATM_OC3_PCR);
817 IF_INIT(printk("iadev->LineRate = %d \n", iadev->LineRate);)
818
819}
820
821static u32 ia_phy_read32(struct iadev_priv *ia, unsigned int reg)
822{
823 return readl(ia->phy + (reg >> 2));
824}
825
826static void ia_phy_write32(struct iadev_priv *ia, unsigned int reg, u32 val)
827{
828 writel(val, ia->phy + (reg >> 2));
829}
830
831static void ia_frontend_intr(struct iadev_priv *iadev)
832{
833 u32 status;
834
835 if (iadev->phy_type & FE_25MBIT_PHY) {
836 status = ia_phy_read32(iadev, MB25_INTR_STATUS);
837 iadev->carrier_detect = (status & MB25_IS_GSB) ? 1 : 0;
838 } else if (iadev->phy_type & FE_DS3_PHY) {
839 ia_phy_read32(iadev, SUNI_DS3_FRM_INTR_STAT);
840 status = ia_phy_read32(iadev, SUNI_DS3_FRM_STAT);
841 iadev->carrier_detect = (status & SUNI_DS3_LOSV) ? 0 : 1;
842 } else if (iadev->phy_type & FE_E3_PHY) {
843 ia_phy_read32(iadev, SUNI_E3_FRM_MAINT_INTR_IND);
844 status = ia_phy_read32(iadev, SUNI_E3_FRM_FRAM_INTR_IND_STAT);
845 iadev->carrier_detect = (status & SUNI_E3_LOS) ? 0 : 1;
846 } else {
847 status = ia_phy_read32(iadev, SUNI_RSOP_STATUS);
848 iadev->carrier_detect = (status & SUNI_LOSV) ? 0 : 1;
849 }
850
851 printk(KERN_INFO "IA: SUNI carrier %s\n",
852 iadev->carrier_detect ? "detected" : "lost signal");
853}
854
855static void ia_mb25_init(struct iadev_priv *iadev)
856{
857#if 0
858 mb25->mb25_master_ctrl = MB25_MC_DRIC | MB25_MC_DREC | MB25_MC_ENABLED;
859#endif
860 ia_phy_write32(iadev, MB25_MASTER_CTRL, MB25_MC_DRIC | MB25_MC_DREC);
861 ia_phy_write32(iadev, MB25_DIAG_CONTROL, 0);
862
863 iadev->carrier_detect =
864 (ia_phy_read32(iadev, MB25_INTR_STATUS) & MB25_IS_GSB) ? 1 : 0;
865}
866
867struct ia_reg {
868 u16 reg;
869 u16 val;
870};
871
872static void ia_phy_write(struct iadev_priv *iadev,
873 const struct ia_reg *regs, int len)
874{
875 while (len--) {
876 ia_phy_write32(iadev, regs->reg, regs->val);
877 regs++;
878 }
879}
880
881static void ia_suni_pm7345_init_ds3(struct iadev_priv *iadev)
882{
883 static const struct ia_reg suni_ds3_init[] = {
884 { SUNI_DS3_FRM_INTR_ENBL, 0x17 },
885 { SUNI_DS3_FRM_CFG, 0x01 },
886 { SUNI_DS3_TRAN_CFG, 0x01 },
887 { SUNI_CONFIG, 0 },
888 { SUNI_SPLR_CFG, 0 },
889 { SUNI_SPLT_CFG, 0 }
890 };
891 u32 status;
892
893 status = ia_phy_read32(iadev, SUNI_DS3_FRM_STAT);
894 iadev->carrier_detect = (status & SUNI_DS3_LOSV) ? 0 : 1;
895
896 ia_phy_write(iadev, suni_ds3_init, ARRAY_SIZE(suni_ds3_init));
897}
898
899static void ia_suni_pm7345_init_e3(struct iadev_priv *iadev)
900{
901 static const struct ia_reg suni_e3_init[] = {
902 { SUNI_E3_FRM_FRAM_OPTIONS, 0x04 },
903 { SUNI_E3_FRM_MAINT_OPTIONS, 0x20 },
904 { SUNI_E3_FRM_FRAM_INTR_ENBL, 0x1d },
905 { SUNI_E3_FRM_MAINT_INTR_ENBL, 0x30 },
906 { SUNI_E3_TRAN_STAT_DIAG_OPTIONS, 0 },
907 { SUNI_E3_TRAN_FRAM_OPTIONS, 0x01 },
908 { SUNI_CONFIG, SUNI_PM7345_E3ENBL },
909 { SUNI_SPLR_CFG, 0x41 },
910 { SUNI_SPLT_CFG, 0x41 }
911 };
912 u32 status;
913
914 status = ia_phy_read32(iadev, SUNI_E3_FRM_FRAM_INTR_IND_STAT);
915 iadev->carrier_detect = (status & SUNI_E3_LOS) ? 0 : 1;
916 ia_phy_write(iadev, suni_e3_init, ARRAY_SIZE(suni_e3_init));
917}
918
919static void ia_suni_pm7345_init(struct iadev_priv *iadev)
920{
921 static const struct ia_reg suni_init[] = {
922 /* Enable RSOP loss of signal interrupt. */
923 { SUNI_INTR_ENBL, 0x28 },
924 /* Clear error counters. */
925 { SUNI_ID_RESET, 0 },
926 /* Clear "PMCTST" in master test register. */
927 { SUNI_MASTER_TEST, 0 },
928
929 { SUNI_RXCP_CTRL, 0x2c },
930 { SUNI_RXCP_FCTRL, 0x81 },
931
932 { SUNI_RXCP_IDLE_PAT_H1, 0 },
933 { SUNI_RXCP_IDLE_PAT_H2, 0 },
934 { SUNI_RXCP_IDLE_PAT_H3, 0 },
935 { SUNI_RXCP_IDLE_PAT_H4, 0x01 },
936
937 { SUNI_RXCP_IDLE_MASK_H1, 0xff },
938 { SUNI_RXCP_IDLE_MASK_H2, 0xff },
939 { SUNI_RXCP_IDLE_MASK_H3, 0xff },
940 { SUNI_RXCP_IDLE_MASK_H4, 0xfe },
941
942 { SUNI_RXCP_CELL_PAT_H1, 0 },
943 { SUNI_RXCP_CELL_PAT_H2, 0 },
944 { SUNI_RXCP_CELL_PAT_H3, 0 },
945 { SUNI_RXCP_CELL_PAT_H4, 0x01 },
946
947 { SUNI_RXCP_CELL_MASK_H1, 0xff },
948 { SUNI_RXCP_CELL_MASK_H2, 0xff },
949 { SUNI_RXCP_CELL_MASK_H3, 0xff },
950 { SUNI_RXCP_CELL_MASK_H4, 0xff },
951
952 { SUNI_TXCP_CTRL, 0xa4 },
953 { SUNI_TXCP_INTR_EN_STS, 0x10 },
954 { SUNI_TXCP_IDLE_PAT_H5, 0x55 }
955 };
956
957 if (iadev->phy_type & FE_DS3_PHY)
958 ia_suni_pm7345_init_ds3(iadev);
959 else
960 ia_suni_pm7345_init_e3(iadev);
961
962 ia_phy_write(iadev, suni_init, ARRAY_SIZE(suni_init));
963
964 ia_phy_write32(iadev, SUNI_CONFIG, ia_phy_read32(iadev, SUNI_CONFIG) &
965 ~(SUNI_PM7345_LLB | SUNI_PM7345_CLB |
966 SUNI_PM7345_DLB | SUNI_PM7345_PLB));
967#ifdef __SNMP__
968 suni_pm7345->suni_rxcp_intr_en_sts |= SUNI_OOCDE;
969#endif /* __SNMP__ */
970 return;
971}
972
973
974/***************************** IA_LIB END *****************************/
975
976#ifdef CONFIG_ATM_IA_DEBUG
977static int tcnter = 0;
978static void xdump( u_char* cp, int length, char* prefix )
979{
980 int col, count;
981 u_char prntBuf[120];
982 u_char* pBuf = prntBuf;
983 count = 0;
984 while(count < length){
985 pBuf += sprintf( pBuf, "%s", prefix );
986 for(col = 0;count + col < length && col < 16; col++){
987 if (col != 0 && (col % 4) == 0)
988 pBuf += sprintf( pBuf, " " );
989 pBuf += sprintf( pBuf, "%02X ", cp[count + col] );
990 }
991 while(col++ < 16){ /* pad end of buffer with blanks */
992 if ((col % 4) == 0)
993 sprintf( pBuf, " " );
994 pBuf += sprintf( pBuf, " " );
995 }
996 pBuf += sprintf( pBuf, " " );
997 for(col = 0;count + col < length && col < 16; col++){
998 u_char c = cp[count + col];
999
1000 if (isascii(c) && isprint(c))
1001 pBuf += sprintf(pBuf, "%c", c);
1002 else
1003 pBuf += sprintf(pBuf, ".");
1004 }
1005 printk("%s\n", prntBuf);
1006 count += col;
1007 pBuf = prntBuf;
1008 }
1009
1010} /* close xdump(... */
1011#endif /* CONFIG_ATM_IA_DEBUG */
1012
1013
1014static struct atm_dev *ia_boards = NULL;
1015
1016#define ACTUAL_RAM_BASE \
1017 RAM_BASE*((iadev->mem)/(128 * 1024))
1018#define ACTUAL_SEG_RAM_BASE \
1019 IPHASE5575_FRAG_CONTROL_RAM_BASE*((iadev->mem)/(128 * 1024))
1020#define ACTUAL_REASS_RAM_BASE \
1021 IPHASE5575_REASS_CONTROL_RAM_BASE*((iadev->mem)/(128 * 1024))
1022
1023
1024/*-- some utilities and memory allocation stuff will come here -------------*/
1025
1026static void desc_dbg(IADEV *iadev) {
1027
1028 u_short tcq_wr_ptr, tcq_st_ptr, tcq_ed_ptr;
1029 u32 i;
1030 void __iomem *tmp;
1031 // regval = readl((u32)ia_cmds->maddr);
1032 tcq_wr_ptr = readw(iadev->seg_reg+TCQ_WR_PTR);
1033 printk("B_tcq_wr = 0x%x desc = %d last desc = %d\n",
1034 tcq_wr_ptr, readw(iadev->seg_ram+tcq_wr_ptr),
1035 readw(iadev->seg_ram+tcq_wr_ptr-2));
1036 printk(" host_tcq_wr = 0x%x host_tcq_rd = 0x%x \n", iadev->host_tcq_wr,
1037 iadev->ffL.tcq_rd);
1038 tcq_st_ptr = readw(iadev->seg_reg+TCQ_ST_ADR);
1039 tcq_ed_ptr = readw(iadev->seg_reg+TCQ_ED_ADR);
1040 printk("tcq_st_ptr = 0x%x tcq_ed_ptr = 0x%x \n", tcq_st_ptr, tcq_ed_ptr);
1041 i = 0;
1042 while (tcq_st_ptr != tcq_ed_ptr) {
1043 tmp = iadev->seg_ram+tcq_st_ptr;
1044 printk("TCQ slot %d desc = %d Addr = %p\n", i++, readw(tmp), tmp);
1045 tcq_st_ptr += 2;
1046 }
1047 for(i=0; i <iadev->num_tx_desc; i++)
1048 printk("Desc_tbl[%d] = %d \n", i, iadev->desc_tbl[i].timestamp);
1049}
1050
1051
1052/*----------------------------- Receiving side stuff --------------------------*/
1053
1054static void rx_excp_rcvd(struct atm_dev *dev)
1055{
1056#if 0 /* closing the receiving size will cause too many excp int */
1057 IADEV *iadev;
1058 u_short state;
1059 u_short excpq_rd_ptr;
1060 //u_short *ptr;
1061 int vci, error = 1;
1062 iadev = INPH_IA_DEV(dev);
1063 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1064 while((state & EXCPQ_EMPTY) != EXCPQ_EMPTY)
1065 { printk("state = %x \n", state);
1066 excpq_rd_ptr = readw(iadev->reass_reg + EXCP_Q_RD_PTR) & 0xffff;
1067 printk("state = %x excpq_rd_ptr = %x \n", state, excpq_rd_ptr);
1068 if (excpq_rd_ptr == *(u16*)(iadev->reass_reg + EXCP_Q_WR_PTR))
1069 IF_ERR(printk("excpq_rd_ptr is wrong!!!\n");)
1070 // TODO: update exception stat
1071 vci = readw(iadev->reass_ram+excpq_rd_ptr);
1072 error = readw(iadev->reass_ram+excpq_rd_ptr+2) & 0x0007;
1073 // pwang_test
1074 excpq_rd_ptr += 4;
1075 if (excpq_rd_ptr > (readw(iadev->reass_reg + EXCP_Q_ED_ADR)& 0xffff))
1076 excpq_rd_ptr = readw(iadev->reass_reg + EXCP_Q_ST_ADR)& 0xffff;
1077 writew( excpq_rd_ptr, iadev->reass_reg + EXCP_Q_RD_PTR);
1078 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1079 }
1080#endif
1081}
1082
1083static void free_desc(struct atm_dev *dev, int desc)
1084{
1085 IADEV *iadev;
1086 iadev = INPH_IA_DEV(dev);
1087 writew(desc, iadev->reass_ram+iadev->rfL.fdq_wr);
1088 iadev->rfL.fdq_wr +=2;
1089 if (iadev->rfL.fdq_wr > iadev->rfL.fdq_ed)
1090 iadev->rfL.fdq_wr = iadev->rfL.fdq_st;
1091 writew(iadev->rfL.fdq_wr, iadev->reass_reg+FREEQ_WR_PTR);
1092}
1093
1094
1095static int rx_pkt(struct atm_dev *dev)
1096{
1097 IADEV *iadev;
1098 struct atm_vcc *vcc;
1099 unsigned short status;
1100 struct rx_buf_desc __iomem *buf_desc_ptr;
1101 int desc;
1102 struct dle* wr_ptr;
1103 int len;
1104 struct sk_buff *skb;
1105 u_int buf_addr, dma_addr;
1106
1107 iadev = INPH_IA_DEV(dev);
1108 if (iadev->rfL.pcq_rd == (readw(iadev->reass_reg+PCQ_WR_PTR)&0xffff))
1109 {
1110 printk(KERN_ERR DEV_LABEL "(itf %d) Receive queue empty\n", dev->number);
1111 return -EINVAL;
1112 }
1113 /* mask 1st 3 bits to get the actual descno. */
1114 desc = readw(iadev->reass_ram+iadev->rfL.pcq_rd) & 0x1fff;
1115 IF_RX(printk("reass_ram = %p iadev->rfL.pcq_rd = 0x%x desc = %d\n",
1116 iadev->reass_ram, iadev->rfL.pcq_rd, desc);
1117 printk(" pcq_wr_ptr = 0x%x\n",
1118 readw(iadev->reass_reg+PCQ_WR_PTR)&0xffff);)
1119 /* update the read pointer - maybe we shud do this in the end*/
1120 if ( iadev->rfL.pcq_rd== iadev->rfL.pcq_ed)
1121 iadev->rfL.pcq_rd = iadev->rfL.pcq_st;
1122 else
1123 iadev->rfL.pcq_rd += 2;
1124 writew(iadev->rfL.pcq_rd, iadev->reass_reg+PCQ_RD_PTR);
1125
1126 /* get the buffer desc entry.
1127 update stuff. - doesn't seem to be any update necessary
1128 */
1129 buf_desc_ptr = iadev->RX_DESC_BASE_ADDR;
1130 /* make the ptr point to the corresponding buffer desc entry */
1131 buf_desc_ptr += desc;
1132 if (!desc || (desc > iadev->num_rx_desc) ||
1133 ((buf_desc_ptr->vc_index & 0xffff) >= iadev->num_vc)) {
1134 free_desc(dev, desc);
1135 IF_ERR(printk("IA: bad descriptor desc = %d \n", desc);)
1136 return -1;
1137 }
1138 vcc = iadev->rx_open[buf_desc_ptr->vc_index & 0xffff];
1139 if (!vcc)
1140 {
1141 free_desc(dev, desc);
1142 printk("IA: null vcc, drop PDU\n");
1143 return -1;
1144 }
1145
1146
1147 /* might want to check the status bits for errors */
1148 status = (u_short) (buf_desc_ptr->desc_mode);
1149 if (status & (RX_CER | RX_PTE | RX_OFL))
1150 {
1151 atomic_inc(&vcc->stats->rx_err);
1152 IF_ERR(printk("IA: bad packet, dropping it");)
1153 if (status & RX_CER) {
1154 IF_ERR(printk(" cause: packet CRC error\n");)
1155 }
1156 else if (status & RX_PTE) {
1157 IF_ERR(printk(" cause: packet time out\n");)
1158 }
1159 else {
1160 IF_ERR(printk(" cause: buffer overflow\n");)
1161 }
1162 goto out_free_desc;
1163 }
1164
1165 /*
1166 build DLE.
1167 */
1168
1169 buf_addr = (buf_desc_ptr->buf_start_hi << 16) | buf_desc_ptr->buf_start_lo;
1170 dma_addr = (buf_desc_ptr->dma_start_hi << 16) | buf_desc_ptr->dma_start_lo;
1171 len = dma_addr - buf_addr;
1172 if (len > iadev->rx_buf_sz) {
1173 printk("Over %d bytes sdu received, dropped!!!\n", iadev->rx_buf_sz);
1174 atomic_inc(&vcc->stats->rx_err);
1175 goto out_free_desc;
1176 }
1177
1178 if (!(skb = atm_alloc_charge(vcc, len, GFP_ATOMIC))) {
1179 if (vcc->vci < 32)
1180 printk("Drop control packets\n");
1181 goto out_free_desc;
1182 }
1183 skb_put(skb,len);
1184 // pwang_test
1185 ATM_SKB(skb)->vcc = vcc;
1186 ATM_DESC(skb) = desc;
1187 skb_queue_tail(&iadev->rx_dma_q, skb);
1188
1189 /* Build the DLE structure */
1190 wr_ptr = iadev->rx_dle_q.write;
1191 wr_ptr->sys_pkt_addr = dma_map_single(&iadev->pci->dev, skb->data,
1192 len, DMA_FROM_DEVICE);
1193 wr_ptr->local_pkt_addr = buf_addr;
1194 wr_ptr->bytes = len; /* We don't know this do we ?? */
1195 wr_ptr->mode = DMA_INT_ENABLE;
1196
1197 /* shud take care of wrap around here too. */
1198 if(++wr_ptr == iadev->rx_dle_q.end)
1199 wr_ptr = iadev->rx_dle_q.start;
1200 iadev->rx_dle_q.write = wr_ptr;
1201 udelay(1);
1202 /* Increment transaction counter */
1203 writel(1, iadev->dma+IPHASE5575_RX_COUNTER);
1204out: return 0;
1205out_free_desc:
1206 free_desc(dev, desc);
1207 goto out;
1208}
1209
1210static void rx_intr(struct atm_dev *dev)
1211{
1212 IADEV *iadev;
1213 u_short status;
1214 u_short state, i;
1215
1216 iadev = INPH_IA_DEV(dev);
1217 status = readl(iadev->reass_reg+REASS_INTR_STATUS_REG) & 0xffff;
1218 IF_EVENT(printk("rx_intr: status = 0x%x\n", status);)
1219 if (status & RX_PKT_RCVD)
1220 {
1221 /* do something */
1222 /* Basically recvd an interrupt for receiving a packet.
1223 A descriptor would have been written to the packet complete
1224 queue. Get all the descriptors and set up dma to move the
1225 packets till the packet complete queue is empty..
1226 */
1227 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1228 IF_EVENT(printk("Rx intr status: RX_PKT_RCVD %08x\n", status);)
1229 while(!(state & PCQ_EMPTY))
1230 {
1231 rx_pkt(dev);
1232 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1233 }
1234 iadev->rxing = 1;
1235 }
1236 if (status & RX_FREEQ_EMPT)
1237 {
1238 if (iadev->rxing) {
1239 iadev->rx_tmp_cnt = iadev->rx_pkt_cnt;
1240 iadev->rx_tmp_jif = jiffies;
1241 iadev->rxing = 0;
1242 }
1243 else if ((time_after(jiffies, iadev->rx_tmp_jif + 50)) &&
1244 ((iadev->rx_pkt_cnt - iadev->rx_tmp_cnt) == 0)) {
1245 for (i = 1; i <= iadev->num_rx_desc; i++)
1246 free_desc(dev, i);
1247printk("Test logic RUN!!!!\n");
1248 writew( ~(RX_FREEQ_EMPT|RX_EXCP_RCVD),iadev->reass_reg+REASS_MASK_REG);
1249 iadev->rxing = 1;
1250 }
1251 IF_EVENT(printk("Rx intr status: RX_FREEQ_EMPT %08x\n", status);)
1252 }
1253
1254 if (status & RX_EXCP_RCVD)
1255 {
1256 /* probably need to handle the exception queue also. */
1257 IF_EVENT(printk("Rx intr status: RX_EXCP_RCVD %08x\n", status);)
1258 rx_excp_rcvd(dev);
1259 }
1260
1261
1262 if (status & RX_RAW_RCVD)
1263 {
1264 /* need to handle the raw incoming cells. This deepnds on
1265 whether we have programmed to receive the raw cells or not.
1266 Else ignore. */
1267 IF_EVENT(printk("Rx intr status: RX_RAW_RCVD %08x\n", status);)
1268 }
1269}
1270
1271
1272static void rx_dle_intr(struct atm_dev *dev)
1273{
1274 IADEV *iadev;
1275 struct atm_vcc *vcc;
1276 struct sk_buff *skb;
1277 int desc;
1278 u_short state;
1279 struct dle *dle, *cur_dle;
1280 u_int dle_lp;
1281 int len;
1282 iadev = INPH_IA_DEV(dev);
1283
1284 /* free all the dles done, that is just update our own dle read pointer
1285 - do we really need to do this. Think not. */
1286 /* DMA is done, just get all the recevie buffers from the rx dma queue
1287 and push them up to the higher layer protocol. Also free the desc
1288 associated with the buffer. */
1289 dle = iadev->rx_dle_q.read;
1290 dle_lp = readl(iadev->dma+IPHASE5575_RX_LIST_ADDR) & (sizeof(struct dle)*DLE_ENTRIES - 1);
1291 cur_dle = (struct dle*)(iadev->rx_dle_q.start + (dle_lp >> 4));
1292 while(dle != cur_dle)
1293 {
1294 /* free the DMAed skb */
1295 skb = skb_dequeue(&iadev->rx_dma_q);
1296 if (!skb)
1297 goto INCR_DLE;
1298 desc = ATM_DESC(skb);
1299 free_desc(dev, desc);
1300
1301 if (!(len = skb->len))
1302 {
1303 printk("rx_dle_intr: skb len 0\n");
1304 dev_kfree_skb_any(skb);
1305 }
1306 else
1307 {
1308 struct cpcs_trailer *trailer;
1309 u_short length;
1310 struct ia_vcc *ia_vcc;
1311
1312 dma_unmap_single(&iadev->pci->dev, iadev->rx_dle_q.write->sys_pkt_addr,
1313 len, DMA_FROM_DEVICE);
1314 /* no VCC related housekeeping done as yet. lets see */
1315 vcc = ATM_SKB(skb)->vcc;
1316 if (!vcc) {
1317 printk("IA: null vcc\n");
1318 dev_kfree_skb_any(skb);
1319 goto INCR_DLE;
1320 }
1321 ia_vcc = INPH_IA_VCC(vcc);
1322 if (ia_vcc == NULL)
1323 {
1324 atomic_inc(&vcc->stats->rx_err);
1325 atm_return(vcc, skb->truesize);
1326 dev_kfree_skb_any(skb);
1327 goto INCR_DLE;
1328 }
1329 // get real pkt length pwang_test
1330 trailer = (struct cpcs_trailer*)((u_char *)skb->data +
1331 skb->len - sizeof(*trailer));
1332 length = swap_byte_order(trailer->length);
1333 if ((length > iadev->rx_buf_sz) || (length >
1334 (skb->len - sizeof(struct cpcs_trailer))))
1335 {
1336 atomic_inc(&vcc->stats->rx_err);
1337 IF_ERR(printk("rx_dle_intr: Bad AAL5 trailer %d (skb len %d)",
1338 length, skb->len);)
1339 atm_return(vcc, skb->truesize);
1340 dev_kfree_skb_any(skb);
1341 goto INCR_DLE;
1342 }
1343 skb_trim(skb, length);
1344
1345 /* Display the packet */
1346 IF_RXPKT(printk("\nDmad Recvd data: len = %d \n", skb->len);
1347 xdump(skb->data, skb->len, "RX: ");
1348 printk("\n");)
1349
1350 IF_RX(printk("rx_dle_intr: skb push");)
1351 vcc->push(vcc,skb);
1352 atomic_inc(&vcc->stats->rx);
1353 iadev->rx_pkt_cnt++;
1354 }
1355INCR_DLE:
1356 if (++dle == iadev->rx_dle_q.end)
1357 dle = iadev->rx_dle_q.start;
1358 }
1359 iadev->rx_dle_q.read = dle;
1360
1361 /* if the interrupts are masked because there were no free desc available,
1362 unmask them now. */
1363 if (!iadev->rxing) {
1364 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1365 if (!(state & FREEQ_EMPTY)) {
1366 state = readl(iadev->reass_reg + REASS_MASK_REG) & 0xffff;
1367 writel(state & ~(RX_FREEQ_EMPT |/* RX_EXCP_RCVD |*/ RX_PKT_RCVD),
1368 iadev->reass_reg+REASS_MASK_REG);
1369 iadev->rxing++;
1370 }
1371 }
1372}
1373
1374
1375static int open_rx(struct atm_vcc *vcc)
1376{
1377 IADEV *iadev;
1378 u_short __iomem *vc_table;
1379 u_short __iomem *reass_ptr;
1380 IF_EVENT(printk("iadev: open_rx %d.%d\n", vcc->vpi, vcc->vci);)
1381
1382 if (vcc->qos.rxtp.traffic_class == ATM_NONE) return 0;
1383 iadev = INPH_IA_DEV(vcc->dev);
1384 if (vcc->qos.rxtp.traffic_class == ATM_ABR) {
1385 if (iadev->phy_type & FE_25MBIT_PHY) {
1386 printk("IA: ABR not support\n");
1387 return -EINVAL;
1388 }
1389 }
1390 /* Make only this VCI in the vc table valid and let all
1391 others be invalid entries */
1392 vc_table = iadev->reass_ram+RX_VC_TABLE*iadev->memSize;
1393 vc_table += vcc->vci;
1394 /* mask the last 6 bits and OR it with 3 for 1K VCs */
1395
1396 *vc_table = vcc->vci << 6;
1397 /* Also keep a list of open rx vcs so that we can attach them with
1398 incoming PDUs later. */
1399 if ((vcc->qos.rxtp.traffic_class == ATM_ABR) ||
1400 (vcc->qos.txtp.traffic_class == ATM_ABR))
1401 {
1402 srv_cls_param_t srv_p;
1403 init_abr_vc(iadev, &srv_p);
1404 ia_open_abr_vc(iadev, &srv_p, vcc, 0);
1405 }
1406 else { /* for UBR later may need to add CBR logic */
1407 reass_ptr = iadev->reass_ram+REASS_TABLE*iadev->memSize;
1408 reass_ptr += vcc->vci;
1409 *reass_ptr = NO_AAL5_PKT;
1410 }
1411
1412 if (iadev->rx_open[vcc->vci])
1413 printk(KERN_CRIT DEV_LABEL "(itf %d): VCI %d already open\n",
1414 vcc->dev->number, vcc->vci);
1415 iadev->rx_open[vcc->vci] = vcc;
1416 return 0;
1417}
1418
1419static int rx_init(struct atm_dev *dev)
1420{
1421 IADEV *iadev;
1422 struct rx_buf_desc __iomem *buf_desc_ptr;
1423 unsigned long rx_pkt_start = 0;
1424 void *dle_addr;
1425 struct abr_vc_table *abr_vc_table;
1426 u16 *vc_table;
1427 u16 *reass_table;
1428 int i,j, vcsize_sel;
1429 u_short freeq_st_adr;
1430 u_short *freeq_start;
1431
1432 iadev = INPH_IA_DEV(dev);
1433 // spin_lock_init(&iadev->rx_lock);
1434
1435 /* Allocate 4k bytes - more aligned than needed (4k boundary) */
1436 dle_addr = dma_alloc_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE,
1437 &iadev->rx_dle_dma, GFP_KERNEL);
1438 if (!dle_addr) {
1439 printk(KERN_ERR DEV_LABEL "can't allocate DLEs\n");
1440 goto err_out;
1441 }
1442 iadev->rx_dle_q.start = (struct dle *)dle_addr;
1443 iadev->rx_dle_q.read = iadev->rx_dle_q.start;
1444 iadev->rx_dle_q.write = iadev->rx_dle_q.start;
1445 iadev->rx_dle_q.end = (struct dle*)((unsigned long)dle_addr+sizeof(struct dle)*DLE_ENTRIES);
1446 /* the end of the dle q points to the entry after the last
1447 DLE that can be used. */
1448
1449 /* write the upper 20 bits of the start address to rx list address register */
1450 /* We know this is 32bit bus addressed so the following is safe */
1451 writel(iadev->rx_dle_dma & 0xfffff000,
1452 iadev->dma + IPHASE5575_RX_LIST_ADDR);
1453 IF_INIT(printk("Tx Dle list addr: 0x%p value: 0x%0x\n",
1454 iadev->dma+IPHASE5575_TX_LIST_ADDR,
1455 readl(iadev->dma + IPHASE5575_TX_LIST_ADDR));
1456 printk("Rx Dle list addr: 0x%p value: 0x%0x\n",
1457 iadev->dma+IPHASE5575_RX_LIST_ADDR,
1458 readl(iadev->dma + IPHASE5575_RX_LIST_ADDR));)
1459
1460 writew(0xffff, iadev->reass_reg+REASS_MASK_REG);
1461 writew(0, iadev->reass_reg+MODE_REG);
1462 writew(RESET_REASS, iadev->reass_reg+REASS_COMMAND_REG);
1463
1464 /* Receive side control memory map
1465 -------------------------------
1466
1467 Buffer descr 0x0000 (736 - 23K)
1468 VP Table 0x5c00 (256 - 512)
1469 Except q 0x5e00 (128 - 512)
1470 Free buffer q 0x6000 (1K - 2K)
1471 Packet comp q 0x6800 (1K - 2K)
1472 Reass Table 0x7000 (1K - 2K)
1473 VC Table 0x7800 (1K - 2K)
1474 ABR VC Table 0x8000 (1K - 32K)
1475 */
1476
1477 /* Base address for Buffer Descriptor Table */
1478 writew(RX_DESC_BASE >> 16, iadev->reass_reg+REASS_DESC_BASE);
1479 /* Set the buffer size register */
1480 writew(iadev->rx_buf_sz, iadev->reass_reg+BUF_SIZE);
1481
1482 /* Initialize each entry in the Buffer Descriptor Table */
1483 iadev->RX_DESC_BASE_ADDR = iadev->reass_ram+RX_DESC_BASE*iadev->memSize;
1484 buf_desc_ptr = iadev->RX_DESC_BASE_ADDR;
1485 memset_io(buf_desc_ptr, 0, sizeof(*buf_desc_ptr));
1486 buf_desc_ptr++;
1487 rx_pkt_start = iadev->rx_pkt_ram;
1488 for(i=1; i<=iadev->num_rx_desc; i++)
1489 {
1490 memset_io(buf_desc_ptr, 0, sizeof(*buf_desc_ptr));
1491 buf_desc_ptr->buf_start_hi = rx_pkt_start >> 16;
1492 buf_desc_ptr->buf_start_lo = rx_pkt_start & 0x0000ffff;
1493 buf_desc_ptr++;
1494 rx_pkt_start += iadev->rx_buf_sz;
1495 }
1496 IF_INIT(printk("Rx Buffer desc ptr: 0x%p\n", buf_desc_ptr);)
1497 i = FREE_BUF_DESC_Q*iadev->memSize;
1498 writew(i >> 16, iadev->reass_reg+REASS_QUEUE_BASE);
1499 writew(i, iadev->reass_reg+FREEQ_ST_ADR);
1500 writew(i+iadev->num_rx_desc*sizeof(u_short),
1501 iadev->reass_reg+FREEQ_ED_ADR);
1502 writew(i, iadev->reass_reg+FREEQ_RD_PTR);
1503 writew(i+iadev->num_rx_desc*sizeof(u_short),
1504 iadev->reass_reg+FREEQ_WR_PTR);
1505 /* Fill the FREEQ with all the free descriptors. */
1506 freeq_st_adr = readw(iadev->reass_reg+FREEQ_ST_ADR);
1507 freeq_start = (u_short *)(iadev->reass_ram+freeq_st_adr);
1508 for(i=1; i<=iadev->num_rx_desc; i++)
1509 {
1510 *freeq_start = (u_short)i;
1511 freeq_start++;
1512 }
1513 IF_INIT(printk("freeq_start: 0x%p\n", freeq_start);)
1514 /* Packet Complete Queue */
1515 i = (PKT_COMP_Q * iadev->memSize) & 0xffff;
1516 writew(i, iadev->reass_reg+PCQ_ST_ADR);
1517 writew(i+iadev->num_vc*sizeof(u_short), iadev->reass_reg+PCQ_ED_ADR);
1518 writew(i, iadev->reass_reg+PCQ_RD_PTR);
1519 writew(i, iadev->reass_reg+PCQ_WR_PTR);
1520
1521 /* Exception Queue */
1522 i = (EXCEPTION_Q * iadev->memSize) & 0xffff;
1523 writew(i, iadev->reass_reg+EXCP_Q_ST_ADR);
1524 writew(i + NUM_RX_EXCP * sizeof(RX_ERROR_Q),
1525 iadev->reass_reg+EXCP_Q_ED_ADR);
1526 writew(i, iadev->reass_reg+EXCP_Q_RD_PTR);
1527 writew(i, iadev->reass_reg+EXCP_Q_WR_PTR);
1528
1529 /* Load local copy of FREEQ and PCQ ptrs */
1530 iadev->rfL.fdq_st = readw(iadev->reass_reg+FREEQ_ST_ADR) & 0xffff;
1531 iadev->rfL.fdq_ed = readw(iadev->reass_reg+FREEQ_ED_ADR) & 0xffff ;
1532 iadev->rfL.fdq_rd = readw(iadev->reass_reg+FREEQ_RD_PTR) & 0xffff;
1533 iadev->rfL.fdq_wr = readw(iadev->reass_reg+FREEQ_WR_PTR) & 0xffff;
1534 iadev->rfL.pcq_st = readw(iadev->reass_reg+PCQ_ST_ADR) & 0xffff;
1535 iadev->rfL.pcq_ed = readw(iadev->reass_reg+PCQ_ED_ADR) & 0xffff;
1536 iadev->rfL.pcq_rd = readw(iadev->reass_reg+PCQ_RD_PTR) & 0xffff;
1537 iadev->rfL.pcq_wr = readw(iadev->reass_reg+PCQ_WR_PTR) & 0xffff;
1538
1539 IF_INIT(printk("INIT:pcq_st:0x%x pcq_ed:0x%x pcq_rd:0x%x pcq_wr:0x%x",
1540 iadev->rfL.pcq_st, iadev->rfL.pcq_ed, iadev->rfL.pcq_rd,
1541 iadev->rfL.pcq_wr);)
1542 /* just for check - no VP TBL */
1543 /* VP Table */
1544 /* writew(0x0b80, iadev->reass_reg+VP_LKUP_BASE); */
1545 /* initialize VP Table for invalid VPIs
1546 - I guess we can write all 1s or 0x000f in the entire memory
1547 space or something similar.
1548 */
1549
1550 /* This seems to work and looks right to me too !!! */
1551 i = REASS_TABLE * iadev->memSize;
1552 writew((i >> 3), iadev->reass_reg+REASS_TABLE_BASE);
1553 /* initialize Reassembly table to I don't know what ???? */
1554 reass_table = (u16 *)(iadev->reass_ram+i);
1555 j = REASS_TABLE_SZ * iadev->memSize;
1556 for(i=0; i < j; i++)
1557 *reass_table++ = NO_AAL5_PKT;
1558 i = 8*1024;
1559 vcsize_sel = 0;
1560 while (i != iadev->num_vc) {
1561 i /= 2;
1562 vcsize_sel++;
1563 }
1564 i = RX_VC_TABLE * iadev->memSize;
1565 writew(((i>>3) & 0xfff8) | vcsize_sel, iadev->reass_reg+VC_LKUP_BASE);
1566 vc_table = (u16 *)(iadev->reass_ram+RX_VC_TABLE*iadev->memSize);
1567 j = RX_VC_TABLE_SZ * iadev->memSize;
1568 for(i = 0; i < j; i++)
1569 {
1570 /* shift the reassembly pointer by 3 + lower 3 bits of
1571 vc_lkup_base register (=3 for 1K VCs) and the last byte
1572 is those low 3 bits.
1573 Shall program this later.
1574 */
1575 *vc_table = (i << 6) | 15; /* for invalid VCI */
1576 vc_table++;
1577 }
1578 /* ABR VC table */
1579 i = ABR_VC_TABLE * iadev->memSize;
1580 writew(i >> 3, iadev->reass_reg+ABR_LKUP_BASE);
1581
1582 i = ABR_VC_TABLE * iadev->memSize;
1583 abr_vc_table = (struct abr_vc_table *)(iadev->reass_ram+i);
1584 j = REASS_TABLE_SZ * iadev->memSize;
1585 memset ((char*)abr_vc_table, 0, j * sizeof(*abr_vc_table));
1586 for(i = 0; i < j; i++) {
1587 abr_vc_table->rdf = 0x0003;
1588 abr_vc_table->air = 0x5eb1;
1589 abr_vc_table++;
1590 }
1591
1592 /* Initialize other registers */
1593
1594 /* VP Filter Register set for VC Reassembly only */
1595 writew(0xff00, iadev->reass_reg+VP_FILTER);
1596 writew(0, iadev->reass_reg+XTRA_RM_OFFSET);
1597 writew(0x1, iadev->reass_reg+PROTOCOL_ID);
1598
1599 /* Packet Timeout Count related Registers :
1600 Set packet timeout to occur in about 3 seconds
1601 Set Packet Aging Interval count register to overflow in about 4 us
1602 */
1603 writew(0xF6F8, iadev->reass_reg+PKT_TM_CNT );
1604
1605 i = (j >> 6) & 0xFF;
1606 j += 2 * (j - 1);
1607 i |= ((j << 2) & 0xFF00);
1608 writew(i, iadev->reass_reg+TMOUT_RANGE);
1609
1610 /* initiate the desc_tble */
1611 for(i=0; i<iadev->num_tx_desc;i++)
1612 iadev->desc_tbl[i].timestamp = 0;
1613
1614 /* to clear the interrupt status register - read it */
1615 readw(iadev->reass_reg+REASS_INTR_STATUS_REG);
1616
1617 /* Mask Register - clear it */
1618 writew(~(RX_FREEQ_EMPT|RX_PKT_RCVD), iadev->reass_reg+REASS_MASK_REG);
1619
1620 skb_queue_head_init(&iadev->rx_dma_q);
1621 iadev->rx_free_desc_qhead = NULL;
1622
1623 iadev->rx_open = kcalloc(iadev->num_vc, sizeof(void *), GFP_KERNEL);
1624 if (!iadev->rx_open) {
1625 printk(KERN_ERR DEV_LABEL "itf %d couldn't get free page\n",
1626 dev->number);
1627 goto err_free_dle;
1628 }
1629
1630 iadev->rxing = 1;
1631 iadev->rx_pkt_cnt = 0;
1632 /* Mode Register */
1633 writew(R_ONLINE, iadev->reass_reg+MODE_REG);
1634 return 0;
1635
1636err_free_dle:
1637 dma_free_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE, iadev->rx_dle_q.start,
1638 iadev->rx_dle_dma);
1639err_out:
1640 return -ENOMEM;
1641}
1642
1643
1644/*
1645 The memory map suggested in appendix A and the coding for it.
1646 Keeping it around just in case we change our mind later.
1647
1648 Buffer descr 0x0000 (128 - 4K)
1649 UBR sched 0x1000 (1K - 4K)
1650 UBR Wait q 0x2000 (1K - 4K)
1651 Commn queues 0x3000 Packet Ready, Trasmit comp(0x3100)
1652 (128 - 256) each
1653 extended VC 0x4000 (1K - 8K)
1654 ABR sched 0x6000 and ABR wait queue (1K - 2K) each
1655 CBR sched 0x7000 (as needed)
1656 VC table 0x8000 (1K - 32K)
1657*/
1658
1659static void tx_intr(struct atm_dev *dev)
1660{
1661 IADEV *iadev;
1662 unsigned short status;
1663 unsigned long flags;
1664
1665 iadev = INPH_IA_DEV(dev);
1666
1667 status = readl(iadev->seg_reg+SEG_INTR_STATUS_REG);
1668 if (status & TRANSMIT_DONE){
1669
1670 IF_EVENT(printk("Transmit Done Intr logic run\n");)
1671 spin_lock_irqsave(&iadev->tx_lock, flags);
1672 ia_tx_poll(iadev);
1673 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1674 writew(TRANSMIT_DONE, iadev->seg_reg+SEG_INTR_STATUS_REG);
1675 if (iadev->close_pending)
1676 wake_up(&iadev->close_wait);
1677 }
1678 if (status & TCQ_NOT_EMPTY)
1679 {
1680 IF_EVENT(printk("TCQ_NOT_EMPTY int received\n");)
1681 }
1682}
1683
1684static void tx_dle_intr(struct atm_dev *dev)
1685{
1686 IADEV *iadev;
1687 struct dle *dle, *cur_dle;
1688 struct sk_buff *skb;
1689 struct atm_vcc *vcc;
1690 struct ia_vcc *iavcc;
1691 u_int dle_lp;
1692 unsigned long flags;
1693
1694 iadev = INPH_IA_DEV(dev);
1695 spin_lock_irqsave(&iadev->tx_lock, flags);
1696 dle = iadev->tx_dle_q.read;
1697 dle_lp = readl(iadev->dma+IPHASE5575_TX_LIST_ADDR) &
1698 (sizeof(struct dle)*DLE_ENTRIES - 1);
1699 cur_dle = (struct dle*)(iadev->tx_dle_q.start + (dle_lp >> 4));
1700 while (dle != cur_dle)
1701 {
1702 /* free the DMAed skb */
1703 skb = skb_dequeue(&iadev->tx_dma_q);
1704 if (!skb) break;
1705
1706 /* Revenge of the 2 dle (skb + trailer) used in ia_pkt_tx() */
1707 if (!((dle - iadev->tx_dle_q.start)%(2*sizeof(struct dle)))) {
1708 dma_unmap_single(&iadev->pci->dev, dle->sys_pkt_addr, skb->len,
1709 DMA_TO_DEVICE);
1710 }
1711 vcc = ATM_SKB(skb)->vcc;
1712 if (!vcc) {
1713 printk("tx_dle_intr: vcc is null\n");
1714 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1715 dev_kfree_skb_any(skb);
1716
1717 return;
1718 }
1719 iavcc = INPH_IA_VCC(vcc);
1720 if (!iavcc) {
1721 printk("tx_dle_intr: iavcc is null\n");
1722 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1723 dev_kfree_skb_any(skb);
1724 return;
1725 }
1726 if (vcc->qos.txtp.pcr >= iadev->rate_limit) {
1727 if ((vcc->pop) && (skb->len != 0))
1728 {
1729 vcc->pop(vcc, skb);
1730 }
1731 else {
1732 dev_kfree_skb_any(skb);
1733 }
1734 }
1735 else { /* Hold the rate-limited skb for flow control */
1736 IA_SKB_STATE(skb) |= IA_DLED;
1737 skb_queue_tail(&iavcc->txing_skb, skb);
1738 }
1739 IF_EVENT(printk("tx_dle_intr: enque skb = 0x%p \n", skb);)
1740 if (++dle == iadev->tx_dle_q.end)
1741 dle = iadev->tx_dle_q.start;
1742 }
1743 iadev->tx_dle_q.read = dle;
1744 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1745}
1746
1747static int open_tx(struct atm_vcc *vcc)
1748{
1749 struct ia_vcc *ia_vcc;
1750 IADEV *iadev;
1751 struct main_vc *vc;
1752 struct ext_vc *evc;
1753 int ret;
1754 IF_EVENT(printk("iadev: open_tx entered vcc->vci = %d\n", vcc->vci);)
1755 if (vcc->qos.txtp.traffic_class == ATM_NONE) return 0;
1756 iadev = INPH_IA_DEV(vcc->dev);
1757
1758 if (iadev->phy_type & FE_25MBIT_PHY) {
1759 if (vcc->qos.txtp.traffic_class == ATM_ABR) {
1760 printk("IA: ABR not support\n");
1761 return -EINVAL;
1762 }
1763 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1764 printk("IA: CBR not support\n");
1765 return -EINVAL;
1766 }
1767 }
1768 ia_vcc = INPH_IA_VCC(vcc);
1769 memset((caddr_t)ia_vcc, 0, sizeof(*ia_vcc));
1770 if (vcc->qos.txtp.max_sdu >
1771 (iadev->tx_buf_sz - sizeof(struct cpcs_trailer))){
1772 printk("IA: SDU size over (%d) the configured SDU size %d\n",
1773 vcc->qos.txtp.max_sdu,iadev->tx_buf_sz);
1774 vcc->dev_data = NULL;
1775 kfree(ia_vcc);
1776 return -EINVAL;
1777 }
1778 ia_vcc->vc_desc_cnt = 0;
1779 ia_vcc->txing = 1;
1780
1781 /* find pcr */
1782 if (vcc->qos.txtp.max_pcr == ATM_MAX_PCR)
1783 vcc->qos.txtp.pcr = iadev->LineRate;
1784 else if ((vcc->qos.txtp.max_pcr == 0)&&( vcc->qos.txtp.pcr <= 0))
1785 vcc->qos.txtp.pcr = iadev->LineRate;
1786 else if ((vcc->qos.txtp.max_pcr > vcc->qos.txtp.pcr) && (vcc->qos.txtp.max_pcr> 0))
1787 vcc->qos.txtp.pcr = vcc->qos.txtp.max_pcr;
1788 if (vcc->qos.txtp.pcr > iadev->LineRate)
1789 vcc->qos.txtp.pcr = iadev->LineRate;
1790 ia_vcc->pcr = vcc->qos.txtp.pcr;
1791
1792 if (ia_vcc->pcr > (iadev->LineRate / 6) ) ia_vcc->ltimeout = HZ / 10;
1793 else if (ia_vcc->pcr > (iadev->LineRate / 130)) ia_vcc->ltimeout = HZ;
1794 else if (ia_vcc->pcr <= 170) ia_vcc->ltimeout = 16 * HZ;
1795 else ia_vcc->ltimeout = 2700 * HZ / ia_vcc->pcr;
1796 if (ia_vcc->pcr < iadev->rate_limit)
1797 skb_queue_head_init (&ia_vcc->txing_skb);
1798 if (ia_vcc->pcr < iadev->rate_limit) {
1799 struct sock *sk = sk_atm(vcc);
1800
1801 if (vcc->qos.txtp.max_sdu != 0) {
1802 if (ia_vcc->pcr > 60000)
1803 sk->sk_sndbuf = vcc->qos.txtp.max_sdu * 5;
1804 else if (ia_vcc->pcr > 2000)
1805 sk->sk_sndbuf = vcc->qos.txtp.max_sdu * 4;
1806 else
1807 sk->sk_sndbuf = vcc->qos.txtp.max_sdu * 3;
1808 }
1809 else
1810 sk->sk_sndbuf = 24576;
1811 }
1812
1813 vc = (struct main_vc *)iadev->MAIN_VC_TABLE_ADDR;
1814 evc = (struct ext_vc *)iadev->EXT_VC_TABLE_ADDR;
1815 vc += vcc->vci;
1816 evc += vcc->vci;
1817 memset((caddr_t)vc, 0, sizeof(*vc));
1818 memset((caddr_t)evc, 0, sizeof(*evc));
1819
1820 /* store the most significant 4 bits of vci as the last 4 bits
1821 of first part of atm header.
1822 store the last 12 bits of vci as first 12 bits of the second
1823 part of the atm header.
1824 */
1825 evc->atm_hdr1 = (vcc->vci >> 12) & 0x000f;
1826 evc->atm_hdr2 = (vcc->vci & 0x0fff) << 4;
1827
1828 /* check the following for different traffic classes */
1829 if (vcc->qos.txtp.traffic_class == ATM_UBR)
1830 {
1831 vc->type = UBR;
1832 vc->status = CRC_APPEND;
1833 vc->acr = cellrate_to_float(iadev->LineRate);
1834 if (vcc->qos.txtp.pcr > 0)
1835 vc->acr = cellrate_to_float(vcc->qos.txtp.pcr);
1836 IF_UBR(printk("UBR: txtp.pcr = 0x%x f_rate = 0x%x\n",
1837 vcc->qos.txtp.max_pcr,vc->acr);)
1838 }
1839 else if (vcc->qos.txtp.traffic_class == ATM_ABR)
1840 { srv_cls_param_t srv_p;
1841 IF_ABR(printk("Tx ABR VCC\n");)
1842 init_abr_vc(iadev, &srv_p);
1843 if (vcc->qos.txtp.pcr > 0)
1844 srv_p.pcr = vcc->qos.txtp.pcr;
1845 if (vcc->qos.txtp.min_pcr > 0) {
1846 int tmpsum = iadev->sum_mcr+iadev->sum_cbr+vcc->qos.txtp.min_pcr;
1847 if (tmpsum > iadev->LineRate)
1848 return -EBUSY;
1849 srv_p.mcr = vcc->qos.txtp.min_pcr;
1850 iadev->sum_mcr += vcc->qos.txtp.min_pcr;
1851 }
1852 else srv_p.mcr = 0;
1853 if (vcc->qos.txtp.icr)
1854 srv_p.icr = vcc->qos.txtp.icr;
1855 if (vcc->qos.txtp.tbe)
1856 srv_p.tbe = vcc->qos.txtp.tbe;
1857 if (vcc->qos.txtp.frtt)
1858 srv_p.frtt = vcc->qos.txtp.frtt;
1859 if (vcc->qos.txtp.rif)
1860 srv_p.rif = vcc->qos.txtp.rif;
1861 if (vcc->qos.txtp.rdf)
1862 srv_p.rdf = vcc->qos.txtp.rdf;
1863 if (vcc->qos.txtp.nrm_pres)
1864 srv_p.nrm = vcc->qos.txtp.nrm;
1865 if (vcc->qos.txtp.trm_pres)
1866 srv_p.trm = vcc->qos.txtp.trm;
1867 if (vcc->qos.txtp.adtf_pres)
1868 srv_p.adtf = vcc->qos.txtp.adtf;
1869 if (vcc->qos.txtp.cdf_pres)
1870 srv_p.cdf = vcc->qos.txtp.cdf;
1871 if (srv_p.icr > srv_p.pcr)
1872 srv_p.icr = srv_p.pcr;
1873 IF_ABR(printk("ABR:vcc->qos.txtp.max_pcr = %d mcr = %d\n",
1874 srv_p.pcr, srv_p.mcr);)
1875 ia_open_abr_vc(iadev, &srv_p, vcc, 1);
1876 } else if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1877 if (iadev->phy_type & FE_25MBIT_PHY) {
1878 printk("IA: CBR not support\n");
1879 return -EINVAL;
1880 }
1881 if (vcc->qos.txtp.max_pcr > iadev->LineRate) {
1882 IF_CBR(printk("PCR is not available\n");)
1883 return -1;
1884 }
1885 vc->type = CBR;
1886 vc->status = CRC_APPEND;
1887 if ((ret = ia_cbr_setup (iadev, vcc)) < 0) {
1888 return ret;
1889 }
1890 } else {
1891 printk("iadev: Non UBR, ABR and CBR traffic not supported\n");
1892 }
1893
1894 iadev->testTable[vcc->vci]->vc_status |= VC_ACTIVE;
1895 IF_EVENT(printk("ia open_tx returning \n");)
1896 return 0;
1897}
1898
1899
1900static int tx_init(struct atm_dev *dev)
1901{
1902 IADEV *iadev;
1903 struct tx_buf_desc *buf_desc_ptr;
1904 unsigned int tx_pkt_start;
1905 void *dle_addr;
1906 int i;
1907 u_short tcq_st_adr;
1908 u_short *tcq_start;
1909 u_short prq_st_adr;
1910 u_short *prq_start;
1911 struct main_vc *vc;
1912 struct ext_vc *evc;
1913 u_short tmp16;
1914 u32 vcsize_sel;
1915
1916 iadev = INPH_IA_DEV(dev);
1917 spin_lock_init(&iadev->tx_lock);
1918
1919 IF_INIT(printk("Tx MASK REG: 0x%0x\n",
1920 readw(iadev->seg_reg+SEG_MASK_REG));)
1921
1922 /* Allocate 4k (boundary aligned) bytes */
1923 dle_addr = dma_alloc_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE,
1924 &iadev->tx_dle_dma, GFP_KERNEL);
1925 if (!dle_addr) {
1926 printk(KERN_ERR DEV_LABEL "can't allocate DLEs\n");
1927 goto err_out;
1928 }
1929 iadev->tx_dle_q.start = (struct dle*)dle_addr;
1930 iadev->tx_dle_q.read = iadev->tx_dle_q.start;
1931 iadev->tx_dle_q.write = iadev->tx_dle_q.start;
1932 iadev->tx_dle_q.end = (struct dle*)((unsigned long)dle_addr+sizeof(struct dle)*DLE_ENTRIES);
1933
1934 /* write the upper 20 bits of the start address to tx list address register */
1935 writel(iadev->tx_dle_dma & 0xfffff000,
1936 iadev->dma + IPHASE5575_TX_LIST_ADDR);
1937 writew(0xffff, iadev->seg_reg+SEG_MASK_REG);
1938 writew(0, iadev->seg_reg+MODE_REG_0);
1939 writew(RESET_SEG, iadev->seg_reg+SEG_COMMAND_REG);
1940 iadev->MAIN_VC_TABLE_ADDR = iadev->seg_ram+MAIN_VC_TABLE*iadev->memSize;
1941 iadev->EXT_VC_TABLE_ADDR = iadev->seg_ram+EXT_VC_TABLE*iadev->memSize;
1942 iadev->ABR_SCHED_TABLE_ADDR=iadev->seg_ram+ABR_SCHED_TABLE*iadev->memSize;
1943
1944 /*
1945 Transmit side control memory map
1946 --------------------------------
1947 Buffer descr 0x0000 (128 - 4K)
1948 Commn queues 0x1000 Transmit comp, Packet ready(0x1400)
1949 (512 - 1K) each
1950 TCQ - 4K, PRQ - 5K
1951 CBR Table 0x1800 (as needed) - 6K
1952 UBR Table 0x3000 (1K - 4K) - 12K
1953 UBR Wait queue 0x4000 (1K - 4K) - 16K
1954 ABR sched 0x5000 and ABR wait queue (1K - 2K) each
1955 ABR Tbl - 20K, ABR Wq - 22K
1956 extended VC 0x6000 (1K - 8K) - 24K
1957 VC Table 0x8000 (1K - 32K) - 32K
1958
1959 Between 0x2000 (8K) and 0x3000 (12K) there is 4K space left for VBR Tbl
1960 and Wait q, which can be allotted later.
1961 */
1962
1963 /* Buffer Descriptor Table Base address */
1964 writew(TX_DESC_BASE, iadev->seg_reg+SEG_DESC_BASE);
1965
1966 /* initialize each entry in the buffer descriptor table */
1967 buf_desc_ptr =(struct tx_buf_desc *)(iadev->seg_ram+TX_DESC_BASE);
1968 memset((caddr_t)buf_desc_ptr, 0, sizeof(*buf_desc_ptr));
1969 buf_desc_ptr++;
1970 tx_pkt_start = TX_PACKET_RAM;
1971 for(i=1; i<=iadev->num_tx_desc; i++)
1972 {
1973 memset((caddr_t)buf_desc_ptr, 0, sizeof(*buf_desc_ptr));
1974 buf_desc_ptr->desc_mode = AAL5;
1975 buf_desc_ptr->buf_start_hi = tx_pkt_start >> 16;
1976 buf_desc_ptr->buf_start_lo = tx_pkt_start & 0x0000ffff;
1977 buf_desc_ptr++;
1978 tx_pkt_start += iadev->tx_buf_sz;
1979 }
1980 iadev->tx_buf = kmalloc_array(iadev->num_tx_desc,
1981 sizeof(*iadev->tx_buf),
1982 GFP_KERNEL);
1983 if (!iadev->tx_buf) {
1984 printk(KERN_ERR DEV_LABEL " couldn't get mem\n");
1985 goto err_free_dle;
1986 }
1987 for (i= 0; i< iadev->num_tx_desc; i++)
1988 {
1989 struct cpcs_trailer *cpcs;
1990
1991 cpcs = kmalloc(sizeof(*cpcs), GFP_KERNEL|GFP_DMA);
1992 if(!cpcs) {
1993 printk(KERN_ERR DEV_LABEL " couldn't get freepage\n");
1994 goto err_free_tx_bufs;
1995 }
1996 iadev->tx_buf[i].cpcs = cpcs;
1997 iadev->tx_buf[i].dma_addr = dma_map_single(&iadev->pci->dev,
1998 cpcs,
1999 sizeof(*cpcs),
2000 DMA_TO_DEVICE);
2001 }
2002 iadev->desc_tbl = kmalloc_array(iadev->num_tx_desc,
2003 sizeof(*iadev->desc_tbl),
2004 GFP_KERNEL);
2005 if (!iadev->desc_tbl) {
2006 printk(KERN_ERR DEV_LABEL " couldn't get mem\n");
2007 goto err_free_all_tx_bufs;
2008 }
2009
2010 /* Communication Queues base address */
2011 i = TX_COMP_Q * iadev->memSize;
2012 writew(i >> 16, iadev->seg_reg+SEG_QUEUE_BASE);
2013
2014 /* Transmit Complete Queue */
2015 writew(i, iadev->seg_reg+TCQ_ST_ADR);
2016 writew(i, iadev->seg_reg+TCQ_RD_PTR);
2017 writew(i+iadev->num_tx_desc*sizeof(u_short),iadev->seg_reg+TCQ_WR_PTR);
2018 iadev->host_tcq_wr = i + iadev->num_tx_desc*sizeof(u_short);
2019 writew(i+2 * iadev->num_tx_desc * sizeof(u_short),
2020 iadev->seg_reg+TCQ_ED_ADR);
2021 /* Fill the TCQ with all the free descriptors. */
2022 tcq_st_adr = readw(iadev->seg_reg+TCQ_ST_ADR);
2023 tcq_start = (u_short *)(iadev->seg_ram+tcq_st_adr);
2024 for(i=1; i<=iadev->num_tx_desc; i++)
2025 {
2026 *tcq_start = (u_short)i;
2027 tcq_start++;
2028 }
2029
2030 /* Packet Ready Queue */
2031 i = PKT_RDY_Q * iadev->memSize;
2032 writew(i, iadev->seg_reg+PRQ_ST_ADR);
2033 writew(i+2 * iadev->num_tx_desc * sizeof(u_short),
2034 iadev->seg_reg+PRQ_ED_ADR);
2035 writew(i, iadev->seg_reg+PRQ_RD_PTR);
2036 writew(i, iadev->seg_reg+PRQ_WR_PTR);
2037
2038 /* Load local copy of PRQ and TCQ ptrs */
2039 iadev->ffL.prq_st = readw(iadev->seg_reg+PRQ_ST_ADR) & 0xffff;
2040 iadev->ffL.prq_ed = readw(iadev->seg_reg+PRQ_ED_ADR) & 0xffff;
2041 iadev->ffL.prq_wr = readw(iadev->seg_reg+PRQ_WR_PTR) & 0xffff;
2042
2043 iadev->ffL.tcq_st = readw(iadev->seg_reg+TCQ_ST_ADR) & 0xffff;
2044 iadev->ffL.tcq_ed = readw(iadev->seg_reg+TCQ_ED_ADR) & 0xffff;
2045 iadev->ffL.tcq_rd = readw(iadev->seg_reg+TCQ_RD_PTR) & 0xffff;
2046
2047 /* Just for safety initializing the queue to have desc 1 always */
2048 /* Fill the PRQ with all the free descriptors. */
2049 prq_st_adr = readw(iadev->seg_reg+PRQ_ST_ADR);
2050 prq_start = (u_short *)(iadev->seg_ram+prq_st_adr);
2051 for(i=1; i<=iadev->num_tx_desc; i++)
2052 {
2053 *prq_start = (u_short)0; /* desc 1 in all entries */
2054 prq_start++;
2055 }
2056 /* CBR Table */
2057 IF_INIT(printk("Start CBR Init\n");)
2058#if 1 /* for 1K VC board, CBR_PTR_BASE is 0 */
2059 writew(0,iadev->seg_reg+CBR_PTR_BASE);
2060#else /* Charlie's logic is wrong ? */
2061 tmp16 = (iadev->seg_ram+CBR_SCHED_TABLE*iadev->memSize)>>17;
2062 IF_INIT(printk("cbr_ptr_base = 0x%x ", tmp16);)
2063 writew(tmp16,iadev->seg_reg+CBR_PTR_BASE);
2064#endif
2065
2066 IF_INIT(printk("value in register = 0x%x\n",
2067 readw(iadev->seg_reg+CBR_PTR_BASE));)
2068 tmp16 = (CBR_SCHED_TABLE*iadev->memSize) >> 1;
2069 writew(tmp16, iadev->seg_reg+CBR_TAB_BEG);
2070 IF_INIT(printk("cbr_tab_beg = 0x%x in reg = 0x%x \n", tmp16,
2071 readw(iadev->seg_reg+CBR_TAB_BEG));)
2072 writew(tmp16, iadev->seg_reg+CBR_TAB_END+1); // CBR_PTR;
2073 tmp16 = (CBR_SCHED_TABLE*iadev->memSize + iadev->num_vc*6 - 2) >> 1;
2074 writew(tmp16, iadev->seg_reg+CBR_TAB_END);
2075 IF_INIT(printk("iadev->seg_reg = 0x%p CBR_PTR_BASE = 0x%x\n",
2076 iadev->seg_reg, readw(iadev->seg_reg+CBR_PTR_BASE));)
2077 IF_INIT(printk("CBR_TAB_BEG = 0x%x, CBR_TAB_END = 0x%x, CBR_PTR = 0x%x\n",
2078 readw(iadev->seg_reg+CBR_TAB_BEG), readw(iadev->seg_reg+CBR_TAB_END),
2079 readw(iadev->seg_reg+CBR_TAB_END+1));)
2080
2081 /* Initialize the CBR Schedualing Table */
2082 memset_io(iadev->seg_ram+CBR_SCHED_TABLE*iadev->memSize,
2083 0, iadev->num_vc*6);
2084 iadev->CbrRemEntries = iadev->CbrTotEntries = iadev->num_vc*3;
2085 iadev->CbrEntryPt = 0;
2086 iadev->Granularity = MAX_ATM_155 / iadev->CbrTotEntries;
2087 iadev->NumEnabledCBR = 0;
2088
2089 /* UBR scheduling Table and wait queue */
2090 /* initialize all bytes of UBR scheduler table and wait queue to 0
2091 - SCHEDSZ is 1K (# of entries).
2092 - UBR Table size is 4K
2093 - UBR wait queue is 4K
2094 since the table and wait queues are contiguous, all the bytes
2095 can be initialized by one memeset.
2096 */
2097
2098 vcsize_sel = 0;
2099 i = 8*1024;
2100 while (i != iadev->num_vc) {
2101 i /= 2;
2102 vcsize_sel++;
2103 }
2104
2105 i = MAIN_VC_TABLE * iadev->memSize;
2106 writew(vcsize_sel | ((i >> 8) & 0xfff8),iadev->seg_reg+VCT_BASE);
2107 i = EXT_VC_TABLE * iadev->memSize;
2108 writew((i >> 8) & 0xfffe, iadev->seg_reg+VCTE_BASE);
2109 i = UBR_SCHED_TABLE * iadev->memSize;
2110 writew((i & 0xffff) >> 11, iadev->seg_reg+UBR_SBPTR_BASE);
2111 i = UBR_WAIT_Q * iadev->memSize;
2112 writew((i >> 7) & 0xffff, iadev->seg_reg+UBRWQ_BASE);
2113 memset((caddr_t)(iadev->seg_ram+UBR_SCHED_TABLE*iadev->memSize),
2114 0, iadev->num_vc*8);
2115 /* ABR scheduling Table(0x5000-0x57ff) and wait queue(0x5800-0x5fff)*/
2116 /* initialize all bytes of ABR scheduler table and wait queue to 0
2117 - SCHEDSZ is 1K (# of entries).
2118 - ABR Table size is 2K
2119 - ABR wait queue is 2K
2120 since the table and wait queues are contiguous, all the bytes
2121 can be initialized by one memeset.
2122 */
2123 i = ABR_SCHED_TABLE * iadev->memSize;
2124 writew((i >> 11) & 0xffff, iadev->seg_reg+ABR_SBPTR_BASE);
2125 i = ABR_WAIT_Q * iadev->memSize;
2126 writew((i >> 7) & 0xffff, iadev->seg_reg+ABRWQ_BASE);
2127
2128 i = ABR_SCHED_TABLE*iadev->memSize;
2129 memset((caddr_t)(iadev->seg_ram+i), 0, iadev->num_vc*4);
2130 vc = (struct main_vc *)iadev->MAIN_VC_TABLE_ADDR;
2131 evc = (struct ext_vc *)iadev->EXT_VC_TABLE_ADDR;
2132 iadev->testTable = kmalloc_array(iadev->num_vc,
2133 sizeof(*iadev->testTable),
2134 GFP_KERNEL);
2135 if (!iadev->testTable) {
2136 printk("Get freepage failed\n");
2137 goto err_free_desc_tbl;
2138 }
2139 for(i=0; i<iadev->num_vc; i++)
2140 {
2141 memset((caddr_t)vc, 0, sizeof(*vc));
2142 memset((caddr_t)evc, 0, sizeof(*evc));
2143 iadev->testTable[i] = kmalloc(sizeof(struct testTable_t),
2144 GFP_KERNEL);
2145 if (!iadev->testTable[i])
2146 goto err_free_test_tables;
2147 iadev->testTable[i]->lastTime = 0;
2148 iadev->testTable[i]->fract = 0;
2149 iadev->testTable[i]->vc_status = VC_UBR;
2150 vc++;
2151 evc++;
2152 }
2153
2154 /* Other Initialization */
2155
2156 /* Max Rate Register */
2157 if (iadev->phy_type & FE_25MBIT_PHY) {
2158 writew(RATE25, iadev->seg_reg+MAXRATE);
2159 writew((UBR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS);
2160 }
2161 else {
2162 writew(cellrate_to_float(iadev->LineRate),iadev->seg_reg+MAXRATE);
2163 writew((UBR_EN | ABR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS);
2164 }
2165 /* Set Idle Header Reigisters to be sure */
2166 writew(0, iadev->seg_reg+IDLEHEADHI);
2167 writew(0, iadev->seg_reg+IDLEHEADLO);
2168
2169 /* Program ABR UBR Priority Register as PRI_ABR_UBR_EQUAL */
2170 writew(0xaa00, iadev->seg_reg+ABRUBR_ARB);
2171
2172 iadev->close_pending = 0;
2173 init_waitqueue_head(&iadev->close_wait);
2174 init_waitqueue_head(&iadev->timeout_wait);
2175 skb_queue_head_init(&iadev->tx_dma_q);
2176 ia_init_rtn_q(&iadev->tx_return_q);
2177
2178 /* RM Cell Protocol ID and Message Type */
2179 writew(RM_TYPE_4_0, iadev->seg_reg+RM_TYPE);
2180 skb_queue_head_init (&iadev->tx_backlog);
2181
2182 /* Mode Register 1 */
2183 writew(MODE_REG_1_VAL, iadev->seg_reg+MODE_REG_1);
2184
2185 /* Mode Register 0 */
2186 writew(T_ONLINE, iadev->seg_reg+MODE_REG_0);
2187
2188 /* Interrupt Status Register - read to clear */
2189 readw(iadev->seg_reg+SEG_INTR_STATUS_REG);
2190
2191 /* Interrupt Mask Reg- don't mask TCQ_NOT_EMPTY interrupt generation */
2192 writew(~(TRANSMIT_DONE | TCQ_NOT_EMPTY), iadev->seg_reg+SEG_MASK_REG);
2193 writew(TRANSMIT_DONE, iadev->seg_reg+SEG_INTR_STATUS_REG);
2194 iadev->tx_pkt_cnt = 0;
2195 iadev->rate_limit = iadev->LineRate / 3;
2196
2197 return 0;
2198
2199err_free_test_tables:
2200 while (--i >= 0)
2201 kfree(iadev->testTable[i]);
2202 kfree(iadev->testTable);
2203err_free_desc_tbl:
2204 kfree(iadev->desc_tbl);
2205err_free_all_tx_bufs:
2206 i = iadev->num_tx_desc;
2207err_free_tx_bufs:
2208 while (--i >= 0) {
2209 struct cpcs_trailer_desc *desc = iadev->tx_buf + i;
2210
2211 dma_unmap_single(&iadev->pci->dev, desc->dma_addr,
2212 sizeof(*desc->cpcs), DMA_TO_DEVICE);
2213 kfree(desc->cpcs);
2214 }
2215 kfree(iadev->tx_buf);
2216err_free_dle:
2217 dma_free_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE, iadev->tx_dle_q.start,
2218 iadev->tx_dle_dma);
2219err_out:
2220 return -ENOMEM;
2221}
2222
2223static irqreturn_t ia_int(int irq, void *dev_id)
2224{
2225 struct atm_dev *dev;
2226 IADEV *iadev;
2227 unsigned int status;
2228 int handled = 0;
2229
2230 dev = dev_id;
2231 iadev = INPH_IA_DEV(dev);
2232 while( (status = readl(iadev->reg+IPHASE5575_BUS_STATUS_REG) & 0x7f))
2233 {
2234 handled = 1;
2235 IF_EVENT(printk("ia_int: status = 0x%x\n", status);)
2236 if (status & STAT_REASSINT)
2237 {
2238 /* do something */
2239 IF_EVENT(printk("REASSINT Bus status reg: %08x\n", status);)
2240 rx_intr(dev);
2241 }
2242 if (status & STAT_DLERINT)
2243 {
2244 /* Clear this bit by writing a 1 to it. */
2245 writel(STAT_DLERINT, iadev->reg + IPHASE5575_BUS_STATUS_REG);
2246 rx_dle_intr(dev);
2247 }
2248 if (status & STAT_SEGINT)
2249 {
2250 /* do something */
2251 IF_EVENT(printk("IA: tx_intr \n");)
2252 tx_intr(dev);
2253 }
2254 if (status & STAT_DLETINT)
2255 {
2256 writel(STAT_DLETINT, iadev->reg + IPHASE5575_BUS_STATUS_REG);
2257 tx_dle_intr(dev);
2258 }
2259 if (status & (STAT_FEINT | STAT_ERRINT | STAT_MARKINT))
2260 {
2261 if (status & STAT_FEINT)
2262 ia_frontend_intr(iadev);
2263 }
2264 }
2265 return IRQ_RETVAL(handled);
2266}
2267
2268
2269
2270/*----------------------------- entries --------------------------------*/
2271static int get_esi(struct atm_dev *dev)
2272{
2273 IADEV *iadev;
2274 int i;
2275 u32 mac1;
2276 u16 mac2;
2277
2278 iadev = INPH_IA_DEV(dev);
2279 mac1 = cpu_to_be32(le32_to_cpu(readl(
2280 iadev->reg+IPHASE5575_MAC1)));
2281 mac2 = cpu_to_be16(le16_to_cpu(readl(iadev->reg+IPHASE5575_MAC2)));
2282 IF_INIT(printk("ESI: 0x%08x%04x\n", mac1, mac2);)
2283 for (i=0; i<MAC1_LEN; i++)
2284 dev->esi[i] = mac1 >>(8*(MAC1_LEN-1-i));
2285
2286 for (i=0; i<MAC2_LEN; i++)
2287 dev->esi[i+MAC1_LEN] = mac2 >>(8*(MAC2_LEN - 1 -i));
2288 return 0;
2289}
2290
2291static int reset_sar(struct atm_dev *dev)
2292{
2293 IADEV *iadev;
2294 int i, error = 1;
2295 unsigned int pci[64];
2296
2297 iadev = INPH_IA_DEV(dev);
2298 for(i=0; i<64; i++)
2299 if ((error = pci_read_config_dword(iadev->pci,
2300 i*4, &pci[i])) != PCIBIOS_SUCCESSFUL)
2301 return error;
2302 writel(0, iadev->reg+IPHASE5575_EXT_RESET);
2303 for(i=0; i<64; i++)
2304 if ((error = pci_write_config_dword(iadev->pci,
2305 i*4, pci[i])) != PCIBIOS_SUCCESSFUL)
2306 return error;
2307 udelay(5);
2308 return 0;
2309}
2310
2311
2312static int ia_init(struct atm_dev *dev)
2313{
2314 IADEV *iadev;
2315 unsigned long real_base;
2316 void __iomem *base;
2317 unsigned short command;
2318 int error, i;
2319
2320 /* The device has been identified and registered. Now we read
2321 necessary configuration info like memory base address,
2322 interrupt number etc */
2323
2324 IF_INIT(printk(">ia_init\n");)
2325 dev->ci_range.vpi_bits = 0;
2326 dev->ci_range.vci_bits = NR_VCI_LD;
2327
2328 iadev = INPH_IA_DEV(dev);
2329 real_base = pci_resource_start (iadev->pci, 0);
2330 iadev->irq = iadev->pci->irq;
2331
2332 error = pci_read_config_word(iadev->pci, PCI_COMMAND, &command);
2333 if (error) {
2334 printk(KERN_ERR DEV_LABEL "(itf %d): init error 0x%x\n",
2335 dev->number,error);
2336 return -EINVAL;
2337 }
2338 IF_INIT(printk(DEV_LABEL "(itf %d): rev.%d,realbase=0x%lx,irq=%d\n",
2339 dev->number, iadev->pci->revision, real_base, iadev->irq);)
2340
2341 /* find mapping size of board */
2342
2343 iadev->pci_map_size = pci_resource_len(iadev->pci, 0);
2344
2345 if (iadev->pci_map_size == 0x100000){
2346 iadev->num_vc = 4096;
2347 dev->ci_range.vci_bits = NR_VCI_4K_LD;
2348 iadev->memSize = 4;
2349 }
2350 else if (iadev->pci_map_size == 0x40000) {
2351 iadev->num_vc = 1024;
2352 iadev->memSize = 1;
2353 }
2354 else {
2355 printk("Unknown pci_map_size = 0x%x\n", iadev->pci_map_size);
2356 return -EINVAL;
2357 }
2358 IF_INIT(printk (DEV_LABEL "map size: %i\n", iadev->pci_map_size);)
2359
2360 /* enable bus mastering */
2361 pci_set_master(iadev->pci);
2362
2363 /*
2364 * Delay at least 1us before doing any mem accesses (how 'bout 10?)
2365 */
2366 udelay(10);
2367
2368 /* mapping the physical address to a virtual address in address space */
2369 base = ioremap(real_base,iadev->pci_map_size); /* ioremap is not resolved ??? */
2370
2371 if (!base)
2372 {
2373 printk(DEV_LABEL " (itf %d): can't set up page mapping\n",
2374 dev->number);
2375 return -ENOMEM;
2376 }
2377 IF_INIT(printk(DEV_LABEL " (itf %d): rev.%d,base=%p,irq=%d\n",
2378 dev->number, iadev->pci->revision, base, iadev->irq);)
2379
2380 /* filling the iphase dev structure */
2381 iadev->mem = iadev->pci_map_size /2;
2382 iadev->real_base = real_base;
2383 iadev->base = base;
2384
2385 /* Bus Interface Control Registers */
2386 iadev->reg = base + REG_BASE;
2387 /* Segmentation Control Registers */
2388 iadev->seg_reg = base + SEG_BASE;
2389 /* Reassembly Control Registers */
2390 iadev->reass_reg = base + REASS_BASE;
2391 /* Front end/ DMA control registers */
2392 iadev->phy = base + PHY_BASE;
2393 iadev->dma = base + PHY_BASE;
2394 /* RAM - Segmentation RAm and Reassembly RAM */
2395 iadev->ram = base + ACTUAL_RAM_BASE;
2396 iadev->seg_ram = base + ACTUAL_SEG_RAM_BASE;
2397 iadev->reass_ram = base + ACTUAL_REASS_RAM_BASE;
2398
2399 /* lets print out the above */
2400 IF_INIT(printk("Base addrs: %p %p %p \n %p %p %p %p\n",
2401 iadev->reg,iadev->seg_reg,iadev->reass_reg,
2402 iadev->phy, iadev->ram, iadev->seg_ram,
2403 iadev->reass_ram);)
2404
2405 /* lets try reading the MAC address */
2406 error = get_esi(dev);
2407 if (error) {
2408 iounmap(iadev->base);
2409 return error;
2410 }
2411 printk("IA: ");
2412 for (i=0; i < ESI_LEN; i++)
2413 printk("%s%02X",i ? "-" : "",dev->esi[i]);
2414 printk("\n");
2415
2416 /* reset SAR */
2417 if (reset_sar(dev)) {
2418 iounmap(iadev->base);
2419 printk("IA: reset SAR fail, please try again\n");
2420 return 1;
2421 }
2422 return 0;
2423}
2424
2425static void ia_update_stats(IADEV *iadev) {
2426 if (!iadev->carrier_detect)
2427 return;
2428 iadev->rx_cell_cnt += readw(iadev->reass_reg+CELL_CTR0)&0xffff;
2429 iadev->rx_cell_cnt += (readw(iadev->reass_reg+CELL_CTR1) & 0xffff) << 16;
2430 iadev->drop_rxpkt += readw(iadev->reass_reg + DRP_PKT_CNTR ) & 0xffff;
2431 iadev->drop_rxcell += readw(iadev->reass_reg + ERR_CNTR) & 0xffff;
2432 iadev->tx_cell_cnt += readw(iadev->seg_reg + CELL_CTR_LO_AUTO)&0xffff;
2433 iadev->tx_cell_cnt += (readw(iadev->seg_reg+CELL_CTR_HIGH_AUTO)&0xffff)<<16;
2434 return;
2435}
2436
2437static void ia_led_timer(struct timer_list *unused) {
2438 unsigned long flags;
2439 static u_char blinking[8] = {0, 0, 0, 0, 0, 0, 0, 0};
2440 u_char i;
2441 static u32 ctrl_reg;
2442 for (i = 0; i < iadev_count; i++) {
2443 if (ia_dev[i]) {
2444 ctrl_reg = readl(ia_dev[i]->reg+IPHASE5575_BUS_CONTROL_REG);
2445 if (blinking[i] == 0) {
2446 blinking[i]++;
2447 ctrl_reg &= (~CTRL_LED);
2448 writel(ctrl_reg, ia_dev[i]->reg+IPHASE5575_BUS_CONTROL_REG);
2449 ia_update_stats(ia_dev[i]);
2450 }
2451 else {
2452 blinking[i] = 0;
2453 ctrl_reg |= CTRL_LED;
2454 writel(ctrl_reg, ia_dev[i]->reg+IPHASE5575_BUS_CONTROL_REG);
2455 spin_lock_irqsave(&ia_dev[i]->tx_lock, flags);
2456 if (ia_dev[i]->close_pending)
2457 wake_up(&ia_dev[i]->close_wait);
2458 ia_tx_poll(ia_dev[i]);
2459 spin_unlock_irqrestore(&ia_dev[i]->tx_lock, flags);
2460 }
2461 }
2462 }
2463 mod_timer(&ia_timer, jiffies + HZ / 4);
2464 return;
2465}
2466
2467static void ia_phy_put(struct atm_dev *dev, unsigned char value,
2468 unsigned long addr)
2469{
2470 writel(value, INPH_IA_DEV(dev)->phy+addr);
2471}
2472
2473static unsigned char ia_phy_get(struct atm_dev *dev, unsigned long addr)
2474{
2475 return readl(INPH_IA_DEV(dev)->phy+addr);
2476}
2477
2478static void ia_free_tx(IADEV *iadev)
2479{
2480 int i;
2481
2482 kfree(iadev->desc_tbl);
2483 for (i = 0; i < iadev->num_vc; i++)
2484 kfree(iadev->testTable[i]);
2485 kfree(iadev->testTable);
2486 for (i = 0; i < iadev->num_tx_desc; i++) {
2487 struct cpcs_trailer_desc *desc = iadev->tx_buf + i;
2488
2489 dma_unmap_single(&iadev->pci->dev, desc->dma_addr,
2490 sizeof(*desc->cpcs), DMA_TO_DEVICE);
2491 kfree(desc->cpcs);
2492 }
2493 kfree(iadev->tx_buf);
2494 dma_free_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE, iadev->tx_dle_q.start,
2495 iadev->tx_dle_dma);
2496}
2497
2498static void ia_free_rx(IADEV *iadev)
2499{
2500 kfree(iadev->rx_open);
2501 dma_free_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE, iadev->rx_dle_q.start,
2502 iadev->rx_dle_dma);
2503}
2504
2505static int ia_start(struct atm_dev *dev)
2506{
2507 IADEV *iadev;
2508 int error;
2509 unsigned char phy;
2510 u32 ctrl_reg;
2511 IF_EVENT(printk(">ia_start\n");)
2512 iadev = INPH_IA_DEV(dev);
2513 if (request_irq(iadev->irq, &ia_int, IRQF_SHARED, DEV_LABEL, dev)) {
2514 printk(KERN_ERR DEV_LABEL "(itf %d): IRQ%d is already in use\n",
2515 dev->number, iadev->irq);
2516 error = -EAGAIN;
2517 goto err_out;
2518 }
2519 /* @@@ should release IRQ on error */
2520 /* enabling memory + master */
2521 if ((error = pci_write_config_word(iadev->pci,
2522 PCI_COMMAND,
2523 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER )))
2524 {
2525 printk(KERN_ERR DEV_LABEL "(itf %d): can't enable memory+"
2526 "master (0x%x)\n",dev->number, error);
2527 error = -EIO;
2528 goto err_free_irq;
2529 }
2530 udelay(10);
2531
2532 /* Maybe we should reset the front end, initialize Bus Interface Control
2533 Registers and see. */
2534
2535 IF_INIT(printk("Bus ctrl reg: %08x\n",
2536 readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG));)
2537 ctrl_reg = readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2538 ctrl_reg = (ctrl_reg & (CTRL_LED | CTRL_FE_RST))
2539 | CTRL_B8
2540 | CTRL_B16
2541 | CTRL_B32
2542 | CTRL_B48
2543 | CTRL_B64
2544 | CTRL_B128
2545 | CTRL_ERRMASK
2546 | CTRL_DLETMASK /* shud be removed l8r */
2547 | CTRL_DLERMASK
2548 | CTRL_SEGMASK
2549 | CTRL_REASSMASK
2550 | CTRL_FEMASK
2551 | CTRL_CSPREEMPT;
2552
2553 writel(ctrl_reg, iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2554
2555 IF_INIT(printk("Bus ctrl reg after initializing: %08x\n",
2556 readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG));
2557 printk("Bus status reg after init: %08x\n",
2558 readl(iadev->reg+IPHASE5575_BUS_STATUS_REG));)
2559
2560 ia_hw_type(iadev);
2561 error = tx_init(dev);
2562 if (error)
2563 goto err_free_irq;
2564 error = rx_init(dev);
2565 if (error)
2566 goto err_free_tx;
2567
2568 ctrl_reg = readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2569 writel(ctrl_reg | CTRL_FE_RST, iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2570 IF_INIT(printk("Bus ctrl reg after initializing: %08x\n",
2571 readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG));)
2572 phy = 0; /* resolve compiler complaint */
2573 IF_INIT (
2574 if ((phy=ia_phy_get(dev,0)) == 0x30)
2575 printk("IA: pm5346,rev.%d\n",phy&0x0f);
2576 else
2577 printk("IA: utopia,rev.%0x\n",phy);)
2578
2579 if (iadev->phy_type & FE_25MBIT_PHY)
2580 ia_mb25_init(iadev);
2581 else if (iadev->phy_type & (FE_DS3_PHY | FE_E3_PHY))
2582 ia_suni_pm7345_init(iadev);
2583 else {
2584 error = suni_init(dev);
2585 if (error)
2586 goto err_free_rx;
2587 if (dev->phy->start) {
2588 error = dev->phy->start(dev);
2589 if (error)
2590 goto err_free_rx;
2591 }
2592 /* Get iadev->carrier_detect status */
2593 ia_frontend_intr(iadev);
2594 }
2595 return 0;
2596
2597err_free_rx:
2598 ia_free_rx(iadev);
2599err_free_tx:
2600 ia_free_tx(iadev);
2601err_free_irq:
2602 free_irq(iadev->irq, dev);
2603err_out:
2604 return error;
2605}
2606
2607static void ia_close(struct atm_vcc *vcc)
2608{
2609 DEFINE_WAIT(wait);
2610 u16 *vc_table;
2611 IADEV *iadev;
2612 struct ia_vcc *ia_vcc;
2613 struct sk_buff *skb = NULL;
2614 struct sk_buff_head tmp_tx_backlog, tmp_vcc_backlog;
2615 unsigned long closetime, flags;
2616
2617 iadev = INPH_IA_DEV(vcc->dev);
2618 ia_vcc = INPH_IA_VCC(vcc);
2619 if (!ia_vcc) return;
2620
2621 IF_EVENT(printk("ia_close: ia_vcc->vc_desc_cnt = %d vci = %d\n",
2622 ia_vcc->vc_desc_cnt,vcc->vci);)
2623 clear_bit(ATM_VF_READY,&vcc->flags);
2624 skb_queue_head_init (&tmp_tx_backlog);
2625 skb_queue_head_init (&tmp_vcc_backlog);
2626 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
2627 iadev->close_pending++;
2628 prepare_to_wait(&iadev->timeout_wait, &wait, TASK_UNINTERRUPTIBLE);
2629 schedule_timeout(msecs_to_jiffies(500));
2630 finish_wait(&iadev->timeout_wait, &wait);
2631 spin_lock_irqsave(&iadev->tx_lock, flags);
2632 while((skb = skb_dequeue(&iadev->tx_backlog))) {
2633 if (ATM_SKB(skb)->vcc == vcc){
2634 if (vcc->pop) vcc->pop(vcc, skb);
2635 else dev_kfree_skb_any(skb);
2636 }
2637 else
2638 skb_queue_tail(&tmp_tx_backlog, skb);
2639 }
2640 while((skb = skb_dequeue(&tmp_tx_backlog)))
2641 skb_queue_tail(&iadev->tx_backlog, skb);
2642 IF_EVENT(printk("IA TX Done decs_cnt = %d\n", ia_vcc->vc_desc_cnt);)
2643 closetime = 300000 / ia_vcc->pcr;
2644 if (closetime == 0)
2645 closetime = 1;
2646 spin_unlock_irqrestore(&iadev->tx_lock, flags);
2647 wait_event_timeout(iadev->close_wait, (ia_vcc->vc_desc_cnt <= 0), closetime);
2648 spin_lock_irqsave(&iadev->tx_lock, flags);
2649 iadev->close_pending--;
2650 iadev->testTable[vcc->vci]->lastTime = 0;
2651 iadev->testTable[vcc->vci]->fract = 0;
2652 iadev->testTable[vcc->vci]->vc_status = VC_UBR;
2653 if (vcc->qos.txtp.traffic_class == ATM_ABR) {
2654 if (vcc->qos.txtp.min_pcr > 0)
2655 iadev->sum_mcr -= vcc->qos.txtp.min_pcr;
2656 }
2657 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
2658 ia_vcc = INPH_IA_VCC(vcc);
2659 iadev->sum_mcr -= ia_vcc->NumCbrEntry*iadev->Granularity;
2660 ia_cbrVc_close (vcc);
2661 }
2662 spin_unlock_irqrestore(&iadev->tx_lock, flags);
2663 }
2664
2665 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
2666 // reset reass table
2667 vc_table = (u16 *)(iadev->reass_ram+REASS_TABLE*iadev->memSize);
2668 vc_table += vcc->vci;
2669 *vc_table = NO_AAL5_PKT;
2670 // reset vc table
2671 vc_table = (u16 *)(iadev->reass_ram+RX_VC_TABLE*iadev->memSize);
2672 vc_table += vcc->vci;
2673 *vc_table = (vcc->vci << 6) | 15;
2674 if (vcc->qos.rxtp.traffic_class == ATM_ABR) {
2675 struct abr_vc_table __iomem *abr_vc_table =
2676 (iadev->reass_ram+ABR_VC_TABLE*iadev->memSize);
2677 abr_vc_table += vcc->vci;
2678 abr_vc_table->rdf = 0x0003;
2679 abr_vc_table->air = 0x5eb1;
2680 }
2681 // Drain the packets
2682 rx_dle_intr(vcc->dev);
2683 iadev->rx_open[vcc->vci] = NULL;
2684 }
2685 kfree(INPH_IA_VCC(vcc));
2686 ia_vcc = NULL;
2687 vcc->dev_data = NULL;
2688 clear_bit(ATM_VF_ADDR,&vcc->flags);
2689 return;
2690}
2691
2692static int ia_open(struct atm_vcc *vcc)
2693{
2694 struct ia_vcc *ia_vcc;
2695 int error;
2696 if (!test_bit(ATM_VF_PARTIAL,&vcc->flags))
2697 {
2698 IF_EVENT(printk("ia: not partially allocated resources\n");)
2699 vcc->dev_data = NULL;
2700 }
2701 if (vcc->vci != ATM_VPI_UNSPEC && vcc->vpi != ATM_VCI_UNSPEC)
2702 {
2703 IF_EVENT(printk("iphase open: unspec part\n");)
2704 set_bit(ATM_VF_ADDR,&vcc->flags);
2705 }
2706 if (vcc->qos.aal != ATM_AAL5)
2707 return -EINVAL;
2708 IF_EVENT(printk(DEV_LABEL "(itf %d): open %d.%d\n",
2709 vcc->dev->number, vcc->vpi, vcc->vci);)
2710
2711 /* Device dependent initialization */
2712 ia_vcc = kmalloc(sizeof(*ia_vcc), GFP_KERNEL);
2713 if (!ia_vcc) return -ENOMEM;
2714 vcc->dev_data = ia_vcc;
2715
2716 if ((error = open_rx(vcc)))
2717 {
2718 IF_EVENT(printk("iadev: error in open_rx, closing\n");)
2719 ia_close(vcc);
2720 return error;
2721 }
2722
2723 if ((error = open_tx(vcc)))
2724 {
2725 IF_EVENT(printk("iadev: error in open_tx, closing\n");)
2726 ia_close(vcc);
2727 return error;
2728 }
2729
2730 set_bit(ATM_VF_READY,&vcc->flags);
2731
2732#if 0
2733 {
2734 static u8 first = 1;
2735 if (first) {
2736 ia_timer.expires = jiffies + 3*HZ;
2737 add_timer(&ia_timer);
2738 first = 0;
2739 }
2740 }
2741#endif
2742 IF_EVENT(printk("ia open returning\n");)
2743 return 0;
2744}
2745
2746static int ia_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags)
2747{
2748 IF_EVENT(printk(">ia_change_qos\n");)
2749 return 0;
2750}
2751
2752static int ia_ioctl(struct atm_dev *dev, unsigned int cmd, void __user *arg)
2753{
2754 IA_CMDBUF ia_cmds;
2755 IADEV *iadev;
2756 int i, board;
2757 u16 __user *tmps;
2758 IF_EVENT(printk(">ia_ioctl\n");)
2759 if (cmd != IA_CMD) {
2760 if (!dev->phy->ioctl) return -EINVAL;
2761 return dev->phy->ioctl(dev,cmd,arg);
2762 }
2763 if (copy_from_user(&ia_cmds, arg, sizeof ia_cmds)) return -EFAULT;
2764 board = ia_cmds.status;
2765
2766 if ((board < 0) || (board > iadev_count))
2767 board = 0;
2768 board = array_index_nospec(board, iadev_count + 1);
2769
2770 iadev = ia_dev[board];
2771 switch (ia_cmds.cmd) {
2772 case MEMDUMP:
2773 {
2774 switch (ia_cmds.sub_cmd) {
2775 case MEMDUMP_SEGREG:
2776 if (!capable(CAP_NET_ADMIN)) return -EPERM;
2777 tmps = (u16 __user *)ia_cmds.buf;
2778 for(i=0; i<0x80; i+=2, tmps++)
2779 if(put_user((u16)(readl(iadev->seg_reg+i) & 0xffff), tmps)) return -EFAULT;
2780 ia_cmds.status = 0;
2781 ia_cmds.len = 0x80;
2782 break;
2783 case MEMDUMP_REASSREG:
2784 if (!capable(CAP_NET_ADMIN)) return -EPERM;
2785 tmps = (u16 __user *)ia_cmds.buf;
2786 for(i=0; i<0x80; i+=2, tmps++)
2787 if(put_user((u16)(readl(iadev->reass_reg+i) & 0xffff), tmps)) return -EFAULT;
2788 ia_cmds.status = 0;
2789 ia_cmds.len = 0x80;
2790 break;
2791 case MEMDUMP_FFL:
2792 {
2793 ia_regs_t *regs_local;
2794 ffredn_t *ffL;
2795 rfredn_t *rfL;
2796
2797 if (!capable(CAP_NET_ADMIN)) return -EPERM;
2798 regs_local = kmalloc(sizeof(*regs_local), GFP_KERNEL);
2799 if (!regs_local) return -ENOMEM;
2800 ffL = ®s_local->ffredn;
2801 rfL = ®s_local->rfredn;
2802 /* Copy real rfred registers into the local copy */
2803 for (i=0; i<(sizeof (rfredn_t))/4; i++)
2804 ((u_int *)rfL)[i] = readl(iadev->reass_reg + i) & 0xffff;
2805 /* Copy real ffred registers into the local copy */
2806 for (i=0; i<(sizeof (ffredn_t))/4; i++)
2807 ((u_int *)ffL)[i] = readl(iadev->seg_reg + i) & 0xffff;
2808
2809 if (copy_to_user(ia_cmds.buf, regs_local,sizeof(ia_regs_t))) {
2810 kfree(regs_local);
2811 return -EFAULT;
2812 }
2813 kfree(regs_local);
2814 printk("Board %d registers dumped\n", board);
2815 ia_cmds.status = 0;
2816 }
2817 break;
2818 case READ_REG:
2819 {
2820 if (!capable(CAP_NET_ADMIN)) return -EPERM;
2821 desc_dbg(iadev);
2822 ia_cmds.status = 0;
2823 }
2824 break;
2825 case 0x6:
2826 {
2827 ia_cmds.status = 0;
2828 printk("skb = 0x%p\n", skb_peek(&iadev->tx_backlog));
2829 printk("rtn_q: 0x%p\n",ia_deque_rtn_q(&iadev->tx_return_q));
2830 }
2831 break;
2832 case 0x8:
2833 {
2834 struct k_sonet_stats *stats;
2835 stats = &PRIV(_ia_dev[board])->sonet_stats;
2836 printk("section_bip: %d\n", atomic_read(&stats->section_bip));
2837 printk("line_bip : %d\n", atomic_read(&stats->line_bip));
2838 printk("path_bip : %d\n", atomic_read(&stats->path_bip));
2839 printk("line_febe : %d\n", atomic_read(&stats->line_febe));
2840 printk("path_febe : %d\n", atomic_read(&stats->path_febe));
2841 printk("corr_hcs : %d\n", atomic_read(&stats->corr_hcs));
2842 printk("uncorr_hcs : %d\n", atomic_read(&stats->uncorr_hcs));
2843 printk("tx_cells : %d\n", atomic_read(&stats->tx_cells));
2844 printk("rx_cells : %d\n", atomic_read(&stats->rx_cells));
2845 }
2846 ia_cmds.status = 0;
2847 break;
2848 case 0x9:
2849 if (!capable(CAP_NET_ADMIN)) return -EPERM;
2850 for (i = 1; i <= iadev->num_rx_desc; i++)
2851 free_desc(_ia_dev[board], i);
2852 writew( ~(RX_FREEQ_EMPT | RX_EXCP_RCVD),
2853 iadev->reass_reg+REASS_MASK_REG);
2854 iadev->rxing = 1;
2855
2856 ia_cmds.status = 0;
2857 break;
2858
2859 case 0xb:
2860 if (!capable(CAP_NET_ADMIN)) return -EPERM;
2861 ia_frontend_intr(iadev);
2862 break;
2863 case 0xa:
2864 if (!capable(CAP_NET_ADMIN)) return -EPERM;
2865 {
2866 ia_cmds.status = 0;
2867 IADebugFlag = ia_cmds.maddr;
2868 printk("New debug option loaded\n");
2869 }
2870 break;
2871 default:
2872 ia_cmds.status = 0;
2873 break;
2874 }
2875 }
2876 break;
2877 default:
2878 break;
2879
2880 }
2881 return 0;
2882}
2883
2884static int ia_pkt_tx (struct atm_vcc *vcc, struct sk_buff *skb) {
2885 IADEV *iadev;
2886 struct dle *wr_ptr;
2887 struct tx_buf_desc __iomem *buf_desc_ptr;
2888 int desc;
2889 int comp_code;
2890 int total_len;
2891 struct cpcs_trailer *trailer;
2892 struct ia_vcc *iavcc;
2893
2894 iadev = INPH_IA_DEV(vcc->dev);
2895 iavcc = INPH_IA_VCC(vcc);
2896 if (!iavcc->txing) {
2897 printk("discard packet on closed VC\n");
2898 if (vcc->pop)
2899 vcc->pop(vcc, skb);
2900 else
2901 dev_kfree_skb_any(skb);
2902 return 0;
2903 }
2904
2905 if (skb->len > iadev->tx_buf_sz - 8) {
2906 printk("Transmit size over tx buffer size\n");
2907 if (vcc->pop)
2908 vcc->pop(vcc, skb);
2909 else
2910 dev_kfree_skb_any(skb);
2911 return 0;
2912 }
2913 if ((unsigned long)skb->data & 3) {
2914 printk("Misaligned SKB\n");
2915 if (vcc->pop)
2916 vcc->pop(vcc, skb);
2917 else
2918 dev_kfree_skb_any(skb);
2919 return 0;
2920 }
2921 /* Get a descriptor number from our free descriptor queue
2922 We get the descr number from the TCQ now, since I am using
2923 the TCQ as a free buffer queue. Initially TCQ will be
2924 initialized with all the descriptors and is hence, full.
2925 */
2926 desc = get_desc (iadev, iavcc);
2927 if (desc == 0xffff)
2928 return 1;
2929 comp_code = desc >> 13;
2930 desc &= 0x1fff;
2931
2932 if ((desc == 0) || (desc > iadev->num_tx_desc))
2933 {
2934 IF_ERR(printk(DEV_LABEL "invalid desc for send: %d\n", desc);)
2935 atomic_inc(&vcc->stats->tx);
2936 if (vcc->pop)
2937 vcc->pop(vcc, skb);
2938 else
2939 dev_kfree_skb_any(skb);
2940 return 0; /* return SUCCESS */
2941 }
2942
2943 if (comp_code)
2944 {
2945 IF_ERR(printk(DEV_LABEL "send desc:%d completion code %d error\n",
2946 desc, comp_code);)
2947 }
2948
2949 /* remember the desc and vcc mapping */
2950 iavcc->vc_desc_cnt++;
2951 iadev->desc_tbl[desc-1].iavcc = iavcc;
2952 iadev->desc_tbl[desc-1].txskb = skb;
2953 IA_SKB_STATE(skb) = 0;
2954
2955 iadev->ffL.tcq_rd += 2;
2956 if (iadev->ffL.tcq_rd > iadev->ffL.tcq_ed)
2957 iadev->ffL.tcq_rd = iadev->ffL.tcq_st;
2958 writew(iadev->ffL.tcq_rd, iadev->seg_reg+TCQ_RD_PTR);
2959
2960 /* Put the descriptor number in the packet ready queue
2961 and put the updated write pointer in the DLE field
2962 */
2963 *(u16*)(iadev->seg_ram+iadev->ffL.prq_wr) = desc;
2964
2965 iadev->ffL.prq_wr += 2;
2966 if (iadev->ffL.prq_wr > iadev->ffL.prq_ed)
2967 iadev->ffL.prq_wr = iadev->ffL.prq_st;
2968
2969 /* Figure out the exact length of the packet and padding required to
2970 make it aligned on a 48 byte boundary. */
2971 total_len = skb->len + sizeof(struct cpcs_trailer);
2972 total_len = ((total_len + 47) / 48) * 48;
2973 IF_TX(printk("ia packet len:%d padding:%d\n", total_len, total_len - skb->len);)
2974
2975 /* Put the packet in a tx buffer */
2976 trailer = iadev->tx_buf[desc-1].cpcs;
2977 IF_TX(printk("Sent: skb = 0x%p skb->data: 0x%p len: %d, desc: %d\n",
2978 skb, skb->data, skb->len, desc);)
2979 trailer->control = 0;
2980 /*big endian*/
2981 trailer->length = ((skb->len & 0xff) << 8) | ((skb->len & 0xff00) >> 8);
2982 trailer->crc32 = 0; /* not needed - dummy bytes */
2983
2984 /* Display the packet */
2985 IF_TXPKT(printk("Sent data: len = %d MsgNum = %d\n",
2986 skb->len, tcnter++);
2987 xdump(skb->data, skb->len, "TX: ");
2988 printk("\n");)
2989
2990 /* Build the buffer descriptor */
2991 buf_desc_ptr = iadev->seg_ram+TX_DESC_BASE;
2992 buf_desc_ptr += desc; /* points to the corresponding entry */
2993 buf_desc_ptr->desc_mode = AAL5 | EOM_EN | APP_CRC32 | CMPL_INT;
2994 /* Huh ? p.115 of users guide describes this as a read-only register */
2995 writew(TRANSMIT_DONE, iadev->seg_reg+SEG_INTR_STATUS_REG);
2996 buf_desc_ptr->vc_index = vcc->vci;
2997 buf_desc_ptr->bytes = total_len;
2998
2999 if (vcc->qos.txtp.traffic_class == ATM_ABR)
3000 clear_lockup (vcc, iadev);
3001
3002 /* Build the DLE structure */
3003 wr_ptr = iadev->tx_dle_q.write;
3004 memset((caddr_t)wr_ptr, 0, sizeof(*wr_ptr));
3005 wr_ptr->sys_pkt_addr = dma_map_single(&iadev->pci->dev, skb->data,
3006 skb->len, DMA_TO_DEVICE);
3007 wr_ptr->local_pkt_addr = (buf_desc_ptr->buf_start_hi << 16) |
3008 buf_desc_ptr->buf_start_lo;
3009 /* wr_ptr->bytes = swap_byte_order(total_len); didn't seem to affect?? */
3010 wr_ptr->bytes = skb->len;
3011
3012 /* hw bug - DLEs of 0x2d, 0x2e, 0x2f cause DMA lockup */
3013 if ((wr_ptr->bytes >> 2) == 0xb)
3014 wr_ptr->bytes = 0x30;
3015
3016 wr_ptr->mode = TX_DLE_PSI;
3017 wr_ptr->prq_wr_ptr_data = 0;
3018
3019 /* end is not to be used for the DLE q */
3020 if (++wr_ptr == iadev->tx_dle_q.end)
3021 wr_ptr = iadev->tx_dle_q.start;
3022
3023 /* Build trailer dle */
3024 wr_ptr->sys_pkt_addr = iadev->tx_buf[desc-1].dma_addr;
3025 wr_ptr->local_pkt_addr = ((buf_desc_ptr->buf_start_hi << 16) |
3026 buf_desc_ptr->buf_start_lo) + total_len - sizeof(struct cpcs_trailer);
3027
3028 wr_ptr->bytes = sizeof(struct cpcs_trailer);
3029 wr_ptr->mode = DMA_INT_ENABLE;
3030 wr_ptr->prq_wr_ptr_data = iadev->ffL.prq_wr;
3031
3032 /* end is not to be used for the DLE q */
3033 if (++wr_ptr == iadev->tx_dle_q.end)
3034 wr_ptr = iadev->tx_dle_q.start;
3035
3036 iadev->tx_dle_q.write = wr_ptr;
3037 ATM_DESC(skb) = vcc->vci;
3038 skb_queue_tail(&iadev->tx_dma_q, skb);
3039
3040 atomic_inc(&vcc->stats->tx);
3041 iadev->tx_pkt_cnt++;
3042 /* Increment transaction counter */
3043 writel(2, iadev->dma+IPHASE5575_TX_COUNTER);
3044
3045#if 0
3046 /* add flow control logic */
3047 if (atomic_read(&vcc->stats->tx) % 20 == 0) {
3048 if (iavcc->vc_desc_cnt > 10) {
3049 vcc->tx_quota = vcc->tx_quota * 3 / 4;
3050 printk("Tx1: vcc->tx_quota = %d \n", (u32)vcc->tx_quota );
3051 iavcc->flow_inc = -1;
3052 iavcc->saved_tx_quota = vcc->tx_quota;
3053 } else if ((iavcc->flow_inc < 0) && (iavcc->vc_desc_cnt < 3)) {
3054 // vcc->tx_quota = 3 * iavcc->saved_tx_quota / 4;
3055 printk("Tx2: vcc->tx_quota = %d \n", (u32)vcc->tx_quota );
3056 iavcc->flow_inc = 0;
3057 }
3058 }
3059#endif
3060 IF_TX(printk("ia send done\n");)
3061 return 0;
3062}
3063
3064static int ia_send(struct atm_vcc *vcc, struct sk_buff *skb)
3065{
3066 IADEV *iadev;
3067 unsigned long flags;
3068
3069 iadev = INPH_IA_DEV(vcc->dev);
3070 if ((!skb)||(skb->len>(iadev->tx_buf_sz-sizeof(struct cpcs_trailer))))
3071 {
3072 if (!skb)
3073 printk(KERN_CRIT "null skb in ia_send\n");
3074 else dev_kfree_skb_any(skb);
3075 return -EINVAL;
3076 }
3077 spin_lock_irqsave(&iadev->tx_lock, flags);
3078 if (!test_bit(ATM_VF_READY,&vcc->flags)){
3079 dev_kfree_skb_any(skb);
3080 spin_unlock_irqrestore(&iadev->tx_lock, flags);
3081 return -EINVAL;
3082 }
3083 ATM_SKB(skb)->vcc = vcc;
3084
3085 if (skb_peek(&iadev->tx_backlog)) {
3086 skb_queue_tail(&iadev->tx_backlog, skb);
3087 }
3088 else {
3089 if (ia_pkt_tx (vcc, skb)) {
3090 skb_queue_tail(&iadev->tx_backlog, skb);
3091 }
3092 }
3093 spin_unlock_irqrestore(&iadev->tx_lock, flags);
3094 return 0;
3095
3096}
3097
3098static int ia_proc_read(struct atm_dev *dev,loff_t *pos,char *page)
3099{
3100 int left = *pos, n;
3101 char *tmpPtr;
3102 IADEV *iadev = INPH_IA_DEV(dev);
3103 if(!left--) {
3104 if (iadev->phy_type == FE_25MBIT_PHY) {
3105 n = sprintf(page, " Board Type : Iphase5525-1KVC-128K\n");
3106 return n;
3107 }
3108 if (iadev->phy_type == FE_DS3_PHY)
3109 n = sprintf(page, " Board Type : Iphase-ATM-DS3");
3110 else if (iadev->phy_type == FE_E3_PHY)
3111 n = sprintf(page, " Board Type : Iphase-ATM-E3");
3112 else if (iadev->phy_type == FE_UTP_OPTION)
3113 n = sprintf(page, " Board Type : Iphase-ATM-UTP155");
3114 else
3115 n = sprintf(page, " Board Type : Iphase-ATM-OC3");
3116 tmpPtr = page + n;
3117 if (iadev->pci_map_size == 0x40000)
3118 n += sprintf(tmpPtr, "-1KVC-");
3119 else
3120 n += sprintf(tmpPtr, "-4KVC-");
3121 tmpPtr = page + n;
3122 if ((iadev->memType & MEM_SIZE_MASK) == MEM_SIZE_1M)
3123 n += sprintf(tmpPtr, "1M \n");
3124 else if ((iadev->memType & MEM_SIZE_MASK) == MEM_SIZE_512K)
3125 n += sprintf(tmpPtr, "512K\n");
3126 else
3127 n += sprintf(tmpPtr, "128K\n");
3128 return n;
3129 }
3130 if (!left) {
3131 return sprintf(page, " Number of Tx Buffer: %u\n"
3132 " Size of Tx Buffer : %u\n"
3133 " Number of Rx Buffer: %u\n"
3134 " Size of Rx Buffer : %u\n"
3135 " Packets Received : %u\n"
3136 " Packets Transmitted: %u\n"
3137 " Cells Received : %u\n"
3138 " Cells Transmitted : %u\n"
3139 " Board Dropped Cells: %u\n"
3140 " Board Dropped Pkts : %u\n",
3141 iadev->num_tx_desc, iadev->tx_buf_sz,
3142 iadev->num_rx_desc, iadev->rx_buf_sz,
3143 iadev->rx_pkt_cnt, iadev->tx_pkt_cnt,
3144 iadev->rx_cell_cnt, iadev->tx_cell_cnt,
3145 iadev->drop_rxcell, iadev->drop_rxpkt);
3146 }
3147 return 0;
3148}
3149
3150static const struct atmdev_ops ops = {
3151 .open = ia_open,
3152 .close = ia_close,
3153 .ioctl = ia_ioctl,
3154 .send = ia_send,
3155 .phy_put = ia_phy_put,
3156 .phy_get = ia_phy_get,
3157 .change_qos = ia_change_qos,
3158 .proc_read = ia_proc_read,
3159 .owner = THIS_MODULE,
3160};
3161
3162static int ia_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3163{
3164 struct atm_dev *dev;
3165 IADEV *iadev;
3166 int ret;
3167
3168 iadev = kzalloc(sizeof(*iadev), GFP_KERNEL);
3169 if (!iadev) {
3170 ret = -ENOMEM;
3171 goto err_out;
3172 }
3173
3174 iadev->pci = pdev;
3175
3176 IF_INIT(printk("ia detected at bus:%d dev: %d function:%d\n",
3177 pdev->bus->number, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));)
3178 if (pci_enable_device(pdev)) {
3179 ret = -ENODEV;
3180 goto err_out_free_iadev;
3181 }
3182 dev = atm_dev_register(DEV_LABEL, &pdev->dev, &ops, -1, NULL);
3183 if (!dev) {
3184 ret = -ENOMEM;
3185 goto err_out_disable_dev;
3186 }
3187 dev->dev_data = iadev;
3188 IF_INIT(printk(DEV_LABEL "registered at (itf :%d)\n", dev->number);)
3189 IF_INIT(printk("dev_id = 0x%p iadev->LineRate = %d \n", dev,
3190 iadev->LineRate);)
3191
3192 pci_set_drvdata(pdev, dev);
3193
3194 ia_dev[iadev_count] = iadev;
3195 _ia_dev[iadev_count] = dev;
3196 iadev_count++;
3197 if (ia_init(dev) || ia_start(dev)) {
3198 IF_INIT(printk("IA register failed!\n");)
3199 iadev_count--;
3200 ia_dev[iadev_count] = NULL;
3201 _ia_dev[iadev_count] = NULL;
3202 ret = -EINVAL;
3203 goto err_out_deregister_dev;
3204 }
3205 IF_EVENT(printk("iadev_count = %d\n", iadev_count);)
3206
3207 iadev->next_board = ia_boards;
3208 ia_boards = dev;
3209
3210 return 0;
3211
3212err_out_deregister_dev:
3213 atm_dev_deregister(dev);
3214err_out_disable_dev:
3215 pci_disable_device(pdev);
3216err_out_free_iadev:
3217 kfree(iadev);
3218err_out:
3219 return ret;
3220}
3221
3222static void ia_remove_one(struct pci_dev *pdev)
3223{
3224 struct atm_dev *dev = pci_get_drvdata(pdev);
3225 IADEV *iadev = INPH_IA_DEV(dev);
3226
3227 /* Disable phy interrupts */
3228 ia_phy_put(dev, ia_phy_get(dev, SUNI_RSOP_CIE) & ~(SUNI_RSOP_CIE_LOSE),
3229 SUNI_RSOP_CIE);
3230 udelay(1);
3231
3232 if (dev->phy && dev->phy->stop)
3233 dev->phy->stop(dev);
3234
3235 /* De-register device */
3236 free_irq(iadev->irq, dev);
3237 iadev_count--;
3238 ia_dev[iadev_count] = NULL;
3239 _ia_dev[iadev_count] = NULL;
3240 IF_EVENT(printk("deregistering iav at (itf:%d)\n", dev->number);)
3241 atm_dev_deregister(dev);
3242
3243 iounmap(iadev->base);
3244 pci_disable_device(pdev);
3245
3246 ia_free_rx(iadev);
3247 ia_free_tx(iadev);
3248
3249 kfree(iadev);
3250}
3251
3252static const struct pci_device_id ia_pci_tbl[] = {
3253 { PCI_VENDOR_ID_IPHASE, 0x0008, PCI_ANY_ID, PCI_ANY_ID, },
3254 { PCI_VENDOR_ID_IPHASE, 0x0009, PCI_ANY_ID, PCI_ANY_ID, },
3255 { 0,}
3256};
3257MODULE_DEVICE_TABLE(pci, ia_pci_tbl);
3258
3259static struct pci_driver ia_driver = {
3260 .name = DEV_LABEL,
3261 .id_table = ia_pci_tbl,
3262 .probe = ia_init_one,
3263 .remove = ia_remove_one,
3264};
3265
3266static int __init ia_module_init(void)
3267{
3268 int ret;
3269
3270 ret = pci_register_driver(&ia_driver);
3271 if (ret >= 0) {
3272 ia_timer.expires = jiffies + 3*HZ;
3273 add_timer(&ia_timer);
3274 } else
3275 printk(KERN_ERR DEV_LABEL ": no adapter found\n");
3276 return ret;
3277}
3278
3279static void __exit ia_module_exit(void)
3280{
3281 pci_unregister_driver(&ia_driver);
3282
3283 del_timer_sync(&ia_timer);
3284}
3285
3286module_init(ia_module_init);
3287module_exit(ia_module_exit);
1/******************************************************************************
2 iphase.c: Device driver for Interphase ATM PCI adapter cards
3 Author: Peter Wang <pwang@iphase.com>
4 Some fixes: Arnaldo Carvalho de Melo <acme@conectiva.com.br>
5 Interphase Corporation <www.iphase.com>
6 Version: 1.0
7*******************************************************************************
8
9 This software may be used and distributed according to the terms
10 of the GNU General Public License (GPL), incorporated herein by reference.
11 Drivers based on this skeleton fall under the GPL and must retain
12 the authorship (implicit copyright) notice.
13
14 This program is distributed in the hope that it will be useful, but
15 WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 General Public License for more details.
18
19 Modified from an incomplete driver for Interphase 5575 1KVC 1M card which
20 was originally written by Monalisa Agrawal at UNH. Now this driver
21 supports a variety of varients of Interphase ATM PCI (i)Chip adapter
22 card family (See www.iphase.com/products/ClassSheet.cfm?ClassID=ATM)
23 in terms of PHY type, the size of control memory and the size of
24 packet memory. The following are the change log and history:
25
26 Bugfix the Mona's UBR driver.
27 Modify the basic memory allocation and dma logic.
28 Port the driver to the latest kernel from 2.0.46.
29 Complete the ABR logic of the driver, and added the ABR work-
30 around for the hardware anormalies.
31 Add the CBR support.
32 Add the flow control logic to the driver to allow rate-limit VC.
33 Add 4K VC support to the board with 512K control memory.
34 Add the support of all the variants of the Interphase ATM PCI
35 (i)Chip adapter cards including x575 (155M OC3 and UTP155), x525
36 (25M UTP25) and x531 (DS3 and E3).
37 Add SMP support.
38
39 Support and updates available at: ftp://ftp.iphase.com/pub/atm
40
41*******************************************************************************/
42
43#include <linux/module.h>
44#include <linux/kernel.h>
45#include <linux/mm.h>
46#include <linux/pci.h>
47#include <linux/errno.h>
48#include <linux/atm.h>
49#include <linux/atmdev.h>
50#include <linux/ctype.h>
51#include <linux/sonet.h>
52#include <linux/skbuff.h>
53#include <linux/time.h>
54#include <linux/delay.h>
55#include <linux/uio.h>
56#include <linux/init.h>
57#include <linux/interrupt.h>
58#include <linux/wait.h>
59#include <linux/slab.h>
60#include <asm/io.h>
61#include <linux/atomic.h>
62#include <linux/uaccess.h>
63#include <asm/string.h>
64#include <asm/byteorder.h>
65#include <linux/vmalloc.h>
66#include <linux/jiffies.h>
67#include <linux/nospec.h>
68#include "iphase.h"
69#include "suni.h"
70#define swap_byte_order(x) (((x & 0xff) << 8) | ((x & 0xff00) >> 8))
71
72#define PRIV(dev) ((struct suni_priv *) dev->phy_data)
73
74static unsigned char ia_phy_get(struct atm_dev *dev, unsigned long addr);
75static void desc_dbg(IADEV *iadev);
76
77static IADEV *ia_dev[8];
78static struct atm_dev *_ia_dev[8];
79static int iadev_count;
80static void ia_led_timer(struct timer_list *unused);
81static DEFINE_TIMER(ia_timer, ia_led_timer);
82static int IA_TX_BUF = DFL_TX_BUFFERS, IA_TX_BUF_SZ = DFL_TX_BUF_SZ;
83static int IA_RX_BUF = DFL_RX_BUFFERS, IA_RX_BUF_SZ = DFL_RX_BUF_SZ;
84static uint IADebugFlag = /* IF_IADBG_ERR | IF_IADBG_CBR| IF_IADBG_INIT_ADAPTER
85 |IF_IADBG_ABR | IF_IADBG_EVENT*/ 0;
86
87module_param(IA_TX_BUF, int, 0);
88module_param(IA_TX_BUF_SZ, int, 0);
89module_param(IA_RX_BUF, int, 0);
90module_param(IA_RX_BUF_SZ, int, 0);
91module_param(IADebugFlag, uint, 0644);
92
93MODULE_DESCRIPTION("Driver for Interphase ATM PCI NICs");
94MODULE_LICENSE("GPL");
95
96/**************************** IA_LIB **********************************/
97
98static void ia_init_rtn_q (IARTN_Q *que)
99{
100 que->next = NULL;
101 que->tail = NULL;
102}
103
104static void ia_enque_head_rtn_q (IARTN_Q *que, IARTN_Q * data)
105{
106 data->next = NULL;
107 if (que->next == NULL)
108 que->next = que->tail = data;
109 else {
110 data->next = que->next;
111 que->next = data;
112 }
113 return;
114}
115
116static int ia_enque_rtn_q (IARTN_Q *que, struct desc_tbl_t data) {
117 IARTN_Q *entry = kmalloc(sizeof(*entry), GFP_ATOMIC);
118 if (!entry)
119 return -ENOMEM;
120 entry->data = data;
121 entry->next = NULL;
122 if (que->next == NULL)
123 que->next = que->tail = entry;
124 else {
125 que->tail->next = entry;
126 que->tail = que->tail->next;
127 }
128 return 1;
129}
130
131static IARTN_Q * ia_deque_rtn_q (IARTN_Q *que) {
132 IARTN_Q *tmpdata;
133 if (que->next == NULL)
134 return NULL;
135 tmpdata = que->next;
136 if ( que->next == que->tail)
137 que->next = que->tail = NULL;
138 else
139 que->next = que->next->next;
140 return tmpdata;
141}
142
143static void ia_hack_tcq(IADEV *dev) {
144
145 u_short desc1;
146 u_short tcq_wr;
147 struct ia_vcc *iavcc_r = NULL;
148
149 tcq_wr = readl(dev->seg_reg+TCQ_WR_PTR) & 0xffff;
150 while (dev->host_tcq_wr != tcq_wr) {
151 desc1 = *(u_short *)(dev->seg_ram + dev->host_tcq_wr);
152 if (!desc1) ;
153 else if (!dev->desc_tbl[desc1 -1].timestamp) {
154 IF_ABR(printk(" Desc %d is reset at %ld\n", desc1 -1, jiffies);)
155 *(u_short *) (dev->seg_ram + dev->host_tcq_wr) = 0;
156 }
157 else if (dev->desc_tbl[desc1 -1].timestamp) {
158 if (!(iavcc_r = dev->desc_tbl[desc1 -1].iavcc)) {
159 printk("IA: Fatal err in get_desc\n");
160 continue;
161 }
162 iavcc_r->vc_desc_cnt--;
163 dev->desc_tbl[desc1 -1].timestamp = 0;
164 IF_EVENT(printk("ia_hack: return_q skb = 0x%p desc = %d\n",
165 dev->desc_tbl[desc1 -1].txskb, desc1);)
166 if (iavcc_r->pcr < dev->rate_limit) {
167 IA_SKB_STATE (dev->desc_tbl[desc1-1].txskb) |= IA_TX_DONE;
168 if (ia_enque_rtn_q(&dev->tx_return_q, dev->desc_tbl[desc1 -1]) < 0)
169 printk("ia_hack_tcq: No memory available\n");
170 }
171 dev->desc_tbl[desc1 -1].iavcc = NULL;
172 dev->desc_tbl[desc1 -1].txskb = NULL;
173 }
174 dev->host_tcq_wr += 2;
175 if (dev->host_tcq_wr > dev->ffL.tcq_ed)
176 dev->host_tcq_wr = dev->ffL.tcq_st;
177 }
178} /* ia_hack_tcq */
179
180static u16 get_desc (IADEV *dev, struct ia_vcc *iavcc) {
181 u_short desc_num, i;
182 struct ia_vcc *iavcc_r = NULL;
183 unsigned long delta;
184 static unsigned long timer = 0;
185 int ltimeout;
186
187 ia_hack_tcq (dev);
188 if((time_after(jiffies,timer+50)) || ((dev->ffL.tcq_rd==dev->host_tcq_wr))) {
189 timer = jiffies;
190 i=0;
191 while (i < dev->num_tx_desc) {
192 if (!dev->desc_tbl[i].timestamp) {
193 i++;
194 continue;
195 }
196 ltimeout = dev->desc_tbl[i].iavcc->ltimeout;
197 delta = jiffies - dev->desc_tbl[i].timestamp;
198 if (delta >= ltimeout) {
199 IF_ABR(printk("RECOVER run!! desc_tbl %d = %d delta = %ld, time = %ld\n", i,dev->desc_tbl[i].timestamp, delta, jiffies);)
200 if (dev->ffL.tcq_rd == dev->ffL.tcq_st)
201 dev->ffL.tcq_rd = dev->ffL.tcq_ed;
202 else
203 dev->ffL.tcq_rd -= 2;
204 *(u_short *)(dev->seg_ram + dev->ffL.tcq_rd) = i+1;
205 if (!dev->desc_tbl[i].txskb || !(iavcc_r = dev->desc_tbl[i].iavcc))
206 printk("Fatal err, desc table vcc or skb is NULL\n");
207 else
208 iavcc_r->vc_desc_cnt--;
209 dev->desc_tbl[i].timestamp = 0;
210 dev->desc_tbl[i].iavcc = NULL;
211 dev->desc_tbl[i].txskb = NULL;
212 }
213 i++;
214 } /* while */
215 }
216 if (dev->ffL.tcq_rd == dev->host_tcq_wr)
217 return 0xFFFF;
218
219 /* Get the next available descriptor number from TCQ */
220 desc_num = *(u_short *)(dev->seg_ram + dev->ffL.tcq_rd);
221
222 while (!desc_num || (dev->desc_tbl[desc_num -1]).timestamp) {
223 dev->ffL.tcq_rd += 2;
224 if (dev->ffL.tcq_rd > dev->ffL.tcq_ed)
225 dev->ffL.tcq_rd = dev->ffL.tcq_st;
226 if (dev->ffL.tcq_rd == dev->host_tcq_wr)
227 return 0xFFFF;
228 desc_num = *(u_short *)(dev->seg_ram + dev->ffL.tcq_rd);
229 }
230
231 /* get system time */
232 dev->desc_tbl[desc_num -1].timestamp = jiffies;
233 return desc_num;
234}
235
236static void clear_lockup (struct atm_vcc *vcc, IADEV *dev) {
237 u_char foundLockUp;
238 vcstatus_t *vcstatus;
239 u_short *shd_tbl;
240 u_short tempCellSlot, tempFract;
241 struct main_vc *abr_vc = (struct main_vc *)dev->MAIN_VC_TABLE_ADDR;
242 struct ext_vc *eabr_vc = (struct ext_vc *)dev->EXT_VC_TABLE_ADDR;
243 u_int i;
244
245 if (vcc->qos.txtp.traffic_class == ATM_ABR) {
246 vcstatus = (vcstatus_t *) &(dev->testTable[vcc->vci]->vc_status);
247 vcstatus->cnt++;
248 foundLockUp = 0;
249 if( vcstatus->cnt == 0x05 ) {
250 abr_vc += vcc->vci;
251 eabr_vc += vcc->vci;
252 if( eabr_vc->last_desc ) {
253 if( (abr_vc->status & 0x07) == ABR_STATE /* 0x2 */ ) {
254 /* Wait for 10 Micro sec */
255 udelay(10);
256 if ((eabr_vc->last_desc)&&((abr_vc->status & 0x07)==ABR_STATE))
257 foundLockUp = 1;
258 }
259 else {
260 tempCellSlot = abr_vc->last_cell_slot;
261 tempFract = abr_vc->fraction;
262 if((tempCellSlot == dev->testTable[vcc->vci]->lastTime)
263 && (tempFract == dev->testTable[vcc->vci]->fract))
264 foundLockUp = 1;
265 dev->testTable[vcc->vci]->lastTime = tempCellSlot;
266 dev->testTable[vcc->vci]->fract = tempFract;
267 }
268 } /* last descriptor */
269 vcstatus->cnt = 0;
270 } /* vcstatus->cnt */
271
272 if (foundLockUp) {
273 IF_ABR(printk("LOCK UP found\n");)
274 writew(0xFFFD, dev->seg_reg+MODE_REG_0);
275 /* Wait for 10 Micro sec */
276 udelay(10);
277 abr_vc->status &= 0xFFF8;
278 abr_vc->status |= 0x0001; /* state is idle */
279 shd_tbl = (u_short *)dev->ABR_SCHED_TABLE_ADDR;
280 for( i = 0; ((i < dev->num_vc) && (shd_tbl[i])); i++ );
281 if (i < dev->num_vc)
282 shd_tbl[i] = vcc->vci;
283 else
284 IF_ERR(printk("ABR Seg. may not continue on VC %x\n",vcc->vci);)
285 writew(T_ONLINE, dev->seg_reg+MODE_REG_0);
286 writew(~(TRANSMIT_DONE|TCQ_NOT_EMPTY), dev->seg_reg+SEG_MASK_REG);
287 writew(TRANSMIT_DONE, dev->seg_reg+SEG_INTR_STATUS_REG);
288 vcstatus->cnt = 0;
289 } /* foundLockUp */
290
291 } /* if an ABR VC */
292
293
294}
295
296/*
297** Conversion of 24-bit cellrate (cells/sec) to 16-bit floating point format.
298**
299** +----+----+------------------+-------------------------------+
300** | R | NZ | 5-bit exponent | 9-bit mantissa |
301** +----+----+------------------+-------------------------------+
302**
303** R = reserved (written as 0)
304** NZ = 0 if 0 cells/sec; 1 otherwise
305**
306** if NZ = 1, rate = 1.mmmmmmmmm x 2^(eeeee) cells/sec
307*/
308static u16
309cellrate_to_float(u32 cr)
310{
311
312#define NZ 0x4000
313#define M_BITS 9 /* Number of bits in mantissa */
314#define E_BITS 5 /* Number of bits in exponent */
315#define M_MASK 0x1ff
316#define E_MASK 0x1f
317 u16 flot;
318 u32 tmp = cr & 0x00ffffff;
319 int i = 0;
320 if (cr == 0)
321 return 0;
322 while (tmp != 1) {
323 tmp >>= 1;
324 i++;
325 }
326 if (i == M_BITS)
327 flot = NZ | (i << M_BITS) | (cr & M_MASK);
328 else if (i < M_BITS)
329 flot = NZ | (i << M_BITS) | ((cr << (M_BITS - i)) & M_MASK);
330 else
331 flot = NZ | (i << M_BITS) | ((cr >> (i - M_BITS)) & M_MASK);
332 return flot;
333}
334
335#if 0
336/*
337** Conversion of 16-bit floating point format to 24-bit cellrate (cells/sec).
338*/
339static u32
340float_to_cellrate(u16 rate)
341{
342 u32 exp, mantissa, cps;
343 if ((rate & NZ) == 0)
344 return 0;
345 exp = (rate >> M_BITS) & E_MASK;
346 mantissa = rate & M_MASK;
347 if (exp == 0)
348 return 1;
349 cps = (1 << M_BITS) | mantissa;
350 if (exp == M_BITS)
351 cps = cps;
352 else if (exp > M_BITS)
353 cps <<= (exp - M_BITS);
354 else
355 cps >>= (M_BITS - exp);
356 return cps;
357}
358#endif
359
360static void init_abr_vc (IADEV *dev, srv_cls_param_t *srv_p) {
361 srv_p->class_type = ATM_ABR;
362 srv_p->pcr = dev->LineRate;
363 srv_p->mcr = 0;
364 srv_p->icr = 0x055cb7;
365 srv_p->tbe = 0xffffff;
366 srv_p->frtt = 0x3a;
367 srv_p->rif = 0xf;
368 srv_p->rdf = 0xb;
369 srv_p->nrm = 0x4;
370 srv_p->trm = 0x7;
371 srv_p->cdf = 0x3;
372 srv_p->adtf = 50;
373}
374
375static int
376ia_open_abr_vc(IADEV *dev, srv_cls_param_t *srv_p,
377 struct atm_vcc *vcc, u8 flag)
378{
379 f_vc_abr_entry *f_abr_vc;
380 r_vc_abr_entry *r_abr_vc;
381 u32 icr;
382 u8 trm, nrm, crm;
383 u16 adtf, air, *ptr16;
384 f_abr_vc =(f_vc_abr_entry *)dev->MAIN_VC_TABLE_ADDR;
385 f_abr_vc += vcc->vci;
386 switch (flag) {
387 case 1: /* FFRED initialization */
388#if 0 /* sanity check */
389 if (srv_p->pcr == 0)
390 return INVALID_PCR;
391 if (srv_p->pcr > dev->LineRate)
392 srv_p->pcr = dev->LineRate;
393 if ((srv_p->mcr + dev->sum_mcr) > dev->LineRate)
394 return MCR_UNAVAILABLE;
395 if (srv_p->mcr > srv_p->pcr)
396 return INVALID_MCR;
397 if (!(srv_p->icr))
398 srv_p->icr = srv_p->pcr;
399 if ((srv_p->icr < srv_p->mcr) || (srv_p->icr > srv_p->pcr))
400 return INVALID_ICR;
401 if ((srv_p->tbe < MIN_TBE) || (srv_p->tbe > MAX_TBE))
402 return INVALID_TBE;
403 if ((srv_p->frtt < MIN_FRTT) || (srv_p->frtt > MAX_FRTT))
404 return INVALID_FRTT;
405 if (srv_p->nrm > MAX_NRM)
406 return INVALID_NRM;
407 if (srv_p->trm > MAX_TRM)
408 return INVALID_TRM;
409 if (srv_p->adtf > MAX_ADTF)
410 return INVALID_ADTF;
411 else if (srv_p->adtf == 0)
412 srv_p->adtf = 1;
413 if (srv_p->cdf > MAX_CDF)
414 return INVALID_CDF;
415 if (srv_p->rif > MAX_RIF)
416 return INVALID_RIF;
417 if (srv_p->rdf > MAX_RDF)
418 return INVALID_RDF;
419#endif
420 memset ((caddr_t)f_abr_vc, 0, sizeof(*f_abr_vc));
421 f_abr_vc->f_vc_type = ABR;
422 nrm = 2 << srv_p->nrm; /* (2 ** (srv_p->nrm +1)) */
423 /* i.e 2**n = 2 << (n-1) */
424 f_abr_vc->f_nrm = nrm << 8 | nrm;
425 trm = 100000/(2 << (16 - srv_p->trm));
426 if ( trm == 0) trm = 1;
427 f_abr_vc->f_nrmexp =(((srv_p->nrm +1) & 0x0f) << 12)|(MRM << 8) | trm;
428 crm = srv_p->tbe / nrm;
429 if (crm == 0) crm = 1;
430 f_abr_vc->f_crm = crm & 0xff;
431 f_abr_vc->f_pcr = cellrate_to_float(srv_p->pcr);
432 icr = min( srv_p->icr, (srv_p->tbe > srv_p->frtt) ?
433 ((srv_p->tbe/srv_p->frtt)*1000000) :
434 (1000000/(srv_p->frtt/srv_p->tbe)));
435 f_abr_vc->f_icr = cellrate_to_float(icr);
436 adtf = (10000 * srv_p->adtf)/8192;
437 if (adtf == 0) adtf = 1;
438 f_abr_vc->f_cdf = ((7 - srv_p->cdf) << 12 | adtf) & 0xfff;
439 f_abr_vc->f_mcr = cellrate_to_float(srv_p->mcr);
440 f_abr_vc->f_acr = f_abr_vc->f_icr;
441 f_abr_vc->f_status = 0x0042;
442 break;
443 case 0: /* RFRED initialization */
444 ptr16 = (u_short *)(dev->reass_ram + REASS_TABLE*dev->memSize);
445 *(ptr16 + vcc->vci) = NO_AAL5_PKT | REASS_ABR;
446 r_abr_vc = (r_vc_abr_entry*)(dev->reass_ram+ABR_VC_TABLE*dev->memSize);
447 r_abr_vc += vcc->vci;
448 r_abr_vc->r_status_rdf = (15 - srv_p->rdf) & 0x000f;
449 air = srv_p->pcr << (15 - srv_p->rif);
450 if (air == 0) air = 1;
451 r_abr_vc->r_air = cellrate_to_float(air);
452 dev->testTable[vcc->vci]->vc_status = VC_ACTIVE | VC_ABR;
453 dev->sum_mcr += srv_p->mcr;
454 dev->n_abr++;
455 break;
456 default:
457 break;
458 }
459 return 0;
460}
461static int ia_cbr_setup (IADEV *dev, struct atm_vcc *vcc) {
462 u32 rateLow=0, rateHigh, rate;
463 int entries;
464 struct ia_vcc *ia_vcc;
465
466 int idealSlot =0, testSlot, toBeAssigned, inc;
467 u32 spacing;
468 u16 *SchedTbl, *TstSchedTbl;
469 u16 cbrVC, vcIndex;
470 u32 fracSlot = 0;
471 u32 sp_mod = 0;
472 u32 sp_mod2 = 0;
473
474 /* IpAdjustTrafficParams */
475 if (vcc->qos.txtp.max_pcr <= 0) {
476 IF_ERR(printk("PCR for CBR not defined\n");)
477 return -1;
478 }
479 rate = vcc->qos.txtp.max_pcr;
480 entries = rate / dev->Granularity;
481 IF_CBR(printk("CBR: CBR entries=0x%x for rate=0x%x & Gran=0x%x\n",
482 entries, rate, dev->Granularity);)
483 if (entries < 1)
484 IF_CBR(printk("CBR: Bandwidth smaller than granularity of CBR table\n");)
485 rateLow = entries * dev->Granularity;
486 rateHigh = (entries + 1) * dev->Granularity;
487 if (3*(rate - rateLow) > (rateHigh - rate))
488 entries++;
489 if (entries > dev->CbrRemEntries) {
490 IF_CBR(printk("CBR: Not enough bandwidth to support this PCR.\n");)
491 IF_CBR(printk("Entries = 0x%x, CbrRemEntries = 0x%x.\n",
492 entries, dev->CbrRemEntries);)
493 return -EBUSY;
494 }
495
496 ia_vcc = INPH_IA_VCC(vcc);
497 ia_vcc->NumCbrEntry = entries;
498 dev->sum_mcr += entries * dev->Granularity;
499 /* IaFFrednInsertCbrSched */
500 // Starting at an arbitrary location, place the entries into the table
501 // as smoothly as possible
502 cbrVC = 0;
503 spacing = dev->CbrTotEntries / entries;
504 sp_mod = dev->CbrTotEntries % entries; // get modulo
505 toBeAssigned = entries;
506 fracSlot = 0;
507 vcIndex = vcc->vci;
508 IF_CBR(printk("Vci=0x%x,Spacing=0x%x,Sp_mod=0x%x\n",vcIndex,spacing,sp_mod);)
509 while (toBeAssigned)
510 {
511 // If this is the first time, start the table loading for this connection
512 // as close to entryPoint as possible.
513 if (toBeAssigned == entries)
514 {
515 idealSlot = dev->CbrEntryPt;
516 dev->CbrEntryPt += 2; // Adding 2 helps to prevent clumping
517 if (dev->CbrEntryPt >= dev->CbrTotEntries)
518 dev->CbrEntryPt -= dev->CbrTotEntries;// Wrap if necessary
519 } else {
520 idealSlot += (u32)(spacing + fracSlot); // Point to the next location
521 // in the table that would be smoothest
522 fracSlot = ((sp_mod + sp_mod2) / entries); // get new integer part
523 sp_mod2 = ((sp_mod + sp_mod2) % entries); // calc new fractional part
524 }
525 if (idealSlot >= (int)dev->CbrTotEntries)
526 idealSlot -= dev->CbrTotEntries;
527 // Continuously check around this ideal value until a null
528 // location is encountered.
529 SchedTbl = (u16*)(dev->seg_ram+CBR_SCHED_TABLE*dev->memSize);
530 inc = 0;
531 testSlot = idealSlot;
532 TstSchedTbl = (u16*)(SchedTbl+testSlot); //set index and read in value
533 IF_CBR(printk("CBR Testslot 0x%x AT Location 0x%p, NumToAssign=%d\n",
534 testSlot, TstSchedTbl,toBeAssigned);)
535 memcpy((caddr_t)&cbrVC,(caddr_t)TstSchedTbl,sizeof(cbrVC));
536 while (cbrVC) // If another VC at this location, we have to keep looking
537 {
538 inc++;
539 testSlot = idealSlot - inc;
540 if (testSlot < 0) { // Wrap if necessary
541 testSlot += dev->CbrTotEntries;
542 IF_CBR(printk("Testslot Wrap. STable Start=0x%p,Testslot=%d\n",
543 SchedTbl,testSlot);)
544 }
545 TstSchedTbl = (u16 *)(SchedTbl + testSlot); // set table index
546 memcpy((caddr_t)&cbrVC,(caddr_t)TstSchedTbl,sizeof(cbrVC));
547 if (!cbrVC)
548 break;
549 testSlot = idealSlot + inc;
550 if (testSlot >= (int)dev->CbrTotEntries) { // Wrap if necessary
551 testSlot -= dev->CbrTotEntries;
552 IF_CBR(printk("TotCbrEntries=%d",dev->CbrTotEntries);)
553 IF_CBR(printk(" Testslot=0x%x ToBeAssgned=%d\n",
554 testSlot, toBeAssigned);)
555 }
556 // set table index and read in value
557 TstSchedTbl = (u16*)(SchedTbl + testSlot);
558 IF_CBR(printk("Reading CBR Tbl from 0x%p, CbrVal=0x%x Iteration %d\n",
559 TstSchedTbl,cbrVC,inc);)
560 memcpy((caddr_t)&cbrVC,(caddr_t)TstSchedTbl,sizeof(cbrVC));
561 } /* while */
562 // Move this VCI number into this location of the CBR Sched table.
563 memcpy((caddr_t)TstSchedTbl, (caddr_t)&vcIndex, sizeof(*TstSchedTbl));
564 dev->CbrRemEntries--;
565 toBeAssigned--;
566 } /* while */
567
568 /* IaFFrednCbrEnable */
569 dev->NumEnabledCBR++;
570 if (dev->NumEnabledCBR == 1) {
571 writew((CBR_EN | UBR_EN | ABR_EN | (0x23 << 2)), dev->seg_reg+STPARMS);
572 IF_CBR(printk("CBR is enabled\n");)
573 }
574 return 0;
575}
576static void ia_cbrVc_close (struct atm_vcc *vcc) {
577 IADEV *iadev;
578 u16 *SchedTbl, NullVci = 0;
579 u32 i, NumFound;
580
581 iadev = INPH_IA_DEV(vcc->dev);
582 iadev->NumEnabledCBR--;
583 SchedTbl = (u16*)(iadev->seg_ram+CBR_SCHED_TABLE*iadev->memSize);
584 if (iadev->NumEnabledCBR == 0) {
585 writew((UBR_EN | ABR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS);
586 IF_CBR (printk("CBR support disabled\n");)
587 }
588 NumFound = 0;
589 for (i=0; i < iadev->CbrTotEntries; i++)
590 {
591 if (*SchedTbl == vcc->vci) {
592 iadev->CbrRemEntries++;
593 *SchedTbl = NullVci;
594 IF_CBR(NumFound++;)
595 }
596 SchedTbl++;
597 }
598 IF_CBR(printk("Exit ia_cbrVc_close, NumRemoved=%d\n",NumFound);)
599}
600
601static int ia_avail_descs(IADEV *iadev) {
602 int tmp = 0;
603 ia_hack_tcq(iadev);
604 if (iadev->host_tcq_wr >= iadev->ffL.tcq_rd)
605 tmp = (iadev->host_tcq_wr - iadev->ffL.tcq_rd) / 2;
606 else
607 tmp = (iadev->ffL.tcq_ed - iadev->ffL.tcq_rd + 2 + iadev->host_tcq_wr -
608 iadev->ffL.tcq_st) / 2;
609 return tmp;
610}
611
612static int ia_pkt_tx (struct atm_vcc *vcc, struct sk_buff *skb);
613
614static int ia_que_tx (IADEV *iadev) {
615 struct sk_buff *skb;
616 int num_desc;
617 struct atm_vcc *vcc;
618 num_desc = ia_avail_descs(iadev);
619
620 while (num_desc && (skb = skb_dequeue(&iadev->tx_backlog))) {
621 if (!(vcc = ATM_SKB(skb)->vcc)) {
622 dev_kfree_skb_any(skb);
623 printk("ia_que_tx: Null vcc\n");
624 break;
625 }
626 if (!test_bit(ATM_VF_READY,&vcc->flags)) {
627 dev_kfree_skb_any(skb);
628 printk("Free the SKB on closed vci %d \n", vcc->vci);
629 break;
630 }
631 if (ia_pkt_tx (vcc, skb)) {
632 skb_queue_head(&iadev->tx_backlog, skb);
633 }
634 num_desc--;
635 }
636 return 0;
637}
638
639static void ia_tx_poll (IADEV *iadev) {
640 struct atm_vcc *vcc = NULL;
641 struct sk_buff *skb = NULL, *skb1 = NULL;
642 struct ia_vcc *iavcc;
643 IARTN_Q * rtne;
644
645 ia_hack_tcq(iadev);
646 while ( (rtne = ia_deque_rtn_q(&iadev->tx_return_q))) {
647 skb = rtne->data.txskb;
648 if (!skb) {
649 printk("ia_tx_poll: skb is null\n");
650 goto out;
651 }
652 vcc = ATM_SKB(skb)->vcc;
653 if (!vcc) {
654 printk("ia_tx_poll: vcc is null\n");
655 dev_kfree_skb_any(skb);
656 goto out;
657 }
658
659 iavcc = INPH_IA_VCC(vcc);
660 if (!iavcc) {
661 printk("ia_tx_poll: iavcc is null\n");
662 dev_kfree_skb_any(skb);
663 goto out;
664 }
665
666 skb1 = skb_dequeue(&iavcc->txing_skb);
667 while (skb1 && (skb1 != skb)) {
668 if (!(IA_SKB_STATE(skb1) & IA_TX_DONE)) {
669 printk("IA_tx_intr: Vci %d lost pkt!!!\n", vcc->vci);
670 }
671 IF_ERR(printk("Release the SKB not match\n");)
672 if ((vcc->pop) && (skb1->len != 0))
673 {
674 vcc->pop(vcc, skb1);
675 IF_EVENT(printk("Transmit Done - skb 0x%lx return\n",
676 (long)skb1);)
677 }
678 else
679 dev_kfree_skb_any(skb1);
680 skb1 = skb_dequeue(&iavcc->txing_skb);
681 }
682 if (!skb1) {
683 IF_EVENT(printk("IA: Vci %d - skb not found requeued\n",vcc->vci);)
684 ia_enque_head_rtn_q (&iadev->tx_return_q, rtne);
685 break;
686 }
687 if ((vcc->pop) && (skb->len != 0))
688 {
689 vcc->pop(vcc, skb);
690 IF_EVENT(printk("Tx Done - skb 0x%lx return\n",(long)skb);)
691 }
692 else
693 dev_kfree_skb_any(skb);
694 kfree(rtne);
695 }
696 ia_que_tx(iadev);
697out:
698 return;
699}
700#if 0
701static void ia_eeprom_put (IADEV *iadev, u32 addr, u_short val)
702{
703 u32 t;
704 int i;
705 /*
706 * Issue a command to enable writes to the NOVRAM
707 */
708 NVRAM_CMD (EXTEND + EWEN);
709 NVRAM_CLR_CE;
710 /*
711 * issue the write command
712 */
713 NVRAM_CMD(IAWRITE + addr);
714 /*
715 * Send the data, starting with D15, then D14, and so on for 16 bits
716 */
717 for (i=15; i>=0; i--) {
718 NVRAM_CLKOUT (val & 0x8000);
719 val <<= 1;
720 }
721 NVRAM_CLR_CE;
722 CFG_OR(NVCE);
723 t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS);
724 while (!(t & NVDO))
725 t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS);
726
727 NVRAM_CLR_CE;
728 /*
729 * disable writes again
730 */
731 NVRAM_CMD(EXTEND + EWDS)
732 NVRAM_CLR_CE;
733 CFG_AND(~NVDI);
734}
735#endif
736
737static u16 ia_eeprom_get (IADEV *iadev, u32 addr)
738{
739 u_short val;
740 u32 t;
741 int i;
742 /*
743 * Read the first bit that was clocked with the falling edge of
744 * the last command data clock
745 */
746 NVRAM_CMD(IAREAD + addr);
747 /*
748 * Now read the rest of the bits, the next bit read is D14, then D13,
749 * and so on.
750 */
751 val = 0;
752 for (i=15; i>=0; i--) {
753 NVRAM_CLKIN(t);
754 val |= (t << i);
755 }
756 NVRAM_CLR_CE;
757 CFG_AND(~NVDI);
758 return val;
759}
760
761static void ia_hw_type(IADEV *iadev) {
762 u_short memType = ia_eeprom_get(iadev, 25);
763 iadev->memType = memType;
764 if ((memType & MEM_SIZE_MASK) == MEM_SIZE_1M) {
765 iadev->num_tx_desc = IA_TX_BUF;
766 iadev->tx_buf_sz = IA_TX_BUF_SZ;
767 iadev->num_rx_desc = IA_RX_BUF;
768 iadev->rx_buf_sz = IA_RX_BUF_SZ;
769 } else if ((memType & MEM_SIZE_MASK) == MEM_SIZE_512K) {
770 if (IA_TX_BUF == DFL_TX_BUFFERS)
771 iadev->num_tx_desc = IA_TX_BUF / 2;
772 else
773 iadev->num_tx_desc = IA_TX_BUF;
774 iadev->tx_buf_sz = IA_TX_BUF_SZ;
775 if (IA_RX_BUF == DFL_RX_BUFFERS)
776 iadev->num_rx_desc = IA_RX_BUF / 2;
777 else
778 iadev->num_rx_desc = IA_RX_BUF;
779 iadev->rx_buf_sz = IA_RX_BUF_SZ;
780 }
781 else {
782 if (IA_TX_BUF == DFL_TX_BUFFERS)
783 iadev->num_tx_desc = IA_TX_BUF / 8;
784 else
785 iadev->num_tx_desc = IA_TX_BUF;
786 iadev->tx_buf_sz = IA_TX_BUF_SZ;
787 if (IA_RX_BUF == DFL_RX_BUFFERS)
788 iadev->num_rx_desc = IA_RX_BUF / 8;
789 else
790 iadev->num_rx_desc = IA_RX_BUF;
791 iadev->rx_buf_sz = IA_RX_BUF_SZ;
792 }
793 iadev->rx_pkt_ram = TX_PACKET_RAM + (iadev->num_tx_desc * iadev->tx_buf_sz);
794 IF_INIT(printk("BUF: tx=%d,sz=%d rx=%d sz= %d rx_pkt_ram=%d\n",
795 iadev->num_tx_desc, iadev->tx_buf_sz, iadev->num_rx_desc,
796 iadev->rx_buf_sz, iadev->rx_pkt_ram);)
797
798#if 0
799 if ((memType & FE_MASK) == FE_SINGLE_MODE) {
800 iadev->phy_type = PHY_OC3C_S;
801 else if ((memType & FE_MASK) == FE_UTP_OPTION)
802 iadev->phy_type = PHY_UTP155;
803 else
804 iadev->phy_type = PHY_OC3C_M;
805#endif
806
807 iadev->phy_type = memType & FE_MASK;
808 IF_INIT(printk("memType = 0x%x iadev->phy_type = 0x%x\n",
809 memType,iadev->phy_type);)
810 if (iadev->phy_type == FE_25MBIT_PHY)
811 iadev->LineRate = (u32)(((25600000/8)*26)/(27*53));
812 else if (iadev->phy_type == FE_DS3_PHY)
813 iadev->LineRate = (u32)(((44736000/8)*26)/(27*53));
814 else if (iadev->phy_type == FE_E3_PHY)
815 iadev->LineRate = (u32)(((34368000/8)*26)/(27*53));
816 else
817 iadev->LineRate = (u32)(ATM_OC3_PCR);
818 IF_INIT(printk("iadev->LineRate = %d \n", iadev->LineRate);)
819
820}
821
822static u32 ia_phy_read32(struct iadev_priv *ia, unsigned int reg)
823{
824 return readl(ia->phy + (reg >> 2));
825}
826
827static void ia_phy_write32(struct iadev_priv *ia, unsigned int reg, u32 val)
828{
829 writel(val, ia->phy + (reg >> 2));
830}
831
832static void ia_frontend_intr(struct iadev_priv *iadev)
833{
834 u32 status;
835
836 if (iadev->phy_type & FE_25MBIT_PHY) {
837 status = ia_phy_read32(iadev, MB25_INTR_STATUS);
838 iadev->carrier_detect = (status & MB25_IS_GSB) ? 1 : 0;
839 } else if (iadev->phy_type & FE_DS3_PHY) {
840 ia_phy_read32(iadev, SUNI_DS3_FRM_INTR_STAT);
841 status = ia_phy_read32(iadev, SUNI_DS3_FRM_STAT);
842 iadev->carrier_detect = (status & SUNI_DS3_LOSV) ? 0 : 1;
843 } else if (iadev->phy_type & FE_E3_PHY) {
844 ia_phy_read32(iadev, SUNI_E3_FRM_MAINT_INTR_IND);
845 status = ia_phy_read32(iadev, SUNI_E3_FRM_FRAM_INTR_IND_STAT);
846 iadev->carrier_detect = (status & SUNI_E3_LOS) ? 0 : 1;
847 } else {
848 status = ia_phy_read32(iadev, SUNI_RSOP_STATUS);
849 iadev->carrier_detect = (status & SUNI_LOSV) ? 0 : 1;
850 }
851
852 printk(KERN_INFO "IA: SUNI carrier %s\n",
853 iadev->carrier_detect ? "detected" : "lost signal");
854}
855
856static void ia_mb25_init(struct iadev_priv *iadev)
857{
858#if 0
859 mb25->mb25_master_ctrl = MB25_MC_DRIC | MB25_MC_DREC | MB25_MC_ENABLED;
860#endif
861 ia_phy_write32(iadev, MB25_MASTER_CTRL, MB25_MC_DRIC | MB25_MC_DREC);
862 ia_phy_write32(iadev, MB25_DIAG_CONTROL, 0);
863
864 iadev->carrier_detect =
865 (ia_phy_read32(iadev, MB25_INTR_STATUS) & MB25_IS_GSB) ? 1 : 0;
866}
867
868struct ia_reg {
869 u16 reg;
870 u16 val;
871};
872
873static void ia_phy_write(struct iadev_priv *iadev,
874 const struct ia_reg *regs, int len)
875{
876 while (len--) {
877 ia_phy_write32(iadev, regs->reg, regs->val);
878 regs++;
879 }
880}
881
882static void ia_suni_pm7345_init_ds3(struct iadev_priv *iadev)
883{
884 static const struct ia_reg suni_ds3_init[] = {
885 { SUNI_DS3_FRM_INTR_ENBL, 0x17 },
886 { SUNI_DS3_FRM_CFG, 0x01 },
887 { SUNI_DS3_TRAN_CFG, 0x01 },
888 { SUNI_CONFIG, 0 },
889 { SUNI_SPLR_CFG, 0 },
890 { SUNI_SPLT_CFG, 0 }
891 };
892 u32 status;
893
894 status = ia_phy_read32(iadev, SUNI_DS3_FRM_STAT);
895 iadev->carrier_detect = (status & SUNI_DS3_LOSV) ? 0 : 1;
896
897 ia_phy_write(iadev, suni_ds3_init, ARRAY_SIZE(suni_ds3_init));
898}
899
900static void ia_suni_pm7345_init_e3(struct iadev_priv *iadev)
901{
902 static const struct ia_reg suni_e3_init[] = {
903 { SUNI_E3_FRM_FRAM_OPTIONS, 0x04 },
904 { SUNI_E3_FRM_MAINT_OPTIONS, 0x20 },
905 { SUNI_E3_FRM_FRAM_INTR_ENBL, 0x1d },
906 { SUNI_E3_FRM_MAINT_INTR_ENBL, 0x30 },
907 { SUNI_E3_TRAN_STAT_DIAG_OPTIONS, 0 },
908 { SUNI_E3_TRAN_FRAM_OPTIONS, 0x01 },
909 { SUNI_CONFIG, SUNI_PM7345_E3ENBL },
910 { SUNI_SPLR_CFG, 0x41 },
911 { SUNI_SPLT_CFG, 0x41 }
912 };
913 u32 status;
914
915 status = ia_phy_read32(iadev, SUNI_E3_FRM_FRAM_INTR_IND_STAT);
916 iadev->carrier_detect = (status & SUNI_E3_LOS) ? 0 : 1;
917 ia_phy_write(iadev, suni_e3_init, ARRAY_SIZE(suni_e3_init));
918}
919
920static void ia_suni_pm7345_init(struct iadev_priv *iadev)
921{
922 static const struct ia_reg suni_init[] = {
923 /* Enable RSOP loss of signal interrupt. */
924 { SUNI_INTR_ENBL, 0x28 },
925 /* Clear error counters. */
926 { SUNI_ID_RESET, 0 },
927 /* Clear "PMCTST" in master test register. */
928 { SUNI_MASTER_TEST, 0 },
929
930 { SUNI_RXCP_CTRL, 0x2c },
931 { SUNI_RXCP_FCTRL, 0x81 },
932
933 { SUNI_RXCP_IDLE_PAT_H1, 0 },
934 { SUNI_RXCP_IDLE_PAT_H2, 0 },
935 { SUNI_RXCP_IDLE_PAT_H3, 0 },
936 { SUNI_RXCP_IDLE_PAT_H4, 0x01 },
937
938 { SUNI_RXCP_IDLE_MASK_H1, 0xff },
939 { SUNI_RXCP_IDLE_MASK_H2, 0xff },
940 { SUNI_RXCP_IDLE_MASK_H3, 0xff },
941 { SUNI_RXCP_IDLE_MASK_H4, 0xfe },
942
943 { SUNI_RXCP_CELL_PAT_H1, 0 },
944 { SUNI_RXCP_CELL_PAT_H2, 0 },
945 { SUNI_RXCP_CELL_PAT_H3, 0 },
946 { SUNI_RXCP_CELL_PAT_H4, 0x01 },
947
948 { SUNI_RXCP_CELL_MASK_H1, 0xff },
949 { SUNI_RXCP_CELL_MASK_H2, 0xff },
950 { SUNI_RXCP_CELL_MASK_H3, 0xff },
951 { SUNI_RXCP_CELL_MASK_H4, 0xff },
952
953 { SUNI_TXCP_CTRL, 0xa4 },
954 { SUNI_TXCP_INTR_EN_STS, 0x10 },
955 { SUNI_TXCP_IDLE_PAT_H5, 0x55 }
956 };
957
958 if (iadev->phy_type & FE_DS3_PHY)
959 ia_suni_pm7345_init_ds3(iadev);
960 else
961 ia_suni_pm7345_init_e3(iadev);
962
963 ia_phy_write(iadev, suni_init, ARRAY_SIZE(suni_init));
964
965 ia_phy_write32(iadev, SUNI_CONFIG, ia_phy_read32(iadev, SUNI_CONFIG) &
966 ~(SUNI_PM7345_LLB | SUNI_PM7345_CLB |
967 SUNI_PM7345_DLB | SUNI_PM7345_PLB));
968#ifdef __SNMP__
969 suni_pm7345->suni_rxcp_intr_en_sts |= SUNI_OOCDE;
970#endif /* __SNMP__ */
971 return;
972}
973
974
975/***************************** IA_LIB END *****************************/
976
977#ifdef CONFIG_ATM_IA_DEBUG
978static int tcnter = 0;
979static void xdump( u_char* cp, int length, char* prefix )
980{
981 int col, count;
982 u_char prntBuf[120];
983 u_char* pBuf = prntBuf;
984 count = 0;
985 while(count < length){
986 pBuf += sprintf( pBuf, "%s", prefix );
987 for(col = 0;count + col < length && col < 16; col++){
988 if (col != 0 && (col % 4) == 0)
989 pBuf += sprintf( pBuf, " " );
990 pBuf += sprintf( pBuf, "%02X ", cp[count + col] );
991 }
992 while(col++ < 16){ /* pad end of buffer with blanks */
993 if ((col % 4) == 0)
994 sprintf( pBuf, " " );
995 pBuf += sprintf( pBuf, " " );
996 }
997 pBuf += sprintf( pBuf, " " );
998 for(col = 0;count + col < length && col < 16; col++){
999 u_char c = cp[count + col];
1000
1001 if (isascii(c) && isprint(c))
1002 pBuf += sprintf(pBuf, "%c", c);
1003 else
1004 pBuf += sprintf(pBuf, ".");
1005 }
1006 printk("%s\n", prntBuf);
1007 count += col;
1008 pBuf = prntBuf;
1009 }
1010
1011} /* close xdump(... */
1012#endif /* CONFIG_ATM_IA_DEBUG */
1013
1014
1015static struct atm_dev *ia_boards = NULL;
1016
1017#define ACTUAL_RAM_BASE \
1018 RAM_BASE*((iadev->mem)/(128 * 1024))
1019#define ACTUAL_SEG_RAM_BASE \
1020 IPHASE5575_FRAG_CONTROL_RAM_BASE*((iadev->mem)/(128 * 1024))
1021#define ACTUAL_REASS_RAM_BASE \
1022 IPHASE5575_REASS_CONTROL_RAM_BASE*((iadev->mem)/(128 * 1024))
1023
1024
1025/*-- some utilities and memory allocation stuff will come here -------------*/
1026
1027static void desc_dbg(IADEV *iadev) {
1028
1029 u_short tcq_wr_ptr, tcq_st_ptr, tcq_ed_ptr;
1030 u32 i;
1031 void __iomem *tmp;
1032 // regval = readl((u32)ia_cmds->maddr);
1033 tcq_wr_ptr = readw(iadev->seg_reg+TCQ_WR_PTR);
1034 printk("B_tcq_wr = 0x%x desc = %d last desc = %d\n",
1035 tcq_wr_ptr, readw(iadev->seg_ram+tcq_wr_ptr),
1036 readw(iadev->seg_ram+tcq_wr_ptr-2));
1037 printk(" host_tcq_wr = 0x%x host_tcq_rd = 0x%x \n", iadev->host_tcq_wr,
1038 iadev->ffL.tcq_rd);
1039 tcq_st_ptr = readw(iadev->seg_reg+TCQ_ST_ADR);
1040 tcq_ed_ptr = readw(iadev->seg_reg+TCQ_ED_ADR);
1041 printk("tcq_st_ptr = 0x%x tcq_ed_ptr = 0x%x \n", tcq_st_ptr, tcq_ed_ptr);
1042 i = 0;
1043 while (tcq_st_ptr != tcq_ed_ptr) {
1044 tmp = iadev->seg_ram+tcq_st_ptr;
1045 printk("TCQ slot %d desc = %d Addr = %p\n", i++, readw(tmp), tmp);
1046 tcq_st_ptr += 2;
1047 }
1048 for(i=0; i <iadev->num_tx_desc; i++)
1049 printk("Desc_tbl[%d] = %d \n", i, iadev->desc_tbl[i].timestamp);
1050}
1051
1052
1053/*----------------------------- Receiving side stuff --------------------------*/
1054
1055static void rx_excp_rcvd(struct atm_dev *dev)
1056{
1057#if 0 /* closing the receiving size will cause too many excp int */
1058 IADEV *iadev;
1059 u_short state;
1060 u_short excpq_rd_ptr;
1061 //u_short *ptr;
1062 int vci, error = 1;
1063 iadev = INPH_IA_DEV(dev);
1064 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1065 while((state & EXCPQ_EMPTY) != EXCPQ_EMPTY)
1066 { printk("state = %x \n", state);
1067 excpq_rd_ptr = readw(iadev->reass_reg + EXCP_Q_RD_PTR) & 0xffff;
1068 printk("state = %x excpq_rd_ptr = %x \n", state, excpq_rd_ptr);
1069 if (excpq_rd_ptr == *(u16*)(iadev->reass_reg + EXCP_Q_WR_PTR))
1070 IF_ERR(printk("excpq_rd_ptr is wrong!!!\n");)
1071 // TODO: update exception stat
1072 vci = readw(iadev->reass_ram+excpq_rd_ptr);
1073 error = readw(iadev->reass_ram+excpq_rd_ptr+2) & 0x0007;
1074 // pwang_test
1075 excpq_rd_ptr += 4;
1076 if (excpq_rd_ptr > (readw(iadev->reass_reg + EXCP_Q_ED_ADR)& 0xffff))
1077 excpq_rd_ptr = readw(iadev->reass_reg + EXCP_Q_ST_ADR)& 0xffff;
1078 writew( excpq_rd_ptr, iadev->reass_reg + EXCP_Q_RD_PTR);
1079 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1080 }
1081#endif
1082}
1083
1084static void free_desc(struct atm_dev *dev, int desc)
1085{
1086 IADEV *iadev;
1087 iadev = INPH_IA_DEV(dev);
1088 writew(desc, iadev->reass_ram+iadev->rfL.fdq_wr);
1089 iadev->rfL.fdq_wr +=2;
1090 if (iadev->rfL.fdq_wr > iadev->rfL.fdq_ed)
1091 iadev->rfL.fdq_wr = iadev->rfL.fdq_st;
1092 writew(iadev->rfL.fdq_wr, iadev->reass_reg+FREEQ_WR_PTR);
1093}
1094
1095
1096static int rx_pkt(struct atm_dev *dev)
1097{
1098 IADEV *iadev;
1099 struct atm_vcc *vcc;
1100 unsigned short status;
1101 struct rx_buf_desc __iomem *buf_desc_ptr;
1102 int desc;
1103 struct dle* wr_ptr;
1104 int len;
1105 struct sk_buff *skb;
1106 u_int buf_addr, dma_addr;
1107
1108 iadev = INPH_IA_DEV(dev);
1109 if (iadev->rfL.pcq_rd == (readw(iadev->reass_reg+PCQ_WR_PTR)&0xffff))
1110 {
1111 printk(KERN_ERR DEV_LABEL "(itf %d) Receive queue empty\n", dev->number);
1112 return -EINVAL;
1113 }
1114 /* mask 1st 3 bits to get the actual descno. */
1115 desc = readw(iadev->reass_ram+iadev->rfL.pcq_rd) & 0x1fff;
1116 IF_RX(printk("reass_ram = %p iadev->rfL.pcq_rd = 0x%x desc = %d\n",
1117 iadev->reass_ram, iadev->rfL.pcq_rd, desc);
1118 printk(" pcq_wr_ptr = 0x%x\n",
1119 readw(iadev->reass_reg+PCQ_WR_PTR)&0xffff);)
1120 /* update the read pointer - maybe we shud do this in the end*/
1121 if ( iadev->rfL.pcq_rd== iadev->rfL.pcq_ed)
1122 iadev->rfL.pcq_rd = iadev->rfL.pcq_st;
1123 else
1124 iadev->rfL.pcq_rd += 2;
1125 writew(iadev->rfL.pcq_rd, iadev->reass_reg+PCQ_RD_PTR);
1126
1127 /* get the buffer desc entry.
1128 update stuff. - doesn't seem to be any update necessary
1129 */
1130 buf_desc_ptr = iadev->RX_DESC_BASE_ADDR;
1131 /* make the ptr point to the corresponding buffer desc entry */
1132 buf_desc_ptr += desc;
1133 if (!desc || (desc > iadev->num_rx_desc) ||
1134 ((buf_desc_ptr->vc_index & 0xffff) >= iadev->num_vc)) {
1135 free_desc(dev, desc);
1136 IF_ERR(printk("IA: bad descriptor desc = %d \n", desc);)
1137 return -1;
1138 }
1139 vcc = iadev->rx_open[buf_desc_ptr->vc_index & 0xffff];
1140 if (!vcc)
1141 {
1142 free_desc(dev, desc);
1143 printk("IA: null vcc, drop PDU\n");
1144 return -1;
1145 }
1146
1147
1148 /* might want to check the status bits for errors */
1149 status = (u_short) (buf_desc_ptr->desc_mode);
1150 if (status & (RX_CER | RX_PTE | RX_OFL))
1151 {
1152 atomic_inc(&vcc->stats->rx_err);
1153 IF_ERR(printk("IA: bad packet, dropping it");)
1154 if (status & RX_CER) {
1155 IF_ERR(printk(" cause: packet CRC error\n");)
1156 }
1157 else if (status & RX_PTE) {
1158 IF_ERR(printk(" cause: packet time out\n");)
1159 }
1160 else {
1161 IF_ERR(printk(" cause: buffer overflow\n");)
1162 }
1163 goto out_free_desc;
1164 }
1165
1166 /*
1167 build DLE.
1168 */
1169
1170 buf_addr = (buf_desc_ptr->buf_start_hi << 16) | buf_desc_ptr->buf_start_lo;
1171 dma_addr = (buf_desc_ptr->dma_start_hi << 16) | buf_desc_ptr->dma_start_lo;
1172 len = dma_addr - buf_addr;
1173 if (len > iadev->rx_buf_sz) {
1174 printk("Over %d bytes sdu received, dropped!!!\n", iadev->rx_buf_sz);
1175 atomic_inc(&vcc->stats->rx_err);
1176 goto out_free_desc;
1177 }
1178
1179 if (!(skb = atm_alloc_charge(vcc, len, GFP_ATOMIC))) {
1180 if (vcc->vci < 32)
1181 printk("Drop control packets\n");
1182 goto out_free_desc;
1183 }
1184 skb_put(skb,len);
1185 // pwang_test
1186 ATM_SKB(skb)->vcc = vcc;
1187 ATM_DESC(skb) = desc;
1188 skb_queue_tail(&iadev->rx_dma_q, skb);
1189
1190 /* Build the DLE structure */
1191 wr_ptr = iadev->rx_dle_q.write;
1192 wr_ptr->sys_pkt_addr = dma_map_single(&iadev->pci->dev, skb->data,
1193 len, DMA_FROM_DEVICE);
1194 wr_ptr->local_pkt_addr = buf_addr;
1195 wr_ptr->bytes = len; /* We don't know this do we ?? */
1196 wr_ptr->mode = DMA_INT_ENABLE;
1197
1198 /* shud take care of wrap around here too. */
1199 if(++wr_ptr == iadev->rx_dle_q.end)
1200 wr_ptr = iadev->rx_dle_q.start;
1201 iadev->rx_dle_q.write = wr_ptr;
1202 udelay(1);
1203 /* Increment transaction counter */
1204 writel(1, iadev->dma+IPHASE5575_RX_COUNTER);
1205out: return 0;
1206out_free_desc:
1207 free_desc(dev, desc);
1208 goto out;
1209}
1210
1211static void rx_intr(struct atm_dev *dev)
1212{
1213 IADEV *iadev;
1214 u_short status;
1215 u_short state, i;
1216
1217 iadev = INPH_IA_DEV(dev);
1218 status = readl(iadev->reass_reg+REASS_INTR_STATUS_REG) & 0xffff;
1219 IF_EVENT(printk("rx_intr: status = 0x%x\n", status);)
1220 if (status & RX_PKT_RCVD)
1221 {
1222 /* do something */
1223 /* Basically recvd an interrupt for receiving a packet.
1224 A descriptor would have been written to the packet complete
1225 queue. Get all the descriptors and set up dma to move the
1226 packets till the packet complete queue is empty..
1227 */
1228 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1229 IF_EVENT(printk("Rx intr status: RX_PKT_RCVD %08x\n", status);)
1230 while(!(state & PCQ_EMPTY))
1231 {
1232 rx_pkt(dev);
1233 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1234 }
1235 iadev->rxing = 1;
1236 }
1237 if (status & RX_FREEQ_EMPT)
1238 {
1239 if (iadev->rxing) {
1240 iadev->rx_tmp_cnt = iadev->rx_pkt_cnt;
1241 iadev->rx_tmp_jif = jiffies;
1242 iadev->rxing = 0;
1243 }
1244 else if ((time_after(jiffies, iadev->rx_tmp_jif + 50)) &&
1245 ((iadev->rx_pkt_cnt - iadev->rx_tmp_cnt) == 0)) {
1246 for (i = 1; i <= iadev->num_rx_desc; i++)
1247 free_desc(dev, i);
1248printk("Test logic RUN!!!!\n");
1249 writew( ~(RX_FREEQ_EMPT|RX_EXCP_RCVD),iadev->reass_reg+REASS_MASK_REG);
1250 iadev->rxing = 1;
1251 }
1252 IF_EVENT(printk("Rx intr status: RX_FREEQ_EMPT %08x\n", status);)
1253 }
1254
1255 if (status & RX_EXCP_RCVD)
1256 {
1257 /* probably need to handle the exception queue also. */
1258 IF_EVENT(printk("Rx intr status: RX_EXCP_RCVD %08x\n", status);)
1259 rx_excp_rcvd(dev);
1260 }
1261
1262
1263 if (status & RX_RAW_RCVD)
1264 {
1265 /* need to handle the raw incoming cells. This deepnds on
1266 whether we have programmed to receive the raw cells or not.
1267 Else ignore. */
1268 IF_EVENT(printk("Rx intr status: RX_RAW_RCVD %08x\n", status);)
1269 }
1270}
1271
1272
1273static void rx_dle_intr(struct atm_dev *dev)
1274{
1275 IADEV *iadev;
1276 struct atm_vcc *vcc;
1277 struct sk_buff *skb;
1278 int desc;
1279 u_short state;
1280 struct dle *dle, *cur_dle;
1281 u_int dle_lp;
1282 int len;
1283 iadev = INPH_IA_DEV(dev);
1284
1285 /* free all the dles done, that is just update our own dle read pointer
1286 - do we really need to do this. Think not. */
1287 /* DMA is done, just get all the recevie buffers from the rx dma queue
1288 and push them up to the higher layer protocol. Also free the desc
1289 associated with the buffer. */
1290 dle = iadev->rx_dle_q.read;
1291 dle_lp = readl(iadev->dma+IPHASE5575_RX_LIST_ADDR) & (sizeof(struct dle)*DLE_ENTRIES - 1);
1292 cur_dle = (struct dle*)(iadev->rx_dle_q.start + (dle_lp >> 4));
1293 while(dle != cur_dle)
1294 {
1295 /* free the DMAed skb */
1296 skb = skb_dequeue(&iadev->rx_dma_q);
1297 if (!skb)
1298 goto INCR_DLE;
1299 desc = ATM_DESC(skb);
1300 free_desc(dev, desc);
1301
1302 if (!(len = skb->len))
1303 {
1304 printk("rx_dle_intr: skb len 0\n");
1305 dev_kfree_skb_any(skb);
1306 }
1307 else
1308 {
1309 struct cpcs_trailer *trailer;
1310 u_short length;
1311 struct ia_vcc *ia_vcc;
1312
1313 dma_unmap_single(&iadev->pci->dev, iadev->rx_dle_q.write->sys_pkt_addr,
1314 len, DMA_FROM_DEVICE);
1315 /* no VCC related housekeeping done as yet. lets see */
1316 vcc = ATM_SKB(skb)->vcc;
1317 if (!vcc) {
1318 printk("IA: null vcc\n");
1319 dev_kfree_skb_any(skb);
1320 goto INCR_DLE;
1321 }
1322 ia_vcc = INPH_IA_VCC(vcc);
1323 if (ia_vcc == NULL)
1324 {
1325 atomic_inc(&vcc->stats->rx_err);
1326 atm_return(vcc, skb->truesize);
1327 dev_kfree_skb_any(skb);
1328 goto INCR_DLE;
1329 }
1330 // get real pkt length pwang_test
1331 trailer = (struct cpcs_trailer*)((u_char *)skb->data +
1332 skb->len - sizeof(*trailer));
1333 length = swap_byte_order(trailer->length);
1334 if ((length > iadev->rx_buf_sz) || (length >
1335 (skb->len - sizeof(struct cpcs_trailer))))
1336 {
1337 atomic_inc(&vcc->stats->rx_err);
1338 IF_ERR(printk("rx_dle_intr: Bad AAL5 trailer %d (skb len %d)",
1339 length, skb->len);)
1340 atm_return(vcc, skb->truesize);
1341 dev_kfree_skb_any(skb);
1342 goto INCR_DLE;
1343 }
1344 skb_trim(skb, length);
1345
1346 /* Display the packet */
1347 IF_RXPKT(printk("\nDmad Recvd data: len = %d \n", skb->len);
1348 xdump(skb->data, skb->len, "RX: ");
1349 printk("\n");)
1350
1351 IF_RX(printk("rx_dle_intr: skb push");)
1352 vcc->push(vcc,skb);
1353 atomic_inc(&vcc->stats->rx);
1354 iadev->rx_pkt_cnt++;
1355 }
1356INCR_DLE:
1357 if (++dle == iadev->rx_dle_q.end)
1358 dle = iadev->rx_dle_q.start;
1359 }
1360 iadev->rx_dle_q.read = dle;
1361
1362 /* if the interrupts are masked because there were no free desc available,
1363 unmask them now. */
1364 if (!iadev->rxing) {
1365 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1366 if (!(state & FREEQ_EMPTY)) {
1367 state = readl(iadev->reass_reg + REASS_MASK_REG) & 0xffff;
1368 writel(state & ~(RX_FREEQ_EMPT |/* RX_EXCP_RCVD |*/ RX_PKT_RCVD),
1369 iadev->reass_reg+REASS_MASK_REG);
1370 iadev->rxing++;
1371 }
1372 }
1373}
1374
1375
1376static int open_rx(struct atm_vcc *vcc)
1377{
1378 IADEV *iadev;
1379 u_short __iomem *vc_table;
1380 u_short __iomem *reass_ptr;
1381 IF_EVENT(printk("iadev: open_rx %d.%d\n", vcc->vpi, vcc->vci);)
1382
1383 if (vcc->qos.rxtp.traffic_class == ATM_NONE) return 0;
1384 iadev = INPH_IA_DEV(vcc->dev);
1385 if (vcc->qos.rxtp.traffic_class == ATM_ABR) {
1386 if (iadev->phy_type & FE_25MBIT_PHY) {
1387 printk("IA: ABR not support\n");
1388 return -EINVAL;
1389 }
1390 }
1391 /* Make only this VCI in the vc table valid and let all
1392 others be invalid entries */
1393 vc_table = iadev->reass_ram+RX_VC_TABLE*iadev->memSize;
1394 vc_table += vcc->vci;
1395 /* mask the last 6 bits and OR it with 3 for 1K VCs */
1396
1397 *vc_table = vcc->vci << 6;
1398 /* Also keep a list of open rx vcs so that we can attach them with
1399 incoming PDUs later. */
1400 if ((vcc->qos.rxtp.traffic_class == ATM_ABR) ||
1401 (vcc->qos.txtp.traffic_class == ATM_ABR))
1402 {
1403 srv_cls_param_t srv_p;
1404 init_abr_vc(iadev, &srv_p);
1405 ia_open_abr_vc(iadev, &srv_p, vcc, 0);
1406 }
1407 else { /* for UBR later may need to add CBR logic */
1408 reass_ptr = iadev->reass_ram+REASS_TABLE*iadev->memSize;
1409 reass_ptr += vcc->vci;
1410 *reass_ptr = NO_AAL5_PKT;
1411 }
1412
1413 if (iadev->rx_open[vcc->vci])
1414 printk(KERN_CRIT DEV_LABEL "(itf %d): VCI %d already open\n",
1415 vcc->dev->number, vcc->vci);
1416 iadev->rx_open[vcc->vci] = vcc;
1417 return 0;
1418}
1419
1420static int rx_init(struct atm_dev *dev)
1421{
1422 IADEV *iadev;
1423 struct rx_buf_desc __iomem *buf_desc_ptr;
1424 unsigned long rx_pkt_start = 0;
1425 void *dle_addr;
1426 struct abr_vc_table *abr_vc_table;
1427 u16 *vc_table;
1428 u16 *reass_table;
1429 int i,j, vcsize_sel;
1430 u_short freeq_st_adr;
1431 u_short *freeq_start;
1432
1433 iadev = INPH_IA_DEV(dev);
1434 // spin_lock_init(&iadev->rx_lock);
1435
1436 /* Allocate 4k bytes - more aligned than needed (4k boundary) */
1437 dle_addr = dma_alloc_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE,
1438 &iadev->rx_dle_dma, GFP_KERNEL);
1439 if (!dle_addr) {
1440 printk(KERN_ERR DEV_LABEL "can't allocate DLEs\n");
1441 goto err_out;
1442 }
1443 iadev->rx_dle_q.start = (struct dle *)dle_addr;
1444 iadev->rx_dle_q.read = iadev->rx_dle_q.start;
1445 iadev->rx_dle_q.write = iadev->rx_dle_q.start;
1446 iadev->rx_dle_q.end = (struct dle*)((unsigned long)dle_addr+sizeof(struct dle)*DLE_ENTRIES);
1447 /* the end of the dle q points to the entry after the last
1448 DLE that can be used. */
1449
1450 /* write the upper 20 bits of the start address to rx list address register */
1451 /* We know this is 32bit bus addressed so the following is safe */
1452 writel(iadev->rx_dle_dma & 0xfffff000,
1453 iadev->dma + IPHASE5575_RX_LIST_ADDR);
1454 IF_INIT(printk("Tx Dle list addr: 0x%p value: 0x%0x\n",
1455 iadev->dma+IPHASE5575_TX_LIST_ADDR,
1456 readl(iadev->dma + IPHASE5575_TX_LIST_ADDR));
1457 printk("Rx Dle list addr: 0x%p value: 0x%0x\n",
1458 iadev->dma+IPHASE5575_RX_LIST_ADDR,
1459 readl(iadev->dma + IPHASE5575_RX_LIST_ADDR));)
1460
1461 writew(0xffff, iadev->reass_reg+REASS_MASK_REG);
1462 writew(0, iadev->reass_reg+MODE_REG);
1463 writew(RESET_REASS, iadev->reass_reg+REASS_COMMAND_REG);
1464
1465 /* Receive side control memory map
1466 -------------------------------
1467
1468 Buffer descr 0x0000 (736 - 23K)
1469 VP Table 0x5c00 (256 - 512)
1470 Except q 0x5e00 (128 - 512)
1471 Free buffer q 0x6000 (1K - 2K)
1472 Packet comp q 0x6800 (1K - 2K)
1473 Reass Table 0x7000 (1K - 2K)
1474 VC Table 0x7800 (1K - 2K)
1475 ABR VC Table 0x8000 (1K - 32K)
1476 */
1477
1478 /* Base address for Buffer Descriptor Table */
1479 writew(RX_DESC_BASE >> 16, iadev->reass_reg+REASS_DESC_BASE);
1480 /* Set the buffer size register */
1481 writew(iadev->rx_buf_sz, iadev->reass_reg+BUF_SIZE);
1482
1483 /* Initialize each entry in the Buffer Descriptor Table */
1484 iadev->RX_DESC_BASE_ADDR = iadev->reass_ram+RX_DESC_BASE*iadev->memSize;
1485 buf_desc_ptr = iadev->RX_DESC_BASE_ADDR;
1486 memset_io(buf_desc_ptr, 0, sizeof(*buf_desc_ptr));
1487 buf_desc_ptr++;
1488 rx_pkt_start = iadev->rx_pkt_ram;
1489 for(i=1; i<=iadev->num_rx_desc; i++)
1490 {
1491 memset_io(buf_desc_ptr, 0, sizeof(*buf_desc_ptr));
1492 buf_desc_ptr->buf_start_hi = rx_pkt_start >> 16;
1493 buf_desc_ptr->buf_start_lo = rx_pkt_start & 0x0000ffff;
1494 buf_desc_ptr++;
1495 rx_pkt_start += iadev->rx_buf_sz;
1496 }
1497 IF_INIT(printk("Rx Buffer desc ptr: 0x%p\n", buf_desc_ptr);)
1498 i = FREE_BUF_DESC_Q*iadev->memSize;
1499 writew(i >> 16, iadev->reass_reg+REASS_QUEUE_BASE);
1500 writew(i, iadev->reass_reg+FREEQ_ST_ADR);
1501 writew(i+iadev->num_rx_desc*sizeof(u_short),
1502 iadev->reass_reg+FREEQ_ED_ADR);
1503 writew(i, iadev->reass_reg+FREEQ_RD_PTR);
1504 writew(i+iadev->num_rx_desc*sizeof(u_short),
1505 iadev->reass_reg+FREEQ_WR_PTR);
1506 /* Fill the FREEQ with all the free descriptors. */
1507 freeq_st_adr = readw(iadev->reass_reg+FREEQ_ST_ADR);
1508 freeq_start = (u_short *)(iadev->reass_ram+freeq_st_adr);
1509 for(i=1; i<=iadev->num_rx_desc; i++)
1510 {
1511 *freeq_start = (u_short)i;
1512 freeq_start++;
1513 }
1514 IF_INIT(printk("freeq_start: 0x%p\n", freeq_start);)
1515 /* Packet Complete Queue */
1516 i = (PKT_COMP_Q * iadev->memSize) & 0xffff;
1517 writew(i, iadev->reass_reg+PCQ_ST_ADR);
1518 writew(i+iadev->num_vc*sizeof(u_short), iadev->reass_reg+PCQ_ED_ADR);
1519 writew(i, iadev->reass_reg+PCQ_RD_PTR);
1520 writew(i, iadev->reass_reg+PCQ_WR_PTR);
1521
1522 /* Exception Queue */
1523 i = (EXCEPTION_Q * iadev->memSize) & 0xffff;
1524 writew(i, iadev->reass_reg+EXCP_Q_ST_ADR);
1525 writew(i + NUM_RX_EXCP * sizeof(RX_ERROR_Q),
1526 iadev->reass_reg+EXCP_Q_ED_ADR);
1527 writew(i, iadev->reass_reg+EXCP_Q_RD_PTR);
1528 writew(i, iadev->reass_reg+EXCP_Q_WR_PTR);
1529
1530 /* Load local copy of FREEQ and PCQ ptrs */
1531 iadev->rfL.fdq_st = readw(iadev->reass_reg+FREEQ_ST_ADR) & 0xffff;
1532 iadev->rfL.fdq_ed = readw(iadev->reass_reg+FREEQ_ED_ADR) & 0xffff ;
1533 iadev->rfL.fdq_rd = readw(iadev->reass_reg+FREEQ_RD_PTR) & 0xffff;
1534 iadev->rfL.fdq_wr = readw(iadev->reass_reg+FREEQ_WR_PTR) & 0xffff;
1535 iadev->rfL.pcq_st = readw(iadev->reass_reg+PCQ_ST_ADR) & 0xffff;
1536 iadev->rfL.pcq_ed = readw(iadev->reass_reg+PCQ_ED_ADR) & 0xffff;
1537 iadev->rfL.pcq_rd = readw(iadev->reass_reg+PCQ_RD_PTR) & 0xffff;
1538 iadev->rfL.pcq_wr = readw(iadev->reass_reg+PCQ_WR_PTR) & 0xffff;
1539
1540 IF_INIT(printk("INIT:pcq_st:0x%x pcq_ed:0x%x pcq_rd:0x%x pcq_wr:0x%x",
1541 iadev->rfL.pcq_st, iadev->rfL.pcq_ed, iadev->rfL.pcq_rd,
1542 iadev->rfL.pcq_wr);)
1543 /* just for check - no VP TBL */
1544 /* VP Table */
1545 /* writew(0x0b80, iadev->reass_reg+VP_LKUP_BASE); */
1546 /* initialize VP Table for invalid VPIs
1547 - I guess we can write all 1s or 0x000f in the entire memory
1548 space or something similar.
1549 */
1550
1551 /* This seems to work and looks right to me too !!! */
1552 i = REASS_TABLE * iadev->memSize;
1553 writew((i >> 3), iadev->reass_reg+REASS_TABLE_BASE);
1554 /* initialize Reassembly table to I don't know what ???? */
1555 reass_table = (u16 *)(iadev->reass_ram+i);
1556 j = REASS_TABLE_SZ * iadev->memSize;
1557 for(i=0; i < j; i++)
1558 *reass_table++ = NO_AAL5_PKT;
1559 i = 8*1024;
1560 vcsize_sel = 0;
1561 while (i != iadev->num_vc) {
1562 i /= 2;
1563 vcsize_sel++;
1564 }
1565 i = RX_VC_TABLE * iadev->memSize;
1566 writew(((i>>3) & 0xfff8) | vcsize_sel, iadev->reass_reg+VC_LKUP_BASE);
1567 vc_table = (u16 *)(iadev->reass_ram+RX_VC_TABLE*iadev->memSize);
1568 j = RX_VC_TABLE_SZ * iadev->memSize;
1569 for(i = 0; i < j; i++)
1570 {
1571 /* shift the reassembly pointer by 3 + lower 3 bits of
1572 vc_lkup_base register (=3 for 1K VCs) and the last byte
1573 is those low 3 bits.
1574 Shall program this later.
1575 */
1576 *vc_table = (i << 6) | 15; /* for invalid VCI */
1577 vc_table++;
1578 }
1579 /* ABR VC table */
1580 i = ABR_VC_TABLE * iadev->memSize;
1581 writew(i >> 3, iadev->reass_reg+ABR_LKUP_BASE);
1582
1583 i = ABR_VC_TABLE * iadev->memSize;
1584 abr_vc_table = (struct abr_vc_table *)(iadev->reass_ram+i);
1585 j = REASS_TABLE_SZ * iadev->memSize;
1586 memset ((char*)abr_vc_table, 0, j * sizeof(*abr_vc_table));
1587 for(i = 0; i < j; i++) {
1588 abr_vc_table->rdf = 0x0003;
1589 abr_vc_table->air = 0x5eb1;
1590 abr_vc_table++;
1591 }
1592
1593 /* Initialize other registers */
1594
1595 /* VP Filter Register set for VC Reassembly only */
1596 writew(0xff00, iadev->reass_reg+VP_FILTER);
1597 writew(0, iadev->reass_reg+XTRA_RM_OFFSET);
1598 writew(0x1, iadev->reass_reg+PROTOCOL_ID);
1599
1600 /* Packet Timeout Count related Registers :
1601 Set packet timeout to occur in about 3 seconds
1602 Set Packet Aging Interval count register to overflow in about 4 us
1603 */
1604 writew(0xF6F8, iadev->reass_reg+PKT_TM_CNT );
1605
1606 i = (j >> 6) & 0xFF;
1607 j += 2 * (j - 1);
1608 i |= ((j << 2) & 0xFF00);
1609 writew(i, iadev->reass_reg+TMOUT_RANGE);
1610
1611 /* initiate the desc_tble */
1612 for(i=0; i<iadev->num_tx_desc;i++)
1613 iadev->desc_tbl[i].timestamp = 0;
1614
1615 /* to clear the interrupt status register - read it */
1616 readw(iadev->reass_reg+REASS_INTR_STATUS_REG);
1617
1618 /* Mask Register - clear it */
1619 writew(~(RX_FREEQ_EMPT|RX_PKT_RCVD), iadev->reass_reg+REASS_MASK_REG);
1620
1621 skb_queue_head_init(&iadev->rx_dma_q);
1622 iadev->rx_free_desc_qhead = NULL;
1623
1624 iadev->rx_open = kcalloc(iadev->num_vc, sizeof(void *), GFP_KERNEL);
1625 if (!iadev->rx_open) {
1626 printk(KERN_ERR DEV_LABEL "itf %d couldn't get free page\n",
1627 dev->number);
1628 goto err_free_dle;
1629 }
1630
1631 iadev->rxing = 1;
1632 iadev->rx_pkt_cnt = 0;
1633 /* Mode Register */
1634 writew(R_ONLINE, iadev->reass_reg+MODE_REG);
1635 return 0;
1636
1637err_free_dle:
1638 dma_free_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE, iadev->rx_dle_q.start,
1639 iadev->rx_dle_dma);
1640err_out:
1641 return -ENOMEM;
1642}
1643
1644
1645/*
1646 The memory map suggested in appendix A and the coding for it.
1647 Keeping it around just in case we change our mind later.
1648
1649 Buffer descr 0x0000 (128 - 4K)
1650 UBR sched 0x1000 (1K - 4K)
1651 UBR Wait q 0x2000 (1K - 4K)
1652 Commn queues 0x3000 Packet Ready, Trasmit comp(0x3100)
1653 (128 - 256) each
1654 extended VC 0x4000 (1K - 8K)
1655 ABR sched 0x6000 and ABR wait queue (1K - 2K) each
1656 CBR sched 0x7000 (as needed)
1657 VC table 0x8000 (1K - 32K)
1658*/
1659
1660static void tx_intr(struct atm_dev *dev)
1661{
1662 IADEV *iadev;
1663 unsigned short status;
1664 unsigned long flags;
1665
1666 iadev = INPH_IA_DEV(dev);
1667
1668 status = readl(iadev->seg_reg+SEG_INTR_STATUS_REG);
1669 if (status & TRANSMIT_DONE){
1670
1671 IF_EVENT(printk("Transmit Done Intr logic run\n");)
1672 spin_lock_irqsave(&iadev->tx_lock, flags);
1673 ia_tx_poll(iadev);
1674 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1675 writew(TRANSMIT_DONE, iadev->seg_reg+SEG_INTR_STATUS_REG);
1676 if (iadev->close_pending)
1677 wake_up(&iadev->close_wait);
1678 }
1679 if (status & TCQ_NOT_EMPTY)
1680 {
1681 IF_EVENT(printk("TCQ_NOT_EMPTY int received\n");)
1682 }
1683}
1684
1685static void tx_dle_intr(struct atm_dev *dev)
1686{
1687 IADEV *iadev;
1688 struct dle *dle, *cur_dle;
1689 struct sk_buff *skb;
1690 struct atm_vcc *vcc;
1691 struct ia_vcc *iavcc;
1692 u_int dle_lp;
1693 unsigned long flags;
1694
1695 iadev = INPH_IA_DEV(dev);
1696 spin_lock_irqsave(&iadev->tx_lock, flags);
1697 dle = iadev->tx_dle_q.read;
1698 dle_lp = readl(iadev->dma+IPHASE5575_TX_LIST_ADDR) &
1699 (sizeof(struct dle)*DLE_ENTRIES - 1);
1700 cur_dle = (struct dle*)(iadev->tx_dle_q.start + (dle_lp >> 4));
1701 while (dle != cur_dle)
1702 {
1703 /* free the DMAed skb */
1704 skb = skb_dequeue(&iadev->tx_dma_q);
1705 if (!skb) break;
1706
1707 /* Revenge of the 2 dle (skb + trailer) used in ia_pkt_tx() */
1708 if (!((dle - iadev->tx_dle_q.start)%(2*sizeof(struct dle)))) {
1709 dma_unmap_single(&iadev->pci->dev, dle->sys_pkt_addr, skb->len,
1710 DMA_TO_DEVICE);
1711 }
1712 vcc = ATM_SKB(skb)->vcc;
1713 if (!vcc) {
1714 printk("tx_dle_intr: vcc is null\n");
1715 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1716 dev_kfree_skb_any(skb);
1717
1718 return;
1719 }
1720 iavcc = INPH_IA_VCC(vcc);
1721 if (!iavcc) {
1722 printk("tx_dle_intr: iavcc is null\n");
1723 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1724 dev_kfree_skb_any(skb);
1725 return;
1726 }
1727 if (vcc->qos.txtp.pcr >= iadev->rate_limit) {
1728 if ((vcc->pop) && (skb->len != 0))
1729 {
1730 vcc->pop(vcc, skb);
1731 }
1732 else {
1733 dev_kfree_skb_any(skb);
1734 }
1735 }
1736 else { /* Hold the rate-limited skb for flow control */
1737 IA_SKB_STATE(skb) |= IA_DLED;
1738 skb_queue_tail(&iavcc->txing_skb, skb);
1739 }
1740 IF_EVENT(printk("tx_dle_intr: enque skb = 0x%p \n", skb);)
1741 if (++dle == iadev->tx_dle_q.end)
1742 dle = iadev->tx_dle_q.start;
1743 }
1744 iadev->tx_dle_q.read = dle;
1745 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1746}
1747
1748static int open_tx(struct atm_vcc *vcc)
1749{
1750 struct ia_vcc *ia_vcc;
1751 IADEV *iadev;
1752 struct main_vc *vc;
1753 struct ext_vc *evc;
1754 int ret;
1755 IF_EVENT(printk("iadev: open_tx entered vcc->vci = %d\n", vcc->vci);)
1756 if (vcc->qos.txtp.traffic_class == ATM_NONE) return 0;
1757 iadev = INPH_IA_DEV(vcc->dev);
1758
1759 if (iadev->phy_type & FE_25MBIT_PHY) {
1760 if (vcc->qos.txtp.traffic_class == ATM_ABR) {
1761 printk("IA: ABR not support\n");
1762 return -EINVAL;
1763 }
1764 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1765 printk("IA: CBR not support\n");
1766 return -EINVAL;
1767 }
1768 }
1769 ia_vcc = INPH_IA_VCC(vcc);
1770 memset((caddr_t)ia_vcc, 0, sizeof(*ia_vcc));
1771 if (vcc->qos.txtp.max_sdu >
1772 (iadev->tx_buf_sz - sizeof(struct cpcs_trailer))){
1773 printk("IA: SDU size over (%d) the configured SDU size %d\n",
1774 vcc->qos.txtp.max_sdu,iadev->tx_buf_sz);
1775 vcc->dev_data = NULL;
1776 kfree(ia_vcc);
1777 return -EINVAL;
1778 }
1779 ia_vcc->vc_desc_cnt = 0;
1780 ia_vcc->txing = 1;
1781
1782 /* find pcr */
1783 if (vcc->qos.txtp.max_pcr == ATM_MAX_PCR)
1784 vcc->qos.txtp.pcr = iadev->LineRate;
1785 else if ((vcc->qos.txtp.max_pcr == 0)&&( vcc->qos.txtp.pcr <= 0))
1786 vcc->qos.txtp.pcr = iadev->LineRate;
1787 else if ((vcc->qos.txtp.max_pcr > vcc->qos.txtp.pcr) && (vcc->qos.txtp.max_pcr> 0))
1788 vcc->qos.txtp.pcr = vcc->qos.txtp.max_pcr;
1789 if (vcc->qos.txtp.pcr > iadev->LineRate)
1790 vcc->qos.txtp.pcr = iadev->LineRate;
1791 ia_vcc->pcr = vcc->qos.txtp.pcr;
1792
1793 if (ia_vcc->pcr > (iadev->LineRate / 6) ) ia_vcc->ltimeout = HZ / 10;
1794 else if (ia_vcc->pcr > (iadev->LineRate / 130)) ia_vcc->ltimeout = HZ;
1795 else if (ia_vcc->pcr <= 170) ia_vcc->ltimeout = 16 * HZ;
1796 else ia_vcc->ltimeout = 2700 * HZ / ia_vcc->pcr;
1797 if (ia_vcc->pcr < iadev->rate_limit)
1798 skb_queue_head_init (&ia_vcc->txing_skb);
1799 if (ia_vcc->pcr < iadev->rate_limit) {
1800 struct sock *sk = sk_atm(vcc);
1801
1802 if (vcc->qos.txtp.max_sdu != 0) {
1803 if (ia_vcc->pcr > 60000)
1804 sk->sk_sndbuf = vcc->qos.txtp.max_sdu * 5;
1805 else if (ia_vcc->pcr > 2000)
1806 sk->sk_sndbuf = vcc->qos.txtp.max_sdu * 4;
1807 else
1808 sk->sk_sndbuf = vcc->qos.txtp.max_sdu * 3;
1809 }
1810 else
1811 sk->sk_sndbuf = 24576;
1812 }
1813
1814 vc = (struct main_vc *)iadev->MAIN_VC_TABLE_ADDR;
1815 evc = (struct ext_vc *)iadev->EXT_VC_TABLE_ADDR;
1816 vc += vcc->vci;
1817 evc += vcc->vci;
1818 memset((caddr_t)vc, 0, sizeof(*vc));
1819 memset((caddr_t)evc, 0, sizeof(*evc));
1820
1821 /* store the most significant 4 bits of vci as the last 4 bits
1822 of first part of atm header.
1823 store the last 12 bits of vci as first 12 bits of the second
1824 part of the atm header.
1825 */
1826 evc->atm_hdr1 = (vcc->vci >> 12) & 0x000f;
1827 evc->atm_hdr2 = (vcc->vci & 0x0fff) << 4;
1828
1829 /* check the following for different traffic classes */
1830 if (vcc->qos.txtp.traffic_class == ATM_UBR)
1831 {
1832 vc->type = UBR;
1833 vc->status = CRC_APPEND;
1834 vc->acr = cellrate_to_float(iadev->LineRate);
1835 if (vcc->qos.txtp.pcr > 0)
1836 vc->acr = cellrate_to_float(vcc->qos.txtp.pcr);
1837 IF_UBR(printk("UBR: txtp.pcr = 0x%x f_rate = 0x%x\n",
1838 vcc->qos.txtp.max_pcr,vc->acr);)
1839 }
1840 else if (vcc->qos.txtp.traffic_class == ATM_ABR)
1841 { srv_cls_param_t srv_p;
1842 IF_ABR(printk("Tx ABR VCC\n");)
1843 init_abr_vc(iadev, &srv_p);
1844 if (vcc->qos.txtp.pcr > 0)
1845 srv_p.pcr = vcc->qos.txtp.pcr;
1846 if (vcc->qos.txtp.min_pcr > 0) {
1847 int tmpsum = iadev->sum_mcr+iadev->sum_cbr+vcc->qos.txtp.min_pcr;
1848 if (tmpsum > iadev->LineRate)
1849 return -EBUSY;
1850 srv_p.mcr = vcc->qos.txtp.min_pcr;
1851 iadev->sum_mcr += vcc->qos.txtp.min_pcr;
1852 }
1853 else srv_p.mcr = 0;
1854 if (vcc->qos.txtp.icr)
1855 srv_p.icr = vcc->qos.txtp.icr;
1856 if (vcc->qos.txtp.tbe)
1857 srv_p.tbe = vcc->qos.txtp.tbe;
1858 if (vcc->qos.txtp.frtt)
1859 srv_p.frtt = vcc->qos.txtp.frtt;
1860 if (vcc->qos.txtp.rif)
1861 srv_p.rif = vcc->qos.txtp.rif;
1862 if (vcc->qos.txtp.rdf)
1863 srv_p.rdf = vcc->qos.txtp.rdf;
1864 if (vcc->qos.txtp.nrm_pres)
1865 srv_p.nrm = vcc->qos.txtp.nrm;
1866 if (vcc->qos.txtp.trm_pres)
1867 srv_p.trm = vcc->qos.txtp.trm;
1868 if (vcc->qos.txtp.adtf_pres)
1869 srv_p.adtf = vcc->qos.txtp.adtf;
1870 if (vcc->qos.txtp.cdf_pres)
1871 srv_p.cdf = vcc->qos.txtp.cdf;
1872 if (srv_p.icr > srv_p.pcr)
1873 srv_p.icr = srv_p.pcr;
1874 IF_ABR(printk("ABR:vcc->qos.txtp.max_pcr = %d mcr = %d\n",
1875 srv_p.pcr, srv_p.mcr);)
1876 ia_open_abr_vc(iadev, &srv_p, vcc, 1);
1877 } else if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1878 if (iadev->phy_type & FE_25MBIT_PHY) {
1879 printk("IA: CBR not support\n");
1880 return -EINVAL;
1881 }
1882 if (vcc->qos.txtp.max_pcr > iadev->LineRate) {
1883 IF_CBR(printk("PCR is not available\n");)
1884 return -1;
1885 }
1886 vc->type = CBR;
1887 vc->status = CRC_APPEND;
1888 if ((ret = ia_cbr_setup (iadev, vcc)) < 0) {
1889 return ret;
1890 }
1891 } else {
1892 printk("iadev: Non UBR, ABR and CBR traffic not supported\n");
1893 }
1894
1895 iadev->testTable[vcc->vci]->vc_status |= VC_ACTIVE;
1896 IF_EVENT(printk("ia open_tx returning \n");)
1897 return 0;
1898}
1899
1900
1901static int tx_init(struct atm_dev *dev)
1902{
1903 IADEV *iadev;
1904 struct tx_buf_desc *buf_desc_ptr;
1905 unsigned int tx_pkt_start;
1906 void *dle_addr;
1907 int i;
1908 u_short tcq_st_adr;
1909 u_short *tcq_start;
1910 u_short prq_st_adr;
1911 u_short *prq_start;
1912 struct main_vc *vc;
1913 struct ext_vc *evc;
1914 u_short tmp16;
1915 u32 vcsize_sel;
1916
1917 iadev = INPH_IA_DEV(dev);
1918 spin_lock_init(&iadev->tx_lock);
1919
1920 IF_INIT(printk("Tx MASK REG: 0x%0x\n",
1921 readw(iadev->seg_reg+SEG_MASK_REG));)
1922
1923 /* Allocate 4k (boundary aligned) bytes */
1924 dle_addr = dma_alloc_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE,
1925 &iadev->tx_dle_dma, GFP_KERNEL);
1926 if (!dle_addr) {
1927 printk(KERN_ERR DEV_LABEL "can't allocate DLEs\n");
1928 goto err_out;
1929 }
1930 iadev->tx_dle_q.start = (struct dle*)dle_addr;
1931 iadev->tx_dle_q.read = iadev->tx_dle_q.start;
1932 iadev->tx_dle_q.write = iadev->tx_dle_q.start;
1933 iadev->tx_dle_q.end = (struct dle*)((unsigned long)dle_addr+sizeof(struct dle)*DLE_ENTRIES);
1934
1935 /* write the upper 20 bits of the start address to tx list address register */
1936 writel(iadev->tx_dle_dma & 0xfffff000,
1937 iadev->dma + IPHASE5575_TX_LIST_ADDR);
1938 writew(0xffff, iadev->seg_reg+SEG_MASK_REG);
1939 writew(0, iadev->seg_reg+MODE_REG_0);
1940 writew(RESET_SEG, iadev->seg_reg+SEG_COMMAND_REG);
1941 iadev->MAIN_VC_TABLE_ADDR = iadev->seg_ram+MAIN_VC_TABLE*iadev->memSize;
1942 iadev->EXT_VC_TABLE_ADDR = iadev->seg_ram+EXT_VC_TABLE*iadev->memSize;
1943 iadev->ABR_SCHED_TABLE_ADDR=iadev->seg_ram+ABR_SCHED_TABLE*iadev->memSize;
1944
1945 /*
1946 Transmit side control memory map
1947 --------------------------------
1948 Buffer descr 0x0000 (128 - 4K)
1949 Commn queues 0x1000 Transmit comp, Packet ready(0x1400)
1950 (512 - 1K) each
1951 TCQ - 4K, PRQ - 5K
1952 CBR Table 0x1800 (as needed) - 6K
1953 UBR Table 0x3000 (1K - 4K) - 12K
1954 UBR Wait queue 0x4000 (1K - 4K) - 16K
1955 ABR sched 0x5000 and ABR wait queue (1K - 2K) each
1956 ABR Tbl - 20K, ABR Wq - 22K
1957 extended VC 0x6000 (1K - 8K) - 24K
1958 VC Table 0x8000 (1K - 32K) - 32K
1959
1960 Between 0x2000 (8K) and 0x3000 (12K) there is 4K space left for VBR Tbl
1961 and Wait q, which can be allotted later.
1962 */
1963
1964 /* Buffer Descriptor Table Base address */
1965 writew(TX_DESC_BASE, iadev->seg_reg+SEG_DESC_BASE);
1966
1967 /* initialize each entry in the buffer descriptor table */
1968 buf_desc_ptr =(struct tx_buf_desc *)(iadev->seg_ram+TX_DESC_BASE);
1969 memset((caddr_t)buf_desc_ptr, 0, sizeof(*buf_desc_ptr));
1970 buf_desc_ptr++;
1971 tx_pkt_start = TX_PACKET_RAM;
1972 for(i=1; i<=iadev->num_tx_desc; i++)
1973 {
1974 memset((caddr_t)buf_desc_ptr, 0, sizeof(*buf_desc_ptr));
1975 buf_desc_ptr->desc_mode = AAL5;
1976 buf_desc_ptr->buf_start_hi = tx_pkt_start >> 16;
1977 buf_desc_ptr->buf_start_lo = tx_pkt_start & 0x0000ffff;
1978 buf_desc_ptr++;
1979 tx_pkt_start += iadev->tx_buf_sz;
1980 }
1981 iadev->tx_buf = kmalloc_array(iadev->num_tx_desc,
1982 sizeof(*iadev->tx_buf),
1983 GFP_KERNEL);
1984 if (!iadev->tx_buf) {
1985 printk(KERN_ERR DEV_LABEL " couldn't get mem\n");
1986 goto err_free_dle;
1987 }
1988 for (i= 0; i< iadev->num_tx_desc; i++)
1989 {
1990 struct cpcs_trailer *cpcs;
1991
1992 cpcs = kmalloc(sizeof(*cpcs), GFP_KERNEL|GFP_DMA);
1993 if(!cpcs) {
1994 printk(KERN_ERR DEV_LABEL " couldn't get freepage\n");
1995 goto err_free_tx_bufs;
1996 }
1997 iadev->tx_buf[i].cpcs = cpcs;
1998 iadev->tx_buf[i].dma_addr = dma_map_single(&iadev->pci->dev,
1999 cpcs,
2000 sizeof(*cpcs),
2001 DMA_TO_DEVICE);
2002 }
2003 iadev->desc_tbl = kmalloc_array(iadev->num_tx_desc,
2004 sizeof(*iadev->desc_tbl),
2005 GFP_KERNEL);
2006 if (!iadev->desc_tbl) {
2007 printk(KERN_ERR DEV_LABEL " couldn't get mem\n");
2008 goto err_free_all_tx_bufs;
2009 }
2010
2011 /* Communication Queues base address */
2012 i = TX_COMP_Q * iadev->memSize;
2013 writew(i >> 16, iadev->seg_reg+SEG_QUEUE_BASE);
2014
2015 /* Transmit Complete Queue */
2016 writew(i, iadev->seg_reg+TCQ_ST_ADR);
2017 writew(i, iadev->seg_reg+TCQ_RD_PTR);
2018 writew(i+iadev->num_tx_desc*sizeof(u_short),iadev->seg_reg+TCQ_WR_PTR);
2019 iadev->host_tcq_wr = i + iadev->num_tx_desc*sizeof(u_short);
2020 writew(i+2 * iadev->num_tx_desc * sizeof(u_short),
2021 iadev->seg_reg+TCQ_ED_ADR);
2022 /* Fill the TCQ with all the free descriptors. */
2023 tcq_st_adr = readw(iadev->seg_reg+TCQ_ST_ADR);
2024 tcq_start = (u_short *)(iadev->seg_ram+tcq_st_adr);
2025 for(i=1; i<=iadev->num_tx_desc; i++)
2026 {
2027 *tcq_start = (u_short)i;
2028 tcq_start++;
2029 }
2030
2031 /* Packet Ready Queue */
2032 i = PKT_RDY_Q * iadev->memSize;
2033 writew(i, iadev->seg_reg+PRQ_ST_ADR);
2034 writew(i+2 * iadev->num_tx_desc * sizeof(u_short),
2035 iadev->seg_reg+PRQ_ED_ADR);
2036 writew(i, iadev->seg_reg+PRQ_RD_PTR);
2037 writew(i, iadev->seg_reg+PRQ_WR_PTR);
2038
2039 /* Load local copy of PRQ and TCQ ptrs */
2040 iadev->ffL.prq_st = readw(iadev->seg_reg+PRQ_ST_ADR) & 0xffff;
2041 iadev->ffL.prq_ed = readw(iadev->seg_reg+PRQ_ED_ADR) & 0xffff;
2042 iadev->ffL.prq_wr = readw(iadev->seg_reg+PRQ_WR_PTR) & 0xffff;
2043
2044 iadev->ffL.tcq_st = readw(iadev->seg_reg+TCQ_ST_ADR) & 0xffff;
2045 iadev->ffL.tcq_ed = readw(iadev->seg_reg+TCQ_ED_ADR) & 0xffff;
2046 iadev->ffL.tcq_rd = readw(iadev->seg_reg+TCQ_RD_PTR) & 0xffff;
2047
2048 /* Just for safety initializing the queue to have desc 1 always */
2049 /* Fill the PRQ with all the free descriptors. */
2050 prq_st_adr = readw(iadev->seg_reg+PRQ_ST_ADR);
2051 prq_start = (u_short *)(iadev->seg_ram+prq_st_adr);
2052 for(i=1; i<=iadev->num_tx_desc; i++)
2053 {
2054 *prq_start = (u_short)0; /* desc 1 in all entries */
2055 prq_start++;
2056 }
2057 /* CBR Table */
2058 IF_INIT(printk("Start CBR Init\n");)
2059#if 1 /* for 1K VC board, CBR_PTR_BASE is 0 */
2060 writew(0,iadev->seg_reg+CBR_PTR_BASE);
2061#else /* Charlie's logic is wrong ? */
2062 tmp16 = (iadev->seg_ram+CBR_SCHED_TABLE*iadev->memSize)>>17;
2063 IF_INIT(printk("cbr_ptr_base = 0x%x ", tmp16);)
2064 writew(tmp16,iadev->seg_reg+CBR_PTR_BASE);
2065#endif
2066
2067 IF_INIT(printk("value in register = 0x%x\n",
2068 readw(iadev->seg_reg+CBR_PTR_BASE));)
2069 tmp16 = (CBR_SCHED_TABLE*iadev->memSize) >> 1;
2070 writew(tmp16, iadev->seg_reg+CBR_TAB_BEG);
2071 IF_INIT(printk("cbr_tab_beg = 0x%x in reg = 0x%x \n", tmp16,
2072 readw(iadev->seg_reg+CBR_TAB_BEG));)
2073 writew(tmp16, iadev->seg_reg+CBR_TAB_END+1); // CBR_PTR;
2074 tmp16 = (CBR_SCHED_TABLE*iadev->memSize + iadev->num_vc*6 - 2) >> 1;
2075 writew(tmp16, iadev->seg_reg+CBR_TAB_END);
2076 IF_INIT(printk("iadev->seg_reg = 0x%p CBR_PTR_BASE = 0x%x\n",
2077 iadev->seg_reg, readw(iadev->seg_reg+CBR_PTR_BASE));)
2078 IF_INIT(printk("CBR_TAB_BEG = 0x%x, CBR_TAB_END = 0x%x, CBR_PTR = 0x%x\n",
2079 readw(iadev->seg_reg+CBR_TAB_BEG), readw(iadev->seg_reg+CBR_TAB_END),
2080 readw(iadev->seg_reg+CBR_TAB_END+1));)
2081
2082 /* Initialize the CBR Schedualing Table */
2083 memset_io(iadev->seg_ram+CBR_SCHED_TABLE*iadev->memSize,
2084 0, iadev->num_vc*6);
2085 iadev->CbrRemEntries = iadev->CbrTotEntries = iadev->num_vc*3;
2086 iadev->CbrEntryPt = 0;
2087 iadev->Granularity = MAX_ATM_155 / iadev->CbrTotEntries;
2088 iadev->NumEnabledCBR = 0;
2089
2090 /* UBR scheduling Table and wait queue */
2091 /* initialize all bytes of UBR scheduler table and wait queue to 0
2092 - SCHEDSZ is 1K (# of entries).
2093 - UBR Table size is 4K
2094 - UBR wait queue is 4K
2095 since the table and wait queues are contiguous, all the bytes
2096 can be initialized by one memeset.
2097 */
2098
2099 vcsize_sel = 0;
2100 i = 8*1024;
2101 while (i != iadev->num_vc) {
2102 i /= 2;
2103 vcsize_sel++;
2104 }
2105
2106 i = MAIN_VC_TABLE * iadev->memSize;
2107 writew(vcsize_sel | ((i >> 8) & 0xfff8),iadev->seg_reg+VCT_BASE);
2108 i = EXT_VC_TABLE * iadev->memSize;
2109 writew((i >> 8) & 0xfffe, iadev->seg_reg+VCTE_BASE);
2110 i = UBR_SCHED_TABLE * iadev->memSize;
2111 writew((i & 0xffff) >> 11, iadev->seg_reg+UBR_SBPTR_BASE);
2112 i = UBR_WAIT_Q * iadev->memSize;
2113 writew((i >> 7) & 0xffff, iadev->seg_reg+UBRWQ_BASE);
2114 memset((caddr_t)(iadev->seg_ram+UBR_SCHED_TABLE*iadev->memSize),
2115 0, iadev->num_vc*8);
2116 /* ABR scheduling Table(0x5000-0x57ff) and wait queue(0x5800-0x5fff)*/
2117 /* initialize all bytes of ABR scheduler table and wait queue to 0
2118 - SCHEDSZ is 1K (# of entries).
2119 - ABR Table size is 2K
2120 - ABR wait queue is 2K
2121 since the table and wait queues are contiguous, all the bytes
2122 can be initialized by one memeset.
2123 */
2124 i = ABR_SCHED_TABLE * iadev->memSize;
2125 writew((i >> 11) & 0xffff, iadev->seg_reg+ABR_SBPTR_BASE);
2126 i = ABR_WAIT_Q * iadev->memSize;
2127 writew((i >> 7) & 0xffff, iadev->seg_reg+ABRWQ_BASE);
2128
2129 i = ABR_SCHED_TABLE*iadev->memSize;
2130 memset((caddr_t)(iadev->seg_ram+i), 0, iadev->num_vc*4);
2131 vc = (struct main_vc *)iadev->MAIN_VC_TABLE_ADDR;
2132 evc = (struct ext_vc *)iadev->EXT_VC_TABLE_ADDR;
2133 iadev->testTable = kmalloc_array(iadev->num_vc,
2134 sizeof(*iadev->testTable),
2135 GFP_KERNEL);
2136 if (!iadev->testTable) {
2137 printk("Get freepage failed\n");
2138 goto err_free_desc_tbl;
2139 }
2140 for(i=0; i<iadev->num_vc; i++)
2141 {
2142 memset((caddr_t)vc, 0, sizeof(*vc));
2143 memset((caddr_t)evc, 0, sizeof(*evc));
2144 iadev->testTable[i] = kmalloc(sizeof(struct testTable_t),
2145 GFP_KERNEL);
2146 if (!iadev->testTable[i])
2147 goto err_free_test_tables;
2148 iadev->testTable[i]->lastTime = 0;
2149 iadev->testTable[i]->fract = 0;
2150 iadev->testTable[i]->vc_status = VC_UBR;
2151 vc++;
2152 evc++;
2153 }
2154
2155 /* Other Initialization */
2156
2157 /* Max Rate Register */
2158 if (iadev->phy_type & FE_25MBIT_PHY) {
2159 writew(RATE25, iadev->seg_reg+MAXRATE);
2160 writew((UBR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS);
2161 }
2162 else {
2163 writew(cellrate_to_float(iadev->LineRate),iadev->seg_reg+MAXRATE);
2164 writew((UBR_EN | ABR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS);
2165 }
2166 /* Set Idle Header Reigisters to be sure */
2167 writew(0, iadev->seg_reg+IDLEHEADHI);
2168 writew(0, iadev->seg_reg+IDLEHEADLO);
2169
2170 /* Program ABR UBR Priority Register as PRI_ABR_UBR_EQUAL */
2171 writew(0xaa00, iadev->seg_reg+ABRUBR_ARB);
2172
2173 iadev->close_pending = 0;
2174 init_waitqueue_head(&iadev->close_wait);
2175 init_waitqueue_head(&iadev->timeout_wait);
2176 skb_queue_head_init(&iadev->tx_dma_q);
2177 ia_init_rtn_q(&iadev->tx_return_q);
2178
2179 /* RM Cell Protocol ID and Message Type */
2180 writew(RM_TYPE_4_0, iadev->seg_reg+RM_TYPE);
2181 skb_queue_head_init (&iadev->tx_backlog);
2182
2183 /* Mode Register 1 */
2184 writew(MODE_REG_1_VAL, iadev->seg_reg+MODE_REG_1);
2185
2186 /* Mode Register 0 */
2187 writew(T_ONLINE, iadev->seg_reg+MODE_REG_0);
2188
2189 /* Interrupt Status Register - read to clear */
2190 readw(iadev->seg_reg+SEG_INTR_STATUS_REG);
2191
2192 /* Interrupt Mask Reg- don't mask TCQ_NOT_EMPTY interrupt generation */
2193 writew(~(TRANSMIT_DONE | TCQ_NOT_EMPTY), iadev->seg_reg+SEG_MASK_REG);
2194 writew(TRANSMIT_DONE, iadev->seg_reg+SEG_INTR_STATUS_REG);
2195 iadev->tx_pkt_cnt = 0;
2196 iadev->rate_limit = iadev->LineRate / 3;
2197
2198 return 0;
2199
2200err_free_test_tables:
2201 while (--i >= 0)
2202 kfree(iadev->testTable[i]);
2203 kfree(iadev->testTable);
2204err_free_desc_tbl:
2205 kfree(iadev->desc_tbl);
2206err_free_all_tx_bufs:
2207 i = iadev->num_tx_desc;
2208err_free_tx_bufs:
2209 while (--i >= 0) {
2210 struct cpcs_trailer_desc *desc = iadev->tx_buf + i;
2211
2212 dma_unmap_single(&iadev->pci->dev, desc->dma_addr,
2213 sizeof(*desc->cpcs), DMA_TO_DEVICE);
2214 kfree(desc->cpcs);
2215 }
2216 kfree(iadev->tx_buf);
2217err_free_dle:
2218 dma_free_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE, iadev->tx_dle_q.start,
2219 iadev->tx_dle_dma);
2220err_out:
2221 return -ENOMEM;
2222}
2223
2224static irqreturn_t ia_int(int irq, void *dev_id)
2225{
2226 struct atm_dev *dev;
2227 IADEV *iadev;
2228 unsigned int status;
2229 int handled = 0;
2230
2231 dev = dev_id;
2232 iadev = INPH_IA_DEV(dev);
2233 while( (status = readl(iadev->reg+IPHASE5575_BUS_STATUS_REG) & 0x7f))
2234 {
2235 handled = 1;
2236 IF_EVENT(printk("ia_int: status = 0x%x\n", status);)
2237 if (status & STAT_REASSINT)
2238 {
2239 /* do something */
2240 IF_EVENT(printk("REASSINT Bus status reg: %08x\n", status);)
2241 rx_intr(dev);
2242 }
2243 if (status & STAT_DLERINT)
2244 {
2245 /* Clear this bit by writing a 1 to it. */
2246 writel(STAT_DLERINT, iadev->reg + IPHASE5575_BUS_STATUS_REG);
2247 rx_dle_intr(dev);
2248 }
2249 if (status & STAT_SEGINT)
2250 {
2251 /* do something */
2252 IF_EVENT(printk("IA: tx_intr \n");)
2253 tx_intr(dev);
2254 }
2255 if (status & STAT_DLETINT)
2256 {
2257 writel(STAT_DLETINT, iadev->reg + IPHASE5575_BUS_STATUS_REG);
2258 tx_dle_intr(dev);
2259 }
2260 if (status & (STAT_FEINT | STAT_ERRINT | STAT_MARKINT))
2261 {
2262 if (status & STAT_FEINT)
2263 ia_frontend_intr(iadev);
2264 }
2265 }
2266 return IRQ_RETVAL(handled);
2267}
2268
2269
2270
2271/*----------------------------- entries --------------------------------*/
2272static int get_esi(struct atm_dev *dev)
2273{
2274 IADEV *iadev;
2275 int i;
2276 u32 mac1;
2277 u16 mac2;
2278
2279 iadev = INPH_IA_DEV(dev);
2280 mac1 = cpu_to_be32(le32_to_cpu(readl(
2281 iadev->reg+IPHASE5575_MAC1)));
2282 mac2 = cpu_to_be16(le16_to_cpu(readl(iadev->reg+IPHASE5575_MAC2)));
2283 IF_INIT(printk("ESI: 0x%08x%04x\n", mac1, mac2);)
2284 for (i=0; i<MAC1_LEN; i++)
2285 dev->esi[i] = mac1 >>(8*(MAC1_LEN-1-i));
2286
2287 for (i=0; i<MAC2_LEN; i++)
2288 dev->esi[i+MAC1_LEN] = mac2 >>(8*(MAC2_LEN - 1 -i));
2289 return 0;
2290}
2291
2292static int reset_sar(struct atm_dev *dev)
2293{
2294 IADEV *iadev;
2295 int i, error;
2296 unsigned int pci[64];
2297
2298 iadev = INPH_IA_DEV(dev);
2299 for (i = 0; i < 64; i++) {
2300 error = pci_read_config_dword(iadev->pci, i * 4, &pci[i]);
2301 if (error != PCIBIOS_SUCCESSFUL)
2302 return error;
2303 }
2304 writel(0, iadev->reg+IPHASE5575_EXT_RESET);
2305 for (i = 0; i < 64; i++) {
2306 error = pci_write_config_dword(iadev->pci, i * 4, pci[i]);
2307 if (error != PCIBIOS_SUCCESSFUL)
2308 return error;
2309 }
2310 udelay(5);
2311 return 0;
2312}
2313
2314
2315static int ia_init(struct atm_dev *dev)
2316{
2317 IADEV *iadev;
2318 unsigned long real_base;
2319 void __iomem *base;
2320 unsigned short command;
2321 int error, i;
2322
2323 /* The device has been identified and registered. Now we read
2324 necessary configuration info like memory base address,
2325 interrupt number etc */
2326
2327 IF_INIT(printk(">ia_init\n");)
2328 dev->ci_range.vpi_bits = 0;
2329 dev->ci_range.vci_bits = NR_VCI_LD;
2330
2331 iadev = INPH_IA_DEV(dev);
2332 real_base = pci_resource_start (iadev->pci, 0);
2333 iadev->irq = iadev->pci->irq;
2334
2335 error = pci_read_config_word(iadev->pci, PCI_COMMAND, &command);
2336 if (error) {
2337 printk(KERN_ERR DEV_LABEL "(itf %d): init error 0x%x\n",
2338 dev->number,error);
2339 return -EINVAL;
2340 }
2341 IF_INIT(printk(DEV_LABEL "(itf %d): rev.%d,realbase=0x%lx,irq=%d\n",
2342 dev->number, iadev->pci->revision, real_base, iadev->irq);)
2343
2344 /* find mapping size of board */
2345
2346 iadev->pci_map_size = pci_resource_len(iadev->pci, 0);
2347
2348 if (iadev->pci_map_size == 0x100000){
2349 iadev->num_vc = 4096;
2350 dev->ci_range.vci_bits = NR_VCI_4K_LD;
2351 iadev->memSize = 4;
2352 }
2353 else if (iadev->pci_map_size == 0x40000) {
2354 iadev->num_vc = 1024;
2355 iadev->memSize = 1;
2356 }
2357 else {
2358 printk("Unknown pci_map_size = 0x%x\n", iadev->pci_map_size);
2359 return -EINVAL;
2360 }
2361 IF_INIT(printk (DEV_LABEL "map size: %i\n", iadev->pci_map_size);)
2362
2363 /* enable bus mastering */
2364 pci_set_master(iadev->pci);
2365
2366 /*
2367 * Delay at least 1us before doing any mem accesses (how 'bout 10?)
2368 */
2369 udelay(10);
2370
2371 /* mapping the physical address to a virtual address in address space */
2372 base = ioremap(real_base,iadev->pci_map_size); /* ioremap is not resolved ??? */
2373
2374 if (!base)
2375 {
2376 printk(DEV_LABEL " (itf %d): can't set up page mapping\n",
2377 dev->number);
2378 return -ENOMEM;
2379 }
2380 IF_INIT(printk(DEV_LABEL " (itf %d): rev.%d,base=%p,irq=%d\n",
2381 dev->number, iadev->pci->revision, base, iadev->irq);)
2382
2383 /* filling the iphase dev structure */
2384 iadev->mem = iadev->pci_map_size /2;
2385 iadev->real_base = real_base;
2386 iadev->base = base;
2387
2388 /* Bus Interface Control Registers */
2389 iadev->reg = base + REG_BASE;
2390 /* Segmentation Control Registers */
2391 iadev->seg_reg = base + SEG_BASE;
2392 /* Reassembly Control Registers */
2393 iadev->reass_reg = base + REASS_BASE;
2394 /* Front end/ DMA control registers */
2395 iadev->phy = base + PHY_BASE;
2396 iadev->dma = base + PHY_BASE;
2397 /* RAM - Segmentation RAm and Reassembly RAM */
2398 iadev->ram = base + ACTUAL_RAM_BASE;
2399 iadev->seg_ram = base + ACTUAL_SEG_RAM_BASE;
2400 iadev->reass_ram = base + ACTUAL_REASS_RAM_BASE;
2401
2402 /* lets print out the above */
2403 IF_INIT(printk("Base addrs: %p %p %p \n %p %p %p %p\n",
2404 iadev->reg,iadev->seg_reg,iadev->reass_reg,
2405 iadev->phy, iadev->ram, iadev->seg_ram,
2406 iadev->reass_ram);)
2407
2408 /* lets try reading the MAC address */
2409 error = get_esi(dev);
2410 if (error) {
2411 iounmap(iadev->base);
2412 return error;
2413 }
2414 printk("IA: ");
2415 for (i=0; i < ESI_LEN; i++)
2416 printk("%s%02X",i ? "-" : "",dev->esi[i]);
2417 printk("\n");
2418
2419 /* reset SAR */
2420 if (reset_sar(dev)) {
2421 iounmap(iadev->base);
2422 printk("IA: reset SAR fail, please try again\n");
2423 return 1;
2424 }
2425 return 0;
2426}
2427
2428static void ia_update_stats(IADEV *iadev) {
2429 if (!iadev->carrier_detect)
2430 return;
2431 iadev->rx_cell_cnt += readw(iadev->reass_reg+CELL_CTR0)&0xffff;
2432 iadev->rx_cell_cnt += (readw(iadev->reass_reg+CELL_CTR1) & 0xffff) << 16;
2433 iadev->drop_rxpkt += readw(iadev->reass_reg + DRP_PKT_CNTR ) & 0xffff;
2434 iadev->drop_rxcell += readw(iadev->reass_reg + ERR_CNTR) & 0xffff;
2435 iadev->tx_cell_cnt += readw(iadev->seg_reg + CELL_CTR_LO_AUTO)&0xffff;
2436 iadev->tx_cell_cnt += (readw(iadev->seg_reg+CELL_CTR_HIGH_AUTO)&0xffff)<<16;
2437 return;
2438}
2439
2440static void ia_led_timer(struct timer_list *unused) {
2441 unsigned long flags;
2442 static u_char blinking[8] = {0, 0, 0, 0, 0, 0, 0, 0};
2443 u_char i;
2444 static u32 ctrl_reg;
2445 for (i = 0; i < iadev_count; i++) {
2446 if (ia_dev[i]) {
2447 ctrl_reg = readl(ia_dev[i]->reg+IPHASE5575_BUS_CONTROL_REG);
2448 if (blinking[i] == 0) {
2449 blinking[i]++;
2450 ctrl_reg &= (~CTRL_LED);
2451 writel(ctrl_reg, ia_dev[i]->reg+IPHASE5575_BUS_CONTROL_REG);
2452 ia_update_stats(ia_dev[i]);
2453 }
2454 else {
2455 blinking[i] = 0;
2456 ctrl_reg |= CTRL_LED;
2457 writel(ctrl_reg, ia_dev[i]->reg+IPHASE5575_BUS_CONTROL_REG);
2458 spin_lock_irqsave(&ia_dev[i]->tx_lock, flags);
2459 if (ia_dev[i]->close_pending)
2460 wake_up(&ia_dev[i]->close_wait);
2461 ia_tx_poll(ia_dev[i]);
2462 spin_unlock_irqrestore(&ia_dev[i]->tx_lock, flags);
2463 }
2464 }
2465 }
2466 mod_timer(&ia_timer, jiffies + HZ / 4);
2467 return;
2468}
2469
2470static void ia_phy_put(struct atm_dev *dev, unsigned char value,
2471 unsigned long addr)
2472{
2473 writel(value, INPH_IA_DEV(dev)->phy+addr);
2474}
2475
2476static unsigned char ia_phy_get(struct atm_dev *dev, unsigned long addr)
2477{
2478 return readl(INPH_IA_DEV(dev)->phy+addr);
2479}
2480
2481static void ia_free_tx(IADEV *iadev)
2482{
2483 int i;
2484
2485 kfree(iadev->desc_tbl);
2486 for (i = 0; i < iadev->num_vc; i++)
2487 kfree(iadev->testTable[i]);
2488 kfree(iadev->testTable);
2489 for (i = 0; i < iadev->num_tx_desc; i++) {
2490 struct cpcs_trailer_desc *desc = iadev->tx_buf + i;
2491
2492 dma_unmap_single(&iadev->pci->dev, desc->dma_addr,
2493 sizeof(*desc->cpcs), DMA_TO_DEVICE);
2494 kfree(desc->cpcs);
2495 }
2496 kfree(iadev->tx_buf);
2497 dma_free_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE, iadev->tx_dle_q.start,
2498 iadev->tx_dle_dma);
2499}
2500
2501static void ia_free_rx(IADEV *iadev)
2502{
2503 kfree(iadev->rx_open);
2504 dma_free_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE, iadev->rx_dle_q.start,
2505 iadev->rx_dle_dma);
2506}
2507
2508static int ia_start(struct atm_dev *dev)
2509{
2510 IADEV *iadev;
2511 int error;
2512 unsigned char phy;
2513 u32 ctrl_reg;
2514 IF_EVENT(printk(">ia_start\n");)
2515 iadev = INPH_IA_DEV(dev);
2516 if (request_irq(iadev->irq, &ia_int, IRQF_SHARED, DEV_LABEL, dev)) {
2517 printk(KERN_ERR DEV_LABEL "(itf %d): IRQ%d is already in use\n",
2518 dev->number, iadev->irq);
2519 error = -EAGAIN;
2520 goto err_out;
2521 }
2522 /* @@@ should release IRQ on error */
2523 /* enabling memory + master */
2524 if ((error = pci_write_config_word(iadev->pci,
2525 PCI_COMMAND,
2526 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER )))
2527 {
2528 printk(KERN_ERR DEV_LABEL "(itf %d): can't enable memory+"
2529 "master (0x%x)\n",dev->number, error);
2530 error = -EIO;
2531 goto err_free_irq;
2532 }
2533 udelay(10);
2534
2535 /* Maybe we should reset the front end, initialize Bus Interface Control
2536 Registers and see. */
2537
2538 IF_INIT(printk("Bus ctrl reg: %08x\n",
2539 readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG));)
2540 ctrl_reg = readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2541 ctrl_reg = (ctrl_reg & (CTRL_LED | CTRL_FE_RST))
2542 | CTRL_B8
2543 | CTRL_B16
2544 | CTRL_B32
2545 | CTRL_B48
2546 | CTRL_B64
2547 | CTRL_B128
2548 | CTRL_ERRMASK
2549 | CTRL_DLETMASK /* shud be removed l8r */
2550 | CTRL_DLERMASK
2551 | CTRL_SEGMASK
2552 | CTRL_REASSMASK
2553 | CTRL_FEMASK
2554 | CTRL_CSPREEMPT;
2555
2556 writel(ctrl_reg, iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2557
2558 IF_INIT(printk("Bus ctrl reg after initializing: %08x\n",
2559 readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG));
2560 printk("Bus status reg after init: %08x\n",
2561 readl(iadev->reg+IPHASE5575_BUS_STATUS_REG));)
2562
2563 ia_hw_type(iadev);
2564 error = tx_init(dev);
2565 if (error)
2566 goto err_free_irq;
2567 error = rx_init(dev);
2568 if (error)
2569 goto err_free_tx;
2570
2571 ctrl_reg = readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2572 writel(ctrl_reg | CTRL_FE_RST, iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2573 IF_INIT(printk("Bus ctrl reg after initializing: %08x\n",
2574 readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG));)
2575 phy = 0; /* resolve compiler complaint */
2576 IF_INIT (
2577 if ((phy=ia_phy_get(dev,0)) == 0x30)
2578 printk("IA: pm5346,rev.%d\n",phy&0x0f);
2579 else
2580 printk("IA: utopia,rev.%0x\n",phy);)
2581
2582 if (iadev->phy_type & FE_25MBIT_PHY)
2583 ia_mb25_init(iadev);
2584 else if (iadev->phy_type & (FE_DS3_PHY | FE_E3_PHY))
2585 ia_suni_pm7345_init(iadev);
2586 else {
2587 error = suni_init(dev);
2588 if (error)
2589 goto err_free_rx;
2590 if (dev->phy->start) {
2591 error = dev->phy->start(dev);
2592 if (error)
2593 goto err_free_rx;
2594 }
2595 /* Get iadev->carrier_detect status */
2596 ia_frontend_intr(iadev);
2597 }
2598 return 0;
2599
2600err_free_rx:
2601 ia_free_rx(iadev);
2602err_free_tx:
2603 ia_free_tx(iadev);
2604err_free_irq:
2605 free_irq(iadev->irq, dev);
2606err_out:
2607 return error;
2608}
2609
2610static void ia_close(struct atm_vcc *vcc)
2611{
2612 DEFINE_WAIT(wait);
2613 u16 *vc_table;
2614 IADEV *iadev;
2615 struct ia_vcc *ia_vcc;
2616 struct sk_buff *skb = NULL;
2617 struct sk_buff_head tmp_tx_backlog, tmp_vcc_backlog;
2618 unsigned long closetime, flags;
2619
2620 iadev = INPH_IA_DEV(vcc->dev);
2621 ia_vcc = INPH_IA_VCC(vcc);
2622 if (!ia_vcc) return;
2623
2624 IF_EVENT(printk("ia_close: ia_vcc->vc_desc_cnt = %d vci = %d\n",
2625 ia_vcc->vc_desc_cnt,vcc->vci);)
2626 clear_bit(ATM_VF_READY,&vcc->flags);
2627 skb_queue_head_init (&tmp_tx_backlog);
2628 skb_queue_head_init (&tmp_vcc_backlog);
2629 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
2630 iadev->close_pending++;
2631 prepare_to_wait(&iadev->timeout_wait, &wait, TASK_UNINTERRUPTIBLE);
2632 schedule_timeout(msecs_to_jiffies(500));
2633 finish_wait(&iadev->timeout_wait, &wait);
2634 spin_lock_irqsave(&iadev->tx_lock, flags);
2635 while((skb = skb_dequeue(&iadev->tx_backlog))) {
2636 if (ATM_SKB(skb)->vcc == vcc){
2637 if (vcc->pop) vcc->pop(vcc, skb);
2638 else dev_kfree_skb_any(skb);
2639 }
2640 else
2641 skb_queue_tail(&tmp_tx_backlog, skb);
2642 }
2643 while((skb = skb_dequeue(&tmp_tx_backlog)))
2644 skb_queue_tail(&iadev->tx_backlog, skb);
2645 IF_EVENT(printk("IA TX Done decs_cnt = %d\n", ia_vcc->vc_desc_cnt);)
2646 closetime = 300000 / ia_vcc->pcr;
2647 if (closetime == 0)
2648 closetime = 1;
2649 spin_unlock_irqrestore(&iadev->tx_lock, flags);
2650 wait_event_timeout(iadev->close_wait, (ia_vcc->vc_desc_cnt <= 0), closetime);
2651 spin_lock_irqsave(&iadev->tx_lock, flags);
2652 iadev->close_pending--;
2653 iadev->testTable[vcc->vci]->lastTime = 0;
2654 iadev->testTable[vcc->vci]->fract = 0;
2655 iadev->testTable[vcc->vci]->vc_status = VC_UBR;
2656 if (vcc->qos.txtp.traffic_class == ATM_ABR) {
2657 if (vcc->qos.txtp.min_pcr > 0)
2658 iadev->sum_mcr -= vcc->qos.txtp.min_pcr;
2659 }
2660 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
2661 ia_vcc = INPH_IA_VCC(vcc);
2662 iadev->sum_mcr -= ia_vcc->NumCbrEntry*iadev->Granularity;
2663 ia_cbrVc_close (vcc);
2664 }
2665 spin_unlock_irqrestore(&iadev->tx_lock, flags);
2666 }
2667
2668 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
2669 // reset reass table
2670 vc_table = (u16 *)(iadev->reass_ram+REASS_TABLE*iadev->memSize);
2671 vc_table += vcc->vci;
2672 *vc_table = NO_AAL5_PKT;
2673 // reset vc table
2674 vc_table = (u16 *)(iadev->reass_ram+RX_VC_TABLE*iadev->memSize);
2675 vc_table += vcc->vci;
2676 *vc_table = (vcc->vci << 6) | 15;
2677 if (vcc->qos.rxtp.traffic_class == ATM_ABR) {
2678 struct abr_vc_table __iomem *abr_vc_table =
2679 (iadev->reass_ram+ABR_VC_TABLE*iadev->memSize);
2680 abr_vc_table += vcc->vci;
2681 abr_vc_table->rdf = 0x0003;
2682 abr_vc_table->air = 0x5eb1;
2683 }
2684 // Drain the packets
2685 rx_dle_intr(vcc->dev);
2686 iadev->rx_open[vcc->vci] = NULL;
2687 }
2688 kfree(INPH_IA_VCC(vcc));
2689 ia_vcc = NULL;
2690 vcc->dev_data = NULL;
2691 clear_bit(ATM_VF_ADDR,&vcc->flags);
2692 return;
2693}
2694
2695static int ia_open(struct atm_vcc *vcc)
2696{
2697 struct ia_vcc *ia_vcc;
2698 int error;
2699 if (!test_bit(ATM_VF_PARTIAL,&vcc->flags))
2700 {
2701 IF_EVENT(printk("ia: not partially allocated resources\n");)
2702 vcc->dev_data = NULL;
2703 }
2704 if (vcc->vci != ATM_VPI_UNSPEC && vcc->vpi != ATM_VCI_UNSPEC)
2705 {
2706 IF_EVENT(printk("iphase open: unspec part\n");)
2707 set_bit(ATM_VF_ADDR,&vcc->flags);
2708 }
2709 if (vcc->qos.aal != ATM_AAL5)
2710 return -EINVAL;
2711 IF_EVENT(printk(DEV_LABEL "(itf %d): open %d.%d\n",
2712 vcc->dev->number, vcc->vpi, vcc->vci);)
2713
2714 /* Device dependent initialization */
2715 ia_vcc = kmalloc(sizeof(*ia_vcc), GFP_KERNEL);
2716 if (!ia_vcc) return -ENOMEM;
2717 vcc->dev_data = ia_vcc;
2718
2719 if ((error = open_rx(vcc)))
2720 {
2721 IF_EVENT(printk("iadev: error in open_rx, closing\n");)
2722 ia_close(vcc);
2723 return error;
2724 }
2725
2726 if ((error = open_tx(vcc)))
2727 {
2728 IF_EVENT(printk("iadev: error in open_tx, closing\n");)
2729 ia_close(vcc);
2730 return error;
2731 }
2732
2733 set_bit(ATM_VF_READY,&vcc->flags);
2734
2735#if 0
2736 {
2737 static u8 first = 1;
2738 if (first) {
2739 ia_timer.expires = jiffies + 3*HZ;
2740 add_timer(&ia_timer);
2741 first = 0;
2742 }
2743 }
2744#endif
2745 IF_EVENT(printk("ia open returning\n");)
2746 return 0;
2747}
2748
2749static int ia_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags)
2750{
2751 IF_EVENT(printk(">ia_change_qos\n");)
2752 return 0;
2753}
2754
2755static int ia_ioctl(struct atm_dev *dev, unsigned int cmd, void __user *arg)
2756{
2757 IA_CMDBUF ia_cmds;
2758 IADEV *iadev;
2759 int i, board;
2760 u16 __user *tmps;
2761 IF_EVENT(printk(">ia_ioctl\n");)
2762 if (cmd != IA_CMD) {
2763 if (!dev->phy->ioctl) return -EINVAL;
2764 return dev->phy->ioctl(dev,cmd,arg);
2765 }
2766 if (copy_from_user(&ia_cmds, arg, sizeof ia_cmds)) return -EFAULT;
2767 board = ia_cmds.status;
2768
2769 if ((board < 0) || (board > iadev_count))
2770 board = 0;
2771 board = array_index_nospec(board, iadev_count + 1);
2772
2773 iadev = ia_dev[board];
2774 switch (ia_cmds.cmd) {
2775 case MEMDUMP:
2776 {
2777 switch (ia_cmds.sub_cmd) {
2778 case MEMDUMP_SEGREG:
2779 if (!capable(CAP_NET_ADMIN)) return -EPERM;
2780 tmps = (u16 __user *)ia_cmds.buf;
2781 for(i=0; i<0x80; i+=2, tmps++)
2782 if(put_user((u16)(readl(iadev->seg_reg+i) & 0xffff), tmps)) return -EFAULT;
2783 ia_cmds.status = 0;
2784 ia_cmds.len = 0x80;
2785 break;
2786 case MEMDUMP_REASSREG:
2787 if (!capable(CAP_NET_ADMIN)) return -EPERM;
2788 tmps = (u16 __user *)ia_cmds.buf;
2789 for(i=0; i<0x80; i+=2, tmps++)
2790 if(put_user((u16)(readl(iadev->reass_reg+i) & 0xffff), tmps)) return -EFAULT;
2791 ia_cmds.status = 0;
2792 ia_cmds.len = 0x80;
2793 break;
2794 case MEMDUMP_FFL:
2795 {
2796 ia_regs_t *regs_local;
2797 ffredn_t *ffL;
2798 rfredn_t *rfL;
2799
2800 if (!capable(CAP_NET_ADMIN)) return -EPERM;
2801 regs_local = kmalloc(sizeof(*regs_local), GFP_KERNEL);
2802 if (!regs_local) return -ENOMEM;
2803 ffL = ®s_local->ffredn;
2804 rfL = ®s_local->rfredn;
2805 /* Copy real rfred registers into the local copy */
2806 for (i=0; i<(sizeof (rfredn_t))/4; i++)
2807 ((u_int *)rfL)[i] = readl(iadev->reass_reg + i) & 0xffff;
2808 /* Copy real ffred registers into the local copy */
2809 for (i=0; i<(sizeof (ffredn_t))/4; i++)
2810 ((u_int *)ffL)[i] = readl(iadev->seg_reg + i) & 0xffff;
2811
2812 if (copy_to_user(ia_cmds.buf, regs_local,sizeof(ia_regs_t))) {
2813 kfree(regs_local);
2814 return -EFAULT;
2815 }
2816 kfree(regs_local);
2817 printk("Board %d registers dumped\n", board);
2818 ia_cmds.status = 0;
2819 }
2820 break;
2821 case READ_REG:
2822 {
2823 if (!capable(CAP_NET_ADMIN)) return -EPERM;
2824 desc_dbg(iadev);
2825 ia_cmds.status = 0;
2826 }
2827 break;
2828 case 0x6:
2829 {
2830 ia_cmds.status = 0;
2831 printk("skb = 0x%p\n", skb_peek(&iadev->tx_backlog));
2832 printk("rtn_q: 0x%p\n",ia_deque_rtn_q(&iadev->tx_return_q));
2833 }
2834 break;
2835 case 0x8:
2836 {
2837 struct k_sonet_stats *stats;
2838 stats = &PRIV(_ia_dev[board])->sonet_stats;
2839 printk("section_bip: %d\n", atomic_read(&stats->section_bip));
2840 printk("line_bip : %d\n", atomic_read(&stats->line_bip));
2841 printk("path_bip : %d\n", atomic_read(&stats->path_bip));
2842 printk("line_febe : %d\n", atomic_read(&stats->line_febe));
2843 printk("path_febe : %d\n", atomic_read(&stats->path_febe));
2844 printk("corr_hcs : %d\n", atomic_read(&stats->corr_hcs));
2845 printk("uncorr_hcs : %d\n", atomic_read(&stats->uncorr_hcs));
2846 printk("tx_cells : %d\n", atomic_read(&stats->tx_cells));
2847 printk("rx_cells : %d\n", atomic_read(&stats->rx_cells));
2848 }
2849 ia_cmds.status = 0;
2850 break;
2851 case 0x9:
2852 if (!capable(CAP_NET_ADMIN)) return -EPERM;
2853 for (i = 1; i <= iadev->num_rx_desc; i++)
2854 free_desc(_ia_dev[board], i);
2855 writew( ~(RX_FREEQ_EMPT | RX_EXCP_RCVD),
2856 iadev->reass_reg+REASS_MASK_REG);
2857 iadev->rxing = 1;
2858
2859 ia_cmds.status = 0;
2860 break;
2861
2862 case 0xb:
2863 if (!capable(CAP_NET_ADMIN)) return -EPERM;
2864 ia_frontend_intr(iadev);
2865 break;
2866 case 0xa:
2867 if (!capable(CAP_NET_ADMIN)) return -EPERM;
2868 {
2869 ia_cmds.status = 0;
2870 IADebugFlag = ia_cmds.maddr;
2871 printk("New debug option loaded\n");
2872 }
2873 break;
2874 default:
2875 ia_cmds.status = 0;
2876 break;
2877 }
2878 }
2879 break;
2880 default:
2881 break;
2882
2883 }
2884 return 0;
2885}
2886
2887static int ia_pkt_tx (struct atm_vcc *vcc, struct sk_buff *skb) {
2888 IADEV *iadev;
2889 struct dle *wr_ptr;
2890 struct tx_buf_desc __iomem *buf_desc_ptr;
2891 int desc;
2892 int comp_code;
2893 int total_len;
2894 struct cpcs_trailer *trailer;
2895 struct ia_vcc *iavcc;
2896
2897 iadev = INPH_IA_DEV(vcc->dev);
2898 iavcc = INPH_IA_VCC(vcc);
2899 if (!iavcc->txing) {
2900 printk("discard packet on closed VC\n");
2901 if (vcc->pop)
2902 vcc->pop(vcc, skb);
2903 else
2904 dev_kfree_skb_any(skb);
2905 return 0;
2906 }
2907
2908 if (skb->len > iadev->tx_buf_sz - 8) {
2909 printk("Transmit size over tx buffer size\n");
2910 if (vcc->pop)
2911 vcc->pop(vcc, skb);
2912 else
2913 dev_kfree_skb_any(skb);
2914 return 0;
2915 }
2916 if ((unsigned long)skb->data & 3) {
2917 printk("Misaligned SKB\n");
2918 if (vcc->pop)
2919 vcc->pop(vcc, skb);
2920 else
2921 dev_kfree_skb_any(skb);
2922 return 0;
2923 }
2924 /* Get a descriptor number from our free descriptor queue
2925 We get the descr number from the TCQ now, since I am using
2926 the TCQ as a free buffer queue. Initially TCQ will be
2927 initialized with all the descriptors and is hence, full.
2928 */
2929 desc = get_desc (iadev, iavcc);
2930 if (desc == 0xffff)
2931 return 1;
2932 comp_code = desc >> 13;
2933 desc &= 0x1fff;
2934
2935 if ((desc == 0) || (desc > iadev->num_tx_desc))
2936 {
2937 IF_ERR(printk(DEV_LABEL "invalid desc for send: %d\n", desc);)
2938 atomic_inc(&vcc->stats->tx);
2939 if (vcc->pop)
2940 vcc->pop(vcc, skb);
2941 else
2942 dev_kfree_skb_any(skb);
2943 return 0; /* return SUCCESS */
2944 }
2945
2946 if (comp_code)
2947 {
2948 IF_ERR(printk(DEV_LABEL "send desc:%d completion code %d error\n",
2949 desc, comp_code);)
2950 }
2951
2952 /* remember the desc and vcc mapping */
2953 iavcc->vc_desc_cnt++;
2954 iadev->desc_tbl[desc-1].iavcc = iavcc;
2955 iadev->desc_tbl[desc-1].txskb = skb;
2956 IA_SKB_STATE(skb) = 0;
2957
2958 iadev->ffL.tcq_rd += 2;
2959 if (iadev->ffL.tcq_rd > iadev->ffL.tcq_ed)
2960 iadev->ffL.tcq_rd = iadev->ffL.tcq_st;
2961 writew(iadev->ffL.tcq_rd, iadev->seg_reg+TCQ_RD_PTR);
2962
2963 /* Put the descriptor number in the packet ready queue
2964 and put the updated write pointer in the DLE field
2965 */
2966 *(u16*)(iadev->seg_ram+iadev->ffL.prq_wr) = desc;
2967
2968 iadev->ffL.prq_wr += 2;
2969 if (iadev->ffL.prq_wr > iadev->ffL.prq_ed)
2970 iadev->ffL.prq_wr = iadev->ffL.prq_st;
2971
2972 /* Figure out the exact length of the packet and padding required to
2973 make it aligned on a 48 byte boundary. */
2974 total_len = skb->len + sizeof(struct cpcs_trailer);
2975 total_len = ((total_len + 47) / 48) * 48;
2976 IF_TX(printk("ia packet len:%d padding:%d\n", total_len, total_len - skb->len);)
2977
2978 /* Put the packet in a tx buffer */
2979 trailer = iadev->tx_buf[desc-1].cpcs;
2980 IF_TX(printk("Sent: skb = 0x%p skb->data: 0x%p len: %d, desc: %d\n",
2981 skb, skb->data, skb->len, desc);)
2982 trailer->control = 0;
2983 /*big endian*/
2984 trailer->length = ((skb->len & 0xff) << 8) | ((skb->len & 0xff00) >> 8);
2985 trailer->crc32 = 0; /* not needed - dummy bytes */
2986
2987 /* Display the packet */
2988 IF_TXPKT(printk("Sent data: len = %d MsgNum = %d\n",
2989 skb->len, tcnter++);
2990 xdump(skb->data, skb->len, "TX: ");
2991 printk("\n");)
2992
2993 /* Build the buffer descriptor */
2994 buf_desc_ptr = iadev->seg_ram+TX_DESC_BASE;
2995 buf_desc_ptr += desc; /* points to the corresponding entry */
2996 buf_desc_ptr->desc_mode = AAL5 | EOM_EN | APP_CRC32 | CMPL_INT;
2997 /* Huh ? p.115 of users guide describes this as a read-only register */
2998 writew(TRANSMIT_DONE, iadev->seg_reg+SEG_INTR_STATUS_REG);
2999 buf_desc_ptr->vc_index = vcc->vci;
3000 buf_desc_ptr->bytes = total_len;
3001
3002 if (vcc->qos.txtp.traffic_class == ATM_ABR)
3003 clear_lockup (vcc, iadev);
3004
3005 /* Build the DLE structure */
3006 wr_ptr = iadev->tx_dle_q.write;
3007 memset((caddr_t)wr_ptr, 0, sizeof(*wr_ptr));
3008 wr_ptr->sys_pkt_addr = dma_map_single(&iadev->pci->dev, skb->data,
3009 skb->len, DMA_TO_DEVICE);
3010 wr_ptr->local_pkt_addr = (buf_desc_ptr->buf_start_hi << 16) |
3011 buf_desc_ptr->buf_start_lo;
3012 /* wr_ptr->bytes = swap_byte_order(total_len); didn't seem to affect?? */
3013 wr_ptr->bytes = skb->len;
3014
3015 /* hw bug - DLEs of 0x2d, 0x2e, 0x2f cause DMA lockup */
3016 if ((wr_ptr->bytes >> 2) == 0xb)
3017 wr_ptr->bytes = 0x30;
3018
3019 wr_ptr->mode = TX_DLE_PSI;
3020 wr_ptr->prq_wr_ptr_data = 0;
3021
3022 /* end is not to be used for the DLE q */
3023 if (++wr_ptr == iadev->tx_dle_q.end)
3024 wr_ptr = iadev->tx_dle_q.start;
3025
3026 /* Build trailer dle */
3027 wr_ptr->sys_pkt_addr = iadev->tx_buf[desc-1].dma_addr;
3028 wr_ptr->local_pkt_addr = ((buf_desc_ptr->buf_start_hi << 16) |
3029 buf_desc_ptr->buf_start_lo) + total_len - sizeof(struct cpcs_trailer);
3030
3031 wr_ptr->bytes = sizeof(struct cpcs_trailer);
3032 wr_ptr->mode = DMA_INT_ENABLE;
3033 wr_ptr->prq_wr_ptr_data = iadev->ffL.prq_wr;
3034
3035 /* end is not to be used for the DLE q */
3036 if (++wr_ptr == iadev->tx_dle_q.end)
3037 wr_ptr = iadev->tx_dle_q.start;
3038
3039 iadev->tx_dle_q.write = wr_ptr;
3040 ATM_DESC(skb) = vcc->vci;
3041 skb_queue_tail(&iadev->tx_dma_q, skb);
3042
3043 atomic_inc(&vcc->stats->tx);
3044 iadev->tx_pkt_cnt++;
3045 /* Increment transaction counter */
3046 writel(2, iadev->dma+IPHASE5575_TX_COUNTER);
3047
3048#if 0
3049 /* add flow control logic */
3050 if (atomic_read(&vcc->stats->tx) % 20 == 0) {
3051 if (iavcc->vc_desc_cnt > 10) {
3052 vcc->tx_quota = vcc->tx_quota * 3 / 4;
3053 printk("Tx1: vcc->tx_quota = %d \n", (u32)vcc->tx_quota );
3054 iavcc->flow_inc = -1;
3055 iavcc->saved_tx_quota = vcc->tx_quota;
3056 } else if ((iavcc->flow_inc < 0) && (iavcc->vc_desc_cnt < 3)) {
3057 // vcc->tx_quota = 3 * iavcc->saved_tx_quota / 4;
3058 printk("Tx2: vcc->tx_quota = %d \n", (u32)vcc->tx_quota );
3059 iavcc->flow_inc = 0;
3060 }
3061 }
3062#endif
3063 IF_TX(printk("ia send done\n");)
3064 return 0;
3065}
3066
3067static int ia_send(struct atm_vcc *vcc, struct sk_buff *skb)
3068{
3069 IADEV *iadev;
3070 unsigned long flags;
3071
3072 iadev = INPH_IA_DEV(vcc->dev);
3073 if ((!skb)||(skb->len>(iadev->tx_buf_sz-sizeof(struct cpcs_trailer))))
3074 {
3075 if (!skb)
3076 printk(KERN_CRIT "null skb in ia_send\n");
3077 else dev_kfree_skb_any(skb);
3078 return -EINVAL;
3079 }
3080 spin_lock_irqsave(&iadev->tx_lock, flags);
3081 if (!test_bit(ATM_VF_READY,&vcc->flags)){
3082 dev_kfree_skb_any(skb);
3083 spin_unlock_irqrestore(&iadev->tx_lock, flags);
3084 return -EINVAL;
3085 }
3086 ATM_SKB(skb)->vcc = vcc;
3087
3088 if (skb_peek(&iadev->tx_backlog)) {
3089 skb_queue_tail(&iadev->tx_backlog, skb);
3090 }
3091 else {
3092 if (ia_pkt_tx (vcc, skb)) {
3093 skb_queue_tail(&iadev->tx_backlog, skb);
3094 }
3095 }
3096 spin_unlock_irqrestore(&iadev->tx_lock, flags);
3097 return 0;
3098
3099}
3100
3101static int ia_proc_read(struct atm_dev *dev,loff_t *pos,char *page)
3102{
3103 int left = *pos, n;
3104 char *tmpPtr;
3105 IADEV *iadev = INPH_IA_DEV(dev);
3106 if(!left--) {
3107 if (iadev->phy_type == FE_25MBIT_PHY) {
3108 n = sprintf(page, " Board Type : Iphase5525-1KVC-128K\n");
3109 return n;
3110 }
3111 if (iadev->phy_type == FE_DS3_PHY)
3112 n = sprintf(page, " Board Type : Iphase-ATM-DS3");
3113 else if (iadev->phy_type == FE_E3_PHY)
3114 n = sprintf(page, " Board Type : Iphase-ATM-E3");
3115 else if (iadev->phy_type == FE_UTP_OPTION)
3116 n = sprintf(page, " Board Type : Iphase-ATM-UTP155");
3117 else
3118 n = sprintf(page, " Board Type : Iphase-ATM-OC3");
3119 tmpPtr = page + n;
3120 if (iadev->pci_map_size == 0x40000)
3121 n += sprintf(tmpPtr, "-1KVC-");
3122 else
3123 n += sprintf(tmpPtr, "-4KVC-");
3124 tmpPtr = page + n;
3125 if ((iadev->memType & MEM_SIZE_MASK) == MEM_SIZE_1M)
3126 n += sprintf(tmpPtr, "1M \n");
3127 else if ((iadev->memType & MEM_SIZE_MASK) == MEM_SIZE_512K)
3128 n += sprintf(tmpPtr, "512K\n");
3129 else
3130 n += sprintf(tmpPtr, "128K\n");
3131 return n;
3132 }
3133 if (!left) {
3134 return sprintf(page, " Number of Tx Buffer: %u\n"
3135 " Size of Tx Buffer : %u\n"
3136 " Number of Rx Buffer: %u\n"
3137 " Size of Rx Buffer : %u\n"
3138 " Packets Received : %u\n"
3139 " Packets Transmitted: %u\n"
3140 " Cells Received : %u\n"
3141 " Cells Transmitted : %u\n"
3142 " Board Dropped Cells: %u\n"
3143 " Board Dropped Pkts : %u\n",
3144 iadev->num_tx_desc, iadev->tx_buf_sz,
3145 iadev->num_rx_desc, iadev->rx_buf_sz,
3146 iadev->rx_pkt_cnt, iadev->tx_pkt_cnt,
3147 iadev->rx_cell_cnt, iadev->tx_cell_cnt,
3148 iadev->drop_rxcell, iadev->drop_rxpkt);
3149 }
3150 return 0;
3151}
3152
3153static const struct atmdev_ops ops = {
3154 .open = ia_open,
3155 .close = ia_close,
3156 .ioctl = ia_ioctl,
3157 .send = ia_send,
3158 .phy_put = ia_phy_put,
3159 .phy_get = ia_phy_get,
3160 .change_qos = ia_change_qos,
3161 .proc_read = ia_proc_read,
3162 .owner = THIS_MODULE,
3163};
3164
3165static int ia_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3166{
3167 struct atm_dev *dev;
3168 IADEV *iadev;
3169 int ret;
3170
3171 iadev = kzalloc(sizeof(*iadev), GFP_KERNEL);
3172 if (!iadev) {
3173 ret = -ENOMEM;
3174 goto err_out;
3175 }
3176
3177 iadev->pci = pdev;
3178
3179 IF_INIT(printk("ia detected at bus:%d dev: %d function:%d\n",
3180 pdev->bus->number, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));)
3181 if (pci_enable_device(pdev)) {
3182 ret = -ENODEV;
3183 goto err_out_free_iadev;
3184 }
3185 dev = atm_dev_register(DEV_LABEL, &pdev->dev, &ops, -1, NULL);
3186 if (!dev) {
3187 ret = -ENOMEM;
3188 goto err_out_disable_dev;
3189 }
3190 dev->dev_data = iadev;
3191 IF_INIT(printk(DEV_LABEL "registered at (itf :%d)\n", dev->number);)
3192 IF_INIT(printk("dev_id = 0x%p iadev->LineRate = %d \n", dev,
3193 iadev->LineRate);)
3194
3195 pci_set_drvdata(pdev, dev);
3196
3197 ia_dev[iadev_count] = iadev;
3198 _ia_dev[iadev_count] = dev;
3199 iadev_count++;
3200 if (ia_init(dev) || ia_start(dev)) {
3201 IF_INIT(printk("IA register failed!\n");)
3202 iadev_count--;
3203 ia_dev[iadev_count] = NULL;
3204 _ia_dev[iadev_count] = NULL;
3205 ret = -EINVAL;
3206 goto err_out_deregister_dev;
3207 }
3208 IF_EVENT(printk("iadev_count = %d\n", iadev_count);)
3209
3210 iadev->next_board = ia_boards;
3211 ia_boards = dev;
3212
3213 return 0;
3214
3215err_out_deregister_dev:
3216 atm_dev_deregister(dev);
3217err_out_disable_dev:
3218 pci_disable_device(pdev);
3219err_out_free_iadev:
3220 kfree(iadev);
3221err_out:
3222 return ret;
3223}
3224
3225static void ia_remove_one(struct pci_dev *pdev)
3226{
3227 struct atm_dev *dev = pci_get_drvdata(pdev);
3228 IADEV *iadev = INPH_IA_DEV(dev);
3229
3230 /* Disable phy interrupts */
3231 ia_phy_put(dev, ia_phy_get(dev, SUNI_RSOP_CIE) & ~(SUNI_RSOP_CIE_LOSE),
3232 SUNI_RSOP_CIE);
3233 udelay(1);
3234
3235 if (dev->phy && dev->phy->stop)
3236 dev->phy->stop(dev);
3237
3238 /* De-register device */
3239 free_irq(iadev->irq, dev);
3240 iadev_count--;
3241 ia_dev[iadev_count] = NULL;
3242 _ia_dev[iadev_count] = NULL;
3243 IF_EVENT(printk("deregistering iav at (itf:%d)\n", dev->number);)
3244 atm_dev_deregister(dev);
3245
3246 iounmap(iadev->base);
3247 pci_disable_device(pdev);
3248
3249 ia_free_rx(iadev);
3250 ia_free_tx(iadev);
3251
3252 kfree(iadev);
3253}
3254
3255static const struct pci_device_id ia_pci_tbl[] = {
3256 { PCI_VENDOR_ID_IPHASE, 0x0008, PCI_ANY_ID, PCI_ANY_ID, },
3257 { PCI_VENDOR_ID_IPHASE, 0x0009, PCI_ANY_ID, PCI_ANY_ID, },
3258 { 0,}
3259};
3260MODULE_DEVICE_TABLE(pci, ia_pci_tbl);
3261
3262static struct pci_driver ia_driver = {
3263 .name = DEV_LABEL,
3264 .id_table = ia_pci_tbl,
3265 .probe = ia_init_one,
3266 .remove = ia_remove_one,
3267};
3268
3269static int __init ia_module_init(void)
3270{
3271 int ret;
3272
3273 ret = pci_register_driver(&ia_driver);
3274 if (ret >= 0) {
3275 ia_timer.expires = jiffies + 3*HZ;
3276 add_timer(&ia_timer);
3277 } else
3278 printk(KERN_ERR DEV_LABEL ": no adapter found\n");
3279 return ret;
3280}
3281
3282static void __exit ia_module_exit(void)
3283{
3284 pci_unregister_driver(&ia_driver);
3285
3286 del_timer_sync(&ia_timer);
3287}
3288
3289module_init(ia_module_init);
3290module_exit(ia_module_exit);