Loading...
1// SPDX-License-Identifier: GPL-2.0
2#include <linux/types.h>
3#include <linux/interrupt.h>
4
5#include <asm/xen/hypercall.h>
6#include <xen/xen.h>
7#include <xen/page.h>
8#include <xen/interface/xen.h>
9#include <xen/interface/vcpu.h>
10#include <xen/interface/xenpmu.h>
11
12#include "xen-ops.h"
13#include "pmu.h"
14
15/* x86_pmu.handle_irq definition */
16#include "../events/perf_event.h"
17
18#define XENPMU_IRQ_PROCESSING 1
19struct xenpmu {
20 /* Shared page between hypervisor and domain */
21 struct xen_pmu_data *xenpmu_data;
22
23 uint8_t flags;
24};
25static DEFINE_PER_CPU(struct xenpmu, xenpmu_shared);
26#define get_xenpmu_data() (this_cpu_ptr(&xenpmu_shared)->xenpmu_data)
27#define get_xenpmu_flags() (this_cpu_ptr(&xenpmu_shared)->flags)
28
29/* Macro for computing address of a PMU MSR bank */
30#define field_offset(ctxt, field) ((void *)((uintptr_t)ctxt + \
31 (uintptr_t)ctxt->field))
32
33/* AMD PMU */
34#define F15H_NUM_COUNTERS 6
35#define F10H_NUM_COUNTERS 4
36
37static __read_mostly uint32_t amd_counters_base;
38static __read_mostly uint32_t amd_ctrls_base;
39static __read_mostly int amd_msr_step;
40static __read_mostly int k7_counters_mirrored;
41static __read_mostly int amd_num_counters;
42
43/* Intel PMU */
44#define MSR_TYPE_COUNTER 0
45#define MSR_TYPE_CTRL 1
46#define MSR_TYPE_GLOBAL 2
47#define MSR_TYPE_ARCH_COUNTER 3
48#define MSR_TYPE_ARCH_CTRL 4
49
50/* Number of general pmu registers (CPUID.EAX[0xa].EAX[8..15]) */
51#define PMU_GENERAL_NR_SHIFT 8
52#define PMU_GENERAL_NR_BITS 8
53#define PMU_GENERAL_NR_MASK (((1 << PMU_GENERAL_NR_BITS) - 1) \
54 << PMU_GENERAL_NR_SHIFT)
55
56/* Number of fixed pmu registers (CPUID.EDX[0xa].EDX[0..4]) */
57#define PMU_FIXED_NR_SHIFT 0
58#define PMU_FIXED_NR_BITS 5
59#define PMU_FIXED_NR_MASK (((1 << PMU_FIXED_NR_BITS) - 1) \
60 << PMU_FIXED_NR_SHIFT)
61
62/* Alias registers (0x4c1) for full-width writes to PMCs */
63#define MSR_PMC_ALIAS_MASK (~(MSR_IA32_PERFCTR0 ^ MSR_IA32_PMC0))
64
65#define INTEL_PMC_TYPE_SHIFT 30
66
67static __read_mostly int intel_num_arch_counters, intel_num_fixed_counters;
68
69
70static void xen_pmu_arch_init(void)
71{
72 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
73
74 switch (boot_cpu_data.x86) {
75 case 0x15:
76 amd_num_counters = F15H_NUM_COUNTERS;
77 amd_counters_base = MSR_F15H_PERF_CTR;
78 amd_ctrls_base = MSR_F15H_PERF_CTL;
79 amd_msr_step = 2;
80 k7_counters_mirrored = 1;
81 break;
82 case 0x10:
83 case 0x12:
84 case 0x14:
85 case 0x16:
86 default:
87 amd_num_counters = F10H_NUM_COUNTERS;
88 amd_counters_base = MSR_K7_PERFCTR0;
89 amd_ctrls_base = MSR_K7_EVNTSEL0;
90 amd_msr_step = 1;
91 k7_counters_mirrored = 0;
92 break;
93 }
94 } else if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
95 amd_num_counters = F10H_NUM_COUNTERS;
96 amd_counters_base = MSR_K7_PERFCTR0;
97 amd_ctrls_base = MSR_K7_EVNTSEL0;
98 amd_msr_step = 1;
99 k7_counters_mirrored = 0;
100 } else {
101 uint32_t eax, ebx, ecx, edx;
102
103 cpuid(0xa, &eax, &ebx, &ecx, &edx);
104
105 intel_num_arch_counters = (eax & PMU_GENERAL_NR_MASK) >>
106 PMU_GENERAL_NR_SHIFT;
107 intel_num_fixed_counters = (edx & PMU_FIXED_NR_MASK) >>
108 PMU_FIXED_NR_SHIFT;
109 }
110}
111
112static inline uint32_t get_fam15h_addr(u32 addr)
113{
114 switch (addr) {
115 case MSR_K7_PERFCTR0:
116 case MSR_K7_PERFCTR1:
117 case MSR_K7_PERFCTR2:
118 case MSR_K7_PERFCTR3:
119 return MSR_F15H_PERF_CTR + (addr - MSR_K7_PERFCTR0);
120 case MSR_K7_EVNTSEL0:
121 case MSR_K7_EVNTSEL1:
122 case MSR_K7_EVNTSEL2:
123 case MSR_K7_EVNTSEL3:
124 return MSR_F15H_PERF_CTL + (addr - MSR_K7_EVNTSEL0);
125 default:
126 break;
127 }
128
129 return addr;
130}
131
132static inline bool is_amd_pmu_msr(unsigned int msr)
133{
134 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
135 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
136 return false;
137
138 if ((msr >= MSR_F15H_PERF_CTL &&
139 msr < MSR_F15H_PERF_CTR + (amd_num_counters * 2)) ||
140 (msr >= MSR_K7_EVNTSEL0 &&
141 msr < MSR_K7_PERFCTR0 + amd_num_counters))
142 return true;
143
144 return false;
145}
146
147static bool is_intel_pmu_msr(u32 msr_index, int *type, int *index)
148{
149 u32 msr_index_pmc;
150
151 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&
152 boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR &&
153 boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)
154 return false;
155
156 switch (msr_index) {
157 case MSR_CORE_PERF_FIXED_CTR_CTRL:
158 case MSR_IA32_DS_AREA:
159 case MSR_IA32_PEBS_ENABLE:
160 *type = MSR_TYPE_CTRL;
161 return true;
162
163 case MSR_CORE_PERF_GLOBAL_CTRL:
164 case MSR_CORE_PERF_GLOBAL_STATUS:
165 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
166 *type = MSR_TYPE_GLOBAL;
167 return true;
168
169 default:
170
171 if ((msr_index >= MSR_CORE_PERF_FIXED_CTR0) &&
172 (msr_index < MSR_CORE_PERF_FIXED_CTR0 +
173 intel_num_fixed_counters)) {
174 *index = msr_index - MSR_CORE_PERF_FIXED_CTR0;
175 *type = MSR_TYPE_COUNTER;
176 return true;
177 }
178
179 if ((msr_index >= MSR_P6_EVNTSEL0) &&
180 (msr_index < MSR_P6_EVNTSEL0 + intel_num_arch_counters)) {
181 *index = msr_index - MSR_P6_EVNTSEL0;
182 *type = MSR_TYPE_ARCH_CTRL;
183 return true;
184 }
185
186 msr_index_pmc = msr_index & MSR_PMC_ALIAS_MASK;
187 if ((msr_index_pmc >= MSR_IA32_PERFCTR0) &&
188 (msr_index_pmc < MSR_IA32_PERFCTR0 +
189 intel_num_arch_counters)) {
190 *type = MSR_TYPE_ARCH_COUNTER;
191 *index = msr_index_pmc - MSR_IA32_PERFCTR0;
192 return true;
193 }
194 return false;
195 }
196}
197
198static bool xen_intel_pmu_emulate(unsigned int msr, u64 *val, int type,
199 int index, bool is_read)
200{
201 uint64_t *reg = NULL;
202 struct xen_pmu_intel_ctxt *ctxt;
203 uint64_t *fix_counters;
204 struct xen_pmu_cntr_pair *arch_cntr_pair;
205 struct xen_pmu_data *xenpmu_data = get_xenpmu_data();
206 uint8_t xenpmu_flags = get_xenpmu_flags();
207
208
209 if (!xenpmu_data || !(xenpmu_flags & XENPMU_IRQ_PROCESSING))
210 return false;
211
212 ctxt = &xenpmu_data->pmu.c.intel;
213
214 switch (msr) {
215 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
216 reg = &ctxt->global_ovf_ctrl;
217 break;
218 case MSR_CORE_PERF_GLOBAL_STATUS:
219 reg = &ctxt->global_status;
220 break;
221 case MSR_CORE_PERF_GLOBAL_CTRL:
222 reg = &ctxt->global_ctrl;
223 break;
224 case MSR_CORE_PERF_FIXED_CTR_CTRL:
225 reg = &ctxt->fixed_ctrl;
226 break;
227 default:
228 switch (type) {
229 case MSR_TYPE_COUNTER:
230 fix_counters = field_offset(ctxt, fixed_counters);
231 reg = &fix_counters[index];
232 break;
233 case MSR_TYPE_ARCH_COUNTER:
234 arch_cntr_pair = field_offset(ctxt, arch_counters);
235 reg = &arch_cntr_pair[index].counter;
236 break;
237 case MSR_TYPE_ARCH_CTRL:
238 arch_cntr_pair = field_offset(ctxt, arch_counters);
239 reg = &arch_cntr_pair[index].control;
240 break;
241 default:
242 return false;
243 }
244 }
245
246 if (reg) {
247 if (is_read)
248 *val = *reg;
249 else {
250 *reg = *val;
251
252 if (msr == MSR_CORE_PERF_GLOBAL_OVF_CTRL)
253 ctxt->global_status &= (~(*val));
254 }
255 return true;
256 }
257
258 return false;
259}
260
261static bool xen_amd_pmu_emulate(unsigned int msr, u64 *val, bool is_read)
262{
263 uint64_t *reg = NULL;
264 int i, off = 0;
265 struct xen_pmu_amd_ctxt *ctxt;
266 uint64_t *counter_regs, *ctrl_regs;
267 struct xen_pmu_data *xenpmu_data = get_xenpmu_data();
268 uint8_t xenpmu_flags = get_xenpmu_flags();
269
270 if (!xenpmu_data || !(xenpmu_flags & XENPMU_IRQ_PROCESSING))
271 return false;
272
273 if (k7_counters_mirrored &&
274 ((msr >= MSR_K7_EVNTSEL0) && (msr <= MSR_K7_PERFCTR3)))
275 msr = get_fam15h_addr(msr);
276
277 ctxt = &xenpmu_data->pmu.c.amd;
278 for (i = 0; i < amd_num_counters; i++) {
279 if (msr == amd_ctrls_base + off) {
280 ctrl_regs = field_offset(ctxt, ctrls);
281 reg = &ctrl_regs[i];
282 break;
283 } else if (msr == amd_counters_base + off) {
284 counter_regs = field_offset(ctxt, counters);
285 reg = &counter_regs[i];
286 break;
287 }
288 off += amd_msr_step;
289 }
290
291 if (reg) {
292 if (is_read)
293 *val = *reg;
294 else
295 *reg = *val;
296
297 return true;
298 }
299 return false;
300}
301
302static bool pmu_msr_chk_emulated(unsigned int msr, uint64_t *val, bool is_read,
303 bool *emul)
304{
305 int type, index = 0;
306
307 if (is_amd_pmu_msr(msr))
308 *emul = xen_amd_pmu_emulate(msr, val, is_read);
309 else if (is_intel_pmu_msr(msr, &type, &index))
310 *emul = xen_intel_pmu_emulate(msr, val, type, index, is_read);
311 else
312 return false;
313
314 return true;
315}
316
317bool pmu_msr_read(unsigned int msr, uint64_t *val, int *err)
318{
319 bool emulated;
320
321 if (!pmu_msr_chk_emulated(msr, val, true, &emulated))
322 return false;
323
324 if (!emulated) {
325 *val = err ? native_read_msr_safe(msr, err)
326 : native_read_msr(msr);
327 }
328
329 return true;
330}
331
332bool pmu_msr_write(unsigned int msr, uint32_t low, uint32_t high, int *err)
333{
334 uint64_t val = ((uint64_t)high << 32) | low;
335 bool emulated;
336
337 if (!pmu_msr_chk_emulated(msr, &val, false, &emulated))
338 return false;
339
340 if (!emulated) {
341 if (err)
342 *err = native_write_msr_safe(msr, low, high);
343 else
344 native_write_msr(msr, low, high);
345 }
346
347 return true;
348}
349
350static unsigned long long xen_amd_read_pmc(int counter)
351{
352 struct xen_pmu_amd_ctxt *ctxt;
353 uint64_t *counter_regs;
354 struct xen_pmu_data *xenpmu_data = get_xenpmu_data();
355 uint8_t xenpmu_flags = get_xenpmu_flags();
356
357 if (!xenpmu_data || !(xenpmu_flags & XENPMU_IRQ_PROCESSING)) {
358 uint32_t msr;
359 int err;
360
361 msr = amd_counters_base + (counter * amd_msr_step);
362 return native_read_msr_safe(msr, &err);
363 }
364
365 ctxt = &xenpmu_data->pmu.c.amd;
366 counter_regs = field_offset(ctxt, counters);
367 return counter_regs[counter];
368}
369
370static unsigned long long xen_intel_read_pmc(int counter)
371{
372 struct xen_pmu_intel_ctxt *ctxt;
373 uint64_t *fixed_counters;
374 struct xen_pmu_cntr_pair *arch_cntr_pair;
375 struct xen_pmu_data *xenpmu_data = get_xenpmu_data();
376 uint8_t xenpmu_flags = get_xenpmu_flags();
377
378 if (!xenpmu_data || !(xenpmu_flags & XENPMU_IRQ_PROCESSING)) {
379 uint32_t msr;
380 int err;
381
382 if (counter & (1 << INTEL_PMC_TYPE_SHIFT))
383 msr = MSR_CORE_PERF_FIXED_CTR0 + (counter & 0xffff);
384 else
385 msr = MSR_IA32_PERFCTR0 + counter;
386
387 return native_read_msr_safe(msr, &err);
388 }
389
390 ctxt = &xenpmu_data->pmu.c.intel;
391 if (counter & (1 << INTEL_PMC_TYPE_SHIFT)) {
392 fixed_counters = field_offset(ctxt, fixed_counters);
393 return fixed_counters[counter & 0xffff];
394 }
395
396 arch_cntr_pair = field_offset(ctxt, arch_counters);
397 return arch_cntr_pair[counter].counter;
398}
399
400unsigned long long xen_read_pmc(int counter)
401{
402 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
403 return xen_amd_read_pmc(counter);
404 else
405 return xen_intel_read_pmc(counter);
406}
407
408int pmu_apic_update(uint32_t val)
409{
410 int ret;
411 struct xen_pmu_data *xenpmu_data = get_xenpmu_data();
412
413 if (!xenpmu_data) {
414 pr_warn_once("%s: pmudata not initialized\n", __func__);
415 return -EINVAL;
416 }
417
418 xenpmu_data->pmu.l.lapic_lvtpc = val;
419
420 if (get_xenpmu_flags() & XENPMU_IRQ_PROCESSING)
421 return 0;
422
423 ret = HYPERVISOR_xenpmu_op(XENPMU_lvtpc_set, NULL);
424
425 return ret;
426}
427
428/* perf callbacks */
429static unsigned int xen_guest_state(void)
430{
431 const struct xen_pmu_data *xenpmu_data = get_xenpmu_data();
432 unsigned int state = 0;
433
434 if (!xenpmu_data) {
435 pr_warn_once("%s: pmudata not initialized\n", __func__);
436 return state;
437 }
438
439 if (!xen_initial_domain() || (xenpmu_data->domain_id >= DOMID_SELF))
440 return state;
441
442 state |= PERF_GUEST_ACTIVE;
443
444 if (xenpmu_data->pmu.pmu_flags & PMU_SAMPLE_PV) {
445 if (xenpmu_data->pmu.pmu_flags & PMU_SAMPLE_USER)
446 state |= PERF_GUEST_USER;
447 } else if (xenpmu_data->pmu.r.regs.cpl & 3) {
448 state |= PERF_GUEST_USER;
449 }
450
451 return state;
452}
453
454static unsigned long xen_get_guest_ip(void)
455{
456 const struct xen_pmu_data *xenpmu_data = get_xenpmu_data();
457
458 if (!xenpmu_data) {
459 pr_warn_once("%s: pmudata not initialized\n", __func__);
460 return 0;
461 }
462
463 return xenpmu_data->pmu.r.regs.ip;
464}
465
466static struct perf_guest_info_callbacks xen_guest_cbs = {
467 .state = xen_guest_state,
468 .get_ip = xen_get_guest_ip,
469};
470
471/* Convert registers from Xen's format to Linux' */
472static void xen_convert_regs(const struct xen_pmu_regs *xen_regs,
473 struct pt_regs *regs, uint64_t pmu_flags)
474{
475 regs->ip = xen_regs->ip;
476 regs->cs = xen_regs->cs;
477 regs->sp = xen_regs->sp;
478
479 if (pmu_flags & PMU_SAMPLE_PV) {
480 if (pmu_flags & PMU_SAMPLE_USER)
481 regs->cs |= 3;
482 else
483 regs->cs &= ~3;
484 } else {
485 if (xen_regs->cpl)
486 regs->cs |= 3;
487 else
488 regs->cs &= ~3;
489 }
490}
491
492irqreturn_t xen_pmu_irq_handler(int irq, void *dev_id)
493{
494 int err, ret = IRQ_NONE;
495 struct pt_regs regs = {0};
496 const struct xen_pmu_data *xenpmu_data = get_xenpmu_data();
497 uint8_t xenpmu_flags = get_xenpmu_flags();
498
499 if (!xenpmu_data) {
500 pr_warn_once("%s: pmudata not initialized\n", __func__);
501 return ret;
502 }
503
504 this_cpu_ptr(&xenpmu_shared)->flags =
505 xenpmu_flags | XENPMU_IRQ_PROCESSING;
506 xen_convert_regs(&xenpmu_data->pmu.r.regs, ®s,
507 xenpmu_data->pmu.pmu_flags);
508 if (x86_pmu.handle_irq(®s))
509 ret = IRQ_HANDLED;
510
511 /* Write out cached context to HW */
512 err = HYPERVISOR_xenpmu_op(XENPMU_flush, NULL);
513 this_cpu_ptr(&xenpmu_shared)->flags = xenpmu_flags;
514 if (err) {
515 pr_warn_once("%s: failed hypercall, err: %d\n", __func__, err);
516 return IRQ_NONE;
517 }
518
519 return ret;
520}
521
522bool is_xen_pmu;
523
524void xen_pmu_init(int cpu)
525{
526 int err;
527 struct xen_pmu_params xp;
528 unsigned long pfn;
529 struct xen_pmu_data *xenpmu_data;
530
531 BUILD_BUG_ON(sizeof(struct xen_pmu_data) > PAGE_SIZE);
532
533 if (xen_hvm_domain() || (cpu != 0 && !is_xen_pmu))
534 return;
535
536 xenpmu_data = (struct xen_pmu_data *)get_zeroed_page(GFP_KERNEL);
537 if (!xenpmu_data) {
538 pr_err("VPMU init: No memory\n");
539 return;
540 }
541 pfn = virt_to_pfn(xenpmu_data);
542
543 xp.val = pfn_to_mfn(pfn);
544 xp.vcpu = cpu;
545 xp.version.maj = XENPMU_VER_MAJ;
546 xp.version.min = XENPMU_VER_MIN;
547 err = HYPERVISOR_xenpmu_op(XENPMU_init, &xp);
548 if (err)
549 goto fail;
550
551 per_cpu(xenpmu_shared, cpu).xenpmu_data = xenpmu_data;
552 per_cpu(xenpmu_shared, cpu).flags = 0;
553
554 if (!is_xen_pmu) {
555 is_xen_pmu = true;
556 perf_register_guest_info_callbacks(&xen_guest_cbs);
557 xen_pmu_arch_init();
558 }
559
560 return;
561
562fail:
563 if (err == -EOPNOTSUPP || err == -ENOSYS)
564 pr_info_once("VPMU disabled by hypervisor.\n");
565 else
566 pr_info_once("Could not initialize VPMU for cpu %d, error %d\n",
567 cpu, err);
568 free_pages((unsigned long)xenpmu_data, 0);
569}
570
571void xen_pmu_finish(int cpu)
572{
573 struct xen_pmu_params xp;
574
575 if (xen_hvm_domain())
576 return;
577
578 xp.vcpu = cpu;
579 xp.version.maj = XENPMU_VER_MAJ;
580 xp.version.min = XENPMU_VER_MIN;
581
582 (void)HYPERVISOR_xenpmu_op(XENPMU_finish, &xp);
583
584 free_pages((unsigned long)per_cpu(xenpmu_shared, cpu).xenpmu_data, 0);
585 per_cpu(xenpmu_shared, cpu).xenpmu_data = NULL;
586}
1// SPDX-License-Identifier: GPL-2.0
2#include <linux/types.h>
3#include <linux/interrupt.h>
4
5#include <asm/xen/hypercall.h>
6#include <xen/xen.h>
7#include <xen/page.h>
8#include <xen/interface/xen.h>
9#include <xen/interface/vcpu.h>
10#include <xen/interface/xenpmu.h>
11
12#include "xen-ops.h"
13
14/* x86_pmu.handle_irq definition */
15#include "../events/perf_event.h"
16
17#define XENPMU_IRQ_PROCESSING 1
18struct xenpmu {
19 /* Shared page between hypervisor and domain */
20 struct xen_pmu_data *xenpmu_data;
21
22 uint8_t flags;
23};
24static DEFINE_PER_CPU(struct xenpmu, xenpmu_shared);
25#define get_xenpmu_data() (this_cpu_ptr(&xenpmu_shared)->xenpmu_data)
26#define get_xenpmu_flags() (this_cpu_ptr(&xenpmu_shared)->flags)
27
28/* Macro for computing address of a PMU MSR bank */
29#define field_offset(ctxt, field) ((void *)((uintptr_t)ctxt + \
30 (uintptr_t)ctxt->field))
31
32/* AMD PMU */
33#define F15H_NUM_COUNTERS 6
34#define F10H_NUM_COUNTERS 4
35
36static __read_mostly uint32_t amd_counters_base;
37static __read_mostly uint32_t amd_ctrls_base;
38static __read_mostly int amd_msr_step;
39static __read_mostly int k7_counters_mirrored;
40static __read_mostly int amd_num_counters;
41
42/* Intel PMU */
43#define MSR_TYPE_COUNTER 0
44#define MSR_TYPE_CTRL 1
45#define MSR_TYPE_GLOBAL 2
46#define MSR_TYPE_ARCH_COUNTER 3
47#define MSR_TYPE_ARCH_CTRL 4
48
49/* Number of general pmu registers (CPUID.EAX[0xa].EAX[8..15]) */
50#define PMU_GENERAL_NR_SHIFT 8
51#define PMU_GENERAL_NR_BITS 8
52#define PMU_GENERAL_NR_MASK (((1 << PMU_GENERAL_NR_BITS) - 1) \
53 << PMU_GENERAL_NR_SHIFT)
54
55/* Number of fixed pmu registers (CPUID.EDX[0xa].EDX[0..4]) */
56#define PMU_FIXED_NR_SHIFT 0
57#define PMU_FIXED_NR_BITS 5
58#define PMU_FIXED_NR_MASK (((1 << PMU_FIXED_NR_BITS) - 1) \
59 << PMU_FIXED_NR_SHIFT)
60
61/* Alias registers (0x4c1) for full-width writes to PMCs */
62#define MSR_PMC_ALIAS_MASK (~(MSR_IA32_PERFCTR0 ^ MSR_IA32_PMC0))
63
64#define INTEL_PMC_TYPE_SHIFT 30
65
66static __read_mostly int intel_num_arch_counters, intel_num_fixed_counters;
67
68
69static void xen_pmu_arch_init(void)
70{
71 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
72
73 switch (boot_cpu_data.x86) {
74 case 0x15:
75 amd_num_counters = F15H_NUM_COUNTERS;
76 amd_counters_base = MSR_F15H_PERF_CTR;
77 amd_ctrls_base = MSR_F15H_PERF_CTL;
78 amd_msr_step = 2;
79 k7_counters_mirrored = 1;
80 break;
81 case 0x10:
82 case 0x12:
83 case 0x14:
84 case 0x16:
85 default:
86 amd_num_counters = F10H_NUM_COUNTERS;
87 amd_counters_base = MSR_K7_PERFCTR0;
88 amd_ctrls_base = MSR_K7_EVNTSEL0;
89 amd_msr_step = 1;
90 k7_counters_mirrored = 0;
91 break;
92 }
93 } else if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
94 amd_num_counters = F10H_NUM_COUNTERS;
95 amd_counters_base = MSR_K7_PERFCTR0;
96 amd_ctrls_base = MSR_K7_EVNTSEL0;
97 amd_msr_step = 1;
98 k7_counters_mirrored = 0;
99 } else {
100 uint32_t eax, ebx, ecx, edx;
101
102 cpuid(0xa, &eax, &ebx, &ecx, &edx);
103
104 intel_num_arch_counters = (eax & PMU_GENERAL_NR_MASK) >>
105 PMU_GENERAL_NR_SHIFT;
106 intel_num_fixed_counters = (edx & PMU_FIXED_NR_MASK) >>
107 PMU_FIXED_NR_SHIFT;
108 }
109}
110
111static inline uint32_t get_fam15h_addr(u32 addr)
112{
113 switch (addr) {
114 case MSR_K7_PERFCTR0:
115 case MSR_K7_PERFCTR1:
116 case MSR_K7_PERFCTR2:
117 case MSR_K7_PERFCTR3:
118 return MSR_F15H_PERF_CTR + (addr - MSR_K7_PERFCTR0);
119 case MSR_K7_EVNTSEL0:
120 case MSR_K7_EVNTSEL1:
121 case MSR_K7_EVNTSEL2:
122 case MSR_K7_EVNTSEL3:
123 return MSR_F15H_PERF_CTL + (addr - MSR_K7_EVNTSEL0);
124 default:
125 break;
126 }
127
128 return addr;
129}
130
131static inline bool is_amd_pmu_msr(unsigned int msr)
132{
133 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
134 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
135 return false;
136
137 if ((msr >= MSR_F15H_PERF_CTL &&
138 msr < MSR_F15H_PERF_CTR + (amd_num_counters * 2)) ||
139 (msr >= MSR_K7_EVNTSEL0 &&
140 msr < MSR_K7_PERFCTR0 + amd_num_counters))
141 return true;
142
143 return false;
144}
145
146static bool is_intel_pmu_msr(u32 msr_index, int *type, int *index)
147{
148 u32 msr_index_pmc;
149
150 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&
151 boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR &&
152 boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)
153 return false;
154
155 switch (msr_index) {
156 case MSR_CORE_PERF_FIXED_CTR_CTRL:
157 case MSR_IA32_DS_AREA:
158 case MSR_IA32_PEBS_ENABLE:
159 *type = MSR_TYPE_CTRL;
160 return true;
161
162 case MSR_CORE_PERF_GLOBAL_CTRL:
163 case MSR_CORE_PERF_GLOBAL_STATUS:
164 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
165 *type = MSR_TYPE_GLOBAL;
166 return true;
167
168 default:
169
170 if ((msr_index >= MSR_CORE_PERF_FIXED_CTR0) &&
171 (msr_index < MSR_CORE_PERF_FIXED_CTR0 +
172 intel_num_fixed_counters)) {
173 *index = msr_index - MSR_CORE_PERF_FIXED_CTR0;
174 *type = MSR_TYPE_COUNTER;
175 return true;
176 }
177
178 if ((msr_index >= MSR_P6_EVNTSEL0) &&
179 (msr_index < MSR_P6_EVNTSEL0 + intel_num_arch_counters)) {
180 *index = msr_index - MSR_P6_EVNTSEL0;
181 *type = MSR_TYPE_ARCH_CTRL;
182 return true;
183 }
184
185 msr_index_pmc = msr_index & MSR_PMC_ALIAS_MASK;
186 if ((msr_index_pmc >= MSR_IA32_PERFCTR0) &&
187 (msr_index_pmc < MSR_IA32_PERFCTR0 +
188 intel_num_arch_counters)) {
189 *type = MSR_TYPE_ARCH_COUNTER;
190 *index = msr_index_pmc - MSR_IA32_PERFCTR0;
191 return true;
192 }
193 return false;
194 }
195}
196
197static bool xen_intel_pmu_emulate(unsigned int msr, u64 *val, int type,
198 int index, bool is_read)
199{
200 uint64_t *reg = NULL;
201 struct xen_pmu_intel_ctxt *ctxt;
202 uint64_t *fix_counters;
203 struct xen_pmu_cntr_pair *arch_cntr_pair;
204 struct xen_pmu_data *xenpmu_data = get_xenpmu_data();
205 uint8_t xenpmu_flags = get_xenpmu_flags();
206
207
208 if (!xenpmu_data || !(xenpmu_flags & XENPMU_IRQ_PROCESSING))
209 return false;
210
211 ctxt = &xenpmu_data->pmu.c.intel;
212
213 switch (msr) {
214 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
215 reg = &ctxt->global_ovf_ctrl;
216 break;
217 case MSR_CORE_PERF_GLOBAL_STATUS:
218 reg = &ctxt->global_status;
219 break;
220 case MSR_CORE_PERF_GLOBAL_CTRL:
221 reg = &ctxt->global_ctrl;
222 break;
223 case MSR_CORE_PERF_FIXED_CTR_CTRL:
224 reg = &ctxt->fixed_ctrl;
225 break;
226 default:
227 switch (type) {
228 case MSR_TYPE_COUNTER:
229 fix_counters = field_offset(ctxt, fixed_counters);
230 reg = &fix_counters[index];
231 break;
232 case MSR_TYPE_ARCH_COUNTER:
233 arch_cntr_pair = field_offset(ctxt, arch_counters);
234 reg = &arch_cntr_pair[index].counter;
235 break;
236 case MSR_TYPE_ARCH_CTRL:
237 arch_cntr_pair = field_offset(ctxt, arch_counters);
238 reg = &arch_cntr_pair[index].control;
239 break;
240 default:
241 return false;
242 }
243 }
244
245 if (reg) {
246 if (is_read)
247 *val = *reg;
248 else {
249 *reg = *val;
250
251 if (msr == MSR_CORE_PERF_GLOBAL_OVF_CTRL)
252 ctxt->global_status &= (~(*val));
253 }
254 return true;
255 }
256
257 return false;
258}
259
260static bool xen_amd_pmu_emulate(unsigned int msr, u64 *val, bool is_read)
261{
262 uint64_t *reg = NULL;
263 int i, off = 0;
264 struct xen_pmu_amd_ctxt *ctxt;
265 uint64_t *counter_regs, *ctrl_regs;
266 struct xen_pmu_data *xenpmu_data = get_xenpmu_data();
267 uint8_t xenpmu_flags = get_xenpmu_flags();
268
269 if (!xenpmu_data || !(xenpmu_flags & XENPMU_IRQ_PROCESSING))
270 return false;
271
272 if (k7_counters_mirrored &&
273 ((msr >= MSR_K7_EVNTSEL0) && (msr <= MSR_K7_PERFCTR3)))
274 msr = get_fam15h_addr(msr);
275
276 ctxt = &xenpmu_data->pmu.c.amd;
277 for (i = 0; i < amd_num_counters; i++) {
278 if (msr == amd_ctrls_base + off) {
279 ctrl_regs = field_offset(ctxt, ctrls);
280 reg = &ctrl_regs[i];
281 break;
282 } else if (msr == amd_counters_base + off) {
283 counter_regs = field_offset(ctxt, counters);
284 reg = &counter_regs[i];
285 break;
286 }
287 off += amd_msr_step;
288 }
289
290 if (reg) {
291 if (is_read)
292 *val = *reg;
293 else
294 *reg = *val;
295
296 return true;
297 }
298 return false;
299}
300
301static bool pmu_msr_chk_emulated(unsigned int msr, uint64_t *val, bool is_read,
302 bool *emul)
303{
304 int type, index = 0;
305
306 if (is_amd_pmu_msr(msr))
307 *emul = xen_amd_pmu_emulate(msr, val, is_read);
308 else if (is_intel_pmu_msr(msr, &type, &index))
309 *emul = xen_intel_pmu_emulate(msr, val, type, index, is_read);
310 else
311 return false;
312
313 return true;
314}
315
316bool pmu_msr_read(unsigned int msr, uint64_t *val, int *err)
317{
318 bool emulated;
319
320 if (!pmu_msr_chk_emulated(msr, val, true, &emulated))
321 return false;
322
323 if (!emulated) {
324 *val = err ? native_read_msr_safe(msr, err)
325 : native_read_msr(msr);
326 }
327
328 return true;
329}
330
331bool pmu_msr_write(unsigned int msr, uint32_t low, uint32_t high, int *err)
332{
333 uint64_t val = ((uint64_t)high << 32) | low;
334 bool emulated;
335
336 if (!pmu_msr_chk_emulated(msr, &val, false, &emulated))
337 return false;
338
339 if (!emulated) {
340 if (err)
341 *err = native_write_msr_safe(msr, low, high);
342 else
343 native_write_msr(msr, low, high);
344 }
345
346 return true;
347}
348
349static unsigned long long xen_amd_read_pmc(int counter)
350{
351 struct xen_pmu_amd_ctxt *ctxt;
352 uint64_t *counter_regs;
353 struct xen_pmu_data *xenpmu_data = get_xenpmu_data();
354 uint8_t xenpmu_flags = get_xenpmu_flags();
355
356 if (!xenpmu_data || !(xenpmu_flags & XENPMU_IRQ_PROCESSING)) {
357 uint32_t msr;
358 int err;
359
360 msr = amd_counters_base + (counter * amd_msr_step);
361 return native_read_msr_safe(msr, &err);
362 }
363
364 ctxt = &xenpmu_data->pmu.c.amd;
365 counter_regs = field_offset(ctxt, counters);
366 return counter_regs[counter];
367}
368
369static unsigned long long xen_intel_read_pmc(int counter)
370{
371 struct xen_pmu_intel_ctxt *ctxt;
372 uint64_t *fixed_counters;
373 struct xen_pmu_cntr_pair *arch_cntr_pair;
374 struct xen_pmu_data *xenpmu_data = get_xenpmu_data();
375 uint8_t xenpmu_flags = get_xenpmu_flags();
376
377 if (!xenpmu_data || !(xenpmu_flags & XENPMU_IRQ_PROCESSING)) {
378 uint32_t msr;
379 int err;
380
381 if (counter & (1 << INTEL_PMC_TYPE_SHIFT))
382 msr = MSR_CORE_PERF_FIXED_CTR0 + (counter & 0xffff);
383 else
384 msr = MSR_IA32_PERFCTR0 + counter;
385
386 return native_read_msr_safe(msr, &err);
387 }
388
389 ctxt = &xenpmu_data->pmu.c.intel;
390 if (counter & (1 << INTEL_PMC_TYPE_SHIFT)) {
391 fixed_counters = field_offset(ctxt, fixed_counters);
392 return fixed_counters[counter & 0xffff];
393 }
394
395 arch_cntr_pair = field_offset(ctxt, arch_counters);
396 return arch_cntr_pair[counter].counter;
397}
398
399unsigned long long xen_read_pmc(int counter)
400{
401 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
402 return xen_amd_read_pmc(counter);
403 else
404 return xen_intel_read_pmc(counter);
405}
406
407int pmu_apic_update(uint32_t val)
408{
409 int ret;
410 struct xen_pmu_data *xenpmu_data = get_xenpmu_data();
411
412 if (!xenpmu_data) {
413 pr_warn_once("%s: pmudata not initialized\n", __func__);
414 return -EINVAL;
415 }
416
417 xenpmu_data->pmu.l.lapic_lvtpc = val;
418
419 if (get_xenpmu_flags() & XENPMU_IRQ_PROCESSING)
420 return 0;
421
422 ret = HYPERVISOR_xenpmu_op(XENPMU_lvtpc_set, NULL);
423
424 return ret;
425}
426
427/* perf callbacks */
428static unsigned int xen_guest_state(void)
429{
430 const struct xen_pmu_data *xenpmu_data = get_xenpmu_data();
431 unsigned int state = 0;
432
433 if (!xenpmu_data) {
434 pr_warn_once("%s: pmudata not initialized\n", __func__);
435 return state;
436 }
437
438 if (!xen_initial_domain() || (xenpmu_data->domain_id >= DOMID_SELF))
439 return state;
440
441 state |= PERF_GUEST_ACTIVE;
442
443 if (xenpmu_data->pmu.pmu_flags & PMU_SAMPLE_PV) {
444 if (xenpmu_data->pmu.pmu_flags & PMU_SAMPLE_USER)
445 state |= PERF_GUEST_USER;
446 } else if (xenpmu_data->pmu.r.regs.cpl & 3) {
447 state |= PERF_GUEST_USER;
448 }
449
450 return state;
451}
452
453static unsigned long xen_get_guest_ip(void)
454{
455 const struct xen_pmu_data *xenpmu_data = get_xenpmu_data();
456
457 if (!xenpmu_data) {
458 pr_warn_once("%s: pmudata not initialized\n", __func__);
459 return 0;
460 }
461
462 return xenpmu_data->pmu.r.regs.ip;
463}
464
465static struct perf_guest_info_callbacks xen_guest_cbs = {
466 .state = xen_guest_state,
467 .get_ip = xen_get_guest_ip,
468};
469
470/* Convert registers from Xen's format to Linux' */
471static void xen_convert_regs(const struct xen_pmu_regs *xen_regs,
472 struct pt_regs *regs, uint64_t pmu_flags)
473{
474 regs->ip = xen_regs->ip;
475 regs->cs = xen_regs->cs;
476 regs->sp = xen_regs->sp;
477
478 if (pmu_flags & PMU_SAMPLE_PV) {
479 if (pmu_flags & PMU_SAMPLE_USER)
480 regs->cs |= 3;
481 else
482 regs->cs &= ~3;
483 } else {
484 if (xen_regs->cpl)
485 regs->cs |= 3;
486 else
487 regs->cs &= ~3;
488 }
489}
490
491irqreturn_t xen_pmu_irq_handler(int irq, void *dev_id)
492{
493 int err, ret = IRQ_NONE;
494 struct pt_regs regs = {0};
495 const struct xen_pmu_data *xenpmu_data = get_xenpmu_data();
496 uint8_t xenpmu_flags = get_xenpmu_flags();
497
498 if (!xenpmu_data) {
499 pr_warn_once("%s: pmudata not initialized\n", __func__);
500 return ret;
501 }
502
503 this_cpu_ptr(&xenpmu_shared)->flags =
504 xenpmu_flags | XENPMU_IRQ_PROCESSING;
505 xen_convert_regs(&xenpmu_data->pmu.r.regs, ®s,
506 xenpmu_data->pmu.pmu_flags);
507 if (x86_pmu.handle_irq(®s))
508 ret = IRQ_HANDLED;
509
510 /* Write out cached context to HW */
511 err = HYPERVISOR_xenpmu_op(XENPMU_flush, NULL);
512 this_cpu_ptr(&xenpmu_shared)->flags = xenpmu_flags;
513 if (err) {
514 pr_warn_once("%s: failed hypercall, err: %d\n", __func__, err);
515 return IRQ_NONE;
516 }
517
518 return ret;
519}
520
521bool is_xen_pmu;
522
523void xen_pmu_init(int cpu)
524{
525 int err;
526 struct xen_pmu_params xp;
527 unsigned long pfn;
528 struct xen_pmu_data *xenpmu_data;
529
530 BUILD_BUG_ON(sizeof(struct xen_pmu_data) > PAGE_SIZE);
531
532 if (xen_hvm_domain() || (cpu != 0 && !is_xen_pmu))
533 return;
534
535 xenpmu_data = (struct xen_pmu_data *)get_zeroed_page(GFP_KERNEL);
536 if (!xenpmu_data) {
537 pr_err("VPMU init: No memory\n");
538 return;
539 }
540 pfn = virt_to_pfn(xenpmu_data);
541
542 xp.val = pfn_to_mfn(pfn);
543 xp.vcpu = cpu;
544 xp.version.maj = XENPMU_VER_MAJ;
545 xp.version.min = XENPMU_VER_MIN;
546 err = HYPERVISOR_xenpmu_op(XENPMU_init, &xp);
547 if (err)
548 goto fail;
549
550 per_cpu(xenpmu_shared, cpu).xenpmu_data = xenpmu_data;
551 per_cpu(xenpmu_shared, cpu).flags = 0;
552
553 if (!is_xen_pmu) {
554 is_xen_pmu = true;
555 perf_register_guest_info_callbacks(&xen_guest_cbs);
556 xen_pmu_arch_init();
557 }
558
559 return;
560
561fail:
562 if (err == -EOPNOTSUPP || err == -ENOSYS)
563 pr_info_once("VPMU disabled by hypervisor.\n");
564 else
565 pr_info_once("Could not initialize VPMU for cpu %d, error %d\n",
566 cpu, err);
567 free_pages((unsigned long)xenpmu_data, 0);
568}
569
570void xen_pmu_finish(int cpu)
571{
572 struct xen_pmu_params xp;
573
574 if (xen_hvm_domain())
575 return;
576
577 xp.vcpu = cpu;
578 xp.version.maj = XENPMU_VER_MAJ;
579 xp.version.min = XENPMU_VER_MIN;
580
581 (void)HYPERVISOR_xenpmu_op(XENPMU_finish, &xp);
582
583 free_pages((unsigned long)per_cpu(xenpmu_shared, cpu).xenpmu_data, 0);
584 per_cpu(xenpmu_shared, cpu).xenpmu_data = NULL;
585}