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1// SPDX-License-Identifier: GPL-2.0
2/* pci.c: UltraSparc PCI controller support.
3 *
4 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
5 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
7 *
8 * OF tree based PCI bus probing taken from the PowerPC port
9 * with minor modifications, see there for credits.
10 */
11
12#include <linux/export.h>
13#include <linux/kernel.h>
14#include <linux/string.h>
15#include <linux/sched.h>
16#include <linux/capability.h>
17#include <linux/errno.h>
18#include <linux/pci.h>
19#include <linux/msi.h>
20#include <linux/irq.h>
21#include <linux/init.h>
22#include <linux/of.h>
23#include <linux/of_device.h>
24#include <linux/pgtable.h>
25
26#include <linux/uaccess.h>
27#include <asm/irq.h>
28#include <asm/prom.h>
29#include <asm/apb.h>
30
31#include "pci_impl.h"
32#include "kernel.h"
33
34/* List of all PCI controllers found in the system. */
35struct pci_pbm_info *pci_pbm_root = NULL;
36
37/* Each PBM found gets a unique index. */
38int pci_num_pbms = 0;
39
40volatile int pci_poke_in_progress;
41volatile int pci_poke_cpu = -1;
42volatile int pci_poke_faulted;
43
44static DEFINE_SPINLOCK(pci_poke_lock);
45
46void pci_config_read8(u8 *addr, u8 *ret)
47{
48 unsigned long flags;
49 u8 byte;
50
51 spin_lock_irqsave(&pci_poke_lock, flags);
52 pci_poke_cpu = smp_processor_id();
53 pci_poke_in_progress = 1;
54 pci_poke_faulted = 0;
55 __asm__ __volatile__("membar #Sync\n\t"
56 "lduba [%1] %2, %0\n\t"
57 "membar #Sync"
58 : "=r" (byte)
59 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
60 : "memory");
61 pci_poke_in_progress = 0;
62 pci_poke_cpu = -1;
63 if (!pci_poke_faulted)
64 *ret = byte;
65 spin_unlock_irqrestore(&pci_poke_lock, flags);
66}
67
68void pci_config_read16(u16 *addr, u16 *ret)
69{
70 unsigned long flags;
71 u16 word;
72
73 spin_lock_irqsave(&pci_poke_lock, flags);
74 pci_poke_cpu = smp_processor_id();
75 pci_poke_in_progress = 1;
76 pci_poke_faulted = 0;
77 __asm__ __volatile__("membar #Sync\n\t"
78 "lduha [%1] %2, %0\n\t"
79 "membar #Sync"
80 : "=r" (word)
81 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
82 : "memory");
83 pci_poke_in_progress = 0;
84 pci_poke_cpu = -1;
85 if (!pci_poke_faulted)
86 *ret = word;
87 spin_unlock_irqrestore(&pci_poke_lock, flags);
88}
89
90void pci_config_read32(u32 *addr, u32 *ret)
91{
92 unsigned long flags;
93 u32 dword;
94
95 spin_lock_irqsave(&pci_poke_lock, flags);
96 pci_poke_cpu = smp_processor_id();
97 pci_poke_in_progress = 1;
98 pci_poke_faulted = 0;
99 __asm__ __volatile__("membar #Sync\n\t"
100 "lduwa [%1] %2, %0\n\t"
101 "membar #Sync"
102 : "=r" (dword)
103 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
104 : "memory");
105 pci_poke_in_progress = 0;
106 pci_poke_cpu = -1;
107 if (!pci_poke_faulted)
108 *ret = dword;
109 spin_unlock_irqrestore(&pci_poke_lock, flags);
110}
111
112void pci_config_write8(u8 *addr, u8 val)
113{
114 unsigned long flags;
115
116 spin_lock_irqsave(&pci_poke_lock, flags);
117 pci_poke_cpu = smp_processor_id();
118 pci_poke_in_progress = 1;
119 pci_poke_faulted = 0;
120 __asm__ __volatile__("membar #Sync\n\t"
121 "stba %0, [%1] %2\n\t"
122 "membar #Sync"
123 : /* no outputs */
124 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
125 : "memory");
126 pci_poke_in_progress = 0;
127 pci_poke_cpu = -1;
128 spin_unlock_irqrestore(&pci_poke_lock, flags);
129}
130
131void pci_config_write16(u16 *addr, u16 val)
132{
133 unsigned long flags;
134
135 spin_lock_irqsave(&pci_poke_lock, flags);
136 pci_poke_cpu = smp_processor_id();
137 pci_poke_in_progress = 1;
138 pci_poke_faulted = 0;
139 __asm__ __volatile__("membar #Sync\n\t"
140 "stha %0, [%1] %2\n\t"
141 "membar #Sync"
142 : /* no outputs */
143 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
144 : "memory");
145 pci_poke_in_progress = 0;
146 pci_poke_cpu = -1;
147 spin_unlock_irqrestore(&pci_poke_lock, flags);
148}
149
150void pci_config_write32(u32 *addr, u32 val)
151{
152 unsigned long flags;
153
154 spin_lock_irqsave(&pci_poke_lock, flags);
155 pci_poke_cpu = smp_processor_id();
156 pci_poke_in_progress = 1;
157 pci_poke_faulted = 0;
158 __asm__ __volatile__("membar #Sync\n\t"
159 "stwa %0, [%1] %2\n\t"
160 "membar #Sync"
161 : /* no outputs */
162 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
163 : "memory");
164 pci_poke_in_progress = 0;
165 pci_poke_cpu = -1;
166 spin_unlock_irqrestore(&pci_poke_lock, flags);
167}
168
169static int ofpci_verbose;
170
171static int __init ofpci_debug(char *str)
172{
173 int val = 0;
174
175 get_option(&str, &val);
176 if (val)
177 ofpci_verbose = 1;
178 return 1;
179}
180
181__setup("ofpci_debug=", ofpci_debug);
182
183static unsigned long pci_parse_of_flags(u32 addr0)
184{
185 unsigned long flags = 0;
186
187 if (addr0 & 0x02000000) {
188 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
189 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
190 if (addr0 & 0x01000000)
191 flags |= IORESOURCE_MEM_64
192 | PCI_BASE_ADDRESS_MEM_TYPE_64;
193 if (addr0 & 0x40000000)
194 flags |= IORESOURCE_PREFETCH
195 | PCI_BASE_ADDRESS_MEM_PREFETCH;
196 } else if (addr0 & 0x01000000)
197 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
198 return flags;
199}
200
201/* The of_device layer has translated all of the assigned-address properties
202 * into physical address resources, we only have to figure out the register
203 * mapping.
204 */
205static void pci_parse_of_addrs(struct platform_device *op,
206 struct device_node *node,
207 struct pci_dev *dev)
208{
209 struct resource *op_res;
210 const u32 *addrs;
211 int proplen;
212
213 addrs = of_get_property(node, "assigned-addresses", &proplen);
214 if (!addrs)
215 return;
216 if (ofpci_verbose)
217 pci_info(dev, " parse addresses (%d bytes) @ %p\n",
218 proplen, addrs);
219 op_res = &op->resource[0];
220 for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
221 struct resource *res;
222 unsigned long flags;
223 int i;
224
225 flags = pci_parse_of_flags(addrs[0]);
226 if (!flags)
227 continue;
228 i = addrs[0] & 0xff;
229 if (ofpci_verbose)
230 pci_info(dev, " start: %llx, end: %llx, i: %x\n",
231 op_res->start, op_res->end, i);
232
233 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
234 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
235 } else if (i == dev->rom_base_reg) {
236 res = &dev->resource[PCI_ROM_RESOURCE];
237 flags |= IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
238 } else {
239 pci_err(dev, "bad cfg reg num 0x%x\n", i);
240 continue;
241 }
242 res->start = op_res->start;
243 res->end = op_res->end;
244 res->flags = flags;
245 res->name = pci_name(dev);
246
247 pci_info(dev, "reg 0x%x: %pR\n", i, res);
248 }
249}
250
251static void pci_init_dev_archdata(struct dev_archdata *sd, void *iommu,
252 void *stc, void *host_controller,
253 struct platform_device *op,
254 int numa_node)
255{
256 sd->iommu = iommu;
257 sd->stc = stc;
258 sd->host_controller = host_controller;
259 sd->op = op;
260 sd->numa_node = numa_node;
261}
262
263static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
264 struct device_node *node,
265 struct pci_bus *bus, int devfn)
266{
267 struct dev_archdata *sd;
268 struct platform_device *op;
269 struct pci_dev *dev;
270 u32 class;
271
272 dev = pci_alloc_dev(bus);
273 if (!dev)
274 return NULL;
275
276 op = of_find_device_by_node(node);
277 sd = &dev->dev.archdata;
278 pci_init_dev_archdata(sd, pbm->iommu, &pbm->stc, pbm, op,
279 pbm->numa_node);
280 sd = &op->dev.archdata;
281 sd->iommu = pbm->iommu;
282 sd->stc = &pbm->stc;
283 sd->numa_node = pbm->numa_node;
284
285 if (of_node_name_eq(node, "ebus"))
286 of_propagate_archdata(op);
287
288 if (ofpci_verbose)
289 pci_info(bus," create device, devfn: %x, type: %s\n",
290 devfn, of_node_get_device_type(node));
291
292 dev->sysdata = node;
293 dev->dev.parent = bus->bridge;
294 dev->dev.bus = &pci_bus_type;
295 dev->dev.of_node = of_node_get(node);
296 dev->devfn = devfn;
297 dev->multifunction = 0; /* maybe a lie? */
298 set_pcie_port_type(dev);
299
300 pci_dev_assign_slot(dev);
301 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
302 dev->device = of_getintprop_default(node, "device-id", 0xffff);
303 dev->subsystem_vendor =
304 of_getintprop_default(node, "subsystem-vendor-id", 0);
305 dev->subsystem_device =
306 of_getintprop_default(node, "subsystem-id", 0);
307
308 dev->cfg_size = pci_cfg_space_size(dev);
309
310 /* We can't actually use the firmware value, we have
311 * to read what is in the register right now. One
312 * reason is that in the case of IDE interfaces the
313 * firmware can sample the value before the the IDE
314 * interface is programmed into native mode.
315 */
316 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
317 dev->class = class >> 8;
318 dev->revision = class & 0xff;
319
320 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
321 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
322
323 /* I have seen IDE devices which will not respond to
324 * the bmdma simplex check reads if bus mastering is
325 * disabled.
326 */
327 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
328 pci_set_master(dev);
329
330 dev->current_state = PCI_UNKNOWN; /* unknown power state */
331 dev->error_state = pci_channel_io_normal;
332 dev->dma_mask = 0xffffffff;
333
334 if (of_node_name_eq(node, "pci")) {
335 /* a PCI-PCI bridge */
336 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
337 dev->rom_base_reg = PCI_ROM_ADDRESS1;
338 } else if (of_node_is_type(node, "cardbus")) {
339 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
340 } else {
341 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
342 dev->rom_base_reg = PCI_ROM_ADDRESS;
343
344 dev->irq = sd->op->archdata.irqs[0];
345 if (dev->irq == 0xffffffff)
346 dev->irq = PCI_IRQ_NONE;
347 }
348
349 pci_info(dev, "[%04x:%04x] type %02x class %#08x\n",
350 dev->vendor, dev->device, dev->hdr_type, dev->class);
351
352 pci_parse_of_addrs(sd->op, node, dev);
353
354 if (ofpci_verbose)
355 pci_info(dev, " adding to system ...\n");
356
357 pci_device_add(dev, bus);
358
359 return dev;
360}
361
362static void apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
363{
364 u32 idx, first, last;
365
366 first = 8;
367 last = 0;
368 for (idx = 0; idx < 8; idx++) {
369 if ((map & (1 << idx)) != 0) {
370 if (first > idx)
371 first = idx;
372 if (last < idx)
373 last = idx;
374 }
375 }
376
377 *first_p = first;
378 *last_p = last;
379}
380
381/* Cook up fake bus resources for SUNW,simba PCI bridges which lack
382 * a proper 'ranges' property.
383 */
384static void apb_fake_ranges(struct pci_dev *dev,
385 struct pci_bus *bus,
386 struct pci_pbm_info *pbm)
387{
388 struct pci_bus_region region;
389 struct resource *res;
390 u32 first, last;
391 u8 map;
392
393 pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
394 apb_calc_first_last(map, &first, &last);
395 res = bus->resource[0];
396 res->flags = IORESOURCE_IO;
397 region.start = (first << 21);
398 region.end = (last << 21) + ((1 << 21) - 1);
399 pcibios_bus_to_resource(dev->bus, res, ®ion);
400
401 pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
402 apb_calc_first_last(map, &first, &last);
403 res = bus->resource[1];
404 res->flags = IORESOURCE_MEM;
405 region.start = (first << 29);
406 region.end = (last << 29) + ((1 << 29) - 1);
407 pcibios_bus_to_resource(dev->bus, res, ®ion);
408}
409
410static void pci_of_scan_bus(struct pci_pbm_info *pbm,
411 struct device_node *node,
412 struct pci_bus *bus);
413
414#define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
415
416static void of_scan_pci_bridge(struct pci_pbm_info *pbm,
417 struct device_node *node,
418 struct pci_dev *dev)
419{
420 struct pci_bus *bus;
421 const u32 *busrange, *ranges;
422 int len, i, simba;
423 struct pci_bus_region region;
424 struct resource *res;
425 unsigned int flags;
426 u64 size;
427
428 if (ofpci_verbose)
429 pci_info(dev, "of_scan_pci_bridge(%pOF)\n", node);
430
431 /* parse bus-range property */
432 busrange = of_get_property(node, "bus-range", &len);
433 if (busrange == NULL || len != 8) {
434 pci_info(dev, "Can't get bus-range for PCI-PCI bridge %pOF\n",
435 node);
436 return;
437 }
438
439 if (ofpci_verbose)
440 pci_info(dev, " Bridge bus range [%u --> %u]\n",
441 busrange[0], busrange[1]);
442
443 ranges = of_get_property(node, "ranges", &len);
444 simba = 0;
445 if (ranges == NULL) {
446 const char *model = of_get_property(node, "model", NULL);
447 if (model && !strcmp(model, "SUNW,simba"))
448 simba = 1;
449 }
450
451 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
452 if (!bus) {
453 pci_err(dev, "Failed to create pci bus for %pOF\n",
454 node);
455 return;
456 }
457
458 bus->primary = dev->bus->number;
459 pci_bus_insert_busn_res(bus, busrange[0], busrange[1]);
460 bus->bridge_ctl = 0;
461
462 if (ofpci_verbose)
463 pci_info(dev, " Bridge ranges[%p] simba[%d]\n",
464 ranges, simba);
465
466 /* parse ranges property, or cook one up by hand for Simba */
467 /* PCI #address-cells == 3 and #size-cells == 2 always */
468 res = &dev->resource[PCI_BRIDGE_RESOURCES];
469 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
470 res->flags = 0;
471 bus->resource[i] = res;
472 ++res;
473 }
474 if (simba) {
475 apb_fake_ranges(dev, bus, pbm);
476 goto after_ranges;
477 } else if (ranges == NULL) {
478 pci_read_bridge_bases(bus);
479 goto after_ranges;
480 }
481 i = 1;
482 for (; len >= 32; len -= 32, ranges += 8) {
483 u64 start;
484
485 if (ofpci_verbose)
486 pci_info(dev, " RAW Range[%08x:%08x:%08x:%08x:%08x:%08x:"
487 "%08x:%08x]\n",
488 ranges[0], ranges[1], ranges[2], ranges[3],
489 ranges[4], ranges[5], ranges[6], ranges[7]);
490
491 flags = pci_parse_of_flags(ranges[0]);
492 size = GET_64BIT(ranges, 6);
493 if (flags == 0 || size == 0)
494 continue;
495
496 /* On PCI-Express systems, PCI bridges that have no devices downstream
497 * have a bogus size value where the first 32-bit cell is 0xffffffff.
498 * This results in a bogus range where start + size overflows.
499 *
500 * Just skip these otherwise the kernel will complain when the resource
501 * tries to be claimed.
502 */
503 if (size >> 32 == 0xffffffff)
504 continue;
505
506 if (flags & IORESOURCE_IO) {
507 res = bus->resource[0];
508 if (res->flags) {
509 pci_err(dev, "ignoring extra I/O range"
510 " for bridge %pOF\n", node);
511 continue;
512 }
513 } else {
514 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
515 pci_err(dev, "too many memory ranges"
516 " for bridge %pOF\n", node);
517 continue;
518 }
519 res = bus->resource[i];
520 ++i;
521 }
522
523 res->flags = flags;
524 region.start = start = GET_64BIT(ranges, 1);
525 region.end = region.start + size - 1;
526
527 if (ofpci_verbose)
528 pci_info(dev, " Using flags[%08x] start[%016llx] size[%016llx]\n",
529 flags, start, size);
530
531 pcibios_bus_to_resource(dev->bus, res, ®ion);
532 }
533after_ranges:
534 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
535 bus->number);
536 if (ofpci_verbose)
537 pci_info(dev, " bus name: %s\n", bus->name);
538
539 pci_of_scan_bus(pbm, node, bus);
540}
541
542static void pci_of_scan_bus(struct pci_pbm_info *pbm,
543 struct device_node *node,
544 struct pci_bus *bus)
545{
546 struct device_node *child;
547 const u32 *reg;
548 int reglen, devfn, prev_devfn;
549 struct pci_dev *dev;
550
551 if (ofpci_verbose)
552 pci_info(bus, "scan_bus[%pOF] bus no %d\n",
553 node, bus->number);
554
555 prev_devfn = -1;
556 for_each_child_of_node(node, child) {
557 if (ofpci_verbose)
558 pci_info(bus, " * %pOF\n", child);
559 reg = of_get_property(child, "reg", ®len);
560 if (reg == NULL || reglen < 20)
561 continue;
562
563 devfn = (reg[0] >> 8) & 0xff;
564
565 /* This is a workaround for some device trees
566 * which list PCI devices twice. On the V100
567 * for example, device number 3 is listed twice.
568 * Once as "pm" and once again as "lomp".
569 */
570 if (devfn == prev_devfn)
571 continue;
572 prev_devfn = devfn;
573
574 /* create a new pci_dev for this device */
575 dev = of_create_pci_dev(pbm, child, bus, devfn);
576 if (!dev)
577 continue;
578 if (ofpci_verbose)
579 pci_info(dev, "dev header type: %x\n", dev->hdr_type);
580
581 if (pci_is_bridge(dev))
582 of_scan_pci_bridge(pbm, child, dev);
583 }
584}
585
586static ssize_t
587show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
588{
589 struct pci_dev *pdev;
590 struct device_node *dp;
591
592 pdev = to_pci_dev(dev);
593 dp = pdev->dev.of_node;
594
595 return scnprintf(buf, PAGE_SIZE, "%pOF\n", dp);
596}
597
598static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
599
600static void pci_bus_register_of_sysfs(struct pci_bus *bus)
601{
602 struct pci_dev *dev;
603 struct pci_bus *child_bus;
604 int err;
605
606 list_for_each_entry(dev, &bus->devices, bus_list) {
607 /* we don't really care if we can create this file or
608 * not, but we need to assign the result of the call
609 * or the world will fall under alien invasion and
610 * everybody will be frozen on a spaceship ready to be
611 * eaten on alpha centauri by some green and jelly
612 * humanoid.
613 */
614 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
615 (void) err;
616 }
617 list_for_each_entry(child_bus, &bus->children, node)
618 pci_bus_register_of_sysfs(child_bus);
619}
620
621static void pci_claim_legacy_resources(struct pci_dev *dev)
622{
623 struct pci_bus_region region;
624 struct resource *p, *root, *conflict;
625
626 if ((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)
627 return;
628
629 p = kzalloc(sizeof(*p), GFP_KERNEL);
630 if (!p)
631 return;
632
633 p->name = "Video RAM area";
634 p->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
635
636 region.start = 0xa0000UL;
637 region.end = region.start + 0x1ffffUL;
638 pcibios_bus_to_resource(dev->bus, p, ®ion);
639
640 root = pci_find_parent_resource(dev, p);
641 if (!root) {
642 pci_info(dev, "can't claim VGA legacy %pR: no compatible bridge window\n", p);
643 goto err;
644 }
645
646 conflict = request_resource_conflict(root, p);
647 if (conflict) {
648 pci_info(dev, "can't claim VGA legacy %pR: address conflict with %s %pR\n",
649 p, conflict->name, conflict);
650 goto err;
651 }
652
653 pci_info(dev, "VGA legacy framebuffer %pR\n", p);
654 return;
655
656err:
657 kfree(p);
658}
659
660static void pci_claim_bus_resources(struct pci_bus *bus)
661{
662 struct pci_bus *child_bus;
663 struct pci_dev *dev;
664
665 list_for_each_entry(dev, &bus->devices, bus_list) {
666 int i;
667
668 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
669 struct resource *r = &dev->resource[i];
670
671 if (r->parent || !r->start || !r->flags)
672 continue;
673
674 if (ofpci_verbose)
675 pci_info(dev, "Claiming Resource %d: %pR\n",
676 i, r);
677
678 pci_claim_resource(dev, i);
679 }
680
681 pci_claim_legacy_resources(dev);
682 }
683
684 list_for_each_entry(child_bus, &bus->children, node)
685 pci_claim_bus_resources(child_bus);
686}
687
688struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm,
689 struct device *parent)
690{
691 LIST_HEAD(resources);
692 struct device_node *node = pbm->op->dev.of_node;
693 struct pci_bus *bus;
694
695 printk("PCI: Scanning PBM %pOF\n", node);
696
697 pci_add_resource_offset(&resources, &pbm->io_space,
698 pbm->io_offset);
699 pci_add_resource_offset(&resources, &pbm->mem_space,
700 pbm->mem_offset);
701 if (pbm->mem64_space.flags)
702 pci_add_resource_offset(&resources, &pbm->mem64_space,
703 pbm->mem64_offset);
704 pbm->busn.start = pbm->pci_first_busno;
705 pbm->busn.end = pbm->pci_last_busno;
706 pbm->busn.flags = IORESOURCE_BUS;
707 pci_add_resource(&resources, &pbm->busn);
708 bus = pci_create_root_bus(parent, pbm->pci_first_busno, pbm->pci_ops,
709 pbm, &resources);
710 if (!bus) {
711 printk(KERN_ERR "Failed to create bus for %pOF\n", node);
712 pci_free_resource_list(&resources);
713 return NULL;
714 }
715
716 pci_of_scan_bus(pbm, node, bus);
717 pci_bus_register_of_sysfs(bus);
718
719 pci_claim_bus_resources(bus);
720
721 pci_bus_add_devices(bus);
722 return bus;
723}
724
725int pcibios_enable_device(struct pci_dev *dev, int mask)
726{
727 u16 cmd, oldcmd;
728 int i;
729
730 pci_read_config_word(dev, PCI_COMMAND, &cmd);
731 oldcmd = cmd;
732
733 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
734 struct resource *res = &dev->resource[i];
735
736 /* Only set up the requested stuff */
737 if (!(mask & (1<<i)))
738 continue;
739
740 if (res->flags & IORESOURCE_IO)
741 cmd |= PCI_COMMAND_IO;
742 if (res->flags & IORESOURCE_MEM)
743 cmd |= PCI_COMMAND_MEMORY;
744 }
745
746 if (cmd != oldcmd) {
747 pci_info(dev, "enabling device (%04x -> %04x)\n", oldcmd, cmd);
748 pci_write_config_word(dev, PCI_COMMAND, cmd);
749 }
750 return 0;
751}
752
753/* Platform support for /proc/bus/pci/X/Y mmap()s. */
754int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma)
755{
756 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
757 resource_size_t ioaddr = pci_resource_start(pdev, bar);
758
759 if (!pbm)
760 return -EINVAL;
761
762 vma->vm_pgoff += (ioaddr + pbm->io_space.start) >> PAGE_SHIFT;
763
764 return 0;
765}
766
767#ifdef CONFIG_NUMA
768int pcibus_to_node(struct pci_bus *pbus)
769{
770 struct pci_pbm_info *pbm = pbus->sysdata;
771
772 return pbm->numa_node;
773}
774EXPORT_SYMBOL(pcibus_to_node);
775#endif
776
777/* Return the domain number for this pci bus */
778
779int pci_domain_nr(struct pci_bus *pbus)
780{
781 struct pci_pbm_info *pbm = pbus->sysdata;
782 int ret;
783
784 if (!pbm) {
785 ret = -ENXIO;
786 } else {
787 ret = pbm->index;
788 }
789
790 return ret;
791}
792EXPORT_SYMBOL(pci_domain_nr);
793
794#ifdef CONFIG_PCI_MSI
795int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
796{
797 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
798 unsigned int irq;
799
800 if (!pbm->setup_msi_irq)
801 return -EINVAL;
802
803 return pbm->setup_msi_irq(&irq, pdev, desc);
804}
805
806void arch_teardown_msi_irq(unsigned int irq)
807{
808 struct msi_desc *entry = irq_get_msi_desc(irq);
809 struct pci_dev *pdev = msi_desc_to_pci_dev(entry);
810 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
811
812 if (pbm->teardown_msi_irq)
813 pbm->teardown_msi_irq(irq, pdev);
814}
815#endif /* !(CONFIG_PCI_MSI) */
816
817/* ALI sound chips generate 31-bits of DMA, a special register
818 * determines what bit 31 is emitted as.
819 */
820int ali_sound_dma_hack(struct device *dev, u64 device_mask)
821{
822 struct iommu *iommu = dev->archdata.iommu;
823 struct pci_dev *ali_isa_bridge;
824 u8 val;
825
826 if (!dev_is_pci(dev))
827 return 0;
828
829 if (to_pci_dev(dev)->vendor != PCI_VENDOR_ID_AL ||
830 to_pci_dev(dev)->device != PCI_DEVICE_ID_AL_M5451 ||
831 device_mask != 0x7fffffff)
832 return 0;
833
834 ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL,
835 PCI_DEVICE_ID_AL_M1533,
836 NULL);
837
838 pci_read_config_byte(ali_isa_bridge, 0x7e, &val);
839 if (iommu->dma_addr_mask & 0x80000000)
840 val |= 0x01;
841 else
842 val &= ~0x01;
843 pci_write_config_byte(ali_isa_bridge, 0x7e, val);
844 pci_dev_put(ali_isa_bridge);
845 return 1;
846}
847
848void pci_resource_to_user(const struct pci_dev *pdev, int bar,
849 const struct resource *rp, resource_size_t *start,
850 resource_size_t *end)
851{
852 struct pci_bus_region region;
853
854 /*
855 * "User" addresses are shown in /sys/devices/pci.../.../resource
856 * and /proc/bus/pci/devices and used as mmap offsets for
857 * /proc/bus/pci/BB/DD.F files (see proc_bus_pci_mmap()).
858 *
859 * On sparc, these are PCI bus addresses, i.e., raw BAR values.
860 */
861 pcibios_resource_to_bus(pdev->bus, ®ion, (struct resource *) rp);
862 *start = region.start;
863 *end = region.end;
864}
865
866void pcibios_set_master(struct pci_dev *dev)
867{
868 /* No special bus mastering setup handling */
869}
870
871#ifdef CONFIG_PCI_IOV
872int pcibios_device_add(struct pci_dev *dev)
873{
874 struct pci_dev *pdev;
875
876 /* Add sriov arch specific initialization here.
877 * Copy dev_archdata from PF to VF
878 */
879 if (dev->is_virtfn) {
880 struct dev_archdata *psd;
881
882 pdev = dev->physfn;
883 psd = &pdev->dev.archdata;
884 pci_init_dev_archdata(&dev->dev.archdata, psd->iommu,
885 psd->stc, psd->host_controller, NULL,
886 psd->numa_node);
887 }
888 return 0;
889}
890#endif /* CONFIG_PCI_IOV */
891
892static int __init pcibios_init(void)
893{
894 pci_dfl_cache_line_size = 64 >> 2;
895 return 0;
896}
897subsys_initcall(pcibios_init);
898
899#ifdef CONFIG_SYSFS
900
901#define SLOT_NAME_SIZE 11 /* Max decimal digits + null in u32 */
902
903static void pcie_bus_slot_names(struct pci_bus *pbus)
904{
905 struct pci_dev *pdev;
906 struct pci_bus *bus;
907
908 list_for_each_entry(pdev, &pbus->devices, bus_list) {
909 char name[SLOT_NAME_SIZE];
910 struct pci_slot *pci_slot;
911 const u32 *slot_num;
912 int len;
913
914 slot_num = of_get_property(pdev->dev.of_node,
915 "physical-slot#", &len);
916
917 if (slot_num == NULL || len != 4)
918 continue;
919
920 snprintf(name, sizeof(name), "%u", slot_num[0]);
921 pci_slot = pci_create_slot(pbus, slot_num[0], name, NULL);
922
923 if (IS_ERR(pci_slot))
924 pr_err("PCI: pci_create_slot returned %ld.\n",
925 PTR_ERR(pci_slot));
926 }
927
928 list_for_each_entry(bus, &pbus->children, node)
929 pcie_bus_slot_names(bus);
930}
931
932static void pci_bus_slot_names(struct device_node *node, struct pci_bus *bus)
933{
934 const struct pci_slot_names {
935 u32 slot_mask;
936 char names[0];
937 } *prop;
938 const char *sp;
939 int len, i;
940 u32 mask;
941
942 prop = of_get_property(node, "slot-names", &len);
943 if (!prop)
944 return;
945
946 mask = prop->slot_mask;
947 sp = prop->names;
948
949 if (ofpci_verbose)
950 pci_info(bus, "Making slots for [%pOF] mask[0x%02x]\n",
951 node, mask);
952
953 i = 0;
954 while (mask) {
955 struct pci_slot *pci_slot;
956 u32 this_bit = 1 << i;
957
958 if (!(mask & this_bit)) {
959 i++;
960 continue;
961 }
962
963 if (ofpci_verbose)
964 pci_info(bus, "Making slot [%s]\n", sp);
965
966 pci_slot = pci_create_slot(bus, i, sp, NULL);
967 if (IS_ERR(pci_slot))
968 pci_err(bus, "pci_create_slot returned %ld\n",
969 PTR_ERR(pci_slot));
970
971 sp += strlen(sp) + 1;
972 mask &= ~this_bit;
973 i++;
974 }
975}
976
977static int __init of_pci_slot_init(void)
978{
979 struct pci_bus *pbus = NULL;
980
981 while ((pbus = pci_find_next_bus(pbus)) != NULL) {
982 struct device_node *node;
983 struct pci_dev *pdev;
984
985 pdev = list_first_entry(&pbus->devices, struct pci_dev,
986 bus_list);
987
988 if (pdev && pci_is_pcie(pdev)) {
989 pcie_bus_slot_names(pbus);
990 } else {
991
992 if (pbus->self) {
993
994 /* PCI->PCI bridge */
995 node = pbus->self->dev.of_node;
996
997 } else {
998 struct pci_pbm_info *pbm = pbus->sysdata;
999
1000 /* Host PCI controller */
1001 node = pbm->op->dev.of_node;
1002 }
1003
1004 pci_bus_slot_names(node, pbus);
1005 }
1006 }
1007
1008 return 0;
1009}
1010device_initcall(of_pci_slot_init);
1011#endif
1// SPDX-License-Identifier: GPL-2.0
2/* pci.c: UltraSparc PCI controller support.
3 *
4 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
5 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
7 *
8 * OF tree based PCI bus probing taken from the PowerPC port
9 * with minor modifications, see there for credits.
10 */
11
12#include <linux/export.h>
13#include <linux/kernel.h>
14#include <linux/string.h>
15#include <linux/sched.h>
16#include <linux/capability.h>
17#include <linux/errno.h>
18#include <linux/pci.h>
19#include <linux/msi.h>
20#include <linux/irq.h>
21#include <linux/init.h>
22#include <linux/of.h>
23#include <linux/of_platform.h>
24#include <linux/pgtable.h>
25#include <linux/platform_device.h>
26
27#include <linux/uaccess.h>
28#include <asm/irq.h>
29#include <asm/prom.h>
30#include <asm/apb.h>
31
32#include "pci_impl.h"
33#include "kernel.h"
34
35/* List of all PCI controllers found in the system. */
36struct pci_pbm_info *pci_pbm_root = NULL;
37
38/* Each PBM found gets a unique index. */
39int pci_num_pbms = 0;
40
41volatile int pci_poke_in_progress;
42volatile int pci_poke_cpu = -1;
43volatile int pci_poke_faulted;
44
45static DEFINE_SPINLOCK(pci_poke_lock);
46
47void pci_config_read8(u8 *addr, u8 *ret)
48{
49 unsigned long flags;
50 u8 byte;
51
52 spin_lock_irqsave(&pci_poke_lock, flags);
53 pci_poke_cpu = smp_processor_id();
54 pci_poke_in_progress = 1;
55 pci_poke_faulted = 0;
56 __asm__ __volatile__("membar #Sync\n\t"
57 "lduba [%1] %2, %0\n\t"
58 "membar #Sync"
59 : "=r" (byte)
60 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
61 : "memory");
62 pci_poke_in_progress = 0;
63 pci_poke_cpu = -1;
64 if (!pci_poke_faulted)
65 *ret = byte;
66 spin_unlock_irqrestore(&pci_poke_lock, flags);
67}
68
69void pci_config_read16(u16 *addr, u16 *ret)
70{
71 unsigned long flags;
72 u16 word;
73
74 spin_lock_irqsave(&pci_poke_lock, flags);
75 pci_poke_cpu = smp_processor_id();
76 pci_poke_in_progress = 1;
77 pci_poke_faulted = 0;
78 __asm__ __volatile__("membar #Sync\n\t"
79 "lduha [%1] %2, %0\n\t"
80 "membar #Sync"
81 : "=r" (word)
82 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
83 : "memory");
84 pci_poke_in_progress = 0;
85 pci_poke_cpu = -1;
86 if (!pci_poke_faulted)
87 *ret = word;
88 spin_unlock_irqrestore(&pci_poke_lock, flags);
89}
90
91void pci_config_read32(u32 *addr, u32 *ret)
92{
93 unsigned long flags;
94 u32 dword;
95
96 spin_lock_irqsave(&pci_poke_lock, flags);
97 pci_poke_cpu = smp_processor_id();
98 pci_poke_in_progress = 1;
99 pci_poke_faulted = 0;
100 __asm__ __volatile__("membar #Sync\n\t"
101 "lduwa [%1] %2, %0\n\t"
102 "membar #Sync"
103 : "=r" (dword)
104 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
105 : "memory");
106 pci_poke_in_progress = 0;
107 pci_poke_cpu = -1;
108 if (!pci_poke_faulted)
109 *ret = dword;
110 spin_unlock_irqrestore(&pci_poke_lock, flags);
111}
112
113void pci_config_write8(u8 *addr, u8 val)
114{
115 unsigned long flags;
116
117 spin_lock_irqsave(&pci_poke_lock, flags);
118 pci_poke_cpu = smp_processor_id();
119 pci_poke_in_progress = 1;
120 pci_poke_faulted = 0;
121 __asm__ __volatile__("membar #Sync\n\t"
122 "stba %0, [%1] %2\n\t"
123 "membar #Sync"
124 : /* no outputs */
125 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
126 : "memory");
127 pci_poke_in_progress = 0;
128 pci_poke_cpu = -1;
129 spin_unlock_irqrestore(&pci_poke_lock, flags);
130}
131
132void pci_config_write16(u16 *addr, u16 val)
133{
134 unsigned long flags;
135
136 spin_lock_irqsave(&pci_poke_lock, flags);
137 pci_poke_cpu = smp_processor_id();
138 pci_poke_in_progress = 1;
139 pci_poke_faulted = 0;
140 __asm__ __volatile__("membar #Sync\n\t"
141 "stha %0, [%1] %2\n\t"
142 "membar #Sync"
143 : /* no outputs */
144 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
145 : "memory");
146 pci_poke_in_progress = 0;
147 pci_poke_cpu = -1;
148 spin_unlock_irqrestore(&pci_poke_lock, flags);
149}
150
151void pci_config_write32(u32 *addr, u32 val)
152{
153 unsigned long flags;
154
155 spin_lock_irqsave(&pci_poke_lock, flags);
156 pci_poke_cpu = smp_processor_id();
157 pci_poke_in_progress = 1;
158 pci_poke_faulted = 0;
159 __asm__ __volatile__("membar #Sync\n\t"
160 "stwa %0, [%1] %2\n\t"
161 "membar #Sync"
162 : /* no outputs */
163 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
164 : "memory");
165 pci_poke_in_progress = 0;
166 pci_poke_cpu = -1;
167 spin_unlock_irqrestore(&pci_poke_lock, flags);
168}
169
170static int ofpci_verbose;
171
172static int __init ofpci_debug(char *str)
173{
174 int val = 0;
175
176 get_option(&str, &val);
177 if (val)
178 ofpci_verbose = 1;
179 return 1;
180}
181
182__setup("ofpci_debug=", ofpci_debug);
183
184static unsigned long pci_parse_of_flags(u32 addr0)
185{
186 unsigned long flags = 0;
187
188 if (addr0 & 0x02000000) {
189 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
190 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
191 if (addr0 & 0x01000000)
192 flags |= IORESOURCE_MEM_64
193 | PCI_BASE_ADDRESS_MEM_TYPE_64;
194 if (addr0 & 0x40000000)
195 flags |= IORESOURCE_PREFETCH
196 | PCI_BASE_ADDRESS_MEM_PREFETCH;
197 } else if (addr0 & 0x01000000)
198 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
199 return flags;
200}
201
202/* The of_device layer has translated all of the assigned-address properties
203 * into physical address resources, we only have to figure out the register
204 * mapping.
205 */
206static void pci_parse_of_addrs(struct platform_device *op,
207 struct device_node *node,
208 struct pci_dev *dev)
209{
210 struct resource *op_res;
211 const u32 *addrs;
212 int proplen;
213
214 addrs = of_get_property(node, "assigned-addresses", &proplen);
215 if (!addrs)
216 return;
217 if (ofpci_verbose)
218 pci_info(dev, " parse addresses (%d bytes) @ %p\n",
219 proplen, addrs);
220 op_res = &op->resource[0];
221 for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
222 struct resource *res;
223 unsigned long flags;
224 int i;
225
226 flags = pci_parse_of_flags(addrs[0]);
227 if (!flags)
228 continue;
229 i = addrs[0] & 0xff;
230 if (ofpci_verbose)
231 pci_info(dev, " start: %llx, end: %llx, i: %x\n",
232 op_res->start, op_res->end, i);
233
234 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
235 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
236 } else if (i == dev->rom_base_reg) {
237 res = &dev->resource[PCI_ROM_RESOURCE];
238 flags |= IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
239 } else {
240 pci_err(dev, "bad cfg reg num 0x%x\n", i);
241 continue;
242 }
243 res->start = op_res->start;
244 res->end = op_res->end;
245 res->flags = flags;
246 res->name = pci_name(dev);
247
248 pci_info(dev, "reg 0x%x: %pR\n", i, res);
249 }
250}
251
252static void pci_init_dev_archdata(struct dev_archdata *sd, void *iommu,
253 void *stc, void *host_controller,
254 struct platform_device *op,
255 int numa_node)
256{
257 sd->iommu = iommu;
258 sd->stc = stc;
259 sd->host_controller = host_controller;
260 sd->op = op;
261 sd->numa_node = numa_node;
262}
263
264static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
265 struct device_node *node,
266 struct pci_bus *bus, int devfn)
267{
268 struct dev_archdata *sd;
269 struct platform_device *op;
270 struct pci_dev *dev;
271 u32 class;
272
273 dev = pci_alloc_dev(bus);
274 if (!dev)
275 return NULL;
276
277 op = of_find_device_by_node(node);
278 sd = &dev->dev.archdata;
279 pci_init_dev_archdata(sd, pbm->iommu, &pbm->stc, pbm, op,
280 pbm->numa_node);
281 sd = &op->dev.archdata;
282 sd->iommu = pbm->iommu;
283 sd->stc = &pbm->stc;
284 sd->numa_node = pbm->numa_node;
285
286 if (of_node_name_eq(node, "ebus"))
287 of_propagate_archdata(op);
288
289 if (ofpci_verbose)
290 pci_info(bus," create device, devfn: %x, type: %s\n",
291 devfn, of_node_get_device_type(node));
292
293 dev->sysdata = node;
294 dev->dev.parent = bus->bridge;
295 dev->dev.bus = &pci_bus_type;
296 dev->dev.of_node = of_node_get(node);
297 dev->devfn = devfn;
298 dev->multifunction = 0; /* maybe a lie? */
299 set_pcie_port_type(dev);
300
301 pci_dev_assign_slot(dev);
302 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
303 dev->device = of_getintprop_default(node, "device-id", 0xffff);
304 dev->subsystem_vendor =
305 of_getintprop_default(node, "subsystem-vendor-id", 0);
306 dev->subsystem_device =
307 of_getintprop_default(node, "subsystem-id", 0);
308
309 dev->cfg_size = pci_cfg_space_size(dev);
310
311 /* We can't actually use the firmware value, we have
312 * to read what is in the register right now. One
313 * reason is that in the case of IDE interfaces the
314 * firmware can sample the value before the IDE
315 * interface is programmed into native mode.
316 */
317 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
318 dev->class = class >> 8;
319 dev->revision = class & 0xff;
320
321 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
322 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
323
324 /* I have seen IDE devices which will not respond to
325 * the bmdma simplex check reads if bus mastering is
326 * disabled.
327 */
328 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
329 pci_set_master(dev);
330
331 dev->current_state = PCI_UNKNOWN; /* unknown power state */
332 dev->error_state = pci_channel_io_normal;
333 dev->dma_mask = 0xffffffff;
334
335 if (of_node_name_eq(node, "pci")) {
336 /* a PCI-PCI bridge */
337 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
338 dev->rom_base_reg = PCI_ROM_ADDRESS1;
339 } else if (of_node_is_type(node, "cardbus")) {
340 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
341 } else {
342 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
343 dev->rom_base_reg = PCI_ROM_ADDRESS;
344
345 dev->irq = sd->op->archdata.irqs[0];
346 if (dev->irq == 0xffffffff)
347 dev->irq = PCI_IRQ_NONE;
348 }
349
350 pci_info(dev, "[%04x:%04x] type %02x class %#08x\n",
351 dev->vendor, dev->device, dev->hdr_type, dev->class);
352
353 pci_parse_of_addrs(sd->op, node, dev);
354
355 if (ofpci_verbose)
356 pci_info(dev, " adding to system ...\n");
357
358 pci_device_add(dev, bus);
359
360 return dev;
361}
362
363static void apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
364{
365 u32 idx, first, last;
366
367 first = 8;
368 last = 0;
369 for (idx = 0; idx < 8; idx++) {
370 if ((map & (1 << idx)) != 0) {
371 if (first > idx)
372 first = idx;
373 if (last < idx)
374 last = idx;
375 }
376 }
377
378 *first_p = first;
379 *last_p = last;
380}
381
382/* Cook up fake bus resources for SUNW,simba PCI bridges which lack
383 * a proper 'ranges' property.
384 */
385static void apb_fake_ranges(struct pci_dev *dev,
386 struct pci_bus *bus,
387 struct pci_pbm_info *pbm)
388{
389 struct pci_bus_region region;
390 struct resource *res;
391 u32 first, last;
392 u8 map;
393
394 pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
395 apb_calc_first_last(map, &first, &last);
396 res = bus->resource[0];
397 res->flags = IORESOURCE_IO;
398 region.start = (first << 21);
399 region.end = (last << 21) + ((1 << 21) - 1);
400 pcibios_bus_to_resource(dev->bus, res, ®ion);
401
402 pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
403 apb_calc_first_last(map, &first, &last);
404 res = bus->resource[1];
405 res->flags = IORESOURCE_MEM;
406 region.start = (first << 29);
407 region.end = (last << 29) + ((1 << 29) - 1);
408 pcibios_bus_to_resource(dev->bus, res, ®ion);
409}
410
411static void pci_of_scan_bus(struct pci_pbm_info *pbm,
412 struct device_node *node,
413 struct pci_bus *bus);
414
415#define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
416
417static void of_scan_pci_bridge(struct pci_pbm_info *pbm,
418 struct device_node *node,
419 struct pci_dev *dev)
420{
421 struct pci_bus *bus;
422 const u32 *busrange, *ranges;
423 int len, i, simba;
424 struct pci_bus_region region;
425 struct resource *res;
426 unsigned int flags;
427 u64 size;
428
429 if (ofpci_verbose)
430 pci_info(dev, "of_scan_pci_bridge(%pOF)\n", node);
431
432 /* parse bus-range property */
433 busrange = of_get_property(node, "bus-range", &len);
434 if (busrange == NULL || len != 8) {
435 pci_info(dev, "Can't get bus-range for PCI-PCI bridge %pOF\n",
436 node);
437 return;
438 }
439
440 if (ofpci_verbose)
441 pci_info(dev, " Bridge bus range [%u --> %u]\n",
442 busrange[0], busrange[1]);
443
444 ranges = of_get_property(node, "ranges", &len);
445 simba = 0;
446 if (ranges == NULL) {
447 const char *model = of_get_property(node, "model", NULL);
448 if (model && !strcmp(model, "SUNW,simba"))
449 simba = 1;
450 }
451
452 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
453 if (!bus) {
454 pci_err(dev, "Failed to create pci bus for %pOF\n",
455 node);
456 return;
457 }
458
459 bus->primary = dev->bus->number;
460 pci_bus_insert_busn_res(bus, busrange[0], busrange[1]);
461 bus->bridge_ctl = 0;
462
463 if (ofpci_verbose)
464 pci_info(dev, " Bridge ranges[%p] simba[%d]\n",
465 ranges, simba);
466
467 /* parse ranges property, or cook one up by hand for Simba */
468 /* PCI #address-cells == 3 and #size-cells == 2 always */
469 res = &dev->resource[PCI_BRIDGE_RESOURCES];
470 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
471 res->flags = 0;
472 bus->resource[i] = res;
473 ++res;
474 }
475 if (simba) {
476 apb_fake_ranges(dev, bus, pbm);
477 goto after_ranges;
478 } else if (ranges == NULL) {
479 pci_read_bridge_bases(bus);
480 goto after_ranges;
481 }
482 i = 1;
483 for (; len >= 32; len -= 32, ranges += 8) {
484 u64 start;
485
486 if (ofpci_verbose)
487 pci_info(dev, " RAW Range[%08x:%08x:%08x:%08x:%08x:%08x:"
488 "%08x:%08x]\n",
489 ranges[0], ranges[1], ranges[2], ranges[3],
490 ranges[4], ranges[5], ranges[6], ranges[7]);
491
492 flags = pci_parse_of_flags(ranges[0]);
493 size = GET_64BIT(ranges, 6);
494 if (flags == 0 || size == 0)
495 continue;
496
497 /* On PCI-Express systems, PCI bridges that have no devices downstream
498 * have a bogus size value where the first 32-bit cell is 0xffffffff.
499 * This results in a bogus range where start + size overflows.
500 *
501 * Just skip these otherwise the kernel will complain when the resource
502 * tries to be claimed.
503 */
504 if (size >> 32 == 0xffffffff)
505 continue;
506
507 if (flags & IORESOURCE_IO) {
508 res = bus->resource[0];
509 if (res->flags) {
510 pci_err(dev, "ignoring extra I/O range"
511 " for bridge %pOF\n", node);
512 continue;
513 }
514 } else {
515 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
516 pci_err(dev, "too many memory ranges"
517 " for bridge %pOF\n", node);
518 continue;
519 }
520 res = bus->resource[i];
521 ++i;
522 }
523
524 res->flags = flags;
525 region.start = start = GET_64BIT(ranges, 1);
526 region.end = region.start + size - 1;
527
528 if (ofpci_verbose)
529 pci_info(dev, " Using flags[%08x] start[%016llx] size[%016llx]\n",
530 flags, start, size);
531
532 pcibios_bus_to_resource(dev->bus, res, ®ion);
533 }
534after_ranges:
535 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
536 bus->number);
537 if (ofpci_verbose)
538 pci_info(dev, " bus name: %s\n", bus->name);
539
540 pci_of_scan_bus(pbm, node, bus);
541}
542
543static void pci_of_scan_bus(struct pci_pbm_info *pbm,
544 struct device_node *node,
545 struct pci_bus *bus)
546{
547 struct device_node *child;
548 const u32 *reg;
549 int reglen, devfn, prev_devfn;
550 struct pci_dev *dev;
551
552 if (ofpci_verbose)
553 pci_info(bus, "scan_bus[%pOF] bus no %d\n",
554 node, bus->number);
555
556 prev_devfn = -1;
557 for_each_child_of_node(node, child) {
558 if (ofpci_verbose)
559 pci_info(bus, " * %pOF\n", child);
560 reg = of_get_property(child, "reg", ®len);
561 if (reg == NULL || reglen < 20)
562 continue;
563
564 devfn = (reg[0] >> 8) & 0xff;
565
566 /* This is a workaround for some device trees
567 * which list PCI devices twice. On the V100
568 * for example, device number 3 is listed twice.
569 * Once as "pm" and once again as "lomp".
570 */
571 if (devfn == prev_devfn)
572 continue;
573 prev_devfn = devfn;
574
575 /* create a new pci_dev for this device */
576 dev = of_create_pci_dev(pbm, child, bus, devfn);
577 if (!dev)
578 continue;
579 if (ofpci_verbose)
580 pci_info(dev, "dev header type: %x\n", dev->hdr_type);
581
582 if (pci_is_bridge(dev))
583 of_scan_pci_bridge(pbm, child, dev);
584 }
585}
586
587static ssize_t
588show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
589{
590 struct pci_dev *pdev;
591 struct device_node *dp;
592
593 pdev = to_pci_dev(dev);
594 dp = pdev->dev.of_node;
595
596 return scnprintf(buf, PAGE_SIZE, "%pOF\n", dp);
597}
598
599static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
600
601static void pci_bus_register_of_sysfs(struct pci_bus *bus)
602{
603 struct pci_dev *dev;
604 struct pci_bus *child_bus;
605 int err;
606
607 list_for_each_entry(dev, &bus->devices, bus_list) {
608 /* we don't really care if we can create this file or
609 * not, but we need to assign the result of the call
610 * or the world will fall under alien invasion and
611 * everybody will be frozen on a spaceship ready to be
612 * eaten on alpha centauri by some green and jelly
613 * humanoid.
614 */
615 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
616 (void) err;
617 }
618 list_for_each_entry(child_bus, &bus->children, node)
619 pci_bus_register_of_sysfs(child_bus);
620}
621
622static void pci_claim_legacy_resources(struct pci_dev *dev)
623{
624 struct pci_bus_region region;
625 struct resource *p, *root, *conflict;
626
627 if ((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)
628 return;
629
630 p = kzalloc(sizeof(*p), GFP_KERNEL);
631 if (!p)
632 return;
633
634 p->name = "Video RAM area";
635 p->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
636
637 region.start = 0xa0000UL;
638 region.end = region.start + 0x1ffffUL;
639 pcibios_bus_to_resource(dev->bus, p, ®ion);
640
641 root = pci_find_parent_resource(dev, p);
642 if (!root) {
643 pci_info(dev, "can't claim VGA legacy %pR: no compatible bridge window\n", p);
644 goto err;
645 }
646
647 conflict = request_resource_conflict(root, p);
648 if (conflict) {
649 pci_info(dev, "can't claim VGA legacy %pR: address conflict with %s %pR\n",
650 p, conflict->name, conflict);
651 goto err;
652 }
653
654 pci_info(dev, "VGA legacy framebuffer %pR\n", p);
655 return;
656
657err:
658 kfree(p);
659}
660
661static void pci_claim_bus_resources(struct pci_bus *bus)
662{
663 struct pci_bus *child_bus;
664 struct pci_dev *dev;
665
666 list_for_each_entry(dev, &bus->devices, bus_list) {
667 struct resource *r;
668 int i;
669
670 pci_dev_for_each_resource(dev, r, i) {
671 if (r->parent || !r->start || !r->flags)
672 continue;
673
674 if (ofpci_verbose)
675 pci_info(dev, "Claiming Resource %d: %pR\n",
676 i, r);
677
678 pci_claim_resource(dev, i);
679 }
680
681 pci_claim_legacy_resources(dev);
682 }
683
684 list_for_each_entry(child_bus, &bus->children, node)
685 pci_claim_bus_resources(child_bus);
686}
687
688struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm,
689 struct device *parent)
690{
691 LIST_HEAD(resources);
692 struct device_node *node = pbm->op->dev.of_node;
693 struct pci_bus *bus;
694
695 printk("PCI: Scanning PBM %pOF\n", node);
696
697 pci_add_resource_offset(&resources, &pbm->io_space,
698 pbm->io_offset);
699 pci_add_resource_offset(&resources, &pbm->mem_space,
700 pbm->mem_offset);
701 if (pbm->mem64_space.flags)
702 pci_add_resource_offset(&resources, &pbm->mem64_space,
703 pbm->mem64_offset);
704 pbm->busn.start = pbm->pci_first_busno;
705 pbm->busn.end = pbm->pci_last_busno;
706 pbm->busn.flags = IORESOURCE_BUS;
707 pci_add_resource(&resources, &pbm->busn);
708 bus = pci_create_root_bus(parent, pbm->pci_first_busno, pbm->pci_ops,
709 pbm, &resources);
710 if (!bus) {
711 printk(KERN_ERR "Failed to create bus for %pOF\n", node);
712 pci_free_resource_list(&resources);
713 return NULL;
714 }
715
716 pci_of_scan_bus(pbm, node, bus);
717 pci_bus_register_of_sysfs(bus);
718
719 pci_claim_bus_resources(bus);
720
721 pci_bus_add_devices(bus);
722 return bus;
723}
724
725int pcibios_enable_device(struct pci_dev *dev, int mask)
726{
727 struct resource *res;
728 u16 cmd, oldcmd;
729 int i;
730
731 pci_read_config_word(dev, PCI_COMMAND, &cmd);
732 oldcmd = cmd;
733
734 pci_dev_for_each_resource(dev, res, i) {
735 /* Only set up the requested stuff */
736 if (!(mask & (1<<i)))
737 continue;
738
739 if (res->flags & IORESOURCE_IO)
740 cmd |= PCI_COMMAND_IO;
741 if (res->flags & IORESOURCE_MEM)
742 cmd |= PCI_COMMAND_MEMORY;
743 }
744
745 if (cmd != oldcmd) {
746 pci_info(dev, "enabling device (%04x -> %04x)\n", oldcmd, cmd);
747 pci_write_config_word(dev, PCI_COMMAND, cmd);
748 }
749 return 0;
750}
751
752/* Platform support for /proc/bus/pci/X/Y mmap()s. */
753int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma)
754{
755 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
756 resource_size_t ioaddr = pci_resource_start(pdev, bar);
757
758 if (!pbm)
759 return -EINVAL;
760
761 vma->vm_pgoff += (ioaddr + pbm->io_space.start) >> PAGE_SHIFT;
762
763 return 0;
764}
765
766#ifdef CONFIG_NUMA
767int pcibus_to_node(struct pci_bus *pbus)
768{
769 struct pci_pbm_info *pbm = pbus->sysdata;
770
771 return pbm->numa_node;
772}
773EXPORT_SYMBOL(pcibus_to_node);
774#endif
775
776/* Return the domain number for this pci bus */
777
778int pci_domain_nr(struct pci_bus *pbus)
779{
780 struct pci_pbm_info *pbm = pbus->sysdata;
781 int ret;
782
783 if (!pbm) {
784 ret = -ENXIO;
785 } else {
786 ret = pbm->index;
787 }
788
789 return ret;
790}
791EXPORT_SYMBOL(pci_domain_nr);
792
793#ifdef CONFIG_PCI_MSI
794int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
795{
796 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
797 unsigned int irq;
798
799 if (!pbm->setup_msi_irq)
800 return -EINVAL;
801
802 return pbm->setup_msi_irq(&irq, pdev, desc);
803}
804
805void arch_teardown_msi_irq(unsigned int irq)
806{
807 struct msi_desc *entry = irq_get_msi_desc(irq);
808 struct pci_dev *pdev = msi_desc_to_pci_dev(entry);
809 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
810
811 if (pbm->teardown_msi_irq)
812 pbm->teardown_msi_irq(irq, pdev);
813}
814#endif /* !(CONFIG_PCI_MSI) */
815
816/* ALI sound chips generate 31-bits of DMA, a special register
817 * determines what bit 31 is emitted as.
818 */
819int ali_sound_dma_hack(struct device *dev, u64 device_mask)
820{
821 struct iommu *iommu = dev->archdata.iommu;
822 struct pci_dev *ali_isa_bridge;
823 u8 val;
824
825 if (!dev_is_pci(dev))
826 return 0;
827
828 if (to_pci_dev(dev)->vendor != PCI_VENDOR_ID_AL ||
829 to_pci_dev(dev)->device != PCI_DEVICE_ID_AL_M5451 ||
830 device_mask != 0x7fffffff)
831 return 0;
832
833 ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL,
834 PCI_DEVICE_ID_AL_M1533,
835 NULL);
836
837 pci_read_config_byte(ali_isa_bridge, 0x7e, &val);
838 if (iommu->dma_addr_mask & 0x80000000)
839 val |= 0x01;
840 else
841 val &= ~0x01;
842 pci_write_config_byte(ali_isa_bridge, 0x7e, val);
843 pci_dev_put(ali_isa_bridge);
844 return 1;
845}
846
847void pci_resource_to_user(const struct pci_dev *pdev, int bar,
848 const struct resource *rp, resource_size_t *start,
849 resource_size_t *end)
850{
851 struct pci_bus_region region;
852
853 /*
854 * "User" addresses are shown in /sys/devices/pci.../.../resource
855 * and /proc/bus/pci/devices and used as mmap offsets for
856 * /proc/bus/pci/BB/DD.F files (see proc_bus_pci_mmap()).
857 *
858 * On sparc, these are PCI bus addresses, i.e., raw BAR values.
859 */
860 pcibios_resource_to_bus(pdev->bus, ®ion, (struct resource *) rp);
861 *start = region.start;
862 *end = region.end;
863}
864
865void pcibios_set_master(struct pci_dev *dev)
866{
867 /* No special bus mastering setup handling */
868}
869
870#ifdef CONFIG_PCI_IOV
871int pcibios_device_add(struct pci_dev *dev)
872{
873 struct pci_dev *pdev;
874
875 /* Add sriov arch specific initialization here.
876 * Copy dev_archdata from PF to VF
877 */
878 if (dev->is_virtfn) {
879 struct dev_archdata *psd;
880
881 pdev = dev->physfn;
882 psd = &pdev->dev.archdata;
883 pci_init_dev_archdata(&dev->dev.archdata, psd->iommu,
884 psd->stc, psd->host_controller, NULL,
885 psd->numa_node);
886 }
887 return 0;
888}
889#endif /* CONFIG_PCI_IOV */
890
891static int __init pcibios_init(void)
892{
893 pci_dfl_cache_line_size = 64 >> 2;
894 return 0;
895}
896subsys_initcall(pcibios_init);
897
898#ifdef CONFIG_SYSFS
899
900#define SLOT_NAME_SIZE 11 /* Max decimal digits + null in u32 */
901
902static void pcie_bus_slot_names(struct pci_bus *pbus)
903{
904 struct pci_dev *pdev;
905 struct pci_bus *bus;
906
907 list_for_each_entry(pdev, &pbus->devices, bus_list) {
908 char name[SLOT_NAME_SIZE];
909 struct pci_slot *pci_slot;
910 const u32 *slot_num;
911 int len;
912
913 slot_num = of_get_property(pdev->dev.of_node,
914 "physical-slot#", &len);
915
916 if (slot_num == NULL || len != 4)
917 continue;
918
919 snprintf(name, sizeof(name), "%u", slot_num[0]);
920 pci_slot = pci_create_slot(pbus, slot_num[0], name, NULL);
921
922 if (IS_ERR(pci_slot))
923 pr_err("PCI: pci_create_slot returned %ld.\n",
924 PTR_ERR(pci_slot));
925 }
926
927 list_for_each_entry(bus, &pbus->children, node)
928 pcie_bus_slot_names(bus);
929}
930
931static void pci_bus_slot_names(struct device_node *node, struct pci_bus *bus)
932{
933 const struct pci_slot_names {
934 u32 slot_mask;
935 char names[0];
936 } *prop;
937 const char *sp;
938 int len, i;
939 u32 mask;
940
941 prop = of_get_property(node, "slot-names", &len);
942 if (!prop)
943 return;
944
945 mask = prop->slot_mask;
946 sp = prop->names;
947
948 if (ofpci_verbose)
949 pci_info(bus, "Making slots for [%pOF] mask[0x%02x]\n",
950 node, mask);
951
952 i = 0;
953 while (mask) {
954 struct pci_slot *pci_slot;
955 u32 this_bit = 1 << i;
956
957 if (!(mask & this_bit)) {
958 i++;
959 continue;
960 }
961
962 if (ofpci_verbose)
963 pci_info(bus, "Making slot [%s]\n", sp);
964
965 pci_slot = pci_create_slot(bus, i, sp, NULL);
966 if (IS_ERR(pci_slot))
967 pci_err(bus, "pci_create_slot returned %ld\n",
968 PTR_ERR(pci_slot));
969
970 sp += strlen(sp) + 1;
971 mask &= ~this_bit;
972 i++;
973 }
974}
975
976static int __init of_pci_slot_init(void)
977{
978 struct pci_bus *pbus = NULL;
979
980 while ((pbus = pci_find_next_bus(pbus)) != NULL) {
981 struct device_node *node;
982 struct pci_dev *pdev;
983
984 pdev = list_first_entry(&pbus->devices, struct pci_dev,
985 bus_list);
986
987 if (pdev && pci_is_pcie(pdev)) {
988 pcie_bus_slot_names(pbus);
989 } else {
990
991 if (pbus->self) {
992
993 /* PCI->PCI bridge */
994 node = pbus->self->dev.of_node;
995
996 } else {
997 struct pci_pbm_info *pbm = pbus->sysdata;
998
999 /* Host PCI controller */
1000 node = pbm->op->dev.of_node;
1001 }
1002
1003 pci_bus_slot_names(node, pbus);
1004 }
1005 }
1006
1007 return 0;
1008}
1009device_initcall(of_pci_slot_init);
1010#endif