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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ARM Ltd. Versatile Express
4 *
5 * CoreTile Express A15x2 (version with Test Chip 1)
6 * Cortex-A15 MPCore (V2P-CA15)
7 *
8 * HBI-0237A
9 */
10
11/dts-v1/;
12#include "vexpress-v2m-rs1.dtsi"
13
14/ {
15 model = "V2P-CA15";
16 arm,hbi = <0x237>;
17 arm,vexpress,site = <0xf>;
18 compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
22
23 chosen { };
24
25 aliases {
26 serial0 = &v2m_serial0;
27 serial1 = &v2m_serial1;
28 serial2 = &v2m_serial2;
29 serial3 = &v2m_serial3;
30 i2c0 = &v2m_i2c_dvi;
31 i2c1 = &v2m_i2c_pcie;
32 };
33
34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 cpu@0 {
39 device_type = "cpu";
40 compatible = "arm,cortex-a15";
41 reg = <0>;
42 };
43
44 cpu@1 {
45 device_type = "cpu";
46 compatible = "arm,cortex-a15";
47 reg = <1>;
48 };
49 };
50
51 memory@80000000 {
52 device_type = "memory";
53 reg = <0 0x80000000 0 0x40000000>;
54 };
55
56 reserved-memory {
57 #address-cells = <2>;
58 #size-cells = <2>;
59 ranges;
60
61 /* Chipselect 2 is physically at 0x18000000 */
62 vram: vram@18000000 {
63 /* 8 MB of designated video RAM */
64 compatible = "shared-dma-pool";
65 reg = <0 0x18000000 0 0x00800000>;
66 no-map;
67 };
68 };
69
70 hdlcd@2b000000 {
71 compatible = "arm,hdlcd";
72 reg = <0 0x2b000000 0 0x1000>;
73 interrupts = <0 85 4>;
74 clocks = <&hdlcd_clk>;
75 clock-names = "pxlclk";
76 };
77
78 memory-controller@2b0a0000 {
79 compatible = "arm,pl341", "arm,primecell";
80 reg = <0 0x2b0a0000 0 0x1000>;
81 clocks = <&sys_pll>;
82 clock-names = "apb_pclk";
83 };
84
85 wdt@2b060000 {
86 compatible = "arm,sp805", "arm,primecell";
87 status = "disabled";
88 reg = <0 0x2b060000 0 0x1000>;
89 interrupts = <0 98 4>;
90 clocks = <&sys_pll>, <&sys_pll>;
91 clock-names = "wdog_clk", "apb_pclk";
92 };
93
94 gic: interrupt-controller@2c001000 {
95 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
96 #interrupt-cells = <3>;
97 #address-cells = <0>;
98 interrupt-controller;
99 reg = <0 0x2c001000 0 0x1000>,
100 <0 0x2c002000 0 0x2000>,
101 <0 0x2c004000 0 0x2000>,
102 <0 0x2c006000 0 0x2000>;
103 interrupts = <1 9 0xf04>;
104 };
105
106 memory-controller@7ffd0000 {
107 compatible = "arm,pl354", "arm,primecell";
108 reg = <0 0x7ffd0000 0 0x1000>;
109 interrupts = <0 86 4>,
110 <0 87 4>;
111 clocks = <&sys_pll>;
112 clock-names = "apb_pclk";
113 };
114
115 dma@7ffb0000 {
116 compatible = "arm,pl330", "arm,primecell";
117 reg = <0 0x7ffb0000 0 0x1000>;
118 interrupts = <0 92 4>,
119 <0 88 4>,
120 <0 89 4>,
121 <0 90 4>,
122 <0 91 4>;
123 clocks = <&sys_pll>;
124 clock-names = "apb_pclk";
125 };
126
127 timer {
128 compatible = "arm,armv7-timer";
129 interrupts = <1 13 0xf08>,
130 <1 14 0xf08>,
131 <1 11 0xf08>,
132 <1 10 0xf08>;
133 };
134
135 pmu {
136 compatible = "arm,cortex-a15-pmu";
137 interrupts = <0 68 4>,
138 <0 69 4>;
139 };
140
141 dcc {
142 compatible = "arm,vexpress,config-bus";
143 arm,vexpress,config-bridge = <&v2m_sysreg>;
144
145 oscclk0 {
146 /* CPU PLL reference clock */
147 compatible = "arm,vexpress-osc";
148 arm,vexpress-sysreg,func = <1 0>;
149 freq-range = <50000000 60000000>;
150 #clock-cells = <0>;
151 clock-output-names = "oscclk0";
152 };
153
154 oscclk4 {
155 /* Multiplexed AXI master clock */
156 compatible = "arm,vexpress-osc";
157 arm,vexpress-sysreg,func = <1 4>;
158 freq-range = <20000000 40000000>;
159 #clock-cells = <0>;
160 clock-output-names = "oscclk4";
161 };
162
163 hdlcd_clk: oscclk5 {
164 /* HDLCD PLL reference clock */
165 compatible = "arm,vexpress-osc";
166 arm,vexpress-sysreg,func = <1 5>;
167 freq-range = <23750000 165000000>;
168 #clock-cells = <0>;
169 clock-output-names = "oscclk5";
170 };
171
172 smbclk: oscclk6 {
173 /* SMB clock */
174 compatible = "arm,vexpress-osc";
175 arm,vexpress-sysreg,func = <1 6>;
176 freq-range = <20000000 50000000>;
177 #clock-cells = <0>;
178 clock-output-names = "oscclk6";
179 };
180
181 sys_pll: oscclk7 {
182 /* SYS PLL reference clock */
183 compatible = "arm,vexpress-osc";
184 arm,vexpress-sysreg,func = <1 7>;
185 freq-range = <20000000 60000000>;
186 #clock-cells = <0>;
187 clock-output-names = "oscclk7";
188 };
189
190 oscclk8 {
191 /* DDR2 PLL reference clock */
192 compatible = "arm,vexpress-osc";
193 arm,vexpress-sysreg,func = <1 8>;
194 freq-range = <40000000 40000000>;
195 #clock-cells = <0>;
196 clock-output-names = "oscclk8";
197 };
198
199 volt-cores {
200 /* CPU core voltage */
201 compatible = "arm,vexpress-volt";
202 arm,vexpress-sysreg,func = <2 0>;
203 regulator-name = "Cores";
204 regulator-min-microvolt = <800000>;
205 regulator-max-microvolt = <1050000>;
206 regulator-always-on;
207 label = "Cores";
208 };
209
210 amp-cores {
211 /* Total current for the two cores */
212 compatible = "arm,vexpress-amp";
213 arm,vexpress-sysreg,func = <3 0>;
214 label = "Cores";
215 };
216
217 temp-dcc {
218 /* DCC internal temperature */
219 compatible = "arm,vexpress-temp";
220 arm,vexpress-sysreg,func = <4 0>;
221 label = "DCC";
222 };
223
224 power-cores {
225 /* Total power */
226 compatible = "arm,vexpress-power";
227 arm,vexpress-sysreg,func = <12 0>;
228 label = "Cores";
229 };
230
231 energy {
232 /* Total energy */
233 compatible = "arm,vexpress-energy";
234 arm,vexpress-sysreg,func = <13 0>;
235 label = "Cores";
236 };
237 };
238
239 bus@8000000 {
240 ranges = <0x8000000 0 0x8000000 0x18000000>;
241 };
242
243 site2: hsb@40000000 {
244 compatible = "simple-bus";
245 #address-cells = <1>;
246 #size-cells = <1>;
247 ranges = <0 0 0x40000000 0x3fef0000>;
248 #interrupt-cells = <1>;
249 interrupt-map-mask = <0 3>;
250 interrupt-map = <0 0 &gic 0 36 4>,
251 <0 1 &gic 0 37 4>,
252 <0 2 &gic 0 38 4>,
253 <0 3 &gic 0 39 4>;
254 };
255};