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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r7s72100 SoC
4 *
5 * Copyright (C) 2013-14 Renesas Solutions Corp.
6 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
7 */
8
9#include <dt-bindings/clock/r7s72100-clock.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12
13/ {
14 compatible = "renesas,r7s72100";
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 aliases {
19 i2c0 = &i2c0;
20 i2c1 = &i2c1;
21 i2c2 = &i2c2;
22 i2c3 = &i2c3;
23 spi0 = &spi0;
24 spi1 = &spi1;
25 spi2 = &spi2;
26 spi3 = &spi3;
27 spi4 = &spi4;
28 };
29
30 /* Fixed factor clocks */
31 b_clk: b {
32 #clock-cells = <0>;
33 compatible = "fixed-factor-clock";
34 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
35 clock-mult = <1>;
36 clock-div = <3>;
37 };
38
39 bsc: bus {
40 compatible = "simple-bus";
41 #address-cells = <1>;
42 #size-cells = <1>;
43 ranges = <0 0 0x18000000>;
44 };
45
46 cpus {
47 #address-cells = <1>;
48 #size-cells = <0>;
49
50 cpu@0 {
51 device_type = "cpu";
52 compatible = "arm,cortex-a9";
53 reg = <0>;
54 clock-frequency = <400000000>;
55 clocks = <&cpg_clocks R7S72100_CLK_I>;
56 next-level-cache = <&L2>;
57 };
58 };
59
60 /* External clocks */
61 extal_clk: extal {
62 #clock-cells = <0>;
63 compatible = "fixed-clock";
64 /* If clk present, value must be set by board */
65 clock-frequency = <0>;
66 };
67
68 p0_clk: p0 {
69 #clock-cells = <0>;
70 compatible = "fixed-factor-clock";
71 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
72 clock-mult = <1>;
73 clock-div = <12>;
74 };
75
76 p1_clk: p1 {
77 #clock-cells = <0>;
78 compatible = "fixed-factor-clock";
79 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
80 clock-mult = <1>;
81 clock-div = <6>;
82 };
83
84 pmu {
85 compatible = "arm,cortex-a9-pmu";
86 interrupts-extended = <&gic GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
87 };
88
89 rtc_x1_clk: rtc_x1 {
90 #clock-cells = <0>;
91 compatible = "fixed-clock";
92 /* If clk present, value must be set by board to 32678 */
93 clock-frequency = <0>;
94 };
95
96 rtc_x3_clk: rtc_x3 {
97 #clock-cells = <0>;
98 compatible = "fixed-clock";
99 /* If clk present, value must be set by board to 4000000 */
100 clock-frequency = <0>;
101 };
102
103 soc {
104 compatible = "simple-bus";
105 interrupt-parent = <&gic>;
106
107 #address-cells = <1>;
108 #size-cells = <1>;
109 ranges;
110
111 L2: cache-controller@3ffff000 {
112 compatible = "arm,pl310-cache";
113 reg = <0x3ffff000 0x1000>;
114 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
115 arm,early-bresp-disable;
116 arm,full-line-zero-disable;
117 cache-unified;
118 cache-level = <2>;
119 };
120
121 scif0: serial@e8007000 {
122 compatible = "renesas,scif-r7s72100", "renesas,scif";
123 reg = <0xe8007000 64>;
124 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
125 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
126 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
127 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
128 interrupt-names = "eri", "rxi", "txi", "bri";
129 clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
130 clock-names = "fck";
131 power-domains = <&cpg_clocks>;
132 status = "disabled";
133 };
134
135 scif1: serial@e8007800 {
136 compatible = "renesas,scif-r7s72100", "renesas,scif";
137 reg = <0xe8007800 64>;
138 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
139 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
140 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
141 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
142 interrupt-names = "eri", "rxi", "txi", "bri";
143 clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
144 clock-names = "fck";
145 power-domains = <&cpg_clocks>;
146 status = "disabled";
147 };
148
149 scif2: serial@e8008000 {
150 compatible = "renesas,scif-r7s72100", "renesas,scif";
151 reg = <0xe8008000 64>;
152 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
156 interrupt-names = "eri", "rxi", "txi", "bri";
157 clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
158 clock-names = "fck";
159 power-domains = <&cpg_clocks>;
160 status = "disabled";
161 };
162
163 scif3: serial@e8008800 {
164 compatible = "renesas,scif-r7s72100", "renesas,scif";
165 reg = <0xe8008800 64>;
166 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
168 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
169 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
170 interrupt-names = "eri", "rxi", "txi", "bri";
171 clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
172 clock-names = "fck";
173 power-domains = <&cpg_clocks>;
174 status = "disabled";
175 };
176
177 scif4: serial@e8009000 {
178 compatible = "renesas,scif-r7s72100", "renesas,scif";
179 reg = <0xe8009000 64>;
180 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
184 interrupt-names = "eri", "rxi", "txi", "bri";
185 clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
186 clock-names = "fck";
187 power-domains = <&cpg_clocks>;
188 status = "disabled";
189 };
190
191 scif5: serial@e8009800 {
192 compatible = "renesas,scif-r7s72100", "renesas,scif";
193 reg = <0xe8009800 64>;
194 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
198 interrupt-names = "eri", "rxi", "txi", "bri";
199 clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
200 clock-names = "fck";
201 power-domains = <&cpg_clocks>;
202 status = "disabled";
203 };
204
205 scif6: serial@e800a000 {
206 compatible = "renesas,scif-r7s72100", "renesas,scif";
207 reg = <0xe800a000 64>;
208 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
212 interrupt-names = "eri", "rxi", "txi", "bri";
213 clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
214 clock-names = "fck";
215 power-domains = <&cpg_clocks>;
216 status = "disabled";
217 };
218
219 scif7: serial@e800a800 {
220 compatible = "renesas,scif-r7s72100", "renesas,scif";
221 reg = <0xe800a800 64>;
222 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
225 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
226 interrupt-names = "eri", "rxi", "txi", "bri";
227 clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
228 clock-names = "fck";
229 power-domains = <&cpg_clocks>;
230 status = "disabled";
231 };
232
233 spi0: spi@e800c800 {
234 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
235 reg = <0xe800c800 0x24>;
236 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
239 interrupt-names = "error", "rx", "tx";
240 clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
241 power-domains = <&cpg_clocks>;
242 num-cs = <1>;
243 #address-cells = <1>;
244 #size-cells = <0>;
245 status = "disabled";
246 };
247
248 spi1: spi@e800d000 {
249 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
250 reg = <0xe800d000 0x24>;
251 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
254 interrupt-names = "error", "rx", "tx";
255 clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
256 power-domains = <&cpg_clocks>;
257 num-cs = <1>;
258 #address-cells = <1>;
259 #size-cells = <0>;
260 status = "disabled";
261 };
262
263 spi2: spi@e800d800 {
264 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
265 reg = <0xe800d800 0x24>;
266 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
268 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
269 interrupt-names = "error", "rx", "tx";
270 clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
271 power-domains = <&cpg_clocks>;
272 num-cs = <1>;
273 #address-cells = <1>;
274 #size-cells = <0>;
275 status = "disabled";
276 };
277
278 spi3: spi@e800e000 {
279 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
280 reg = <0xe800e000 0x24>;
281 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
284 interrupt-names = "error", "rx", "tx";
285 clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
286 power-domains = <&cpg_clocks>;
287 num-cs = <1>;
288 #address-cells = <1>;
289 #size-cells = <0>;
290 status = "disabled";
291 };
292
293 spi4: spi@e800e800 {
294 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
295 reg = <0xe800e800 0x24>;
296 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
299 interrupt-names = "error", "rx", "tx";
300 clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
301 power-domains = <&cpg_clocks>;
302 num-cs = <1>;
303 #address-cells = <1>;
304 #size-cells = <0>;
305 status = "disabled";
306 };
307
308 usbhs0: usb@e8010000 {
309 compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
310 reg = <0xe8010000 0x1a0>;
311 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
312 clocks = <&mstp7_clks R7S72100_CLK_USB0>;
313 renesas,buswait = <4>;
314 power-domains = <&cpg_clocks>;
315 status = "disabled";
316 };
317
318 usbhs1: usb@e8207000 {
319 compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
320 reg = <0xe8207000 0x1a0>;
321 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&mstp7_clks R7S72100_CLK_USB1>;
323 renesas,buswait = <4>;
324 power-domains = <&cpg_clocks>;
325 status = "disabled";
326 };
327
328 mmcif: mmc@e804c800 {
329 compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
330 reg = <0xe804c800 0x80>;
331 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
335 dmas = <&dmac 0x2cc9>, <&dmac 0x2cca>;
336 dma-names = "tx", "rx";
337 power-domains = <&cpg_clocks>;
338 status = "disabled";
339 };
340
341 sdhi0: mmc@e804e000 {
342 compatible = "renesas,sdhi-r7s72100";
343 reg = <0xe804e000 0x100>;
344 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
346 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
347
348 clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
349 <&mstp12_clks R7S72100_CLK_SDHI01>;
350 clock-names = "core", "cd";
351 power-domains = <&cpg_clocks>;
352 cap-sd-highspeed;
353 cap-sdio-irq;
354 status = "disabled";
355 };
356
357 sdhi1: mmc@e804e800 {
358 compatible = "renesas,sdhi-r7s72100";
359 reg = <0xe804e800 0x100>;
360 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
361 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
362 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
363
364 clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
365 <&mstp12_clks R7S72100_CLK_SDHI11>;
366 clock-names = "core", "cd";
367 power-domains = <&cpg_clocks>;
368 cap-sd-highspeed;
369 cap-sdio-irq;
370 status = "disabled";
371 };
372
373 dmac: dma-controller@e8200000 {
374 compatible = "renesas,r7s72100-dmac",
375 "renesas,rz-dmac";
376 reg = <0xe8200000 0x1000>,
377 <0xfcfe1000 0x20>;
378 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
379 <GIC_SPI 9 IRQ_TYPE_EDGE_RISING>,
380 <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>,
381 <GIC_SPI 11 IRQ_TYPE_EDGE_RISING>,
382 <GIC_SPI 12 IRQ_TYPE_EDGE_RISING>,
383 <GIC_SPI 13 IRQ_TYPE_EDGE_RISING>,
384 <GIC_SPI 14 IRQ_TYPE_EDGE_RISING>,
385 <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>,
386 <GIC_SPI 16 IRQ_TYPE_EDGE_RISING>,
387 <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>,
388 <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>,
389 <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
390 <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
391 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
392 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
393 <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>,
394 <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>;
395 interrupt-names = "error",
396 "ch0", "ch1", "ch2", "ch3",
397 "ch4", "ch5", "ch6", "ch7",
398 "ch8", "ch9", "ch10", "ch11",
399 "ch12", "ch13", "ch14", "ch15";
400 #dma-cells = <1>;
401 dma-channels = <16>;
402 };
403
404 gic: interrupt-controller@e8201000 {
405 compatible = "arm,pl390";
406 #interrupt-cells = <3>;
407 #address-cells = <0>;
408 interrupt-controller;
409 reg = <0xe8201000 0x1000>,
410 <0xe8202000 0x1000>;
411 };
412
413 ether: ethernet@e8203000 {
414 compatible = "renesas,ether-r7s72100";
415 reg = <0xe8203000 0x800>,
416 <0xe8204800 0x200>;
417 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
419 power-domains = <&cpg_clocks>;
420 phy-mode = "mii";
421 #address-cells = <1>;
422 #size-cells = <0>;
423 status = "disabled";
424 };
425
426 ceu: camera@e8210000 {
427 reg = <0xe8210000 0x3000>;
428 compatible = "renesas,r7s72100-ceu";
429 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&mstp6_clks R7S72100_CLK_CEU>;
431 power-domains = <&cpg_clocks>;
432 status = "disabled";
433 };
434
435 wdt: watchdog@fcfe0000 {
436 compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
437 reg = <0xfcfe0000 0x6>;
438 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
439 clocks = <&p0_clk>;
440 };
441
442 /* Special CPG clocks */
443 cpg_clocks: cpg_clocks@fcfe0000 {
444 #clock-cells = <1>;
445 compatible = "renesas,r7s72100-cpg-clocks",
446 "renesas,rz-cpg-clocks";
447 reg = <0xfcfe0000 0x18>;
448 clocks = <&extal_clk>, <&usb_x1_clk>;
449 clock-output-names = "pll", "i", "g";
450 #power-domain-cells = <0>;
451 };
452
453 /* MSTP clocks */
454 mstp3_clks: mstp3_clks@fcfe0420 {
455 #clock-cells = <1>;
456 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
457 reg = <0xfcfe0420 4>;
458 clocks = <&p0_clk>;
459 clock-indices = <R7S72100_CLK_MTU2>;
460 clock-output-names = "mtu2";
461 };
462
463 mstp4_clks: mstp4_clks@fcfe0424 {
464 #clock-cells = <1>;
465 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
466 reg = <0xfcfe0424 4>;
467 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
468 <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
469 clock-indices = <
470 R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3
471 R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7
472 >;
473 clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
474 };
475
476 mstp5_clks: mstp5_clks@fcfe0428 {
477 #clock-cells = <1>;
478 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
479 reg = <0xfcfe0428 4>;
480 clocks = <&p0_clk>, <&p0_clk>;
481 clock-indices = <R7S72100_CLK_OSTM0 R7S72100_CLK_OSTM1>;
482 clock-output-names = "ostm0", "ostm1";
483 };
484
485 mstp6_clks: mstp6_clks@fcfe042c {
486 #clock-cells = <1>;
487 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
488 reg = <0xfcfe042c 4>;
489 clocks = <&b_clk>, <&p0_clk>;
490 clock-indices = <R7S72100_CLK_CEU R7S72100_CLK_RTC>;
491 clock-output-names = "ceu", "rtc";
492 };
493
494 mstp7_clks: mstp7_clks@fcfe0430 {
495 #clock-cells = <1>;
496 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
497 reg = <0xfcfe0430 4>;
498 clocks = <&b_clk>, <&p1_clk>, <&p1_clk>;
499 clock-indices = <R7S72100_CLK_ETHER R7S72100_CLK_USB0 R7S72100_CLK_USB1>;
500 clock-output-names = "ether", "usb0", "usb1";
501 };
502
503 mstp8_clks: mstp8_clks@fcfe0434 {
504 #clock-cells = <1>;
505 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
506 reg = <0xfcfe0434 4>;
507 clocks = <&p1_clk>;
508 clock-indices = <R7S72100_CLK_MMCIF>;
509 clock-output-names = "mmcif";
510 };
511
512 mstp9_clks: mstp9_clks@fcfe0438 {
513 #clock-cells = <1>;
514 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
515 reg = <0xfcfe0438 4>;
516 clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>, <&b_clk>, <&b_clk>;
517 clock-indices = <
518 R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
519 R7S72100_CLK_SPIBSC0 R7S72100_CLK_SPIBSC1
520 >;
521 clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3", "spibsc0", "spibsc1";
522 };
523
524 mstp10_clks: mstp10_clks@fcfe043c {
525 #clock-cells = <1>;
526 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
527 reg = <0xfcfe043c 4>;
528 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
529 <&p1_clk>;
530 clock-indices = <
531 R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3
532 R7S72100_CLK_SPI4
533 >;
534 clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4";
535 };
536 mstp12_clks: mstp12_clks@fcfe0444 {
537 #clock-cells = <1>;
538 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
539 reg = <0xfcfe0444 4>;
540 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
541 clock-indices = <
542 R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01
543 R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11
544 >;
545 clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
546 };
547
548 pinctrl: pinctrl@fcfe3000 {
549 compatible = "renesas,r7s72100-ports";
550
551 reg = <0xfcfe3000 0x4230>;
552
553 port0: gpio-0 {
554 gpio-controller;
555 #gpio-cells = <2>;
556 gpio-ranges = <&pinctrl 0 0 6>;
557 };
558
559 port1: gpio-1 {
560 gpio-controller;
561 #gpio-cells = <2>;
562 gpio-ranges = <&pinctrl 0 16 16>;
563 };
564
565 port2: gpio-2 {
566 gpio-controller;
567 #gpio-cells = <2>;
568 gpio-ranges = <&pinctrl 0 32 16>;
569 };
570
571 port3: gpio-3 {
572 gpio-controller;
573 #gpio-cells = <2>;
574 gpio-ranges = <&pinctrl 0 48 16>;
575 };
576
577 port4: gpio-4 {
578 gpio-controller;
579 #gpio-cells = <2>;
580 gpio-ranges = <&pinctrl 0 64 16>;
581 };
582
583 port5: gpio-5 {
584 gpio-controller;
585 #gpio-cells = <2>;
586 gpio-ranges = <&pinctrl 0 80 11>;
587 };
588
589 port6: gpio-6 {
590 gpio-controller;
591 #gpio-cells = <2>;
592 gpio-ranges = <&pinctrl 0 96 16>;
593 };
594
595 port7: gpio-7 {
596 gpio-controller;
597 #gpio-cells = <2>;
598 gpio-ranges = <&pinctrl 0 112 16>;
599 };
600
601 port8: gpio-8 {
602 gpio-controller;
603 #gpio-cells = <2>;
604 gpio-ranges = <&pinctrl 0 128 16>;
605 };
606
607 port9: gpio-9 {
608 gpio-controller;
609 #gpio-cells = <2>;
610 gpio-ranges = <&pinctrl 0 144 8>;
611 };
612
613 port10: gpio-10 {
614 gpio-controller;
615 #gpio-cells = <2>;
616 gpio-ranges = <&pinctrl 0 160 16>;
617 };
618
619 port11: gpio-11 {
620 gpio-controller;
621 #gpio-cells = <2>;
622 gpio-ranges = <&pinctrl 0 176 16>;
623 };
624 };
625
626 ostm0: timer@fcfec000 {
627 compatible = "renesas,r7s72100-ostm", "renesas,ostm";
628 reg = <0xfcfec000 0x30>;
629 interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
630 clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
631 power-domains = <&cpg_clocks>;
632 status = "disabled";
633 };
634
635 ostm1: timer@fcfec400 {
636 compatible = "renesas,r7s72100-ostm", "renesas,ostm";
637 reg = <0xfcfec400 0x30>;
638 interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>;
639 clocks = <&mstp5_clks R7S72100_CLK_OSTM1>;
640 power-domains = <&cpg_clocks>;
641 status = "disabled";
642 };
643
644 i2c0: i2c@fcfee000 {
645 #address-cells = <1>;
646 #size-cells = <0>;
647 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
648 reg = <0xfcfee000 0x44>;
649 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
650 <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
651 <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
652 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
653 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
654 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
655 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
656 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
657 interrupt-names = "tei", "ri", "ti", "spi", "sti",
658 "naki", "ali", "tmoi";
659 clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
660 clock-frequency = <100000>;
661 power-domains = <&cpg_clocks>;
662 status = "disabled";
663 };
664
665 i2c1: i2c@fcfee400 {
666 #address-cells = <1>;
667 #size-cells = <0>;
668 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
669 reg = <0xfcfee400 0x44>;
670 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
671 <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
672 <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
673 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
674 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
675 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
676 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
677 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
678 interrupt-names = "tei", "ri", "ti", "spi", "sti",
679 "naki", "ali", "tmoi";
680 clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
681 clock-frequency = <100000>;
682 power-domains = <&cpg_clocks>;
683 status = "disabled";
684 };
685
686 i2c2: i2c@fcfee800 {
687 #address-cells = <1>;
688 #size-cells = <0>;
689 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
690 reg = <0xfcfee800 0x44>;
691 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
692 <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
693 <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
694 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
695 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
696 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
697 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
698 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
699 interrupt-names = "tei", "ri", "ti", "spi", "sti",
700 "naki", "ali", "tmoi";
701 clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
702 clock-frequency = <100000>;
703 power-domains = <&cpg_clocks>;
704 status = "disabled";
705 };
706
707 i2c3: i2c@fcfeec00 {
708 #address-cells = <1>;
709 #size-cells = <0>;
710 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
711 reg = <0xfcfeec00 0x44>;
712 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
713 <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
714 <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
715 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
716 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
717 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
718 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
719 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
720 interrupt-names = "tei", "ri", "ti", "spi", "sti",
721 "naki", "ali", "tmoi";
722 clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
723 clock-frequency = <100000>;
724 power-domains = <&cpg_clocks>;
725 status = "disabled";
726 };
727
728 irqc: interrupt-controller@fcfef800 {
729 compatible = "renesas,r7s72100-irqc",
730 "renesas,rza1-irqc";
731 #interrupt-cells = <2>;
732 #address-cells = <0>;
733 interrupt-controller;
734 reg = <0xfcfef800 0x6>;
735 interrupt-map =
736 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
737 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
738 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
739 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
740 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
741 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
742 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
743 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
744 interrupt-map-mask = <7 0>;
745 };
746
747 mtu2: timer@fcff0000 {
748 compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
749 reg = <0xfcff0000 0x400>;
750 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
751 interrupt-names = "tgi0a";
752 clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
753 clock-names = "fck";
754 power-domains = <&cpg_clocks>;
755 status = "disabled";
756 };
757
758 rtc: rtc@fcff1000 {
759 compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc";
760 reg = <0xfcff1000 0x2e>;
761 interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
762 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
763 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
764 interrupt-names = "alarm", "period", "carry";
765 clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>,
766 <&rtc_x3_clk>, <&extal_clk>;
767 clock-names = "fck", "rtc_x1", "rtc_x3", "extal";
768 power-domains = <&cpg_clocks>;
769 status = "disabled";
770 };
771 };
772
773 usb_x1_clk: usb_x1 {
774 #clock-cells = <0>;
775 compatible = "fixed-clock";
776 /* If clk present, value must be set by board */
777 clock-frequency = <0>;
778 };
779};