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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung Exynos5420 SoC device tree source
4 *
5 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 *
8 * Samsung Exynos5420 SoC device nodes are listed in this file.
9 * Exynos5420 based board files can include this file and provide
10 * values for board specfic bindings.
11 */
12
13#include "exynos54xx.dtsi"
14#include <dt-bindings/clock/exynos5420.h>
15#include <dt-bindings/clock/exynos-audss-clk.h>
16#include <dt-bindings/interrupt-controller/arm-gic.h>
17
18/ {
19 compatible = "samsung,exynos5420", "samsung,exynos5";
20
21 aliases {
22 mshc0 = &mmc_0;
23 mshc1 = &mmc_1;
24 mshc2 = &mmc_2;
25 pinctrl0 = &pinctrl_0;
26 pinctrl1 = &pinctrl_1;
27 pinctrl2 = &pinctrl_2;
28 pinctrl3 = &pinctrl_3;
29 pinctrl4 = &pinctrl_4;
30 i2c8 = &hsi2c_8;
31 i2c9 = &hsi2c_9;
32 i2c10 = &hsi2c_10;
33 gsc0 = &gsc_0;
34 gsc1 = &gsc_1;
35 spi0 = &spi_0;
36 spi1 = &spi_1;
37 spi2 = &spi_2;
38 };
39
40 /*
41 * The 'cpus' node is not present here but instead it is provided
42 * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
43 */
44
45 cluster_a15_opp_table: opp-table0 {
46 compatible = "operating-points-v2";
47 opp-shared;
48
49 opp-1800000000 {
50 opp-hz = /bits/ 64 <1800000000>;
51 opp-microvolt = <1250000 1250000 1500000>;
52 clock-latency-ns = <140000>;
53 };
54 opp-1700000000 {
55 opp-hz = /bits/ 64 <1700000000>;
56 opp-microvolt = <1212500 1212500 1500000>;
57 clock-latency-ns = <140000>;
58 };
59 opp-1600000000 {
60 opp-hz = /bits/ 64 <1600000000>;
61 opp-microvolt = <1175000 1175000 1500000>;
62 clock-latency-ns = <140000>;
63 };
64 opp-1500000000 {
65 opp-hz = /bits/ 64 <1500000000>;
66 opp-microvolt = <1137500 1137500 1500000>;
67 clock-latency-ns = <140000>;
68 };
69 opp-1400000000 {
70 opp-hz = /bits/ 64 <1400000000>;
71 opp-microvolt = <1112500 1112500 1500000>;
72 clock-latency-ns = <140000>;
73 };
74 opp-1300000000 {
75 opp-hz = /bits/ 64 <1300000000>;
76 opp-microvolt = <1062500 1062500 1500000>;
77 clock-latency-ns = <140000>;
78 };
79 opp-1200000000 {
80 opp-hz = /bits/ 64 <1200000000>;
81 opp-microvolt = <1037500 1037500 1500000>;
82 clock-latency-ns = <140000>;
83 };
84 opp-1100000000 {
85 opp-hz = /bits/ 64 <1100000000>;
86 opp-microvolt = <1012500 1012500 1500000>;
87 clock-latency-ns = <140000>;
88 };
89 opp-1000000000 {
90 opp-hz = /bits/ 64 <1000000000>;
91 opp-microvolt = < 987500 987500 1500000>;
92 clock-latency-ns = <140000>;
93 };
94 opp-900000000 {
95 opp-hz = /bits/ 64 <900000000>;
96 opp-microvolt = < 962500 962500 1500000>;
97 clock-latency-ns = <140000>;
98 };
99 opp-800000000 {
100 opp-hz = /bits/ 64 <800000000>;
101 opp-microvolt = < 937500 937500 1500000>;
102 clock-latency-ns = <140000>;
103 };
104 opp-700000000 {
105 opp-hz = /bits/ 64 <700000000>;
106 opp-microvolt = < 912500 912500 1500000>;
107 clock-latency-ns = <140000>;
108 };
109 };
110
111 cluster_a7_opp_table: opp-table1 {
112 compatible = "operating-points-v2";
113 opp-shared;
114
115 opp-1300000000 {
116 opp-hz = /bits/ 64 <1300000000>;
117 opp-microvolt = <1275000>;
118 clock-latency-ns = <140000>;
119 };
120 opp-1200000000 {
121 opp-hz = /bits/ 64 <1200000000>;
122 opp-microvolt = <1212500>;
123 clock-latency-ns = <140000>;
124 };
125 opp-1100000000 {
126 opp-hz = /bits/ 64 <1100000000>;
127 opp-microvolt = <1162500>;
128 clock-latency-ns = <140000>;
129 };
130 opp-1000000000 {
131 opp-hz = /bits/ 64 <1000000000>;
132 opp-microvolt = <1112500>;
133 clock-latency-ns = <140000>;
134 };
135 opp-900000000 {
136 opp-hz = /bits/ 64 <900000000>;
137 opp-microvolt = <1062500>;
138 clock-latency-ns = <140000>;
139 };
140 opp-800000000 {
141 opp-hz = /bits/ 64 <800000000>;
142 opp-microvolt = <1025000>;
143 clock-latency-ns = <140000>;
144 };
145 opp-700000000 {
146 opp-hz = /bits/ 64 <700000000>;
147 opp-microvolt = <975000>;
148 clock-latency-ns = <140000>;
149 };
150 opp-600000000 {
151 opp-hz = /bits/ 64 <600000000>;
152 opp-microvolt = <937500>;
153 clock-latency-ns = <140000>;
154 };
155 };
156
157 soc: soc {
158 cci: cci@10d20000 {
159 compatible = "arm,cci-400";
160 #address-cells = <1>;
161 #size-cells = <1>;
162 reg = <0x10d20000 0x1000>;
163 ranges = <0x0 0x10d20000 0x6000>;
164
165 cci_control0: slave-if@4000 {
166 compatible = "arm,cci-400-ctrl-if";
167 interface-type = "ace";
168 reg = <0x4000 0x1000>;
169 };
170 cci_control1: slave-if@5000 {
171 compatible = "arm,cci-400-ctrl-if";
172 interface-type = "ace";
173 reg = <0x5000 0x1000>;
174 };
175 };
176
177 clock: clock-controller@10010000 {
178 compatible = "samsung,exynos5420-clock", "syscon";
179 reg = <0x10010000 0x30000>;
180 #clock-cells = <1>;
181 };
182
183 clock_audss: audss-clock-controller@3810000 {
184 compatible = "samsung,exynos5420-audss-clock";
185 reg = <0x03810000 0x0C>;
186 #clock-cells = <1>;
187 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
188 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
189 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
190 power-domains = <&mau_pd>;
191 };
192
193 mfc: codec@11000000 {
194 compatible = "samsung,mfc-v7";
195 reg = <0x11000000 0x10000>;
196 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&clock CLK_MFC>;
198 clock-names = "mfc";
199 power-domains = <&mfc_pd>;
200 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
201 iommu-names = "left", "right";
202 };
203
204 mmc_0: mmc@12200000 {
205 compatible = "samsung,exynos5420-dw-mshc-smu";
206 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
207 #address-cells = <1>;
208 #size-cells = <0>;
209 reg = <0x12200000 0x2000>;
210 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
211 clock-names = "biu", "ciu";
212 fifo-depth = <0x40>;
213 status = "disabled";
214 };
215
216 mmc_1: mmc@12210000 {
217 compatible = "samsung,exynos5420-dw-mshc-smu";
218 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
219 #address-cells = <1>;
220 #size-cells = <0>;
221 reg = <0x12210000 0x2000>;
222 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
223 clock-names = "biu", "ciu";
224 fifo-depth = <0x40>;
225 status = "disabled";
226 };
227
228 mmc_2: mmc@12220000 {
229 compatible = "samsung,exynos5420-dw-mshc";
230 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
231 #address-cells = <1>;
232 #size-cells = <0>;
233 reg = <0x12220000 0x1000>;
234 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
235 clock-names = "biu", "ciu";
236 fifo-depth = <0x40>;
237 status = "disabled";
238 };
239
240 dmc: memory-controller@10c20000 {
241 compatible = "samsung,exynos5422-dmc";
242 reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
243 clocks = <&clock CLK_FOUT_SPLL>,
244 <&clock CLK_MOUT_SCLK_SPLL>,
245 <&clock CLK_FF_DOUT_SPLL2>,
246 <&clock CLK_FOUT_BPLL>,
247 <&clock CLK_MOUT_BPLL>,
248 <&clock CLK_SCLK_BPLL>,
249 <&clock CLK_MOUT_MX_MSPLL_CCORE>,
250 <&clock CLK_MOUT_MCLK_CDREX>;
251 clock-names = "fout_spll",
252 "mout_sclk_spll",
253 "ff_dout_spll2",
254 "fout_bpll",
255 "mout_bpll",
256 "sclk_bpll",
257 "mout_mx_mspll_ccore",
258 "mout_mclk_cdrex";
259 samsung,syscon-clk = <&clock>;
260 status = "disabled";
261 };
262
263 nocp_mem0_0: nocp@10ca1000 {
264 compatible = "samsung,exynos5420-nocp";
265 reg = <0x10CA1000 0x200>;
266 status = "disabled";
267 };
268
269 nocp_mem0_1: nocp@10ca1400 {
270 compatible = "samsung,exynos5420-nocp";
271 reg = <0x10CA1400 0x200>;
272 status = "disabled";
273 };
274
275 nocp_mem1_0: nocp@10ca1800 {
276 compatible = "samsung,exynos5420-nocp";
277 reg = <0x10CA1800 0x200>;
278 status = "disabled";
279 };
280
281 nocp_mem1_1: nocp@10ca1c00 {
282 compatible = "samsung,exynos5420-nocp";
283 reg = <0x10CA1C00 0x200>;
284 status = "disabled";
285 };
286
287 nocp_g3d_0: nocp@11a51000 {
288 compatible = "samsung,exynos5420-nocp";
289 reg = <0x11A51000 0x200>;
290 status = "disabled";
291 };
292
293 nocp_g3d_1: nocp@11a51400 {
294 compatible = "samsung,exynos5420-nocp";
295 reg = <0x11A51400 0x200>;
296 status = "disabled";
297 };
298
299 ppmu_dmc0_0: ppmu@10d00000 {
300 compatible = "samsung,exynos-ppmu";
301 reg = <0x10d00000 0x2000>;
302 clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
303 clock-names = "ppmu";
304 events {
305 ppmu_event3_dmc0_0: ppmu-event3-dmc0-0 {
306 event-name = "ppmu-event3-dmc0-0";
307 };
308 };
309 };
310
311 ppmu_dmc0_1: ppmu@10d10000 {
312 compatible = "samsung,exynos-ppmu";
313 reg = <0x10d10000 0x2000>;
314 clocks = <&clock CLK_PCLK_PPMU_DREX0_1>;
315 clock-names = "ppmu";
316 events {
317 ppmu_event3_dmc0_1: ppmu-event3-dmc0-1 {
318 event-name = "ppmu-event3-dmc0-1";
319 };
320 };
321 };
322
323 ppmu_dmc1_0: ppmu@10d60000 {
324 compatible = "samsung,exynos-ppmu";
325 reg = <0x10d60000 0x2000>;
326 clocks = <&clock CLK_PCLK_PPMU_DREX1_0>;
327 clock-names = "ppmu";
328 events {
329 ppmu_event3_dmc1_0: ppmu-event3-dmc1-0 {
330 event-name = "ppmu-event3-dmc1-0";
331 };
332 };
333 };
334
335 ppmu_dmc1_1: ppmu@10d70000 {
336 compatible = "samsung,exynos-ppmu";
337 reg = <0x10d70000 0x2000>;
338 clocks = <&clock CLK_PCLK_PPMU_DREX1_1>;
339 clock-names = "ppmu";
340 events {
341 ppmu_event3_dmc1_1: ppmu-event3-dmc1-1 {
342 event-name = "ppmu-event3-dmc1-1";
343 };
344 };
345 };
346
347 gsc_pd: power-domain@10044000 {
348 compatible = "samsung,exynos4210-pd";
349 reg = <0x10044000 0x20>;
350 #power-domain-cells = <0>;
351 label = "GSC";
352 };
353
354 isp_pd: power-domain@10044020 {
355 compatible = "samsung,exynos4210-pd";
356 reg = <0x10044020 0x20>;
357 #power-domain-cells = <0>;
358 label = "ISP";
359 };
360
361 mfc_pd: power-domain@10044060 {
362 compatible = "samsung,exynos4210-pd";
363 reg = <0x10044060 0x20>;
364 #power-domain-cells = <0>;
365 label = "MFC";
366 };
367
368 g3d_pd: power-domain@10044080 {
369 compatible = "samsung,exynos4210-pd";
370 reg = <0x10044080 0x20>;
371 #power-domain-cells = <0>;
372 label = "G3D";
373 };
374
375 disp_pd: power-domain@100440c0 {
376 compatible = "samsung,exynos4210-pd";
377 reg = <0x100440C0 0x20>;
378 #power-domain-cells = <0>;
379 label = "DISP";
380 };
381
382 mau_pd: power-domain@100440e0 {
383 compatible = "samsung,exynos4210-pd";
384 reg = <0x100440E0 0x20>;
385 #power-domain-cells = <0>;
386 label = "MAU";
387 };
388
389 msc_pd: power-domain@10044120 {
390 compatible = "samsung,exynos4210-pd";
391 reg = <0x10044120 0x20>;
392 #power-domain-cells = <0>;
393 label = "MSC";
394 };
395
396 pinctrl_0: pinctrl@13400000 {
397 compatible = "samsung,exynos5420-pinctrl";
398 reg = <0x13400000 0x1000>;
399 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
400
401 wakeup-interrupt-controller {
402 compatible = "samsung,exynos4210-wakeup-eint";
403 interrupt-parent = <&gic>;
404 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
405 };
406 };
407
408 pinctrl_1: pinctrl@13410000 {
409 compatible = "samsung,exynos5420-pinctrl";
410 reg = <0x13410000 0x1000>;
411 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
412 };
413
414 pinctrl_2: pinctrl@14000000 {
415 compatible = "samsung,exynos5420-pinctrl";
416 reg = <0x14000000 0x1000>;
417 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
418 };
419
420 pinctrl_3: pinctrl@14010000 {
421 compatible = "samsung,exynos5420-pinctrl";
422 reg = <0x14010000 0x1000>;
423 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
424 };
425
426 pinctrl_4: pinctrl@3860000 {
427 compatible = "samsung,exynos5420-pinctrl";
428 reg = <0x03860000 0x1000>;
429 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
430 power-domains = <&mau_pd>;
431 };
432
433 adma: dma-controller@3880000 {
434 compatible = "arm,pl330", "arm,primecell";
435 reg = <0x03880000 0x1000>;
436 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&clock_audss EXYNOS_ADMA>;
438 clock-names = "apb_pclk";
439 #dma-cells = <1>;
440 power-domains = <&mau_pd>;
441 };
442
443 pdma0: dma-controller@121a0000 {
444 compatible = "arm,pl330", "arm,primecell";
445 reg = <0x121A0000 0x1000>;
446 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
447 clocks = <&clock CLK_PDMA0>;
448 clock-names = "apb_pclk";
449 #dma-cells = <1>;
450 };
451
452 pdma1: dma-controller@121b0000 {
453 compatible = "arm,pl330", "arm,primecell";
454 reg = <0x121B0000 0x1000>;
455 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&clock CLK_PDMA1>;
457 clock-names = "apb_pclk";
458 #dma-cells = <1>;
459 };
460
461 mdma0: dma-controller@10800000 {
462 compatible = "arm,pl330", "arm,primecell";
463 reg = <0x10800000 0x1000>;
464 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
465 clocks = <&clock CLK_MDMA0>;
466 clock-names = "apb_pclk";
467 #dma-cells = <1>;
468 };
469
470 mdma1: dma-controller@11c10000 {
471 compatible = "arm,pl330", "arm,primecell";
472 reg = <0x11C10000 0x1000>;
473 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&clock CLK_MDMA1>;
475 clock-names = "apb_pclk";
476 #dma-cells = <1>;
477 /*
478 * MDMA1 can support both secure and non-secure
479 * AXI transactions. When this is enabled in
480 * the kernel for boards that run in secure
481 * mode, we are getting imprecise external
482 * aborts causing the kernel to oops.
483 */
484 status = "disabled";
485 };
486
487 i2s0: i2s@3830000 {
488 compatible = "samsung,exynos5420-i2s";
489 reg = <0x03830000 0x100>;
490 dmas = <&adma 0>,
491 <&adma 2>,
492 <&adma 1>;
493 dma-names = "tx", "rx", "tx-sec";
494 clocks = <&clock_audss EXYNOS_I2S_BUS>,
495 <&clock_audss EXYNOS_I2S_BUS>,
496 <&clock_audss EXYNOS_SCLK_I2S>;
497 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
498 #clock-cells = <1>;
499 clock-output-names = "i2s_cdclk0";
500 #sound-dai-cells = <1>;
501 samsung,idma-addr = <0x03000000>;
502 pinctrl-names = "default";
503 pinctrl-0 = <&i2s0_bus>;
504 power-domains = <&mau_pd>;
505 status = "disabled";
506 };
507
508 i2s1: i2s@12d60000 {
509 compatible = "samsung,exynos5420-i2s";
510 reg = <0x12D60000 0x100>;
511 dmas = <&pdma1 12>,
512 <&pdma1 11>;
513 dma-names = "tx", "rx";
514 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
515 clock-names = "iis", "i2s_opclk0";
516 #clock-cells = <1>;
517 clock-output-names = "i2s_cdclk1";
518 #sound-dai-cells = <1>;
519 pinctrl-names = "default";
520 pinctrl-0 = <&i2s1_bus>;
521 status = "disabled";
522 };
523
524 i2s2: i2s@12d70000 {
525 compatible = "samsung,exynos5420-i2s";
526 reg = <0x12D70000 0x100>;
527 dmas = <&pdma0 12>,
528 <&pdma0 11>;
529 dma-names = "tx", "rx";
530 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
531 clock-names = "iis", "i2s_opclk0";
532 #clock-cells = <1>;
533 clock-output-names = "i2s_cdclk2";
534 #sound-dai-cells = <1>;
535 pinctrl-names = "default";
536 pinctrl-0 = <&i2s2_bus>;
537 status = "disabled";
538 };
539
540 spi_0: spi@12d20000 {
541 compatible = "samsung,exynos4210-spi";
542 reg = <0x12d20000 0x100>;
543 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
544 dmas = <&pdma0 5
545 &pdma0 4>;
546 dma-names = "tx", "rx";
547 #address-cells = <1>;
548 #size-cells = <0>;
549 pinctrl-names = "default";
550 pinctrl-0 = <&spi0_bus>;
551 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
552 clock-names = "spi", "spi_busclk0";
553 status = "disabled";
554 };
555
556 spi_1: spi@12d30000 {
557 compatible = "samsung,exynos4210-spi";
558 reg = <0x12d30000 0x100>;
559 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
560 dmas = <&pdma1 5
561 &pdma1 4>;
562 dma-names = "tx", "rx";
563 #address-cells = <1>;
564 #size-cells = <0>;
565 pinctrl-names = "default";
566 pinctrl-0 = <&spi1_bus>;
567 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
568 clock-names = "spi", "spi_busclk0";
569 status = "disabled";
570 };
571
572 spi_2: spi@12d40000 {
573 compatible = "samsung,exynos4210-spi";
574 reg = <0x12d40000 0x100>;
575 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
576 dmas = <&pdma0 7
577 &pdma0 6>;
578 dma-names = "tx", "rx";
579 #address-cells = <1>;
580 #size-cells = <0>;
581 pinctrl-names = "default";
582 pinctrl-0 = <&spi2_bus>;
583 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
584 clock-names = "spi", "spi_busclk0";
585 status = "disabled";
586 };
587
588 dp_phy: dp-video-phy {
589 compatible = "samsung,exynos5420-dp-video-phy";
590 samsung,pmu-syscon = <&pmu_system_controller>;
591 #phy-cells = <0>;
592 };
593
594 mipi_phy: mipi-video-phy {
595 compatible = "samsung,s5pv210-mipi-video-phy";
596 syscon = <&pmu_system_controller>;
597 #phy-cells = <1>;
598 };
599
600 dsi@14500000 {
601 compatible = "samsung,exynos5410-mipi-dsi";
602 reg = <0x14500000 0x10000>;
603 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
604 phys = <&mipi_phy 1>;
605 phy-names = "dsim";
606 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
607 clock-names = "bus_clk", "pll_clk";
608 #address-cells = <1>;
609 #size-cells = <0>;
610 status = "disabled";
611 };
612
613 hsi2c_8: i2c@12e00000 {
614 compatible = "samsung,exynos5250-hsi2c";
615 reg = <0x12E00000 0x1000>;
616 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
617 #address-cells = <1>;
618 #size-cells = <0>;
619 pinctrl-names = "default";
620 pinctrl-0 = <&i2c8_hs_bus>;
621 clocks = <&clock CLK_USI4>;
622 clock-names = "hsi2c";
623 status = "disabled";
624 };
625
626 hsi2c_9: i2c@12e10000 {
627 compatible = "samsung,exynos5250-hsi2c";
628 reg = <0x12E10000 0x1000>;
629 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
630 #address-cells = <1>;
631 #size-cells = <0>;
632 pinctrl-names = "default";
633 pinctrl-0 = <&i2c9_hs_bus>;
634 clocks = <&clock CLK_USI5>;
635 clock-names = "hsi2c";
636 status = "disabled";
637 };
638
639 hsi2c_10: i2c@12e20000 {
640 compatible = "samsung,exynos5250-hsi2c";
641 reg = <0x12E20000 0x1000>;
642 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
643 #address-cells = <1>;
644 #size-cells = <0>;
645 pinctrl-names = "default";
646 pinctrl-0 = <&i2c10_hs_bus>;
647 clocks = <&clock CLK_USI6>;
648 clock-names = "hsi2c";
649 status = "disabled";
650 };
651
652 hdmi: hdmi@14530000 {
653 compatible = "samsung,exynos5420-hdmi";
654 reg = <0x14530000 0x70000>;
655 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
656 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
657 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
658 <&clock CLK_MOUT_HDMI>;
659 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
660 "sclk_hdmiphy", "mout_hdmi";
661 phy = <&hdmiphy>;
662 samsung,syscon-phandle = <&pmu_system_controller>;
663 status = "disabled";
664 power-domains = <&disp_pd>;
665 #sound-dai-cells = <0>;
666 };
667
668 hdmiphy: hdmiphy@145d0000 {
669 reg = <0x145D0000 0x20>;
670 };
671
672 hdmicec: cec@101b0000 {
673 compatible = "samsung,s5p-cec";
674 reg = <0x101B0000 0x200>;
675 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
676 clocks = <&clock CLK_HDMI_CEC>;
677 clock-names = "hdmicec";
678 samsung,syscon-phandle = <&pmu_system_controller>;
679 hdmi-phandle = <&hdmi>;
680 pinctrl-names = "default";
681 pinctrl-0 = <&hdmi_cec>;
682 status = "disabled";
683 };
684
685 mixer: mixer@14450000 {
686 compatible = "samsung,exynos5420-mixer";
687 reg = <0x14450000 0x10000>;
688 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
689 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
690 <&clock CLK_SCLK_HDMI>;
691 clock-names = "mixer", "hdmi", "sclk_hdmi";
692 power-domains = <&disp_pd>;
693 iommus = <&sysmmu_tv>;
694 status = "disabled";
695 };
696
697 rotator: rotator@11c00000 {
698 compatible = "samsung,exynos5250-rotator";
699 reg = <0x11C00000 0x64>;
700 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
701 clocks = <&clock CLK_ROTATOR>;
702 clock-names = "rotator";
703 iommus = <&sysmmu_rotator>;
704 };
705
706 gsc_0: video-scaler@13e00000 {
707 compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
708 reg = <0x13e00000 0x1000>;
709 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
710 clocks = <&clock CLK_GSCL0>;
711 clock-names = "gscl";
712 power-domains = <&gsc_pd>;
713 iommus = <&sysmmu_gscl0>;
714 };
715
716 gsc_1: video-scaler@13e10000 {
717 compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
718 reg = <0x13e10000 0x1000>;
719 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
720 clocks = <&clock CLK_GSCL1>;
721 clock-names = "gscl";
722 power-domains = <&gsc_pd>;
723 iommus = <&sysmmu_gscl1>;
724 };
725
726 gpu: gpu@11800000 {
727 compatible = "samsung,exynos5420-mali", "arm,mali-t628";
728 reg = <0x11800000 0x5000>;
729 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
730 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
731 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
732 interrupt-names = "job", "mmu", "gpu";
733
734 clocks = <&clock CLK_G3D>;
735 clock-names = "core";
736 power-domains = <&g3d_pd>;
737 operating-points-v2 = <&gpu_opp_table>;
738
739 status = "disabled";
740 #cooling-cells = <2>;
741
742 gpu_opp_table: opp-table {
743 compatible = "operating-points-v2";
744
745 opp-177000000 {
746 opp-hz = /bits/ 64 <177000000>;
747 opp-microvolt = <812500>;
748 };
749 opp-266000000 {
750 opp-hz = /bits/ 64 <266000000>;
751 opp-microvolt = <862500>;
752 };
753 opp-350000000 {
754 opp-hz = /bits/ 64 <350000000>;
755 opp-microvolt = <912500>;
756 };
757 opp-420000000 {
758 opp-hz = /bits/ 64 <420000000>;
759 opp-microvolt = <962500>;
760 };
761 opp-480000000 {
762 opp-hz = /bits/ 64 <480000000>;
763 opp-microvolt = <1000000>;
764 };
765 opp-543000000 {
766 opp-hz = /bits/ 64 <543000000>;
767 opp-microvolt = <1037500>;
768 };
769 opp-600000000 {
770 opp-hz = /bits/ 64 <600000000>;
771 opp-microvolt = <1150000>;
772 };
773 };
774 };
775
776 scaler_0: scaler@12800000 {
777 compatible = "samsung,exynos5420-scaler";
778 reg = <0x12800000 0x1294>;
779 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH>;
780 clocks = <&clock CLK_MSCL0>;
781 clock-names = "mscl";
782 power-domains = <&msc_pd>;
783 iommus = <&sysmmu_scaler0r>, <&sysmmu_scaler0w>;
784 };
785
786 scaler_1: scaler@12810000 {
787 compatible = "samsung,exynos5420-scaler";
788 reg = <0x12810000 0x1294>;
789 interrupts = <0 221 IRQ_TYPE_LEVEL_HIGH>;
790 clocks = <&clock CLK_MSCL1>;
791 clock-names = "mscl";
792 power-domains = <&msc_pd>;
793 iommus = <&sysmmu_scaler1r>, <&sysmmu_scaler1w>;
794 };
795
796 scaler_2: scaler@12820000 {
797 compatible = "samsung,exynos5420-scaler";
798 reg = <0x12820000 0x1294>;
799 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>;
800 clocks = <&clock CLK_MSCL2>;
801 clock-names = "mscl";
802 power-domains = <&msc_pd>;
803 iommus = <&sysmmu_scaler2r>, <&sysmmu_scaler2w>;
804 };
805
806 jpeg_0: jpeg@11f50000 {
807 compatible = "samsung,exynos5420-jpeg";
808 reg = <0x11F50000 0x1000>;
809 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
810 clock-names = "jpeg";
811 clocks = <&clock CLK_JPEG>;
812 iommus = <&sysmmu_jpeg0>;
813 };
814
815 jpeg_1: jpeg@11f60000 {
816 compatible = "samsung,exynos5420-jpeg";
817 reg = <0x11F60000 0x1000>;
818 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
819 clock-names = "jpeg";
820 clocks = <&clock CLK_JPEG2>;
821 iommus = <&sysmmu_jpeg1>;
822 };
823
824 pmu_system_controller: system-controller@10040000 {
825 compatible = "samsung,exynos5420-pmu", "syscon";
826 reg = <0x10040000 0x5000>;
827 clock-names = "clkout16";
828 clocks = <&clock CLK_FIN_PLL>;
829 #clock-cells = <1>;
830 interrupt-controller;
831 #interrupt-cells = <3>;
832 interrupt-parent = <&gic>;
833 };
834
835 tmu_cpu0: tmu@10060000 {
836 compatible = "samsung,exynos5420-tmu";
837 reg = <0x10060000 0x100>;
838 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
839 clocks = <&clock CLK_TMU>;
840 clock-names = "tmu_apbif";
841 #thermal-sensor-cells = <0>;
842 };
843
844 tmu_cpu1: tmu@10064000 {
845 compatible = "samsung,exynos5420-tmu";
846 reg = <0x10064000 0x100>;
847 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
848 clocks = <&clock CLK_TMU>;
849 clock-names = "tmu_apbif";
850 #thermal-sensor-cells = <0>;
851 };
852
853 tmu_cpu2: tmu@10068000 {
854 compatible = "samsung,exynos5420-tmu-ext-triminfo";
855 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
856 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
857 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
858 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
859 #thermal-sensor-cells = <0>;
860 };
861
862 tmu_cpu3: tmu@1006c000 {
863 compatible = "samsung,exynos5420-tmu-ext-triminfo";
864 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
865 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
866 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
867 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
868 #thermal-sensor-cells = <0>;
869 };
870
871 tmu_gpu: tmu@100a0000 {
872 compatible = "samsung,exynos5420-tmu-ext-triminfo";
873 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
874 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
875 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
876 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
877 #thermal-sensor-cells = <0>;
878 };
879
880 sysmmu_g2dr: sysmmu@10a60000 {
881 compatible = "samsung,exynos-sysmmu";
882 reg = <0x10A60000 0x1000>;
883 interrupt-parent = <&combiner>;
884 interrupts = <24 5>;
885 clock-names = "sysmmu", "master";
886 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
887 #iommu-cells = <0>;
888 };
889
890 sysmmu_g2dw: sysmmu@10a70000 {
891 compatible = "samsung,exynos-sysmmu";
892 reg = <0x10A70000 0x1000>;
893 interrupt-parent = <&combiner>;
894 interrupts = <22 2>;
895 clock-names = "sysmmu", "master";
896 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
897 #iommu-cells = <0>;
898 };
899
900 sysmmu_tv: sysmmu@14650000 {
901 compatible = "samsung,exynos-sysmmu";
902 reg = <0x14650000 0x1000>;
903 interrupt-parent = <&combiner>;
904 interrupts = <7 4>;
905 clock-names = "sysmmu", "master";
906 clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>;
907 power-domains = <&disp_pd>;
908 #iommu-cells = <0>;
909 };
910
911 sysmmu_gscl0: sysmmu@13e80000 {
912 compatible = "samsung,exynos-sysmmu";
913 reg = <0x13E80000 0x1000>;
914 interrupt-parent = <&combiner>;
915 interrupts = <2 0>;
916 clock-names = "sysmmu", "master";
917 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
918 power-domains = <&gsc_pd>;
919 #iommu-cells = <0>;
920 };
921
922 sysmmu_gscl1: sysmmu@13e90000 {
923 compatible = "samsung,exynos-sysmmu";
924 reg = <0x13E90000 0x1000>;
925 interrupt-parent = <&combiner>;
926 interrupts = <2 2>;
927 clock-names = "sysmmu", "master";
928 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
929 power-domains = <&gsc_pd>;
930 #iommu-cells = <0>;
931 };
932
933 sysmmu_scaler0r: sysmmu@12880000 {
934 compatible = "samsung,exynos-sysmmu";
935 reg = <0x12880000 0x1000>;
936 interrupt-parent = <&combiner>;
937 interrupts = <22 4>;
938 clock-names = "sysmmu", "master";
939 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
940 power-domains = <&msc_pd>;
941 #iommu-cells = <0>;
942 };
943
944 sysmmu_scaler1r: sysmmu@12890000 {
945 compatible = "samsung,exynos-sysmmu";
946 reg = <0x12890000 0x1000>;
947 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
948 clock-names = "sysmmu", "master";
949 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
950 power-domains = <&msc_pd>;
951 #iommu-cells = <0>;
952 };
953
954 sysmmu_scaler2r: sysmmu@128a0000 {
955 compatible = "samsung,exynos-sysmmu";
956 reg = <0x128A0000 0x1000>;
957 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
958 clock-names = "sysmmu", "master";
959 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
960 power-domains = <&msc_pd>;
961 #iommu-cells = <0>;
962 };
963
964 sysmmu_scaler0w: sysmmu@128c0000 {
965 compatible = "samsung,exynos-sysmmu";
966 reg = <0x128C0000 0x1000>;
967 interrupt-parent = <&combiner>;
968 interrupts = <27 2>;
969 clock-names = "sysmmu", "master";
970 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
971 power-domains = <&msc_pd>;
972 #iommu-cells = <0>;
973 };
974
975 sysmmu_scaler1w: sysmmu@128d0000 {
976 compatible = "samsung,exynos-sysmmu";
977 reg = <0x128D0000 0x1000>;
978 interrupt-parent = <&combiner>;
979 interrupts = <22 6>;
980 clock-names = "sysmmu", "master";
981 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
982 power-domains = <&msc_pd>;
983 #iommu-cells = <0>;
984 };
985
986 sysmmu_scaler2w: sysmmu@128e0000 {
987 compatible = "samsung,exynos-sysmmu";
988 reg = <0x128E0000 0x1000>;
989 interrupt-parent = <&combiner>;
990 interrupts = <19 6>;
991 clock-names = "sysmmu", "master";
992 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
993 power-domains = <&msc_pd>;
994 #iommu-cells = <0>;
995 };
996
997 sysmmu_rotator: sysmmu@11d40000 {
998 compatible = "samsung,exynos-sysmmu";
999 reg = <0x11D40000 0x1000>;
1000 interrupt-parent = <&combiner>;
1001 interrupts = <4 0>;
1002 clock-names = "sysmmu", "master";
1003 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
1004 #iommu-cells = <0>;
1005 };
1006
1007 sysmmu_jpeg0: sysmmu@11f10000 {
1008 compatible = "samsung,exynos-sysmmu";
1009 reg = <0x11F10000 0x1000>;
1010 interrupt-parent = <&combiner>;
1011 interrupts = <4 2>;
1012 clock-names = "sysmmu", "master";
1013 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
1014 #iommu-cells = <0>;
1015 };
1016
1017 sysmmu_jpeg1: sysmmu@11f20000 {
1018 compatible = "samsung,exynos-sysmmu";
1019 reg = <0x11F20000 0x1000>;
1020 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
1021 clock-names = "sysmmu", "master";
1022 clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
1023 #iommu-cells = <0>;
1024 };
1025
1026 sysmmu_mfc_l: sysmmu@11200000 {
1027 compatible = "samsung,exynos-sysmmu";
1028 reg = <0x11200000 0x1000>;
1029 interrupt-parent = <&combiner>;
1030 interrupts = <6 2>;
1031 clock-names = "sysmmu", "master";
1032 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
1033 power-domains = <&mfc_pd>;
1034 #iommu-cells = <0>;
1035 };
1036
1037 sysmmu_mfc_r: sysmmu@11210000 {
1038 compatible = "samsung,exynos-sysmmu";
1039 reg = <0x11210000 0x1000>;
1040 interrupt-parent = <&combiner>;
1041 interrupts = <8 5>;
1042 clock-names = "sysmmu", "master";
1043 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
1044 power-domains = <&mfc_pd>;
1045 #iommu-cells = <0>;
1046 };
1047
1048 sysmmu_fimd1_0: sysmmu@14640000 {
1049 compatible = "samsung,exynos-sysmmu";
1050 reg = <0x14640000 0x1000>;
1051 interrupt-parent = <&combiner>;
1052 interrupts = <3 2>;
1053 clock-names = "sysmmu", "master";
1054 clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
1055 power-domains = <&disp_pd>;
1056 #iommu-cells = <0>;
1057 };
1058
1059 sysmmu_fimd1_1: sysmmu@14680000 {
1060 compatible = "samsung,exynos-sysmmu";
1061 reg = <0x14680000 0x1000>;
1062 interrupt-parent = <&combiner>;
1063 interrupts = <3 0>;
1064 clock-names = "sysmmu", "master";
1065 clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>;
1066 power-domains = <&disp_pd>;
1067 #iommu-cells = <0>;
1068 };
1069
1070 bus_wcore: bus-wcore {
1071 compatible = "samsung,exynos-bus";
1072 clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
1073 clock-names = "bus";
1074 status = "disabled";
1075 };
1076
1077 bus_noc: bus-noc {
1078 compatible = "samsung,exynos-bus";
1079 clocks = <&clock CLK_DOUT_ACLK100_NOC>;
1080 clock-names = "bus";
1081 status = "disabled";
1082 };
1083
1084 bus_fsys_apb: bus-fsys-apb {
1085 compatible = "samsung,exynos-bus";
1086 clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
1087 clock-names = "bus";
1088 status = "disabled";
1089 };
1090
1091 bus_fsys: bus-fsys {
1092 compatible = "samsung,exynos-bus";
1093 clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
1094 clock-names = "bus";
1095 status = "disabled";
1096 };
1097
1098 bus_fsys2: bus-fsys2 {
1099 compatible = "samsung,exynos-bus";
1100 clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
1101 clock-names = "bus";
1102 status = "disabled";
1103 };
1104
1105 bus_mfc: bus-mfc {
1106 compatible = "samsung,exynos-bus";
1107 clocks = <&clock CLK_DOUT_ACLK333>;
1108 clock-names = "bus";
1109 status = "disabled";
1110 };
1111
1112 bus_gen: bus-gen {
1113 compatible = "samsung,exynos-bus";
1114 clocks = <&clock CLK_DOUT_ACLK266>;
1115 clock-names = "bus";
1116 status = "disabled";
1117 };
1118
1119 bus_peri: bus-peri {
1120 compatible = "samsung,exynos-bus";
1121 clocks = <&clock CLK_DOUT_ACLK66>;
1122 clock-names = "bus";
1123 status = "disabled";
1124 };
1125
1126 bus_g2d: bus-g2d {
1127 compatible = "samsung,exynos-bus";
1128 clocks = <&clock CLK_DOUT_ACLK333_G2D>;
1129 clock-names = "bus";
1130 status = "disabled";
1131 };
1132
1133 bus_g2d_acp: bus-g2d-acp {
1134 compatible = "samsung,exynos-bus";
1135 clocks = <&clock CLK_DOUT_ACLK266_G2D>;
1136 clock-names = "bus";
1137 status = "disabled";
1138 };
1139
1140 bus_jpeg: bus-jpeg {
1141 compatible = "samsung,exynos-bus";
1142 clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
1143 clock-names = "bus";
1144 status = "disabled";
1145 };
1146
1147 bus_jpeg_apb: bus-jpeg-apb {
1148 compatible = "samsung,exynos-bus";
1149 clocks = <&clock CLK_DOUT_ACLK166>;
1150 clock-names = "bus";
1151 status = "disabled";
1152 };
1153
1154 bus_disp1_fimd: bus-disp1-fimd {
1155 compatible = "samsung,exynos-bus";
1156 clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
1157 clock-names = "bus";
1158 status = "disabled";
1159 };
1160
1161 bus_disp1: bus-disp1 {
1162 compatible = "samsung,exynos-bus";
1163 clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
1164 clock-names = "bus";
1165 status = "disabled";
1166 };
1167
1168 bus_gscl_scaler: bus-gscl-scaler {
1169 compatible = "samsung,exynos-bus";
1170 clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
1171 clock-names = "bus";
1172 status = "disabled";
1173 };
1174
1175 bus_mscl: bus-mscl {
1176 compatible = "samsung,exynos-bus";
1177 clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
1178 clock-names = "bus";
1179 status = "disabled";
1180 };
1181 };
1182
1183 thermal-zones {
1184 cpu0_thermal: cpu0-thermal {
1185 thermal-sensors = <&tmu_cpu0>;
1186 #include "exynos5420-trip-points.dtsi"
1187 };
1188 cpu1_thermal: cpu1-thermal {
1189 thermal-sensors = <&tmu_cpu1>;
1190 #include "exynos5420-trip-points.dtsi"
1191 };
1192 cpu2_thermal: cpu2-thermal {
1193 thermal-sensors = <&tmu_cpu2>;
1194 #include "exynos5420-trip-points.dtsi"
1195 };
1196 cpu3_thermal: cpu3-thermal {
1197 thermal-sensors = <&tmu_cpu3>;
1198 #include "exynos5420-trip-points.dtsi"
1199 };
1200 gpu_thermal: gpu-thermal {
1201 thermal-sensors = <&tmu_gpu>;
1202 #include "exynos5420-trip-points.dtsi"
1203 };
1204 };
1205};
1206
1207&adc {
1208 clocks = <&clock CLK_TSADC>;
1209 clock-names = "adc";
1210 samsung,syscon-phandle = <&pmu_system_controller>;
1211};
1212
1213&dp {
1214 clocks = <&clock CLK_DP1>;
1215 clock-names = "dp";
1216 phys = <&dp_phy>;
1217 phy-names = "dp";
1218 power-domains = <&disp_pd>;
1219};
1220
1221&fimd {
1222 compatible = "samsung,exynos5420-fimd";
1223 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1224 clock-names = "sclk_fimd", "fimd";
1225 power-domains = <&disp_pd>;
1226 iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>;
1227 iommu-names = "m0", "m1";
1228};
1229
1230&g2d {
1231 iommus = <&sysmmu_g2dr>, <&sysmmu_g2dw>;
1232 clocks = <&clock CLK_G2D>;
1233 clock-names = "fimg2d";
1234 status = "okay";
1235};
1236
1237&i2c_0 {
1238 clocks = <&clock CLK_I2C0>;
1239 clock-names = "i2c";
1240 pinctrl-names = "default";
1241 pinctrl-0 = <&i2c0_bus>;
1242};
1243
1244&i2c_1 {
1245 clocks = <&clock CLK_I2C1>;
1246 clock-names = "i2c";
1247 pinctrl-names = "default";
1248 pinctrl-0 = <&i2c1_bus>;
1249};
1250
1251&i2c_2 {
1252 clocks = <&clock CLK_I2C2>;
1253 clock-names = "i2c";
1254 pinctrl-names = "default";
1255 pinctrl-0 = <&i2c2_bus>;
1256};
1257
1258&i2c_3 {
1259 clocks = <&clock CLK_I2C3>;
1260 clock-names = "i2c";
1261 pinctrl-names = "default";
1262 pinctrl-0 = <&i2c3_bus>;
1263};
1264
1265&hsi2c_4 {
1266 clocks = <&clock CLK_USI0>;
1267 clock-names = "hsi2c";
1268 pinctrl-names = "default";
1269 pinctrl-0 = <&i2c4_hs_bus>;
1270};
1271
1272&hsi2c_5 {
1273 clocks = <&clock CLK_USI1>;
1274 clock-names = "hsi2c";
1275 pinctrl-names = "default";
1276 pinctrl-0 = <&i2c5_hs_bus>;
1277};
1278
1279&hsi2c_6 {
1280 clocks = <&clock CLK_USI2>;
1281 clock-names = "hsi2c";
1282 pinctrl-names = "default";
1283 pinctrl-0 = <&i2c6_hs_bus>;
1284};
1285
1286&hsi2c_7 {
1287 clocks = <&clock CLK_USI3>;
1288 clock-names = "hsi2c";
1289 pinctrl-names = "default";
1290 pinctrl-0 = <&i2c7_hs_bus>;
1291};
1292
1293&mct {
1294 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
1295 clock-names = "fin_pll", "mct";
1296};
1297
1298&prng {
1299 clocks = <&clock CLK_SSS>;
1300 clock-names = "secss";
1301};
1302
1303&pwm {
1304 clocks = <&clock CLK_PWM>;
1305 clock-names = "timers";
1306};
1307
1308&rtc {
1309 clocks = <&clock CLK_RTC>;
1310 clock-names = "rtc";
1311 interrupt-parent = <&pmu_system_controller>;
1312 status = "disabled";
1313};
1314
1315&serial_0 {
1316 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1317 clock-names = "uart", "clk_uart_baud0";
1318 dmas = <&pdma0 13>, <&pdma0 14>;
1319 dma-names = "rx", "tx";
1320};
1321
1322&serial_1 {
1323 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1324 clock-names = "uart", "clk_uart_baud0";
1325 dmas = <&pdma1 15>, <&pdma1 16>;
1326 dma-names = "rx", "tx";
1327};
1328
1329&serial_2 {
1330 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1331 clock-names = "uart", "clk_uart_baud0";
1332 dmas = <&pdma0 15>, <&pdma0 16>;
1333 dma-names = "rx", "tx";
1334};
1335
1336&serial_3 {
1337 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1338 clock-names = "uart", "clk_uart_baud0";
1339 dmas = <&pdma1 17>, <&pdma1 18>;
1340 dma-names = "rx", "tx";
1341};
1342
1343&sss {
1344 clocks = <&clock CLK_SSS>;
1345 clock-names = "secss";
1346};
1347
1348&trng {
1349 clocks = <&clock CLK_SSS>;
1350 clock-names = "secss";
1351};
1352
1353&usbdrd3_0 {
1354 clocks = <&clock CLK_USBD300>;
1355 clock-names = "usbdrd30";
1356};
1357
1358&usbdrd_phy0 {
1359 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
1360 clock-names = "phy", "ref";
1361 samsung,pmu-syscon = <&pmu_system_controller>;
1362};
1363
1364&usbdrd3_1 {
1365 clocks = <&clock CLK_USBD301>;
1366 clock-names = "usbdrd30";
1367};
1368
1369&usbdrd_dwc3_1 {
1370 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1371};
1372
1373&usbdrd_phy1 {
1374 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
1375 clock-names = "phy", "ref";
1376 samsung,pmu-syscon = <&pmu_system_controller>;
1377};
1378
1379&usbhost1 {
1380 clocks = <&clock CLK_USBH20>;
1381 clock-names = "usbhost";
1382};
1383
1384&usbhost2 {
1385 clocks = <&clock CLK_USBH20>;
1386 clock-names = "usbhost";
1387};
1388
1389&usb2_phy {
1390 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
1391 clock-names = "phy", "ref";
1392 samsung,sysreg-phandle = <&sysreg_system_controller>;
1393 samsung,pmureg-phandle = <&pmu_system_controller>;
1394};
1395
1396&watchdog {
1397 clocks = <&clock CLK_WDT>;
1398 clock-names = "watchdog";
1399 samsung,syscon-phandle = <&pmu_system_controller>;
1400};
1401
1402#include "exynos5420-pinctrl.dtsi"
1403#include "exynos-syscon-restart.dtsi"