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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
4 *
5 * Copyright (C) 2018-2020 Xilinx Inc.
6 *
7 * Author: Anurag Kumar Vulisha <anuragku@xilinx.com>
8 * Author: Subbaraya Sundeep <sundeep.lkml@gmail.com>
9 * Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 *
11 * This driver is tested for USB, SATA and Display Port currently.
12 * Other controllers PCIe and SGMII should also work but that is
13 * experimental as of now.
14 */
15
16#include <linux/clk.h>
17#include <linux/delay.h>
18#include <linux/io.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/phy/phy.h>
23#include <linux/platform_device.h>
24#include <linux/slab.h>
25
26#include <dt-bindings/phy/phy.h>
27
28/*
29 * Lane Registers
30 */
31
32/* TX De-emphasis parameters */
33#define L0_TX_ANA_TM_18 0x0048
34#define L0_TX_ANA_TM_118 0x01d8
35#define L0_TX_ANA_TM_118_FORCE_17_0 BIT(0)
36
37/* DN Resistor calibration code parameters */
38#define L0_TXPMA_ST_3 0x0b0c
39#define L0_DN_CALIB_CODE 0x3f
40
41/* PMA control parameters */
42#define L0_TXPMD_TM_45 0x0cb4
43#define L0_TXPMD_TM_48 0x0cc0
44#define L0_TXPMD_TM_45_OVER_DP_MAIN BIT(0)
45#define L0_TXPMD_TM_45_ENABLE_DP_MAIN BIT(1)
46#define L0_TXPMD_TM_45_OVER_DP_POST1 BIT(2)
47#define L0_TXPMD_TM_45_ENABLE_DP_POST1 BIT(3)
48#define L0_TXPMD_TM_45_OVER_DP_POST2 BIT(4)
49#define L0_TXPMD_TM_45_ENABLE_DP_POST2 BIT(5)
50
51/* PCS control parameters */
52#define L0_TM_DIG_6 0x106c
53#define L0_TM_DIS_DESCRAMBLE_DECODER 0x0f
54#define L0_TX_DIG_61 0x00f4
55#define L0_TM_DISABLE_SCRAMBLE_ENCODER 0x0f
56
57/* PLL Test Mode register parameters */
58#define L0_TM_PLL_DIG_37 0x2094
59#define L0_TM_COARSE_CODE_LIMIT 0x10
60
61/* PLL SSC step size offsets */
62#define L0_PLL_SS_STEPS_0_LSB 0x2368
63#define L0_PLL_SS_STEPS_1_MSB 0x236c
64#define L0_PLL_SS_STEP_SIZE_0_LSB 0x2370
65#define L0_PLL_SS_STEP_SIZE_1 0x2374
66#define L0_PLL_SS_STEP_SIZE_2 0x2378
67#define L0_PLL_SS_STEP_SIZE_3_MSB 0x237c
68#define L0_PLL_STATUS_READ_1 0x23e4
69
70/* SSC step size parameters */
71#define STEP_SIZE_0_MASK 0xff
72#define STEP_SIZE_1_MASK 0xff
73#define STEP_SIZE_2_MASK 0xff
74#define STEP_SIZE_3_MASK 0x3
75#define STEP_SIZE_SHIFT 8
76#define FORCE_STEP_SIZE 0x10
77#define FORCE_STEPS 0x20
78#define STEPS_0_MASK 0xff
79#define STEPS_1_MASK 0x07
80
81/* Reference clock selection parameters */
82#define L0_Ln_REF_CLK_SEL(n) (0x2860 + (n) * 4)
83#define L0_REF_CLK_SEL_MASK 0x8f
84
85/* Calibration digital logic parameters */
86#define L3_TM_CALIB_DIG19 0xec4c
87#define L3_CALIB_DONE_STATUS 0xef14
88#define L3_TM_CALIB_DIG18 0xec48
89#define L3_TM_CALIB_DIG19_NSW 0x07
90#define L3_TM_CALIB_DIG18_NSW 0xe0
91#define L3_TM_OVERRIDE_NSW_CODE 0x20
92#define L3_CALIB_DONE 0x02
93#define L3_NSW_SHIFT 5
94#define L3_NSW_PIPE_SHIFT 4
95#define L3_NSW_CALIB_SHIFT 3
96
97#define PHY_REG_OFFSET 0x4000
98
99/*
100 * Global Registers
101 */
102
103/* Refclk selection parameters */
104#define PLL_REF_SEL(n) (0x10000 + (n) * 4)
105#define PLL_FREQ_MASK 0x1f
106#define PLL_STATUS_LOCKED 0x10
107
108/* Inter Connect Matrix parameters */
109#define ICM_CFG0 0x10010
110#define ICM_CFG1 0x10014
111#define ICM_CFG0_L0_MASK 0x07
112#define ICM_CFG0_L1_MASK 0x70
113#define ICM_CFG1_L2_MASK 0x07
114#define ICM_CFG2_L3_MASK 0x70
115#define ICM_CFG_SHIFT 4
116
117/* Inter Connect Matrix allowed protocols */
118#define ICM_PROTOCOL_PD 0x0
119#define ICM_PROTOCOL_PCIE 0x1
120#define ICM_PROTOCOL_SATA 0x2
121#define ICM_PROTOCOL_USB 0x3
122#define ICM_PROTOCOL_DP 0x4
123#define ICM_PROTOCOL_SGMII 0x5
124
125/* Test Mode common reset control parameters */
126#define TM_CMN_RST 0x10018
127#define TM_CMN_RST_EN 0x1
128#define TM_CMN_RST_SET 0x2
129#define TM_CMN_RST_MASK 0x3
130
131/* Bus width parameters */
132#define TX_PROT_BUS_WIDTH 0x10040
133#define RX_PROT_BUS_WIDTH 0x10044
134#define PROT_BUS_WIDTH_10 0x0
135#define PROT_BUS_WIDTH_20 0x1
136#define PROT_BUS_WIDTH_40 0x2
137#define PROT_BUS_WIDTH_SHIFT(n) ((n) * 2)
138#define PROT_BUS_WIDTH_MASK(n) GENMASK((n) * 2 + 1, (n) * 2)
139
140/* Number of GT lanes */
141#define NUM_LANES 4
142
143/* SIOU SATA control register */
144#define SATA_CONTROL_OFFSET 0x0100
145
146/* Total number of controllers */
147#define CONTROLLERS_PER_LANE 5
148
149/* Protocol Type parameters */
150#define XPSGTR_TYPE_USB0 0 /* USB controller 0 */
151#define XPSGTR_TYPE_USB1 1 /* USB controller 1 */
152#define XPSGTR_TYPE_SATA_0 2 /* SATA controller lane 0 */
153#define XPSGTR_TYPE_SATA_1 3 /* SATA controller lane 1 */
154#define XPSGTR_TYPE_PCIE_0 4 /* PCIe controller lane 0 */
155#define XPSGTR_TYPE_PCIE_1 5 /* PCIe controller lane 1 */
156#define XPSGTR_TYPE_PCIE_2 6 /* PCIe controller lane 2 */
157#define XPSGTR_TYPE_PCIE_3 7 /* PCIe controller lane 3 */
158#define XPSGTR_TYPE_DP_0 8 /* Display Port controller lane 0 */
159#define XPSGTR_TYPE_DP_1 9 /* Display Port controller lane 1 */
160#define XPSGTR_TYPE_SGMII0 10 /* Ethernet SGMII controller 0 */
161#define XPSGTR_TYPE_SGMII1 11 /* Ethernet SGMII controller 1 */
162#define XPSGTR_TYPE_SGMII2 12 /* Ethernet SGMII controller 2 */
163#define XPSGTR_TYPE_SGMII3 13 /* Ethernet SGMII controller 3 */
164
165/* Timeout values */
166#define TIMEOUT_US 1000
167
168struct xpsgtr_dev;
169
170/**
171 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
172 * @refclk_rate: PLL reference clock frequency
173 * @pll_ref_clk: value to be written to register for corresponding ref clk rate
174 * @steps: number of steps of SSC (Spread Spectrum Clock)
175 * @step_size: step size of each step
176 */
177struct xpsgtr_ssc {
178 u32 refclk_rate;
179 u8 pll_ref_clk;
180 u32 steps;
181 u32 step_size;
182};
183
184/**
185 * struct xpsgtr_phy - representation of a lane
186 * @phy: pointer to the kernel PHY device
187 * @type: controller which uses this lane
188 * @lane: lane number
189 * @protocol: protocol in which the lane operates
190 * @skip_phy_init: skip phy_init() if true
191 * @dev: pointer to the xpsgtr_dev instance
192 * @refclk: reference clock index
193 */
194struct xpsgtr_phy {
195 struct phy *phy;
196 u8 type;
197 u8 lane;
198 u8 protocol;
199 bool skip_phy_init;
200 struct xpsgtr_dev *dev;
201 unsigned int refclk;
202};
203
204/**
205 * struct xpsgtr_dev - representation of a ZynMP GT device
206 * @dev: pointer to device
207 * @serdes: serdes base address
208 * @siou: siou base address
209 * @gtr_mutex: mutex for locking
210 * @phys: PHY lanes
211 * @refclk_sscs: spread spectrum settings for the reference clocks
212 * @clk: reference clocks
213 * @tx_term_fix: fix for GT issue
214 * @saved_icm_cfg0: stored value of ICM CFG0 register
215 * @saved_icm_cfg1: stored value of ICM CFG1 register
216 */
217struct xpsgtr_dev {
218 struct device *dev;
219 void __iomem *serdes;
220 void __iomem *siou;
221 struct mutex gtr_mutex; /* mutex for locking */
222 struct xpsgtr_phy phys[NUM_LANES];
223 const struct xpsgtr_ssc *refclk_sscs[NUM_LANES];
224 struct clk *clk[NUM_LANES];
225 bool tx_term_fix;
226 unsigned int saved_icm_cfg0;
227 unsigned int saved_icm_cfg1;
228};
229
230/*
231 * Configuration Data
232 */
233
234/* lookup table to hold all settings needed for a ref clock frequency */
235static const struct xpsgtr_ssc ssc_lookup[] = {
236 { 19200000, 0x05, 608, 264020 },
237 { 20000000, 0x06, 634, 243454 },
238 { 24000000, 0x07, 760, 168973 },
239 { 26000000, 0x08, 824, 143860 },
240 { 27000000, 0x09, 856, 86551 },
241 { 38400000, 0x0a, 1218, 65896 },
242 { 40000000, 0x0b, 634, 243454 },
243 { 52000000, 0x0c, 824, 143860 },
244 { 100000000, 0x0d, 1058, 87533 },
245 { 108000000, 0x0e, 856, 86551 },
246 { 125000000, 0x0f, 992, 119497 },
247 { 135000000, 0x10, 1070, 55393 },
248 { 150000000, 0x11, 792, 187091 }
249};
250
251/*
252 * I/O Accessors
253 */
254
255static inline u32 xpsgtr_read(struct xpsgtr_dev *gtr_dev, u32 reg)
256{
257 return readl(gtr_dev->serdes + reg);
258}
259
260static inline void xpsgtr_write(struct xpsgtr_dev *gtr_dev, u32 reg, u32 value)
261{
262 writel(value, gtr_dev->serdes + reg);
263}
264
265static inline void xpsgtr_clr_set(struct xpsgtr_dev *gtr_dev, u32 reg,
266 u32 clr, u32 set)
267{
268 u32 value = xpsgtr_read(gtr_dev, reg);
269
270 value &= ~clr;
271 value |= set;
272 xpsgtr_write(gtr_dev, reg, value);
273}
274
275static inline u32 xpsgtr_read_phy(struct xpsgtr_phy *gtr_phy, u32 reg)
276{
277 void __iomem *addr = gtr_phy->dev->serdes
278 + gtr_phy->lane * PHY_REG_OFFSET + reg;
279
280 return readl(addr);
281}
282
283static inline void xpsgtr_write_phy(struct xpsgtr_phy *gtr_phy,
284 u32 reg, u32 value)
285{
286 void __iomem *addr = gtr_phy->dev->serdes
287 + gtr_phy->lane * PHY_REG_OFFSET + reg;
288
289 writel(value, addr);
290}
291
292static inline void xpsgtr_clr_set_phy(struct xpsgtr_phy *gtr_phy,
293 u32 reg, u32 clr, u32 set)
294{
295 void __iomem *addr = gtr_phy->dev->serdes
296 + gtr_phy->lane * PHY_REG_OFFSET + reg;
297
298 writel((readl(addr) & ~clr) | set, addr);
299}
300
301/*
302 * Hardware Configuration
303 */
304
305/* Wait for the PLL to lock (with a timeout). */
306static int xpsgtr_wait_pll_lock(struct phy *phy)
307{
308 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
309 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
310 unsigned int timeout = TIMEOUT_US;
311 int ret;
312
313 dev_dbg(gtr_dev->dev, "Waiting for PLL lock\n");
314
315 while (1) {
316 u32 reg = xpsgtr_read_phy(gtr_phy, L0_PLL_STATUS_READ_1);
317
318 if ((reg & PLL_STATUS_LOCKED) == PLL_STATUS_LOCKED) {
319 ret = 0;
320 break;
321 }
322
323 if (--timeout == 0) {
324 ret = -ETIMEDOUT;
325 break;
326 }
327
328 udelay(1);
329 }
330
331 if (ret == -ETIMEDOUT)
332 dev_err(gtr_dev->dev,
333 "lane %u (type %u, protocol %u): PLL lock timeout\n",
334 gtr_phy->lane, gtr_phy->type, gtr_phy->protocol);
335
336 return ret;
337}
338
339/* Configure PLL and spread-sprectrum clock. */
340static void xpsgtr_configure_pll(struct xpsgtr_phy *gtr_phy)
341{
342 const struct xpsgtr_ssc *ssc;
343 u32 step_size;
344
345 ssc = gtr_phy->dev->refclk_sscs[gtr_phy->refclk];
346 step_size = ssc->step_size;
347
348 xpsgtr_clr_set(gtr_phy->dev, PLL_REF_SEL(gtr_phy->lane),
349 PLL_FREQ_MASK, ssc->pll_ref_clk);
350
351 /* Enable lane clock sharing, if required */
352 if (gtr_phy->refclk != gtr_phy->lane) {
353 /* Lane3 Ref Clock Selection Register */
354 xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane),
355 L0_REF_CLK_SEL_MASK, 1 << gtr_phy->refclk);
356 }
357
358 /* SSC step size [7:0] */
359 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_0_LSB,
360 STEP_SIZE_0_MASK, step_size & STEP_SIZE_0_MASK);
361
362 /* SSC step size [15:8] */
363 step_size >>= STEP_SIZE_SHIFT;
364 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_1,
365 STEP_SIZE_1_MASK, step_size & STEP_SIZE_1_MASK);
366
367 /* SSC step size [23:16] */
368 step_size >>= STEP_SIZE_SHIFT;
369 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_2,
370 STEP_SIZE_2_MASK, step_size & STEP_SIZE_2_MASK);
371
372 /* SSC steps [7:0] */
373 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEPS_0_LSB,
374 STEPS_0_MASK, ssc->steps & STEPS_0_MASK);
375
376 /* SSC steps [10:8] */
377 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEPS_1_MSB,
378 STEPS_1_MASK,
379 (ssc->steps >> STEP_SIZE_SHIFT) & STEPS_1_MASK);
380
381 /* SSC step size [24:25] */
382 step_size >>= STEP_SIZE_SHIFT;
383 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_3_MSB,
384 STEP_SIZE_3_MASK, (step_size & STEP_SIZE_3_MASK) |
385 FORCE_STEP_SIZE | FORCE_STEPS);
386}
387
388/* Configure the lane protocol. */
389static void xpsgtr_lane_set_protocol(struct xpsgtr_phy *gtr_phy)
390{
391 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
392 u8 protocol = gtr_phy->protocol;
393
394 switch (gtr_phy->lane) {
395 case 0:
396 xpsgtr_clr_set(gtr_dev, ICM_CFG0, ICM_CFG0_L0_MASK, protocol);
397 break;
398 case 1:
399 xpsgtr_clr_set(gtr_dev, ICM_CFG0, ICM_CFG0_L1_MASK,
400 protocol << ICM_CFG_SHIFT);
401 break;
402 case 2:
403 xpsgtr_clr_set(gtr_dev, ICM_CFG1, ICM_CFG0_L0_MASK, protocol);
404 break;
405 case 3:
406 xpsgtr_clr_set(gtr_dev, ICM_CFG1, ICM_CFG0_L1_MASK,
407 protocol << ICM_CFG_SHIFT);
408 break;
409 default:
410 /* We already checked 0 <= lane <= 3 */
411 break;
412 }
413}
414
415/* Bypass (de)scrambler and 8b/10b decoder and encoder. */
416static void xpsgtr_bypass_scrambler_8b10b(struct xpsgtr_phy *gtr_phy)
417{
418 xpsgtr_write_phy(gtr_phy, L0_TM_DIG_6, L0_TM_DIS_DESCRAMBLE_DECODER);
419 xpsgtr_write_phy(gtr_phy, L0_TX_DIG_61, L0_TM_DISABLE_SCRAMBLE_ENCODER);
420}
421
422/* DP-specific initialization. */
423static void xpsgtr_phy_init_dp(struct xpsgtr_phy *gtr_phy)
424{
425 xpsgtr_write_phy(gtr_phy, L0_TXPMD_TM_45,
426 L0_TXPMD_TM_45_OVER_DP_MAIN |
427 L0_TXPMD_TM_45_ENABLE_DP_MAIN |
428 L0_TXPMD_TM_45_OVER_DP_POST1 |
429 L0_TXPMD_TM_45_OVER_DP_POST2 |
430 L0_TXPMD_TM_45_ENABLE_DP_POST2);
431 xpsgtr_write_phy(gtr_phy, L0_TX_ANA_TM_118,
432 L0_TX_ANA_TM_118_FORCE_17_0);
433}
434
435/* SATA-specific initialization. */
436static void xpsgtr_phy_init_sata(struct xpsgtr_phy *gtr_phy)
437{
438 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
439
440 xpsgtr_bypass_scrambler_8b10b(gtr_phy);
441
442 writel(gtr_phy->lane, gtr_dev->siou + SATA_CONTROL_OFFSET);
443}
444
445/* SGMII-specific initialization. */
446static void xpsgtr_phy_init_sgmii(struct xpsgtr_phy *gtr_phy)
447{
448 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
449 u32 mask = PROT_BUS_WIDTH_MASK(gtr_phy->lane);
450 u32 val = PROT_BUS_WIDTH_10 << PROT_BUS_WIDTH_SHIFT(gtr_phy->lane);
451
452 /* Set SGMII protocol TX and RX bus width to 10 bits. */
453 xpsgtr_clr_set(gtr_dev, TX_PROT_BUS_WIDTH, mask, val);
454 xpsgtr_clr_set(gtr_dev, RX_PROT_BUS_WIDTH, mask, val);
455
456 xpsgtr_bypass_scrambler_8b10b(gtr_phy);
457}
458
459/* Configure TX de-emphasis and margining for DP. */
460static void xpsgtr_phy_configure_dp(struct xpsgtr_phy *gtr_phy, unsigned int pre,
461 unsigned int voltage)
462{
463 static const u8 voltage_swing[4][4] = {
464 { 0x2a, 0x27, 0x24, 0x20 },
465 { 0x27, 0x23, 0x20, 0xff },
466 { 0x24, 0x20, 0xff, 0xff },
467 { 0xff, 0xff, 0xff, 0xff }
468 };
469 static const u8 pre_emphasis[4][4] = {
470 { 0x02, 0x02, 0x02, 0x02 },
471 { 0x01, 0x01, 0x01, 0xff },
472 { 0x00, 0x00, 0xff, 0xff },
473 { 0xff, 0xff, 0xff, 0xff }
474 };
475
476 xpsgtr_write_phy(gtr_phy, L0_TXPMD_TM_48, voltage_swing[pre][voltage]);
477 xpsgtr_write_phy(gtr_phy, L0_TX_ANA_TM_18, pre_emphasis[pre][voltage]);
478}
479
480/*
481 * PHY Operations
482 */
483
484static bool xpsgtr_phy_init_required(struct xpsgtr_phy *gtr_phy)
485{
486 /*
487 * As USB may save the snapshot of the states during hibernation, doing
488 * phy_init() will put the USB controller into reset, resulting in the
489 * losing of the saved snapshot. So try to avoid phy_init() for USB
490 * except when gtr_phy->skip_phy_init is false (this happens when FPD is
491 * shutdown during suspend or when gt lane is changed from current one)
492 */
493 if (gtr_phy->protocol == ICM_PROTOCOL_USB && gtr_phy->skip_phy_init)
494 return false;
495 else
496 return true;
497}
498
499/*
500 * There is a functional issue in the GT. The TX termination resistance can be
501 * out of spec due to a issue in the calibration logic. This is the workaround
502 * to fix it, required for XCZU9EG silicon.
503 */
504static int xpsgtr_phy_tx_term_fix(struct xpsgtr_phy *gtr_phy)
505{
506 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
507 u32 timeout = TIMEOUT_US;
508 u32 nsw;
509
510 /* Enabling Test Mode control for CMN Rest */
511 xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_SET);
512
513 /* Set Test Mode reset */
514 xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_EN);
515
516 xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG18, 0x00);
517 xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG19, L3_TM_OVERRIDE_NSW_CODE);
518
519 /*
520 * As a part of work around sequence for PMOS calibration fix,
521 * we need to configure any lane ICM_CFG to valid protocol. This
522 * will deassert the CMN_Resetn signal.
523 */
524 xpsgtr_lane_set_protocol(gtr_phy);
525
526 /* Clear Test Mode reset */
527 xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_SET);
528
529 dev_dbg(gtr_dev->dev, "calibrating...\n");
530
531 do {
532 u32 reg = xpsgtr_read(gtr_dev, L3_CALIB_DONE_STATUS);
533
534 if ((reg & L3_CALIB_DONE) == L3_CALIB_DONE)
535 break;
536
537 if (!--timeout) {
538 dev_err(gtr_dev->dev, "calibration time out\n");
539 return -ETIMEDOUT;
540 }
541
542 udelay(1);
543 } while (timeout > 0);
544
545 dev_dbg(gtr_dev->dev, "calibration done\n");
546
547 /* Reading NMOS Register Code */
548 nsw = xpsgtr_read(gtr_dev, L0_TXPMA_ST_3) & L0_DN_CALIB_CODE;
549
550 /* Set Test Mode reset */
551 xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_EN);
552
553 /* Writing NMOS register values back [5:3] */
554 xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG19, nsw >> L3_NSW_CALIB_SHIFT);
555
556 /* Writing NMOS register value [2:0] */
557 xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG18,
558 ((nsw & L3_TM_CALIB_DIG19_NSW) << L3_NSW_SHIFT) |
559 (1 << L3_NSW_PIPE_SHIFT));
560
561 /* Clear Test Mode reset */
562 xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_SET);
563
564 return 0;
565}
566
567static int xpsgtr_phy_init(struct phy *phy)
568{
569 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
570 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
571 int ret = 0;
572
573 mutex_lock(>r_dev->gtr_mutex);
574
575 /* Skip initialization if not required. */
576 if (!xpsgtr_phy_init_required(gtr_phy))
577 goto out;
578
579 if (gtr_dev->tx_term_fix) {
580 ret = xpsgtr_phy_tx_term_fix(gtr_phy);
581 if (ret < 0)
582 goto out;
583
584 gtr_dev->tx_term_fix = false;
585 }
586
587 /* Enable coarse code saturation limiting logic. */
588 xpsgtr_write_phy(gtr_phy, L0_TM_PLL_DIG_37, L0_TM_COARSE_CODE_LIMIT);
589
590 /*
591 * Configure the PLL, the lane protocol, and perform protocol-specific
592 * initialization.
593 */
594 xpsgtr_configure_pll(gtr_phy);
595 xpsgtr_lane_set_protocol(gtr_phy);
596
597 switch (gtr_phy->protocol) {
598 case ICM_PROTOCOL_DP:
599 xpsgtr_phy_init_dp(gtr_phy);
600 break;
601
602 case ICM_PROTOCOL_SATA:
603 xpsgtr_phy_init_sata(gtr_phy);
604 break;
605
606 case ICM_PROTOCOL_SGMII:
607 xpsgtr_phy_init_sgmii(gtr_phy);
608 break;
609 }
610
611out:
612 mutex_unlock(>r_dev->gtr_mutex);
613 return ret;
614}
615
616static int xpsgtr_phy_exit(struct phy *phy)
617{
618 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
619
620 gtr_phy->skip_phy_init = false;
621
622 return 0;
623}
624
625static int xpsgtr_phy_power_on(struct phy *phy)
626{
627 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
628 int ret = 0;
629
630 /* Skip initialization if not required. */
631 if (!xpsgtr_phy_init_required(gtr_phy))
632 return ret;
633 /*
634 * Wait for the PLL to lock. For DP, only wait on DP0 to avoid
635 * cumulating waits for both lanes. The user is expected to initialize
636 * lane 0 last.
637 */
638 if (gtr_phy->protocol != ICM_PROTOCOL_DP ||
639 gtr_phy->type == XPSGTR_TYPE_DP_0)
640 ret = xpsgtr_wait_pll_lock(phy);
641
642 return ret;
643}
644
645static int xpsgtr_phy_configure(struct phy *phy, union phy_configure_opts *opts)
646{
647 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
648
649 if (gtr_phy->protocol != ICM_PROTOCOL_DP)
650 return 0;
651
652 xpsgtr_phy_configure_dp(gtr_phy, opts->dp.pre[0], opts->dp.voltage[0]);
653
654 return 0;
655}
656
657static const struct phy_ops xpsgtr_phyops = {
658 .init = xpsgtr_phy_init,
659 .exit = xpsgtr_phy_exit,
660 .power_on = xpsgtr_phy_power_on,
661 .configure = xpsgtr_phy_configure,
662 .owner = THIS_MODULE,
663};
664
665/*
666 * OF Xlate Support
667 */
668
669/* Set the lane type and protocol based on the PHY type and instance number. */
670static int xpsgtr_set_lane_type(struct xpsgtr_phy *gtr_phy, u8 phy_type,
671 unsigned int phy_instance)
672{
673 unsigned int num_phy_types;
674 const int *phy_types;
675
676 switch (phy_type) {
677 case PHY_TYPE_SATA: {
678 static const int types[] = {
679 XPSGTR_TYPE_SATA_0,
680 XPSGTR_TYPE_SATA_1,
681 };
682
683 phy_types = types;
684 num_phy_types = ARRAY_SIZE(types);
685 gtr_phy->protocol = ICM_PROTOCOL_SATA;
686 break;
687 }
688 case PHY_TYPE_USB3: {
689 static const int types[] = {
690 XPSGTR_TYPE_USB0,
691 XPSGTR_TYPE_USB1,
692 };
693
694 phy_types = types;
695 num_phy_types = ARRAY_SIZE(types);
696 gtr_phy->protocol = ICM_PROTOCOL_USB;
697 break;
698 }
699 case PHY_TYPE_DP: {
700 static const int types[] = {
701 XPSGTR_TYPE_DP_0,
702 XPSGTR_TYPE_DP_1,
703 };
704
705 phy_types = types;
706 num_phy_types = ARRAY_SIZE(types);
707 gtr_phy->protocol = ICM_PROTOCOL_DP;
708 break;
709 }
710 case PHY_TYPE_PCIE: {
711 static const int types[] = {
712 XPSGTR_TYPE_PCIE_0,
713 XPSGTR_TYPE_PCIE_1,
714 XPSGTR_TYPE_PCIE_2,
715 XPSGTR_TYPE_PCIE_3,
716 };
717
718 phy_types = types;
719 num_phy_types = ARRAY_SIZE(types);
720 gtr_phy->protocol = ICM_PROTOCOL_PCIE;
721 break;
722 }
723 case PHY_TYPE_SGMII: {
724 static const int types[] = {
725 XPSGTR_TYPE_SGMII0,
726 XPSGTR_TYPE_SGMII1,
727 XPSGTR_TYPE_SGMII2,
728 XPSGTR_TYPE_SGMII3,
729 };
730
731 phy_types = types;
732 num_phy_types = ARRAY_SIZE(types);
733 gtr_phy->protocol = ICM_PROTOCOL_SGMII;
734 break;
735 }
736 default:
737 return -EINVAL;
738 }
739
740 if (phy_instance >= num_phy_types)
741 return -EINVAL;
742
743 gtr_phy->type = phy_types[phy_instance];
744 return 0;
745}
746
747/*
748 * Valid combinations of controllers and lanes (Interconnect Matrix).
749 */
750static const unsigned int icm_matrix[NUM_LANES][CONTROLLERS_PER_LANE] = {
751 { XPSGTR_TYPE_PCIE_0, XPSGTR_TYPE_SATA_0, XPSGTR_TYPE_USB0,
752 XPSGTR_TYPE_DP_1, XPSGTR_TYPE_SGMII0 },
753 { XPSGTR_TYPE_PCIE_1, XPSGTR_TYPE_SATA_1, XPSGTR_TYPE_USB0,
754 XPSGTR_TYPE_DP_0, XPSGTR_TYPE_SGMII1 },
755 { XPSGTR_TYPE_PCIE_2, XPSGTR_TYPE_SATA_0, XPSGTR_TYPE_USB0,
756 XPSGTR_TYPE_DP_1, XPSGTR_TYPE_SGMII2 },
757 { XPSGTR_TYPE_PCIE_3, XPSGTR_TYPE_SATA_1, XPSGTR_TYPE_USB1,
758 XPSGTR_TYPE_DP_0, XPSGTR_TYPE_SGMII3 }
759};
760
761/* Translate OF phandle and args to PHY instance. */
762static struct phy *xpsgtr_xlate(struct device *dev,
763 struct of_phandle_args *args)
764{
765 struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev);
766 struct xpsgtr_phy *gtr_phy;
767 unsigned int phy_instance;
768 unsigned int phy_lane;
769 unsigned int phy_type;
770 unsigned int refclk;
771 unsigned int i;
772 int ret;
773
774 if (args->args_count != 4) {
775 dev_err(dev, "Invalid number of cells in 'phy' property\n");
776 return ERR_PTR(-EINVAL);
777 }
778
779 /*
780 * Get the PHY parameters from the OF arguments and derive the lane
781 * type.
782 */
783 phy_lane = args->args[0];
784 if (phy_lane >= ARRAY_SIZE(gtr_dev->phys)) {
785 dev_err(dev, "Invalid lane number %u\n", phy_lane);
786 return ERR_PTR(-ENODEV);
787 }
788
789 gtr_phy = >r_dev->phys[phy_lane];
790 phy_type = args->args[1];
791 phy_instance = args->args[2];
792
793 ret = xpsgtr_set_lane_type(gtr_phy, phy_type, phy_instance);
794 if (ret < 0) {
795 dev_err(gtr_dev->dev, "Invalid PHY type and/or instance\n");
796 return ERR_PTR(ret);
797 }
798
799 refclk = args->args[3];
800 if (refclk >= ARRAY_SIZE(gtr_dev->refclk_sscs) ||
801 !gtr_dev->refclk_sscs[refclk]) {
802 dev_err(dev, "Invalid reference clock number %u\n", refclk);
803 return ERR_PTR(-EINVAL);
804 }
805
806 gtr_phy->refclk = refclk;
807
808 /*
809 * Ensure that the Interconnect Matrix is obeyed, i.e a given lane type
810 * is allowed to operate on the lane.
811 */
812 for (i = 0; i < CONTROLLERS_PER_LANE; i++) {
813 if (icm_matrix[phy_lane][i] == gtr_phy->type)
814 return gtr_phy->phy;
815 }
816
817 return ERR_PTR(-EINVAL);
818}
819
820/*
821 * Power Management
822 */
823
824static int __maybe_unused xpsgtr_suspend(struct device *dev)
825{
826 struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev);
827 unsigned int i;
828
829 /* Save the snapshot ICM_CFG registers. */
830 gtr_dev->saved_icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0);
831 gtr_dev->saved_icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1);
832
833 for (i = 0; i < ARRAY_SIZE(gtr_dev->clk); i++)
834 clk_disable_unprepare(gtr_dev->clk[i]);
835
836 return 0;
837}
838
839static int __maybe_unused xpsgtr_resume(struct device *dev)
840{
841 struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev);
842 unsigned int icm_cfg0, icm_cfg1;
843 unsigned int i;
844 bool skip_phy_init;
845 int err;
846
847 for (i = 0; i < ARRAY_SIZE(gtr_dev->clk); i++) {
848 err = clk_prepare_enable(gtr_dev->clk[i]);
849 if (err)
850 goto err_clk_put;
851 }
852
853 icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0);
854 icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1);
855
856 /* Return if no GT lanes got configured before suspend. */
857 if (!gtr_dev->saved_icm_cfg0 && !gtr_dev->saved_icm_cfg1)
858 return 0;
859
860 /* Check if the ICM configurations changed after suspend. */
861 if (icm_cfg0 == gtr_dev->saved_icm_cfg0 &&
862 icm_cfg1 == gtr_dev->saved_icm_cfg1)
863 skip_phy_init = true;
864 else
865 skip_phy_init = false;
866
867 /* Update the skip_phy_init for all gtr_phy instances. */
868 for (i = 0; i < ARRAY_SIZE(gtr_dev->phys); i++)
869 gtr_dev->phys[i].skip_phy_init = skip_phy_init;
870
871 return 0;
872
873err_clk_put:
874 while (i--)
875 clk_disable_unprepare(gtr_dev->clk[i]);
876
877 return err;
878}
879
880static const struct dev_pm_ops xpsgtr_pm_ops = {
881 SET_SYSTEM_SLEEP_PM_OPS(xpsgtr_suspend, xpsgtr_resume)
882};
883
884/*
885 * Probe & Platform Driver
886 */
887
888static int xpsgtr_get_ref_clocks(struct xpsgtr_dev *gtr_dev)
889{
890 unsigned int refclk;
891 int ret;
892
893 for (refclk = 0; refclk < ARRAY_SIZE(gtr_dev->refclk_sscs); ++refclk) {
894 unsigned long rate;
895 unsigned int i;
896 struct clk *clk;
897 char name[8];
898
899 snprintf(name, sizeof(name), "ref%u", refclk);
900 clk = devm_clk_get_optional(gtr_dev->dev, name);
901 if (IS_ERR(clk)) {
902 ret = dev_err_probe(gtr_dev->dev, PTR_ERR(clk),
903 "Failed to get reference clock %u\n",
904 refclk);
905 goto err_clk_put;
906 }
907
908 if (!clk)
909 continue;
910
911 ret = clk_prepare_enable(clk);
912 if (ret)
913 goto err_clk_put;
914
915 gtr_dev->clk[refclk] = clk;
916
917 /*
918 * Get the spread spectrum (SSC) settings for the reference
919 * clock rate.
920 */
921 rate = clk_get_rate(clk);
922
923 for (i = 0 ; i < ARRAY_SIZE(ssc_lookup); i++) {
924 if (rate == ssc_lookup[i].refclk_rate) {
925 gtr_dev->refclk_sscs[refclk] = &ssc_lookup[i];
926 break;
927 }
928 }
929
930 if (i == ARRAY_SIZE(ssc_lookup)) {
931 dev_err(gtr_dev->dev,
932 "Invalid rate %lu for reference clock %u\n",
933 rate, refclk);
934 ret = -EINVAL;
935 goto err_clk_put;
936 }
937 }
938
939 return 0;
940
941err_clk_put:
942 while (refclk--)
943 clk_disable_unprepare(gtr_dev->clk[refclk]);
944
945 return ret;
946}
947
948static int xpsgtr_probe(struct platform_device *pdev)
949{
950 struct device_node *np = pdev->dev.of_node;
951 struct xpsgtr_dev *gtr_dev;
952 struct phy_provider *provider;
953 unsigned int port;
954 unsigned int i;
955 int ret;
956
957 gtr_dev = devm_kzalloc(&pdev->dev, sizeof(*gtr_dev), GFP_KERNEL);
958 if (!gtr_dev)
959 return -ENOMEM;
960
961 gtr_dev->dev = &pdev->dev;
962 platform_set_drvdata(pdev, gtr_dev);
963
964 mutex_init(>r_dev->gtr_mutex);
965
966 if (of_device_is_compatible(np, "xlnx,zynqmp-psgtr"))
967 gtr_dev->tx_term_fix =
968 of_property_read_bool(np, "xlnx,tx-termination-fix");
969
970 /* Acquire resources. */
971 gtr_dev->serdes = devm_platform_ioremap_resource_byname(pdev, "serdes");
972 if (IS_ERR(gtr_dev->serdes))
973 return PTR_ERR(gtr_dev->serdes);
974
975 gtr_dev->siou = devm_platform_ioremap_resource_byname(pdev, "siou");
976 if (IS_ERR(gtr_dev->siou))
977 return PTR_ERR(gtr_dev->siou);
978
979 ret = xpsgtr_get_ref_clocks(gtr_dev);
980 if (ret)
981 return ret;
982
983 /* Create PHYs. */
984 for (port = 0; port < ARRAY_SIZE(gtr_dev->phys); ++port) {
985 struct xpsgtr_phy *gtr_phy = >r_dev->phys[port];
986 struct phy *phy;
987
988 gtr_phy->lane = port;
989 gtr_phy->dev = gtr_dev;
990
991 phy = devm_phy_create(&pdev->dev, np, &xpsgtr_phyops);
992 if (IS_ERR(phy)) {
993 dev_err(&pdev->dev, "failed to create PHY\n");
994 ret = PTR_ERR(phy);
995 goto err_clk_put;
996 }
997
998 gtr_phy->phy = phy;
999 phy_set_drvdata(phy, gtr_phy);
1000 }
1001
1002 /* Register the PHY provider. */
1003 provider = devm_of_phy_provider_register(&pdev->dev, xpsgtr_xlate);
1004 if (IS_ERR(provider)) {
1005 dev_err(&pdev->dev, "registering provider failed\n");
1006 ret = PTR_ERR(provider);
1007 goto err_clk_put;
1008 }
1009 return 0;
1010
1011err_clk_put:
1012 for (i = 0; i < ARRAY_SIZE(gtr_dev->clk); i++)
1013 clk_disable_unprepare(gtr_dev->clk[i]);
1014
1015 return ret;
1016}
1017
1018static const struct of_device_id xpsgtr_of_match[] = {
1019 { .compatible = "xlnx,zynqmp-psgtr", },
1020 { .compatible = "xlnx,zynqmp-psgtr-v1.1", },
1021 {},
1022};
1023MODULE_DEVICE_TABLE(of, xpsgtr_of_match);
1024
1025static struct platform_driver xpsgtr_driver = {
1026 .probe = xpsgtr_probe,
1027 .driver = {
1028 .name = "xilinx-psgtr",
1029 .of_match_table = xpsgtr_of_match,
1030 .pm = &xpsgtr_pm_ops,
1031 },
1032};
1033
1034module_platform_driver(xpsgtr_driver);
1035
1036MODULE_AUTHOR("Xilinx Inc.");
1037MODULE_LICENSE("GPL v2");
1038MODULE_DESCRIPTION("Xilinx ZynqMP High speed Gigabit Transceiver");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
4 *
5 * Copyright (C) 2018-2020 Xilinx Inc.
6 *
7 * Author: Anurag Kumar Vulisha <anuragku@xilinx.com>
8 * Author: Subbaraya Sundeep <sundeep.lkml@gmail.com>
9 * Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 *
11 * This driver is tested for USB, SGMII, SATA and Display Port currently.
12 * PCIe should also work but that is experimental as of now.
13 */
14
15#include <linux/clk.h>
16#include <linux/debugfs.h>
17#include <linux/delay.h>
18#include <linux/io.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/phy/phy.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25#include <linux/slab.h>
26
27#include <dt-bindings/phy/phy.h>
28
29/*
30 * Lane Registers
31 */
32
33/* TX De-emphasis parameters */
34#define L0_TX_ANA_TM_18 0x0048
35#define L0_TX_ANA_TM_118 0x01d8
36#define L0_TX_ANA_TM_118_FORCE_17_0 BIT(0)
37
38/* DN Resistor calibration code parameters */
39#define L0_TXPMA_ST_3 0x0b0c
40#define L0_DN_CALIB_CODE 0x3f
41
42/* PMA control parameters */
43#define L0_TXPMD_TM_45 0x0cb4
44#define L0_TXPMD_TM_48 0x0cc0
45#define L0_TXPMD_TM_45_OVER_DP_MAIN BIT(0)
46#define L0_TXPMD_TM_45_ENABLE_DP_MAIN BIT(1)
47#define L0_TXPMD_TM_45_OVER_DP_POST1 BIT(2)
48#define L0_TXPMD_TM_45_ENABLE_DP_POST1 BIT(3)
49#define L0_TXPMD_TM_45_OVER_DP_POST2 BIT(4)
50#define L0_TXPMD_TM_45_ENABLE_DP_POST2 BIT(5)
51
52/* PCS control parameters */
53#define L0_TM_DIG_6 0x106c
54#define L0_TM_DIS_DESCRAMBLE_DECODER 0x0f
55#define L0_TX_DIG_61 0x00f4
56#define L0_TM_DISABLE_SCRAMBLE_ENCODER 0x0f
57
58/* PLL Test Mode register parameters */
59#define L0_TM_PLL_DIG_37 0x2094
60#define L0_TM_COARSE_CODE_LIMIT 0x10
61
62/* PLL SSC step size offsets */
63#define L0_PLL_SS_STEPS_0_LSB 0x2368
64#define L0_PLL_SS_STEPS_1_MSB 0x236c
65#define L0_PLL_SS_STEP_SIZE_0_LSB 0x2370
66#define L0_PLL_SS_STEP_SIZE_1 0x2374
67#define L0_PLL_SS_STEP_SIZE_2 0x2378
68#define L0_PLL_SS_STEP_SIZE_3_MSB 0x237c
69#define L0_PLL_STATUS_READ_1 0x23e4
70
71/* SSC step size parameters */
72#define STEP_SIZE_0_MASK 0xff
73#define STEP_SIZE_1_MASK 0xff
74#define STEP_SIZE_2_MASK 0xff
75#define STEP_SIZE_3_MASK 0x3
76#define STEP_SIZE_SHIFT 8
77#define FORCE_STEP_SIZE 0x10
78#define FORCE_STEPS 0x20
79#define STEPS_0_MASK 0xff
80#define STEPS_1_MASK 0x07
81
82/* Reference clock selection parameters */
83#define L0_Ln_REF_CLK_SEL(n) (0x2860 + (n) * 4)
84#define L0_REF_CLK_LCL_SEL BIT(7)
85#define L0_REF_CLK_SEL_MASK 0x9f
86
87/* Calibration digital logic parameters */
88#define L3_TM_CALIB_DIG19 0xec4c
89#define L3_CALIB_DONE_STATUS 0xef14
90#define L3_TM_CALIB_DIG18 0xec48
91#define L3_TM_CALIB_DIG19_NSW 0x07
92#define L3_TM_CALIB_DIG18_NSW 0xe0
93#define L3_TM_OVERRIDE_NSW_CODE 0x20
94#define L3_CALIB_DONE 0x02
95#define L3_NSW_SHIFT 5
96#define L3_NSW_PIPE_SHIFT 4
97#define L3_NSW_CALIB_SHIFT 3
98
99#define PHY_REG_OFFSET 0x4000
100
101/*
102 * Global Registers
103 */
104
105/* Refclk selection parameters */
106#define PLL_REF_SEL(n) (0x10000 + (n) * 4)
107#define PLL_FREQ_MASK 0x1f
108#define PLL_STATUS_LOCKED 0x10
109
110/* Inter Connect Matrix parameters */
111#define ICM_CFG0 0x10010
112#define ICM_CFG1 0x10014
113#define ICM_CFG0_L0_MASK 0x07
114#define ICM_CFG0_L1_MASK 0x70
115#define ICM_CFG1_L2_MASK 0x07
116#define ICM_CFG2_L3_MASK 0x70
117#define ICM_CFG_SHIFT 4
118
119/* Inter Connect Matrix allowed protocols */
120#define ICM_PROTOCOL_PD 0x0
121#define ICM_PROTOCOL_PCIE 0x1
122#define ICM_PROTOCOL_SATA 0x2
123#define ICM_PROTOCOL_USB 0x3
124#define ICM_PROTOCOL_DP 0x4
125#define ICM_PROTOCOL_SGMII 0x5
126
127static const char *const xpsgtr_icm_str[] = {
128 [ICM_PROTOCOL_PD] = "none",
129 [ICM_PROTOCOL_PCIE] = "PCIe",
130 [ICM_PROTOCOL_SATA] = "SATA",
131 [ICM_PROTOCOL_USB] = "USB",
132 [ICM_PROTOCOL_DP] = "DisplayPort",
133 [ICM_PROTOCOL_SGMII] = "SGMII",
134};
135
136/* Test Mode common reset control parameters */
137#define TM_CMN_RST 0x10018
138#define TM_CMN_RST_EN 0x1
139#define TM_CMN_RST_SET 0x2
140#define TM_CMN_RST_MASK 0x3
141
142/* Bus width parameters */
143#define TX_PROT_BUS_WIDTH 0x10040
144#define RX_PROT_BUS_WIDTH 0x10044
145#define PROT_BUS_WIDTH_10 0x0
146#define PROT_BUS_WIDTH_20 0x1
147#define PROT_BUS_WIDTH_40 0x2
148#define PROT_BUS_WIDTH_SHIFT(n) ((n) * 2)
149#define PROT_BUS_WIDTH_MASK(n) GENMASK((n) * 2 + 1, (n) * 2)
150
151/* Number of GT lanes */
152#define NUM_LANES 4
153
154/* SIOU SATA control register */
155#define SATA_CONTROL_OFFSET 0x0100
156
157/* Total number of controllers */
158#define CONTROLLERS_PER_LANE 5
159
160/* Timeout values */
161#define TIMEOUT_US 1000
162
163/* Lane 0/1/2/3 offset */
164#define DIG_8(n) ((0x4000 * (n)) + 0x1074)
165#define ILL13(n) ((0x4000 * (n)) + 0x1994)
166#define DIG_10(n) ((0x4000 * (n)) + 0x107c)
167#define RST_DLY(n) ((0x4000 * (n)) + 0x19a4)
168#define BYP_15(n) ((0x4000 * (n)) + 0x1038)
169#define BYP_12(n) ((0x4000 * (n)) + 0x102c)
170#define MISC3(n) ((0x4000 * (n)) + 0x19ac)
171#define EQ11(n) ((0x4000 * (n)) + 0x1978)
172
173static u32 save_reg_address[] = {
174 /* Lane 0/1/2/3 Register */
175 DIG_8(0), ILL13(0), DIG_10(0), RST_DLY(0), BYP_15(0), BYP_12(0), MISC3(0), EQ11(0),
176 DIG_8(1), ILL13(1), DIG_10(1), RST_DLY(1), BYP_15(1), BYP_12(1), MISC3(1), EQ11(1),
177 DIG_8(2), ILL13(2), DIG_10(2), RST_DLY(2), BYP_15(2), BYP_12(2), MISC3(2), EQ11(2),
178 DIG_8(3), ILL13(3), DIG_10(3), RST_DLY(3), BYP_15(3), BYP_12(3), MISC3(3), EQ11(3),
179};
180
181struct xpsgtr_dev;
182
183/**
184 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
185 * @refclk_rate: PLL reference clock frequency
186 * @pll_ref_clk: value to be written to register for corresponding ref clk rate
187 * @steps: number of steps of SSC (Spread Spectrum Clock)
188 * @step_size: step size of each step
189 */
190struct xpsgtr_ssc {
191 u32 refclk_rate;
192 u8 pll_ref_clk;
193 u32 steps;
194 u32 step_size;
195};
196
197/**
198 * struct xpsgtr_phy - representation of a lane
199 * @phy: pointer to the kernel PHY device
200 * @instance: instance of the protocol type (such as the lane within a
201 * protocol, or the USB/Ethernet controller)
202 * @lane: lane number
203 * @protocol: protocol in which the lane operates
204 * @skip_phy_init: skip phy_init() if true
205 * @dev: pointer to the xpsgtr_dev instance
206 * @refclk: reference clock index
207 */
208struct xpsgtr_phy {
209 struct phy *phy;
210 u8 instance;
211 u8 lane;
212 u8 protocol;
213 bool skip_phy_init;
214 struct xpsgtr_dev *dev;
215 unsigned int refclk;
216};
217
218/**
219 * struct xpsgtr_dev - representation of a ZynMP GT device
220 * @dev: pointer to device
221 * @serdes: serdes base address
222 * @siou: siou base address
223 * @gtr_mutex: mutex for locking
224 * @phys: PHY lanes
225 * @refclk_sscs: spread spectrum settings for the reference clocks
226 * @clk: reference clocks
227 * @tx_term_fix: fix for GT issue
228 * @saved_icm_cfg0: stored value of ICM CFG0 register
229 * @saved_icm_cfg1: stored value of ICM CFG1 register
230 * @saved_regs: registers to be saved/restored during suspend/resume
231 */
232struct xpsgtr_dev {
233 struct device *dev;
234 void __iomem *serdes;
235 void __iomem *siou;
236 struct mutex gtr_mutex; /* mutex for locking */
237 struct xpsgtr_phy phys[NUM_LANES];
238 const struct xpsgtr_ssc *refclk_sscs[NUM_LANES];
239 struct clk *clk[NUM_LANES];
240 bool tx_term_fix;
241 unsigned int saved_icm_cfg0;
242 unsigned int saved_icm_cfg1;
243 u32 *saved_regs;
244};
245
246/*
247 * Configuration Data
248 */
249
250/* lookup table to hold all settings needed for a ref clock frequency */
251static const struct xpsgtr_ssc ssc_lookup[] = {
252 { 19200000, 0x05, 608, 264020 },
253 { 20000000, 0x06, 634, 243454 },
254 { 24000000, 0x07, 760, 168973 },
255 { 26000000, 0x08, 824, 143860 },
256 { 27000000, 0x09, 856, 86551 },
257 { 38400000, 0x0a, 1218, 65896 },
258 { 40000000, 0x0b, 634, 243454 },
259 { 52000000, 0x0c, 824, 143860 },
260 { 100000000, 0x0d, 1058, 87533 },
261 { 108000000, 0x0e, 856, 86551 },
262 { 125000000, 0x0f, 992, 119497 },
263 { 135000000, 0x10, 1070, 55393 },
264 { 150000000, 0x11, 792, 187091 }
265};
266
267/*
268 * I/O Accessors
269 */
270
271static inline u32 xpsgtr_read(struct xpsgtr_dev *gtr_dev, u32 reg)
272{
273 return readl(gtr_dev->serdes + reg);
274}
275
276static inline void xpsgtr_write(struct xpsgtr_dev *gtr_dev, u32 reg, u32 value)
277{
278 writel(value, gtr_dev->serdes + reg);
279}
280
281static inline void xpsgtr_clr_set(struct xpsgtr_dev *gtr_dev, u32 reg,
282 u32 clr, u32 set)
283{
284 u32 value = xpsgtr_read(gtr_dev, reg);
285
286 value &= ~clr;
287 value |= set;
288 xpsgtr_write(gtr_dev, reg, value);
289}
290
291static inline u32 xpsgtr_read_phy(struct xpsgtr_phy *gtr_phy, u32 reg)
292{
293 void __iomem *addr = gtr_phy->dev->serdes
294 + gtr_phy->lane * PHY_REG_OFFSET + reg;
295
296 return readl(addr);
297}
298
299static inline void xpsgtr_write_phy(struct xpsgtr_phy *gtr_phy,
300 u32 reg, u32 value)
301{
302 void __iomem *addr = gtr_phy->dev->serdes
303 + gtr_phy->lane * PHY_REG_OFFSET + reg;
304
305 writel(value, addr);
306}
307
308static inline void xpsgtr_clr_set_phy(struct xpsgtr_phy *gtr_phy,
309 u32 reg, u32 clr, u32 set)
310{
311 void __iomem *addr = gtr_phy->dev->serdes
312 + gtr_phy->lane * PHY_REG_OFFSET + reg;
313
314 writel((readl(addr) & ~clr) | set, addr);
315}
316
317/**
318 * xpsgtr_save_lane_regs - Saves registers on suspend
319 * @gtr_dev: pointer to phy controller context structure
320 */
321static void xpsgtr_save_lane_regs(struct xpsgtr_dev *gtr_dev)
322{
323 int i;
324
325 for (i = 0; i < ARRAY_SIZE(save_reg_address); i++)
326 gtr_dev->saved_regs[i] = xpsgtr_read(gtr_dev,
327 save_reg_address[i]);
328}
329
330/**
331 * xpsgtr_restore_lane_regs - Restores registers on resume
332 * @gtr_dev: pointer to phy controller context structure
333 */
334static void xpsgtr_restore_lane_regs(struct xpsgtr_dev *gtr_dev)
335{
336 int i;
337
338 for (i = 0; i < ARRAY_SIZE(save_reg_address); i++)
339 xpsgtr_write(gtr_dev, save_reg_address[i],
340 gtr_dev->saved_regs[i]);
341}
342
343/*
344 * Hardware Configuration
345 */
346
347/* Wait for the PLL to lock (with a timeout). */
348static int xpsgtr_wait_pll_lock(struct phy *phy)
349{
350 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
351 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
352 unsigned int timeout = TIMEOUT_US;
353 u8 protocol = gtr_phy->protocol;
354 int ret;
355
356 dev_dbg(gtr_dev->dev, "Waiting for PLL lock\n");
357
358 /*
359 * For DP and PCIe, only the instance 0 PLL is used. Switch to that phy
360 * so we wait on the right PLL.
361 */
362 if ((protocol == ICM_PROTOCOL_DP || protocol == ICM_PROTOCOL_PCIE) &&
363 gtr_phy->instance) {
364 int i;
365
366 for (i = 0; i < NUM_LANES; i++) {
367 gtr_phy = >r_dev->phys[i];
368
369 if (gtr_phy->protocol == protocol && !gtr_phy->instance)
370 goto got_phy;
371 }
372
373 return -EBUSY;
374 }
375
376got_phy:
377 while (1) {
378 u32 reg = xpsgtr_read_phy(gtr_phy, L0_PLL_STATUS_READ_1);
379
380 if ((reg & PLL_STATUS_LOCKED) == PLL_STATUS_LOCKED) {
381 ret = 0;
382 break;
383 }
384
385 if (--timeout == 0) {
386 ret = -ETIMEDOUT;
387 break;
388 }
389
390 udelay(1);
391 }
392
393 if (ret == -ETIMEDOUT)
394 dev_err(gtr_dev->dev,
395 "lane %u (protocol %u, instance %u): PLL lock timeout\n",
396 gtr_phy->lane, gtr_phy->protocol, gtr_phy->instance);
397
398 return ret;
399}
400
401/* Configure PLL and spread-sprectrum clock. */
402static void xpsgtr_configure_pll(struct xpsgtr_phy *gtr_phy)
403{
404 const struct xpsgtr_ssc *ssc;
405 u32 step_size;
406
407 ssc = gtr_phy->dev->refclk_sscs[gtr_phy->refclk];
408 step_size = ssc->step_size;
409
410 xpsgtr_clr_set(gtr_phy->dev, PLL_REF_SEL(gtr_phy->lane),
411 PLL_FREQ_MASK, ssc->pll_ref_clk);
412
413 /* Enable lane clock sharing, if required */
414 if (gtr_phy->refclk == gtr_phy->lane)
415 xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane),
416 L0_REF_CLK_SEL_MASK, L0_REF_CLK_LCL_SEL);
417 else
418 xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane),
419 L0_REF_CLK_SEL_MASK, 1 << gtr_phy->refclk);
420
421 /* SSC step size [7:0] */
422 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_0_LSB,
423 STEP_SIZE_0_MASK, step_size & STEP_SIZE_0_MASK);
424
425 /* SSC step size [15:8] */
426 step_size >>= STEP_SIZE_SHIFT;
427 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_1,
428 STEP_SIZE_1_MASK, step_size & STEP_SIZE_1_MASK);
429
430 /* SSC step size [23:16] */
431 step_size >>= STEP_SIZE_SHIFT;
432 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_2,
433 STEP_SIZE_2_MASK, step_size & STEP_SIZE_2_MASK);
434
435 /* SSC steps [7:0] */
436 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEPS_0_LSB,
437 STEPS_0_MASK, ssc->steps & STEPS_0_MASK);
438
439 /* SSC steps [10:8] */
440 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEPS_1_MSB,
441 STEPS_1_MASK,
442 (ssc->steps >> STEP_SIZE_SHIFT) & STEPS_1_MASK);
443
444 /* SSC step size [24:25] */
445 step_size >>= STEP_SIZE_SHIFT;
446 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_3_MSB,
447 STEP_SIZE_3_MASK, (step_size & STEP_SIZE_3_MASK) |
448 FORCE_STEP_SIZE | FORCE_STEPS);
449}
450
451/* Configure the lane protocol. */
452static void xpsgtr_lane_set_protocol(struct xpsgtr_phy *gtr_phy)
453{
454 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
455 u8 protocol = gtr_phy->protocol;
456
457 switch (gtr_phy->lane) {
458 case 0:
459 xpsgtr_clr_set(gtr_dev, ICM_CFG0, ICM_CFG0_L0_MASK, protocol);
460 break;
461 case 1:
462 xpsgtr_clr_set(gtr_dev, ICM_CFG0, ICM_CFG0_L1_MASK,
463 protocol << ICM_CFG_SHIFT);
464 break;
465 case 2:
466 xpsgtr_clr_set(gtr_dev, ICM_CFG1, ICM_CFG0_L0_MASK, protocol);
467 break;
468 case 3:
469 xpsgtr_clr_set(gtr_dev, ICM_CFG1, ICM_CFG0_L1_MASK,
470 protocol << ICM_CFG_SHIFT);
471 break;
472 default:
473 /* We already checked 0 <= lane <= 3 */
474 break;
475 }
476}
477
478/* Bypass (de)scrambler and 8b/10b decoder and encoder. */
479static void xpsgtr_bypass_scrambler_8b10b(struct xpsgtr_phy *gtr_phy)
480{
481 xpsgtr_write_phy(gtr_phy, L0_TM_DIG_6, L0_TM_DIS_DESCRAMBLE_DECODER);
482 xpsgtr_write_phy(gtr_phy, L0_TX_DIG_61, L0_TM_DISABLE_SCRAMBLE_ENCODER);
483}
484
485/* DP-specific initialization. */
486static void xpsgtr_phy_init_dp(struct xpsgtr_phy *gtr_phy)
487{
488 xpsgtr_write_phy(gtr_phy, L0_TXPMD_TM_45,
489 L0_TXPMD_TM_45_OVER_DP_MAIN |
490 L0_TXPMD_TM_45_ENABLE_DP_MAIN |
491 L0_TXPMD_TM_45_OVER_DP_POST1 |
492 L0_TXPMD_TM_45_OVER_DP_POST2 |
493 L0_TXPMD_TM_45_ENABLE_DP_POST2);
494 xpsgtr_write_phy(gtr_phy, L0_TX_ANA_TM_118,
495 L0_TX_ANA_TM_118_FORCE_17_0);
496}
497
498/* SATA-specific initialization. */
499static void xpsgtr_phy_init_sata(struct xpsgtr_phy *gtr_phy)
500{
501 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
502
503 xpsgtr_bypass_scrambler_8b10b(gtr_phy);
504
505 writel(gtr_phy->lane, gtr_dev->siou + SATA_CONTROL_OFFSET);
506}
507
508/* SGMII-specific initialization. */
509static void xpsgtr_phy_init_sgmii(struct xpsgtr_phy *gtr_phy)
510{
511 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
512 u32 mask = PROT_BUS_WIDTH_MASK(gtr_phy->lane);
513 u32 val = PROT_BUS_WIDTH_10 << PROT_BUS_WIDTH_SHIFT(gtr_phy->lane);
514
515 /* Set SGMII protocol TX and RX bus width to 10 bits. */
516 xpsgtr_clr_set(gtr_dev, TX_PROT_BUS_WIDTH, mask, val);
517 xpsgtr_clr_set(gtr_dev, RX_PROT_BUS_WIDTH, mask, val);
518
519 xpsgtr_bypass_scrambler_8b10b(gtr_phy);
520}
521
522/* Configure TX de-emphasis and margining for DP. */
523static void xpsgtr_phy_configure_dp(struct xpsgtr_phy *gtr_phy, unsigned int pre,
524 unsigned int voltage)
525{
526 static const u8 voltage_swing[4][4] = {
527 { 0x2a, 0x27, 0x24, 0x20 },
528 { 0x27, 0x23, 0x20, 0xff },
529 { 0x24, 0x20, 0xff, 0xff },
530 { 0xff, 0xff, 0xff, 0xff }
531 };
532 static const u8 pre_emphasis[4][4] = {
533 { 0x02, 0x02, 0x02, 0x02 },
534 { 0x01, 0x01, 0x01, 0xff },
535 { 0x00, 0x00, 0xff, 0xff },
536 { 0xff, 0xff, 0xff, 0xff }
537 };
538
539 xpsgtr_write_phy(gtr_phy, L0_TXPMD_TM_48, voltage_swing[pre][voltage]);
540 xpsgtr_write_phy(gtr_phy, L0_TX_ANA_TM_18, pre_emphasis[pre][voltage]);
541}
542
543/*
544 * PHY Operations
545 */
546
547static bool xpsgtr_phy_init_required(struct xpsgtr_phy *gtr_phy)
548{
549 /*
550 * As USB may save the snapshot of the states during hibernation, doing
551 * phy_init() will put the USB controller into reset, resulting in the
552 * losing of the saved snapshot. So try to avoid phy_init() for USB
553 * except when gtr_phy->skip_phy_init is false (this happens when FPD is
554 * shutdown during suspend or when gt lane is changed from current one)
555 */
556 if (gtr_phy->protocol == ICM_PROTOCOL_USB && gtr_phy->skip_phy_init)
557 return false;
558 else
559 return true;
560}
561
562/*
563 * There is a functional issue in the GT. The TX termination resistance can be
564 * out of spec due to a issue in the calibration logic. This is the workaround
565 * to fix it, required for XCZU9EG silicon.
566 */
567static int xpsgtr_phy_tx_term_fix(struct xpsgtr_phy *gtr_phy)
568{
569 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
570 u32 timeout = TIMEOUT_US;
571 u32 nsw;
572
573 /* Enabling Test Mode control for CMN Rest */
574 xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_SET);
575
576 /* Set Test Mode reset */
577 xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_EN);
578
579 xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG18, 0x00);
580 xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG19, L3_TM_OVERRIDE_NSW_CODE);
581
582 /*
583 * As a part of work around sequence for PMOS calibration fix,
584 * we need to configure any lane ICM_CFG to valid protocol. This
585 * will deassert the CMN_Resetn signal.
586 */
587 xpsgtr_lane_set_protocol(gtr_phy);
588
589 /* Clear Test Mode reset */
590 xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_SET);
591
592 dev_dbg(gtr_dev->dev, "calibrating...\n");
593
594 do {
595 u32 reg = xpsgtr_read(gtr_dev, L3_CALIB_DONE_STATUS);
596
597 if ((reg & L3_CALIB_DONE) == L3_CALIB_DONE)
598 break;
599
600 if (!--timeout) {
601 dev_err(gtr_dev->dev, "calibration time out\n");
602 return -ETIMEDOUT;
603 }
604
605 udelay(1);
606 } while (timeout > 0);
607
608 dev_dbg(gtr_dev->dev, "calibration done\n");
609
610 /* Reading NMOS Register Code */
611 nsw = xpsgtr_read(gtr_dev, L0_TXPMA_ST_3) & L0_DN_CALIB_CODE;
612
613 /* Set Test Mode reset */
614 xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_EN);
615
616 /* Writing NMOS register values back [5:3] */
617 xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG19, nsw >> L3_NSW_CALIB_SHIFT);
618
619 /* Writing NMOS register value [2:0] */
620 xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG18,
621 ((nsw & L3_TM_CALIB_DIG19_NSW) << L3_NSW_SHIFT) |
622 (1 << L3_NSW_PIPE_SHIFT));
623
624 /* Clear Test Mode reset */
625 xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_SET);
626
627 return 0;
628}
629
630static int xpsgtr_phy_init(struct phy *phy)
631{
632 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
633 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
634 int ret = 0;
635
636 mutex_lock(>r_dev->gtr_mutex);
637
638 /* Configure and enable the clock when peripheral phy_init call */
639 if (clk_prepare_enable(gtr_dev->clk[gtr_phy->refclk]))
640 goto out;
641
642 /* Skip initialization if not required. */
643 if (!xpsgtr_phy_init_required(gtr_phy))
644 goto out;
645
646 if (gtr_dev->tx_term_fix) {
647 ret = xpsgtr_phy_tx_term_fix(gtr_phy);
648 if (ret < 0)
649 goto out;
650
651 gtr_dev->tx_term_fix = false;
652 }
653
654 /* Enable coarse code saturation limiting logic. */
655 xpsgtr_write_phy(gtr_phy, L0_TM_PLL_DIG_37, L0_TM_COARSE_CODE_LIMIT);
656
657 /*
658 * Configure the PLL, the lane protocol, and perform protocol-specific
659 * initialization.
660 */
661 xpsgtr_configure_pll(gtr_phy);
662 xpsgtr_lane_set_protocol(gtr_phy);
663
664 switch (gtr_phy->protocol) {
665 case ICM_PROTOCOL_DP:
666 xpsgtr_phy_init_dp(gtr_phy);
667 break;
668
669 case ICM_PROTOCOL_SATA:
670 xpsgtr_phy_init_sata(gtr_phy);
671 break;
672
673 case ICM_PROTOCOL_SGMII:
674 xpsgtr_phy_init_sgmii(gtr_phy);
675 break;
676 }
677
678out:
679 mutex_unlock(>r_dev->gtr_mutex);
680 return ret;
681}
682
683static int xpsgtr_phy_exit(struct phy *phy)
684{
685 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
686 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
687
688 gtr_phy->skip_phy_init = false;
689
690 /* Ensure that disable clock only, which configure for lane */
691 clk_disable_unprepare(gtr_dev->clk[gtr_phy->refclk]);
692
693 return 0;
694}
695
696static int xpsgtr_phy_power_on(struct phy *phy)
697{
698 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
699 int ret = 0;
700
701 /* Skip initialization if not required. */
702 if (!xpsgtr_phy_init_required(gtr_phy))
703 return ret;
704 return xpsgtr_wait_pll_lock(phy);
705}
706
707static int xpsgtr_phy_configure(struct phy *phy, union phy_configure_opts *opts)
708{
709 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
710
711 if (gtr_phy->protocol != ICM_PROTOCOL_DP)
712 return 0;
713
714 xpsgtr_phy_configure_dp(gtr_phy, opts->dp.pre[0], opts->dp.voltage[0]);
715
716 return 0;
717}
718
719static const struct phy_ops xpsgtr_phyops = {
720 .init = xpsgtr_phy_init,
721 .exit = xpsgtr_phy_exit,
722 .power_on = xpsgtr_phy_power_on,
723 .configure = xpsgtr_phy_configure,
724 .owner = THIS_MODULE,
725};
726
727/*
728 * OF Xlate Support
729 */
730
731/* Set the lane protocol and instance based on the PHY type and instance number. */
732static int xpsgtr_set_lane_type(struct xpsgtr_phy *gtr_phy, u8 phy_type,
733 unsigned int phy_instance)
734{
735 unsigned int num_phy_types;
736
737 switch (phy_type) {
738 case PHY_TYPE_SATA:
739 num_phy_types = 2;
740 gtr_phy->protocol = ICM_PROTOCOL_SATA;
741 break;
742 case PHY_TYPE_USB3:
743 num_phy_types = 2;
744 gtr_phy->protocol = ICM_PROTOCOL_USB;
745 break;
746 case PHY_TYPE_DP:
747 num_phy_types = 2;
748 gtr_phy->protocol = ICM_PROTOCOL_DP;
749 break;
750 case PHY_TYPE_PCIE:
751 num_phy_types = 4;
752 gtr_phy->protocol = ICM_PROTOCOL_PCIE;
753 break;
754 case PHY_TYPE_SGMII:
755 num_phy_types = 4;
756 gtr_phy->protocol = ICM_PROTOCOL_SGMII;
757 break;
758 default:
759 return -EINVAL;
760 }
761
762 if (phy_instance >= num_phy_types)
763 return -EINVAL;
764
765 gtr_phy->instance = phy_instance;
766 return 0;
767}
768
769/*
770 * Valid combinations of controllers and lanes (Interconnect Matrix). Each
771 * "instance" represents one controller for a lane. For PCIe and DP, the
772 * "instance" is the logical lane in the link. For SATA, USB, and SGMII,
773 * the instance is the index of the controller.
774 *
775 * This information is only used to validate the devicetree reference, and is
776 * not used when programming the hardware.
777 */
778static const unsigned int icm_matrix[NUM_LANES][CONTROLLERS_PER_LANE] = {
779 /* PCIe, SATA, USB, DP, SGMII */
780 { 0, 0, 0, 1, 0 }, /* Lane 0 */
781 { 1, 1, 0, 0, 1 }, /* Lane 1 */
782 { 2, 0, 0, 1, 2 }, /* Lane 2 */
783 { 3, 1, 1, 0, 3 }, /* Lane 3 */
784};
785
786/* Translate OF phandle and args to PHY instance. */
787static struct phy *xpsgtr_xlate(struct device *dev,
788 const struct of_phandle_args *args)
789{
790 struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev);
791 struct xpsgtr_phy *gtr_phy;
792 unsigned int phy_instance;
793 unsigned int phy_lane;
794 unsigned int phy_type;
795 unsigned int refclk;
796 unsigned int i;
797 int ret;
798
799 if (args->args_count != 4) {
800 dev_err(dev, "Invalid number of cells in 'phy' property\n");
801 return ERR_PTR(-EINVAL);
802 }
803
804 /*
805 * Get the PHY parameters from the OF arguments and derive the lane
806 * type.
807 */
808 phy_lane = args->args[0];
809 if (phy_lane >= ARRAY_SIZE(gtr_dev->phys)) {
810 dev_err(dev, "Invalid lane number %u\n", phy_lane);
811 return ERR_PTR(-ENODEV);
812 }
813
814 gtr_phy = >r_dev->phys[phy_lane];
815 phy_type = args->args[1];
816 phy_instance = args->args[2];
817
818 guard(mutex)(>r_phy->phy->mutex);
819 ret = xpsgtr_set_lane_type(gtr_phy, phy_type, phy_instance);
820 if (ret < 0) {
821 dev_err(gtr_dev->dev, "Invalid PHY type and/or instance\n");
822 return ERR_PTR(ret);
823 }
824
825 refclk = args->args[3];
826 if (refclk >= ARRAY_SIZE(gtr_dev->refclk_sscs) ||
827 !gtr_dev->refclk_sscs[refclk]) {
828 dev_err(dev, "Invalid reference clock number %u\n", refclk);
829 return ERR_PTR(-EINVAL);
830 }
831
832 gtr_phy->refclk = refclk;
833
834 /*
835 * Ensure that the Interconnect Matrix is obeyed, i.e a given lane type
836 * is allowed to operate on the lane.
837 */
838 for (i = 0; i < CONTROLLERS_PER_LANE; i++) {
839 if (icm_matrix[phy_lane][i] == gtr_phy->instance)
840 return gtr_phy->phy;
841 }
842
843 return ERR_PTR(-EINVAL);
844}
845
846/*
847 * DebugFS
848 */
849
850static int xpsgtr_status_read(struct seq_file *seq, void *data)
851{
852 struct device *dev = seq->private;
853 struct xpsgtr_phy *gtr_phy = dev_get_drvdata(dev);
854 struct clk *clk;
855 u32 pll_status;
856
857 mutex_lock(>r_phy->phy->mutex);
858 pll_status = xpsgtr_read_phy(gtr_phy, L0_PLL_STATUS_READ_1);
859 clk = gtr_phy->dev->clk[gtr_phy->refclk];
860
861 seq_printf(seq, "Lane: %u\n", gtr_phy->lane);
862 seq_printf(seq, "Protocol: %s\n",
863 xpsgtr_icm_str[gtr_phy->protocol]);
864 seq_printf(seq, "Instance: %u\n", gtr_phy->instance);
865 seq_printf(seq, "Reference clock: %u (%pC)\n", gtr_phy->refclk, clk);
866 seq_printf(seq, "Reference rate: %lu\n", clk_get_rate(clk));
867 seq_printf(seq, "PLL locked: %s\n",
868 pll_status & PLL_STATUS_LOCKED ? "yes" : "no");
869
870 mutex_unlock(>r_phy->phy->mutex);
871 return 0;
872}
873
874/*
875 * Power Management
876 */
877
878static int xpsgtr_runtime_suspend(struct device *dev)
879{
880 struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev);
881
882 /* Save the snapshot ICM_CFG registers. */
883 gtr_dev->saved_icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0);
884 gtr_dev->saved_icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1);
885
886 xpsgtr_save_lane_regs(gtr_dev);
887
888 return 0;
889}
890
891static int xpsgtr_runtime_resume(struct device *dev)
892{
893 struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev);
894 unsigned int icm_cfg0, icm_cfg1;
895 unsigned int i;
896 bool skip_phy_init;
897
898 xpsgtr_restore_lane_regs(gtr_dev);
899
900 icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0);
901 icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1);
902
903 /* Return if no GT lanes got configured before suspend. */
904 if (!gtr_dev->saved_icm_cfg0 && !gtr_dev->saved_icm_cfg1)
905 return 0;
906
907 /* Check if the ICM configurations changed after suspend. */
908 if (icm_cfg0 == gtr_dev->saved_icm_cfg0 &&
909 icm_cfg1 == gtr_dev->saved_icm_cfg1)
910 skip_phy_init = true;
911 else
912 skip_phy_init = false;
913
914 /* Update the skip_phy_init for all gtr_phy instances. */
915 for (i = 0; i < ARRAY_SIZE(gtr_dev->phys); i++)
916 gtr_dev->phys[i].skip_phy_init = skip_phy_init;
917
918 return 0;
919}
920
921static DEFINE_RUNTIME_DEV_PM_OPS(xpsgtr_pm_ops, xpsgtr_runtime_suspend,
922 xpsgtr_runtime_resume, NULL);
923/*
924 * Probe & Platform Driver
925 */
926
927static int xpsgtr_get_ref_clocks(struct xpsgtr_dev *gtr_dev)
928{
929 unsigned int refclk;
930
931 for (refclk = 0; refclk < ARRAY_SIZE(gtr_dev->refclk_sscs); ++refclk) {
932 unsigned long rate;
933 unsigned int i;
934 struct clk *clk;
935 char name[8];
936
937 snprintf(name, sizeof(name), "ref%u", refclk);
938 clk = devm_clk_get_optional(gtr_dev->dev, name);
939 if (IS_ERR(clk)) {
940 return dev_err_probe(gtr_dev->dev, PTR_ERR(clk),
941 "Failed to get ref clock %u\n",
942 refclk);
943 }
944
945 if (!clk)
946 continue;
947
948 gtr_dev->clk[refclk] = clk;
949
950 /*
951 * Get the spread spectrum (SSC) settings for the reference
952 * clock rate.
953 */
954 rate = clk_get_rate(clk);
955
956 for (i = 0 ; i < ARRAY_SIZE(ssc_lookup); i++) {
957 /* Allow an error of 100 ppm */
958 unsigned long error = ssc_lookup[i].refclk_rate / 10000;
959
960 if (abs(rate - ssc_lookup[i].refclk_rate) < error) {
961 gtr_dev->refclk_sscs[refclk] = &ssc_lookup[i];
962 break;
963 }
964 }
965
966 if (i == ARRAY_SIZE(ssc_lookup)) {
967 dev_err(gtr_dev->dev,
968 "Invalid rate %lu for reference clock %u\n",
969 rate, refclk);
970 return -EINVAL;
971 }
972 }
973
974 return 0;
975}
976
977static int xpsgtr_probe(struct platform_device *pdev)
978{
979 struct device_node *np = pdev->dev.of_node;
980 struct xpsgtr_dev *gtr_dev;
981 struct phy_provider *provider;
982 unsigned int port;
983 int ret;
984
985 gtr_dev = devm_kzalloc(&pdev->dev, sizeof(*gtr_dev), GFP_KERNEL);
986 if (!gtr_dev)
987 return -ENOMEM;
988
989 gtr_dev->dev = &pdev->dev;
990 platform_set_drvdata(pdev, gtr_dev);
991
992 mutex_init(>r_dev->gtr_mutex);
993
994 if (of_device_is_compatible(np, "xlnx,zynqmp-psgtr"))
995 gtr_dev->tx_term_fix =
996 of_property_read_bool(np, "xlnx,tx-termination-fix");
997
998 /* Acquire resources. */
999 gtr_dev->serdes = devm_platform_ioremap_resource_byname(pdev, "serdes");
1000 if (IS_ERR(gtr_dev->serdes))
1001 return PTR_ERR(gtr_dev->serdes);
1002
1003 gtr_dev->siou = devm_platform_ioremap_resource_byname(pdev, "siou");
1004 if (IS_ERR(gtr_dev->siou))
1005 return PTR_ERR(gtr_dev->siou);
1006
1007 ret = xpsgtr_get_ref_clocks(gtr_dev);
1008 if (ret)
1009 return ret;
1010
1011 /* Create PHYs. */
1012 for (port = 0; port < ARRAY_SIZE(gtr_dev->phys); ++port) {
1013 struct xpsgtr_phy *gtr_phy = >r_dev->phys[port];
1014 struct phy *phy;
1015
1016 gtr_phy->lane = port;
1017 gtr_phy->dev = gtr_dev;
1018
1019 phy = devm_phy_create(&pdev->dev, np, &xpsgtr_phyops);
1020 if (IS_ERR(phy)) {
1021 dev_err(&pdev->dev, "failed to create PHY\n");
1022 return PTR_ERR(phy);
1023 }
1024
1025 gtr_phy->phy = phy;
1026 phy_set_drvdata(phy, gtr_phy);
1027 debugfs_create_devm_seqfile(&phy->dev, "status", phy->debugfs,
1028 xpsgtr_status_read);
1029 }
1030
1031 /* Register the PHY provider. */
1032 provider = devm_of_phy_provider_register(&pdev->dev, xpsgtr_xlate);
1033 if (IS_ERR(provider)) {
1034 dev_err(&pdev->dev, "registering provider failed\n");
1035 return PTR_ERR(provider);
1036 }
1037
1038 pm_runtime_set_active(gtr_dev->dev);
1039 pm_runtime_enable(gtr_dev->dev);
1040
1041 ret = pm_runtime_resume_and_get(gtr_dev->dev);
1042 if (ret < 0) {
1043 pm_runtime_disable(gtr_dev->dev);
1044 return ret;
1045 }
1046
1047 gtr_dev->saved_regs = devm_kmalloc(gtr_dev->dev,
1048 sizeof(save_reg_address),
1049 GFP_KERNEL);
1050 if (!gtr_dev->saved_regs)
1051 return -ENOMEM;
1052
1053 return 0;
1054}
1055
1056static void xpsgtr_remove(struct platform_device *pdev)
1057{
1058 struct xpsgtr_dev *gtr_dev = platform_get_drvdata(pdev);
1059
1060 pm_runtime_disable(gtr_dev->dev);
1061 pm_runtime_put_noidle(gtr_dev->dev);
1062 pm_runtime_set_suspended(gtr_dev->dev);
1063}
1064
1065static const struct of_device_id xpsgtr_of_match[] = {
1066 { .compatible = "xlnx,zynqmp-psgtr", },
1067 { .compatible = "xlnx,zynqmp-psgtr-v1.1", },
1068 {},
1069};
1070MODULE_DEVICE_TABLE(of, xpsgtr_of_match);
1071
1072static struct platform_driver xpsgtr_driver = {
1073 .probe = xpsgtr_probe,
1074 .remove = xpsgtr_remove,
1075 .driver = {
1076 .name = "xilinx-psgtr",
1077 .of_match_table = xpsgtr_of_match,
1078 .pm = pm_ptr(&xpsgtr_pm_ops),
1079 },
1080};
1081
1082module_platform_driver(xpsgtr_driver);
1083
1084MODULE_AUTHOR("Xilinx Inc.");
1085MODULE_LICENSE("GPL v2");
1086MODULE_DESCRIPTION("Xilinx ZynqMP High speed Gigabit Transceiver");