Loading...
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __SDHCI_PCI_H
3#define __SDHCI_PCI_H
4
5/*
6 * PCI device IDs, sub IDs
7 */
8
9#define PCI_DEVICE_ID_O2_SDS0 0x8420
10#define PCI_DEVICE_ID_O2_SDS1 0x8421
11#define PCI_DEVICE_ID_O2_FUJIN2 0x8520
12#define PCI_DEVICE_ID_O2_SEABIRD0 0x8620
13#define PCI_DEVICE_ID_O2_SEABIRD1 0x8621
14
15#define PCI_DEVICE_ID_INTEL_PCH_SDIO0 0x8809
16#define PCI_DEVICE_ID_INTEL_PCH_SDIO1 0x880a
17#define PCI_DEVICE_ID_INTEL_BYT_EMMC 0x0f14
18#define PCI_DEVICE_ID_INTEL_BYT_SDIO 0x0f15
19#define PCI_DEVICE_ID_INTEL_BYT_SD 0x0f16
20#define PCI_DEVICE_ID_INTEL_BYT_EMMC2 0x0f50
21#define PCI_DEVICE_ID_INTEL_BSW_EMMC 0x2294
22#define PCI_DEVICE_ID_INTEL_BSW_SDIO 0x2295
23#define PCI_DEVICE_ID_INTEL_BSW_SD 0x2296
24#define PCI_DEVICE_ID_INTEL_MRFLD_MMC 0x1190
25#define PCI_DEVICE_ID_INTEL_CLV_SDIO0 0x08f9
26#define PCI_DEVICE_ID_INTEL_CLV_SDIO1 0x08fa
27#define PCI_DEVICE_ID_INTEL_CLV_SDIO2 0x08fb
28#define PCI_DEVICE_ID_INTEL_CLV_EMMC0 0x08e5
29#define PCI_DEVICE_ID_INTEL_CLV_EMMC1 0x08e6
30#define PCI_DEVICE_ID_INTEL_QRK_SD 0x08A7
31#define PCI_DEVICE_ID_INTEL_SPT_EMMC 0x9d2b
32#define PCI_DEVICE_ID_INTEL_SPT_SDIO 0x9d2c
33#define PCI_DEVICE_ID_INTEL_SPT_SD 0x9d2d
34#define PCI_DEVICE_ID_INTEL_DNV_EMMC 0x19db
35#define PCI_DEVICE_ID_INTEL_CDF_EMMC 0x18db
36#define PCI_DEVICE_ID_INTEL_BXT_SD 0x0aca
37#define PCI_DEVICE_ID_INTEL_BXT_EMMC 0x0acc
38#define PCI_DEVICE_ID_INTEL_BXT_SDIO 0x0ad0
39#define PCI_DEVICE_ID_INTEL_BXTM_SD 0x1aca
40#define PCI_DEVICE_ID_INTEL_BXTM_EMMC 0x1acc
41#define PCI_DEVICE_ID_INTEL_BXTM_SDIO 0x1ad0
42#define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca
43#define PCI_DEVICE_ID_INTEL_APL_EMMC 0x5acc
44#define PCI_DEVICE_ID_INTEL_APL_SDIO 0x5ad0
45#define PCI_DEVICE_ID_INTEL_GLK_SD 0x31ca
46#define PCI_DEVICE_ID_INTEL_GLK_EMMC 0x31cc
47#define PCI_DEVICE_ID_INTEL_GLK_SDIO 0x31d0
48#define PCI_DEVICE_ID_INTEL_CNP_EMMC 0x9dc4
49#define PCI_DEVICE_ID_INTEL_CNP_SD 0x9df5
50#define PCI_DEVICE_ID_INTEL_CNPH_SD 0xa375
51#define PCI_DEVICE_ID_INTEL_ICP_EMMC 0x34c4
52#define PCI_DEVICE_ID_INTEL_ICP_SD 0x34f8
53#define PCI_DEVICE_ID_INTEL_EHL_EMMC 0x4b47
54#define PCI_DEVICE_ID_INTEL_EHL_SD 0x4b48
55#define PCI_DEVICE_ID_INTEL_CML_EMMC 0x02c4
56#define PCI_DEVICE_ID_INTEL_CML_SD 0x02f5
57#define PCI_DEVICE_ID_INTEL_CMLH_SD 0x06f5
58#define PCI_DEVICE_ID_INTEL_JSL_EMMC 0x4dc4
59#define PCI_DEVICE_ID_INTEL_JSL_SD 0x4df8
60#define PCI_DEVICE_ID_INTEL_LKF_EMMC 0x98c4
61#define PCI_DEVICE_ID_INTEL_LKF_SD 0x98f8
62#define PCI_DEVICE_ID_INTEL_ADL_EMMC 0x54c4
63
64#define PCI_DEVICE_ID_SYSKONNECT_8000 0x8000
65#define PCI_DEVICE_ID_VIA_95D0 0x95d0
66#define PCI_DEVICE_ID_REALTEK_5250 0x5250
67
68#define PCI_SUBDEVICE_ID_NI_7884 0x7884
69#define PCI_SUBDEVICE_ID_NI_78E3 0x78e3
70
71#define PCI_VENDOR_ID_ARASAN 0x16e6
72#define PCI_DEVICE_ID_ARASAN_PHY_EMMC 0x0670
73
74#define PCI_DEVICE_ID_SYNOPSYS_DWC_MSHC 0xc202
75
76#define PCI_DEVICE_ID_GLI_9755 0x9755
77#define PCI_DEVICE_ID_GLI_9750 0x9750
78#define PCI_DEVICE_ID_GLI_9763E 0xe763
79
80/*
81 * PCI device class and mask
82 */
83
84#define SYSTEM_SDHCI (PCI_CLASS_SYSTEM_SDHCI << 8)
85#define PCI_CLASS_MASK 0xFFFF00
86
87/*
88 * Macros for PCI device-description
89 */
90
91#define _PCI_VEND(vend) PCI_VENDOR_ID_##vend
92#define _PCI_DEV(vend, dev) PCI_DEVICE_ID_##vend##_##dev
93#define _PCI_SUBDEV(subvend, subdev) PCI_SUBDEVICE_ID_##subvend##_##subdev
94
95#define SDHCI_PCI_DEVICE(vend, dev, cfg) { \
96 .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \
97 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \
98 .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \
99}
100
101#define SDHCI_PCI_SUBDEVICE(vend, dev, subvend, subdev, cfg) { \
102 .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \
103 .subvendor = _PCI_VEND(subvend), \
104 .subdevice = _PCI_SUBDEV(subvend, subdev), \
105 .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \
106}
107
108#define SDHCI_PCI_DEVICE_CLASS(vend, cl, cl_msk, cfg) { \
109 .vendor = _PCI_VEND(vend), .device = PCI_ANY_ID, \
110 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \
111 .class = (cl), .class_mask = (cl_msk), \
112 .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \
113}
114
115/*
116 * PCI registers
117 */
118
119#define PCI_SDHCI_IFPIO 0x00
120#define PCI_SDHCI_IFDMA 0x01
121#define PCI_SDHCI_IFVENDOR 0x02
122
123#define PCI_SLOT_INFO 0x40 /* 8 bits */
124#define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
125#define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
126
127#define MAX_SLOTS 8
128
129struct sdhci_pci_chip;
130struct sdhci_pci_slot;
131
132struct sdhci_pci_fixes {
133 unsigned int quirks;
134 unsigned int quirks2;
135 bool allow_runtime_pm;
136 bool own_cd_for_runtime_pm;
137
138 int (*probe) (struct sdhci_pci_chip *);
139
140 int (*probe_slot) (struct sdhci_pci_slot *);
141 int (*add_host) (struct sdhci_pci_slot *);
142 void (*remove_slot) (struct sdhci_pci_slot *, int);
143
144#ifdef CONFIG_PM_SLEEP
145 int (*suspend) (struct sdhci_pci_chip *);
146 int (*resume) (struct sdhci_pci_chip *);
147#endif
148#ifdef CONFIG_PM
149 int (*runtime_suspend) (struct sdhci_pci_chip *);
150 int (*runtime_resume) (struct sdhci_pci_chip *);
151#endif
152
153 const struct sdhci_ops *ops;
154 size_t priv_size;
155};
156
157struct sdhci_pci_slot {
158 struct sdhci_pci_chip *chip;
159 struct sdhci_host *host;
160
161 int cd_idx;
162 bool cd_override_level;
163
164 void (*hw_reset)(struct sdhci_host *host);
165 unsigned long private[] ____cacheline_aligned;
166};
167
168struct sdhci_pci_chip {
169 struct pci_dev *pdev;
170
171 unsigned int quirks;
172 unsigned int quirks2;
173 bool allow_runtime_pm;
174 bool pm_retune;
175 bool rpm_retune;
176 const struct sdhci_pci_fixes *fixes;
177
178 int num_slots; /* Slots on controller */
179 struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */
180};
181
182static inline void *sdhci_pci_priv(struct sdhci_pci_slot *slot)
183{
184 return (void *)slot->private;
185}
186
187#ifdef CONFIG_PM_SLEEP
188int sdhci_pci_resume_host(struct sdhci_pci_chip *chip);
189#endif
190int sdhci_pci_enable_dma(struct sdhci_host *host);
191
192extern const struct sdhci_pci_fixes sdhci_arasan;
193extern const struct sdhci_pci_fixes sdhci_snps;
194extern const struct sdhci_pci_fixes sdhci_o2;
195extern const struct sdhci_pci_fixes sdhci_gl9750;
196extern const struct sdhci_pci_fixes sdhci_gl9755;
197extern const struct sdhci_pci_fixes sdhci_gl9763e;
198
199#endif /* __SDHCI_PCI_H */
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __SDHCI_PCI_H
3#define __SDHCI_PCI_H
4
5/*
6 * PCI device IDs, sub IDs
7 */
8
9#define PCI_DEVICE_ID_O2_SDS0 0x8420
10#define PCI_DEVICE_ID_O2_SDS1 0x8421
11#define PCI_DEVICE_ID_O2_FUJIN2 0x8520
12#define PCI_DEVICE_ID_O2_SEABIRD0 0x8620
13#define PCI_DEVICE_ID_O2_SEABIRD1 0x8621
14#define PCI_DEVICE_ID_O2_GG8_9860 0x9860
15#define PCI_DEVICE_ID_O2_GG8_9861 0x9861
16#define PCI_DEVICE_ID_O2_GG8_9862 0x9862
17#define PCI_DEVICE_ID_O2_GG8_9863 0x9863
18
19#define PCI_DEVICE_ID_INTEL_PCH_SDIO0 0x8809
20#define PCI_DEVICE_ID_INTEL_PCH_SDIO1 0x880a
21#define PCI_DEVICE_ID_INTEL_BYT_EMMC 0x0f14
22#define PCI_DEVICE_ID_INTEL_BYT_SDIO 0x0f15
23#define PCI_DEVICE_ID_INTEL_BYT_SD 0x0f16
24#define PCI_DEVICE_ID_INTEL_BYT_EMMC2 0x0f50
25#define PCI_DEVICE_ID_INTEL_BSW_EMMC 0x2294
26#define PCI_DEVICE_ID_INTEL_BSW_SDIO 0x2295
27#define PCI_DEVICE_ID_INTEL_BSW_SD 0x2296
28#define PCI_DEVICE_ID_INTEL_MRFLD_MMC 0x1190
29#define PCI_DEVICE_ID_INTEL_CLV_SDIO0 0x08f9
30#define PCI_DEVICE_ID_INTEL_CLV_SDIO1 0x08fa
31#define PCI_DEVICE_ID_INTEL_CLV_SDIO2 0x08fb
32#define PCI_DEVICE_ID_INTEL_CLV_EMMC0 0x08e5
33#define PCI_DEVICE_ID_INTEL_CLV_EMMC1 0x08e6
34#define PCI_DEVICE_ID_INTEL_QRK_SD 0x08A7
35#define PCI_DEVICE_ID_INTEL_SPT_EMMC 0x9d2b
36#define PCI_DEVICE_ID_INTEL_SPT_SDIO 0x9d2c
37#define PCI_DEVICE_ID_INTEL_SPT_SD 0x9d2d
38#define PCI_DEVICE_ID_INTEL_DNV_EMMC 0x19db
39#define PCI_DEVICE_ID_INTEL_CDF_EMMC 0x18db
40#define PCI_DEVICE_ID_INTEL_BXT_SD 0x0aca
41#define PCI_DEVICE_ID_INTEL_BXT_EMMC 0x0acc
42#define PCI_DEVICE_ID_INTEL_BXT_SDIO 0x0ad0
43#define PCI_DEVICE_ID_INTEL_BXTM_SD 0x1aca
44#define PCI_DEVICE_ID_INTEL_BXTM_EMMC 0x1acc
45#define PCI_DEVICE_ID_INTEL_BXTM_SDIO 0x1ad0
46#define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca
47#define PCI_DEVICE_ID_INTEL_APL_EMMC 0x5acc
48#define PCI_DEVICE_ID_INTEL_APL_SDIO 0x5ad0
49#define PCI_DEVICE_ID_INTEL_GLK_SD 0x31ca
50#define PCI_DEVICE_ID_INTEL_GLK_EMMC 0x31cc
51#define PCI_DEVICE_ID_INTEL_GLK_SDIO 0x31d0
52#define PCI_DEVICE_ID_INTEL_CNP_EMMC 0x9dc4
53#define PCI_DEVICE_ID_INTEL_CNP_SD 0x9df5
54#define PCI_DEVICE_ID_INTEL_CNPH_SD 0xa375
55#define PCI_DEVICE_ID_INTEL_ICP_EMMC 0x34c4
56#define PCI_DEVICE_ID_INTEL_ICP_SD 0x34f8
57#define PCI_DEVICE_ID_INTEL_EHL_EMMC 0x4b47
58#define PCI_DEVICE_ID_INTEL_EHL_SD 0x4b48
59#define PCI_DEVICE_ID_INTEL_CML_EMMC 0x02c4
60#define PCI_DEVICE_ID_INTEL_CML_SD 0x02f5
61#define PCI_DEVICE_ID_INTEL_CMLH_SD 0x06f5
62#define PCI_DEVICE_ID_INTEL_JSL_EMMC 0x4dc4
63#define PCI_DEVICE_ID_INTEL_JSL_SD 0x4df8
64#define PCI_DEVICE_ID_INTEL_LKF_EMMC 0x98c4
65#define PCI_DEVICE_ID_INTEL_LKF_SD 0x98f8
66#define PCI_DEVICE_ID_INTEL_ADL_EMMC 0x54c4
67
68#define PCI_DEVICE_ID_SYSKONNECT_8000 0x8000
69#define PCI_DEVICE_ID_VIA_95D0 0x95d0
70#define PCI_DEVICE_ID_REALTEK_5250 0x5250
71
72#define PCI_SUBDEVICE_ID_NI_7884 0x7884
73#define PCI_SUBDEVICE_ID_NI_78E3 0x78e3
74
75#define PCI_VENDOR_ID_ARASAN 0x16e6
76#define PCI_DEVICE_ID_ARASAN_PHY_EMMC 0x0670
77
78#define PCI_DEVICE_ID_SYNOPSYS_DWC_MSHC 0xc202
79
80#define PCI_DEVICE_ID_GLI_9755 0x9755
81#define PCI_DEVICE_ID_GLI_9750 0x9750
82#define PCI_DEVICE_ID_GLI_9763E 0xe763
83#define PCI_DEVICE_ID_GLI_9767 0x9767
84
85/*
86 * PCI device class and mask
87 */
88
89#define SYSTEM_SDHCI (PCI_CLASS_SYSTEM_SDHCI << 8)
90#define PCI_CLASS_MASK 0xFFFF00
91
92/*
93 * Macros for PCI device-description
94 */
95
96#define _PCI_VEND(vend) PCI_VENDOR_ID_##vend
97#define _PCI_DEV(vend, dev) PCI_DEVICE_ID_##vend##_##dev
98#define _PCI_SUBDEV(subvend, subdev) PCI_SUBDEVICE_ID_##subvend##_##subdev
99
100#define SDHCI_PCI_DEVICE(vend, dev, cfg) { \
101 .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \
102 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \
103 .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \
104}
105
106#define SDHCI_PCI_SUBDEVICE(vend, dev, subvend, subdev, cfg) { \
107 .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \
108 .subvendor = _PCI_VEND(subvend), \
109 .subdevice = _PCI_SUBDEV(subvend, subdev), \
110 .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \
111}
112
113#define SDHCI_PCI_DEVICE_CLASS(vend, cl, cl_msk, cfg) { \
114 .vendor = _PCI_VEND(vend), .device = PCI_ANY_ID, \
115 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \
116 .class = (cl), .class_mask = (cl_msk), \
117 .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \
118}
119
120/*
121 * PCI registers
122 */
123
124#define PCI_SDHCI_IFPIO 0x00
125#define PCI_SDHCI_IFDMA 0x01
126#define PCI_SDHCI_IFVENDOR 0x02
127
128#define PCI_SLOT_INFO 0x40 /* 8 bits */
129#define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
130#define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
131
132#define MAX_SLOTS 8
133
134struct sdhci_pci_chip;
135struct sdhci_pci_slot;
136
137struct sdhci_pci_fixes {
138 unsigned int quirks;
139 unsigned int quirks2;
140 bool allow_runtime_pm;
141 bool own_cd_for_runtime_pm;
142
143 int (*probe) (struct sdhci_pci_chip *);
144
145 int (*probe_slot) (struct sdhci_pci_slot *);
146 int (*add_host) (struct sdhci_pci_slot *);
147 void (*remove_slot) (struct sdhci_pci_slot *, int);
148 void (*remove_host) (struct sdhci_pci_slot *, int);
149
150#ifdef CONFIG_PM_SLEEP
151 int (*suspend) (struct sdhci_pci_chip *);
152 int (*resume) (struct sdhci_pci_chip *);
153#endif
154#ifdef CONFIG_PM
155 int (*runtime_suspend) (struct sdhci_pci_chip *);
156 int (*runtime_resume) (struct sdhci_pci_chip *);
157#endif
158
159 const struct sdhci_ops *ops;
160 const struct dmi_system_id *cd_gpio_override;
161 size_t priv_size;
162};
163
164struct sdhci_pci_slot {
165 struct sdhci_pci_chip *chip;
166 struct sdhci_host *host;
167
168 int cd_idx;
169 bool cd_override_level;
170
171 void (*hw_reset)(struct sdhci_host *host);
172 unsigned long private[] ____cacheline_aligned;
173};
174
175struct sdhci_pci_chip {
176 struct pci_dev *pdev;
177
178 unsigned int quirks;
179 unsigned int quirks2;
180 bool allow_runtime_pm;
181 bool pm_retune;
182 bool rpm_retune;
183 const struct sdhci_pci_fixes *fixes;
184
185 int num_slots; /* Slots on controller */
186 struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */
187};
188
189static inline void *sdhci_pci_priv(struct sdhci_pci_slot *slot)
190{
191 return (void *)slot->private;
192}
193
194int sdhci_pci_uhs2_add_host(struct sdhci_pci_slot *slot);
195void sdhci_pci_uhs2_remove_host(struct sdhci_pci_slot *slot, int dead);
196#ifdef CONFIG_PM_SLEEP
197int sdhci_pci_resume_host(struct sdhci_pci_chip *chip);
198#endif
199int sdhci_pci_enable_dma(struct sdhci_host *host);
200
201extern const struct sdhci_pci_fixes sdhci_arasan;
202extern const struct sdhci_pci_fixes sdhci_snps;
203extern const struct sdhci_pci_fixes sdhci_o2;
204extern const struct sdhci_pci_fixes sdhci_gl9750;
205extern const struct sdhci_pci_fixes sdhci_gl9755;
206extern const struct sdhci_pci_fixes sdhci_gl9763e;
207extern const struct sdhci_pci_fixes sdhci_gl9767;
208
209#endif /* __SDHCI_PCI_H */