1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright 2019 NXP.
  4 */
  5
  6#include <linux/clk.h>
  7#include <linux/of_device.h>
  8#include <linux/of_graph.h>
 
  9#include <linux/pm_runtime.h>
 10#include <linux/slab.h>
 11#include <drm/drm_bridge_connector.h>
 12#include <drm/drm_device.h>
 13#include <drm/drm_modeset_helper.h>
 14
 15#include "dcss-dev.h"
 16#include "dcss-kms.h"
 17
 18static void dcss_clocks_enable(struct dcss_dev *dcss)
 19{
 20	clk_prepare_enable(dcss->axi_clk);
 21	clk_prepare_enable(dcss->apb_clk);
 22	clk_prepare_enable(dcss->rtrm_clk);
 23	clk_prepare_enable(dcss->dtrc_clk);
 24	clk_prepare_enable(dcss->pix_clk);
 25}
 26
 27static void dcss_clocks_disable(struct dcss_dev *dcss)
 28{
 29	clk_disable_unprepare(dcss->pix_clk);
 30	clk_disable_unprepare(dcss->dtrc_clk);
 31	clk_disable_unprepare(dcss->rtrm_clk);
 32	clk_disable_unprepare(dcss->apb_clk);
 33	clk_disable_unprepare(dcss->axi_clk);
 34}
 35
 36static void dcss_disable_dtg_and_ss_cb(void *data)
 37{
 38	struct dcss_dev *dcss = data;
 39
 40	dcss->disable_callback = NULL;
 41
 42	dcss_ss_shutoff(dcss->ss);
 43	dcss_dtg_shutoff(dcss->dtg);
 44
 45	complete(&dcss->disable_completion);
 46}
 47
 48void dcss_disable_dtg_and_ss(struct dcss_dev *dcss)
 49{
 50	dcss->disable_callback = dcss_disable_dtg_and_ss_cb;
 51}
 52
 53void dcss_enable_dtg_and_ss(struct dcss_dev *dcss)
 54{
 55	if (dcss->disable_callback)
 56		dcss->disable_callback = NULL;
 57
 58	dcss_dtg_enable(dcss->dtg);
 59	dcss_ss_enable(dcss->ss);
 60}
 61
 62static int dcss_submodules_init(struct dcss_dev *dcss)
 63{
 64	int ret = 0;
 65	u32 base_addr = dcss->start_addr;
 66	const struct dcss_type_data *devtype = dcss->devtype;
 67
 68	dcss_clocks_enable(dcss);
 69
 70	ret = dcss_blkctl_init(dcss, base_addr + devtype->blkctl_ofs);
 71	if (ret)
 72		return ret;
 73
 74	ret = dcss_ctxld_init(dcss, base_addr + devtype->ctxld_ofs);
 75	if (ret)
 76		goto ctxld_err;
 77
 78	ret = dcss_dtg_init(dcss, base_addr + devtype->dtg_ofs);
 79	if (ret)
 80		goto dtg_err;
 81
 82	ret = dcss_ss_init(dcss, base_addr + devtype->ss_ofs);
 83	if (ret)
 84		goto ss_err;
 85
 86	ret = dcss_dpr_init(dcss, base_addr + devtype->dpr_ofs);
 87	if (ret)
 88		goto dpr_err;
 89
 90	ret = dcss_scaler_init(dcss, base_addr + devtype->scaler_ofs);
 91	if (ret)
 92		goto scaler_err;
 93
 94	dcss_clocks_disable(dcss);
 95
 96	return 0;
 97
 98scaler_err:
 99	dcss_dpr_exit(dcss->dpr);
100
101dpr_err:
102	dcss_ss_exit(dcss->ss);
103
104ss_err:
105	dcss_dtg_exit(dcss->dtg);
106
107dtg_err:
108	dcss_ctxld_exit(dcss->ctxld);
109
110ctxld_err:
111	dcss_blkctl_exit(dcss->blkctl);
112
113	dcss_clocks_disable(dcss);
114
115	return ret;
116}
117
118static void dcss_submodules_stop(struct dcss_dev *dcss)
119{
120	dcss_clocks_enable(dcss);
121	dcss_scaler_exit(dcss->scaler);
122	dcss_dpr_exit(dcss->dpr);
123	dcss_ss_exit(dcss->ss);
124	dcss_dtg_exit(dcss->dtg);
125	dcss_ctxld_exit(dcss->ctxld);
126	dcss_blkctl_exit(dcss->blkctl);
127	dcss_clocks_disable(dcss);
128}
129
130static int dcss_clks_init(struct dcss_dev *dcss)
131{
132	int i;
133	struct {
134		const char *id;
135		struct clk **clk;
136	} clks[] = {
137		{"apb",   &dcss->apb_clk},
138		{"axi",   &dcss->axi_clk},
139		{"pix",   &dcss->pix_clk},
140		{"rtrm",  &dcss->rtrm_clk},
141		{"dtrc",  &dcss->dtrc_clk},
142	};
143
144	for (i = 0; i < ARRAY_SIZE(clks); i++) {
145		*clks[i].clk = devm_clk_get(dcss->dev, clks[i].id);
146		if (IS_ERR(*clks[i].clk)) {
147			dev_err(dcss->dev, "failed to get %s clock\n",
148				clks[i].id);
149			return PTR_ERR(*clks[i].clk);
150		}
151	}
152
153	return 0;
154}
155
156static void dcss_clks_release(struct dcss_dev *dcss)
157{
158	devm_clk_put(dcss->dev, dcss->dtrc_clk);
159	devm_clk_put(dcss->dev, dcss->rtrm_clk);
160	devm_clk_put(dcss->dev, dcss->pix_clk);
161	devm_clk_put(dcss->dev, dcss->axi_clk);
162	devm_clk_put(dcss->dev, dcss->apb_clk);
163}
164
165struct dcss_dev *dcss_dev_create(struct device *dev, bool hdmi_output)
166{
167	struct platform_device *pdev = to_platform_device(dev);
168	int ret;
169	struct resource *res;
170	struct dcss_dev *dcss;
171	const struct dcss_type_data *devtype;
172
173	devtype = of_device_get_match_data(dev);
174	if (!devtype) {
175		dev_err(dev, "no device match found\n");
176		return ERR_PTR(-ENODEV);
177	}
178
179	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
180	if (!res) {
181		dev_err(dev, "cannot get memory resource\n");
182		return ERR_PTR(-EINVAL);
183	}
184
185	dcss = kzalloc(sizeof(*dcss), GFP_KERNEL);
 
 
 
 
 
186	if (!dcss)
187		return ERR_PTR(-ENOMEM);
188
189	dcss->dev = dev;
190	dcss->devtype = devtype;
191	dcss->hdmi_output = hdmi_output;
192
193	ret = dcss_clks_init(dcss);
194	if (ret) {
195		dev_err(dev, "clocks initialization failed\n");
196		goto err;
197	}
198
199	dcss->of_port = of_graph_get_port_by_id(dev->of_node, 0);
200	if (!dcss->of_port) {
201		dev_err(dev, "no port@0 node in %s\n", dev->of_node->full_name);
202		ret = -ENODEV;
203		goto clks_err;
204	}
205
206	dcss->start_addr = res->start;
207
208	ret = dcss_submodules_init(dcss);
209	if (ret) {
210		of_node_put(dcss->of_port);
211		dev_err(dev, "submodules initialization failed\n");
212		goto clks_err;
213	}
214
215	init_completion(&dcss->disable_completion);
216
217	pm_runtime_set_autosuspend_delay(dev, 100);
218	pm_runtime_use_autosuspend(dev);
219	pm_runtime_set_suspended(dev);
220	pm_runtime_allow(dev);
221	pm_runtime_enable(dev);
222
223	return dcss;
224
225clks_err:
226	dcss_clks_release(dcss);
227
228err:
229	kfree(dcss);
230
231	return ERR_PTR(ret);
232}
233
234void dcss_dev_destroy(struct dcss_dev *dcss)
235{
236	if (!pm_runtime_suspended(dcss->dev)) {
237		dcss_ctxld_suspend(dcss->ctxld);
238		dcss_clocks_disable(dcss);
239	}
240
241	of_node_put(dcss->of_port);
242
243	pm_runtime_disable(dcss->dev);
244
245	dcss_submodules_stop(dcss);
246
247	dcss_clks_release(dcss);
248
249	kfree(dcss);
250}
251
252#ifdef CONFIG_PM_SLEEP
253int dcss_dev_suspend(struct device *dev)
254{
255	struct dcss_dev *dcss = dcss_drv_dev_to_dcss(dev);
256	struct drm_device *ddev = dcss_drv_dev_to_drm(dev);
257	struct dcss_kms_dev *kms = container_of(ddev, struct dcss_kms_dev, base);
258	int ret;
259
260	drm_bridge_connector_disable_hpd(kms->connector);
261
262	drm_mode_config_helper_suspend(ddev);
263
264	if (pm_runtime_suspended(dev))
265		return 0;
266
267	ret = dcss_ctxld_suspend(dcss->ctxld);
268	if (ret)
269		return ret;
270
271	dcss_clocks_disable(dcss);
272
273	return 0;
274}
275
276int dcss_dev_resume(struct device *dev)
277{
278	struct dcss_dev *dcss = dcss_drv_dev_to_dcss(dev);
279	struct drm_device *ddev = dcss_drv_dev_to_drm(dev);
280	struct dcss_kms_dev *kms = container_of(ddev, struct dcss_kms_dev, base);
281
282	if (pm_runtime_suspended(dev)) {
283		drm_mode_config_helper_resume(ddev);
284		return 0;
285	}
286
287	dcss_clocks_enable(dcss);
288
289	dcss_blkctl_cfg(dcss->blkctl);
290
291	dcss_ctxld_resume(dcss->ctxld);
292
293	drm_mode_config_helper_resume(ddev);
294
295	drm_bridge_connector_enable_hpd(kms->connector);
296
297	return 0;
298}
299#endif /* CONFIG_PM_SLEEP */
300
301#ifdef CONFIG_PM
302int dcss_dev_runtime_suspend(struct device *dev)
303{
304	struct dcss_dev *dcss = dcss_drv_dev_to_dcss(dev);
305	int ret;
306
307	ret = dcss_ctxld_suspend(dcss->ctxld);
308	if (ret)
309		return ret;
310
311	dcss_clocks_disable(dcss);
312
313	return 0;
314}
315
316int dcss_dev_runtime_resume(struct device *dev)
317{
318	struct dcss_dev *dcss = dcss_drv_dev_to_dcss(dev);
319
320	dcss_clocks_enable(dcss);
321
322	dcss_blkctl_cfg(dcss->blkctl);
323
324	dcss_ctxld_resume(dcss->ctxld);
325
326	return 0;
327}
328#endif /* CONFIG_PM */
 
 
 
 

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright 2019 NXP.
  4 */
  5
  6#include <linux/clk.h>
  7#include <linux/of.h>
  8#include <linux/of_graph.h>
  9#include <linux/platform_device.h>
 10#include <linux/pm_runtime.h>
 11#include <linux/slab.h>
 12#include <drm/drm_bridge_connector.h>
 13#include <drm/drm_device.h>
 14#include <drm/drm_modeset_helper.h>
 15
 16#include "dcss-dev.h"
 17#include "dcss-kms.h"
 18
 19static void dcss_clocks_enable(struct dcss_dev *dcss)
 20{
 21	clk_prepare_enable(dcss->axi_clk);
 22	clk_prepare_enable(dcss->apb_clk);
 23	clk_prepare_enable(dcss->rtrm_clk);
 24	clk_prepare_enable(dcss->dtrc_clk);
 25	clk_prepare_enable(dcss->pix_clk);
 26}
 27
 28static void dcss_clocks_disable(struct dcss_dev *dcss)
 29{
 30	clk_disable_unprepare(dcss->pix_clk);
 31	clk_disable_unprepare(dcss->dtrc_clk);
 32	clk_disable_unprepare(dcss->rtrm_clk);
 33	clk_disable_unprepare(dcss->apb_clk);
 34	clk_disable_unprepare(dcss->axi_clk);
 35}
 36
 37static void dcss_disable_dtg_and_ss_cb(void *data)
 38{
 39	struct dcss_dev *dcss = data;
 40
 41	dcss->disable_callback = NULL;
 42
 43	dcss_ss_shutoff(dcss->ss);
 44	dcss_dtg_shutoff(dcss->dtg);
 45
 46	complete(&dcss->disable_completion);
 47}
 48
 49void dcss_disable_dtg_and_ss(struct dcss_dev *dcss)
 50{
 51	dcss->disable_callback = dcss_disable_dtg_and_ss_cb;
 52}
 53
 54void dcss_enable_dtg_and_ss(struct dcss_dev *dcss)
 55{
 56	if (dcss->disable_callback)
 57		dcss->disable_callback = NULL;
 58
 59	dcss_dtg_enable(dcss->dtg);
 60	dcss_ss_enable(dcss->ss);
 61}
 62
 63static int dcss_submodules_init(struct dcss_dev *dcss)
 64{
 65	int ret = 0;
 66	u32 base_addr = dcss->start_addr;
 67	const struct dcss_type_data *devtype = dcss->devtype;
 68
 69	dcss_clocks_enable(dcss);
 70
 71	ret = dcss_blkctl_init(dcss, base_addr + devtype->blkctl_ofs);
 72	if (ret)
 73		return ret;
 74
 75	ret = dcss_ctxld_init(dcss, base_addr + devtype->ctxld_ofs);
 76	if (ret)
 77		goto ctxld_err;
 78
 79	ret = dcss_dtg_init(dcss, base_addr + devtype->dtg_ofs);
 80	if (ret)
 81		goto dtg_err;
 82
 83	ret = dcss_ss_init(dcss, base_addr + devtype->ss_ofs);
 84	if (ret)
 85		goto ss_err;
 86
 87	ret = dcss_dpr_init(dcss, base_addr + devtype->dpr_ofs);
 88	if (ret)
 89		goto dpr_err;
 90
 91	ret = dcss_scaler_init(dcss, base_addr + devtype->scaler_ofs);
 92	if (ret)
 93		goto scaler_err;
 94
 95	dcss_clocks_disable(dcss);
 96
 97	return 0;
 98
 99scaler_err:
100	dcss_dpr_exit(dcss->dpr);
101
102dpr_err:
103	dcss_ss_exit(dcss->ss);
104
105ss_err:
106	dcss_dtg_exit(dcss->dtg);
107
108dtg_err:
109	dcss_ctxld_exit(dcss->ctxld);
110
111ctxld_err:
 
 
112	dcss_clocks_disable(dcss);
113
114	return ret;
115}
116
117static void dcss_submodules_stop(struct dcss_dev *dcss)
118{
119	dcss_clocks_enable(dcss);
120	dcss_scaler_exit(dcss->scaler);
121	dcss_dpr_exit(dcss->dpr);
122	dcss_ss_exit(dcss->ss);
123	dcss_dtg_exit(dcss->dtg);
124	dcss_ctxld_exit(dcss->ctxld);
 
125	dcss_clocks_disable(dcss);
126}
127
128static int dcss_clks_init(struct dcss_dev *dcss)
129{
130	int i;
131	struct {
132		const char *id;
133		struct clk **clk;
134	} clks[] = {
135		{"apb",   &dcss->apb_clk},
136		{"axi",   &dcss->axi_clk},
137		{"pix",   &dcss->pix_clk},
138		{"rtrm",  &dcss->rtrm_clk},
139		{"dtrc",  &dcss->dtrc_clk},
140	};
141
142	for (i = 0; i < ARRAY_SIZE(clks); i++) {
143		*clks[i].clk = devm_clk_get(dcss->dev, clks[i].id);
144		if (IS_ERR(*clks[i].clk)) {
145			dev_err(dcss->dev, "failed to get %s clock\n",
146				clks[i].id);
147			return PTR_ERR(*clks[i].clk);
148		}
149	}
150
151	return 0;
152}
153
154static void dcss_clks_release(struct dcss_dev *dcss)
155{
156	devm_clk_put(dcss->dev, dcss->dtrc_clk);
157	devm_clk_put(dcss->dev, dcss->rtrm_clk);
158	devm_clk_put(dcss->dev, dcss->pix_clk);
159	devm_clk_put(dcss->dev, dcss->axi_clk);
160	devm_clk_put(dcss->dev, dcss->apb_clk);
161}
162
163struct dcss_dev *dcss_dev_create(struct device *dev, bool hdmi_output)
164{
165	struct platform_device *pdev = to_platform_device(dev);
166	int ret;
167	struct resource *res;
168	struct dcss_dev *dcss;
169	const struct dcss_type_data *devtype;
170
171	devtype = of_device_get_match_data(dev);
172	if (!devtype) {
173		dev_err(dev, "no device match found\n");
174		return ERR_PTR(-ENODEV);
175	}
176
177	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
178	if (!res) {
179		dev_err(dev, "cannot get memory resource\n");
180		return ERR_PTR(-EINVAL);
181	}
182
183	if (!devm_request_mem_region(dev, res->start, resource_size(res), "dcss")) {
184		dev_err(dev, "cannot request memory region\n");
185		return ERR_PTR(-EBUSY);
186	}
187
188	dcss = devm_kzalloc(dev, sizeof(*dcss), GFP_KERNEL);
189	if (!dcss)
190		return ERR_PTR(-ENOMEM);
191
192	dcss->dev = dev;
193	dcss->devtype = devtype;
194	dcss->hdmi_output = hdmi_output;
195
196	ret = dcss_clks_init(dcss);
197	if (ret) {
198		dev_err(dev, "clocks initialization failed\n");
199		return ERR_PTR(ret);
200	}
201
202	dcss->of_port = of_graph_get_port_by_id(dev->of_node, 0);
203	if (!dcss->of_port) {
204		dev_err(dev, "no port@0 node in %pOF\n", dev->of_node);
205		ret = -ENODEV;
206		goto clks_err;
207	}
208
209	dcss->start_addr = res->start;
210
211	ret = dcss_submodules_init(dcss);
212	if (ret) {
213		of_node_put(dcss->of_port);
214		dev_err(dev, "submodules initialization failed\n");
215		goto clks_err;
216	}
217
218	init_completion(&dcss->disable_completion);
219
220	pm_runtime_set_autosuspend_delay(dev, 100);
221	pm_runtime_use_autosuspend(dev);
222	pm_runtime_set_suspended(dev);
223	pm_runtime_allow(dev);
224	pm_runtime_enable(dev);
225
226	return dcss;
227
228clks_err:
229	dcss_clks_release(dcss);
230
 
 
 
231	return ERR_PTR(ret);
232}
233
234void dcss_dev_destroy(struct dcss_dev *dcss)
235{
236	if (!pm_runtime_suspended(dcss->dev)) {
237		dcss_ctxld_suspend(dcss->ctxld);
238		dcss_clocks_disable(dcss);
239	}
240
241	of_node_put(dcss->of_port);
242
243	pm_runtime_disable(dcss->dev);
244
245	dcss_submodules_stop(dcss);
246
247	dcss_clks_release(dcss);
 
 
248}
249
250static int dcss_dev_suspend(struct device *dev)
 
251{
252	struct dcss_dev *dcss = dcss_drv_dev_to_dcss(dev);
253	struct drm_device *ddev = dcss_drv_dev_to_drm(dev);
 
254	int ret;
255
 
 
256	drm_mode_config_helper_suspend(ddev);
257
258	if (pm_runtime_suspended(dev))
259		return 0;
260
261	ret = dcss_ctxld_suspend(dcss->ctxld);
262	if (ret)
263		return ret;
264
265	dcss_clocks_disable(dcss);
266
267	return 0;
268}
269
270static int dcss_dev_resume(struct device *dev)
271{
272	struct dcss_dev *dcss = dcss_drv_dev_to_dcss(dev);
273	struct drm_device *ddev = dcss_drv_dev_to_drm(dev);
 
274
275	if (pm_runtime_suspended(dev)) {
276		drm_mode_config_helper_resume(ddev);
277		return 0;
278	}
279
280	dcss_clocks_enable(dcss);
281
282	dcss_blkctl_cfg(dcss->blkctl);
283
284	dcss_ctxld_resume(dcss->ctxld);
285
286	drm_mode_config_helper_resume(ddev);
287
 
 
288	return 0;
289}
 
290
291static int dcss_dev_runtime_suspend(struct device *dev)
 
292{
293	struct dcss_dev *dcss = dcss_drv_dev_to_dcss(dev);
294	int ret;
295
296	ret = dcss_ctxld_suspend(dcss->ctxld);
297	if (ret)
298		return ret;
299
300	dcss_clocks_disable(dcss);
301
302	return 0;
303}
304
305static int dcss_dev_runtime_resume(struct device *dev)
306{
307	struct dcss_dev *dcss = dcss_drv_dev_to_dcss(dev);
308
309	dcss_clocks_enable(dcss);
310
311	dcss_blkctl_cfg(dcss->blkctl);
312
313	dcss_ctxld_resume(dcss->ctxld);
314
315	return 0;
316}
317
318EXPORT_GPL_DEV_PM_OPS(dcss_dev_pm_ops) = {
319	RUNTIME_PM_OPS(dcss_dev_runtime_suspend, dcss_dev_runtime_resume, NULL)
320	SYSTEM_SLEEP_PM_OPS(dcss_dev_suspend, dcss_dev_resume)
321};