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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Xilinx gpio driver for xps/axi_gpio IP.
4 *
5 * Copyright 2008 - 2013 Xilinx, Inc.
6 */
7
8#include <linux/bitmap.h>
9#include <linux/bitops.h>
10#include <linux/clk.h>
11#include <linux/errno.h>
12#include <linux/gpio/driver.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/irq.h>
17#include <linux/module.h>
18#include <linux/of_device.h>
19#include <linux/of_platform.h>
20#include <linux/pm_runtime.h>
21#include <linux/slab.h>
22
23/* Register Offset Definitions */
24#define XGPIO_DATA_OFFSET (0x0) /* Data register */
25#define XGPIO_TRI_OFFSET (0x4) /* I/O direction register */
26
27#define XGPIO_CHANNEL0_OFFSET 0x0
28#define XGPIO_CHANNEL1_OFFSET 0x8
29
30#define XGPIO_GIER_OFFSET 0x11c /* Global Interrupt Enable */
31#define XGPIO_GIER_IE BIT(31)
32#define XGPIO_IPISR_OFFSET 0x120 /* IP Interrupt Status */
33#define XGPIO_IPIER_OFFSET 0x128 /* IP Interrupt Enable */
34
35/* Read/Write access to the GPIO registers */
36#if defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_X86)
37# define xgpio_readreg(offset) readl(offset)
38# define xgpio_writereg(offset, val) writel(val, offset)
39#else
40# define xgpio_readreg(offset) __raw_readl(offset)
41# define xgpio_writereg(offset, val) __raw_writel(val, offset)
42#endif
43
44/**
45 * struct xgpio_instance - Stores information about GPIO device
46 * @gc: GPIO chip
47 * @regs: register block
48 * @hw_map: GPIO pin mapping on hardware side
49 * @sw_map: GPIO pin mapping on software side
50 * @state: GPIO write state shadow register
51 * @last_irq_read: GPIO read state register from last interrupt
52 * @dir: GPIO direction shadow register
53 * @gpio_lock: Lock used for synchronization
54 * @irq: IRQ used by GPIO device
55 * @irqchip: IRQ chip
56 * @enable: GPIO IRQ enable/disable bitfield
57 * @rising_edge: GPIO IRQ rising edge enable/disable bitfield
58 * @falling_edge: GPIO IRQ falling edge enable/disable bitfield
59 * @clk: clock resource for this driver
60 */
61struct xgpio_instance {
62 struct gpio_chip gc;
63 void __iomem *regs;
64 DECLARE_BITMAP(hw_map, 64);
65 DECLARE_BITMAP(sw_map, 64);
66 DECLARE_BITMAP(state, 64);
67 DECLARE_BITMAP(last_irq_read, 64);
68 DECLARE_BITMAP(dir, 64);
69 spinlock_t gpio_lock; /* For serializing operations */
70 int irq;
71 struct irq_chip irqchip;
72 DECLARE_BITMAP(enable, 64);
73 DECLARE_BITMAP(rising_edge, 64);
74 DECLARE_BITMAP(falling_edge, 64);
75 struct clk *clk;
76};
77
78static inline int xgpio_from_bit(struct xgpio_instance *chip, int bit)
79{
80 return bitmap_bitremap(bit, chip->hw_map, chip->sw_map, 64);
81}
82
83static inline int xgpio_to_bit(struct xgpio_instance *chip, int gpio)
84{
85 return bitmap_bitremap(gpio, chip->sw_map, chip->hw_map, 64);
86}
87
88static inline u32 xgpio_get_value32(const unsigned long *map, int bit)
89{
90 const size_t index = BIT_WORD(bit);
91 const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5);
92
93 return (map[index] >> offset) & 0xFFFFFFFFul;
94}
95
96static inline void xgpio_set_value32(unsigned long *map, int bit, u32 v)
97{
98 const size_t index = BIT_WORD(bit);
99 const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5);
100
101 map[index] &= ~(0xFFFFFFFFul << offset);
102 map[index] |= (unsigned long)v << offset;
103}
104
105static inline int xgpio_regoffset(struct xgpio_instance *chip, int ch)
106{
107 switch (ch) {
108 case 0:
109 return XGPIO_CHANNEL0_OFFSET;
110 case 1:
111 return XGPIO_CHANNEL1_OFFSET;
112 default:
113 return -EINVAL;
114 }
115}
116
117static void xgpio_read_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a)
118{
119 void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32);
120
121 xgpio_set_value32(a, bit, xgpio_readreg(addr));
122}
123
124static void xgpio_write_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a)
125{
126 void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32);
127
128 xgpio_writereg(addr, xgpio_get_value32(a, bit));
129}
130
131static void xgpio_read_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a)
132{
133 int bit, lastbit = xgpio_to_bit(chip, chip->gc.ngpio - 1);
134
135 for (bit = 0; bit <= lastbit ; bit += 32)
136 xgpio_read_ch(chip, reg, bit, a);
137}
138
139static void xgpio_write_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a)
140{
141 int bit, lastbit = xgpio_to_bit(chip, chip->gc.ngpio - 1);
142
143 for (bit = 0; bit <= lastbit ; bit += 32)
144 xgpio_write_ch(chip, reg, bit, a);
145}
146
147/**
148 * xgpio_get - Read the specified signal of the GPIO device.
149 * @gc: Pointer to gpio_chip device structure.
150 * @gpio: GPIO signal number.
151 *
152 * This function reads the specified signal of the GPIO device.
153 *
154 * Return:
155 * 0 if direction of GPIO signals is set as input otherwise it
156 * returns negative error value.
157 */
158static int xgpio_get(struct gpio_chip *gc, unsigned int gpio)
159{
160 struct xgpio_instance *chip = gpiochip_get_data(gc);
161 int bit = xgpio_to_bit(chip, gpio);
162 DECLARE_BITMAP(state, 64);
163
164 xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, state);
165
166 return test_bit(bit, state);
167}
168
169/**
170 * xgpio_set - Write the specified signal of the GPIO device.
171 * @gc: Pointer to gpio_chip device structure.
172 * @gpio: GPIO signal number.
173 * @val: Value to be written to specified signal.
174 *
175 * This function writes the specified value in to the specified signal of the
176 * GPIO device.
177 */
178static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
179{
180 unsigned long flags;
181 struct xgpio_instance *chip = gpiochip_get_data(gc);
182 int bit = xgpio_to_bit(chip, gpio);
183
184 spin_lock_irqsave(&chip->gpio_lock, flags);
185
186 /* Write to GPIO signal and set its direction to output */
187 __assign_bit(bit, chip->state, val);
188
189 xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state);
190
191 spin_unlock_irqrestore(&chip->gpio_lock, flags);
192}
193
194/**
195 * xgpio_set_multiple - Write the specified signals of the GPIO device.
196 * @gc: Pointer to gpio_chip device structure.
197 * @mask: Mask of the GPIOS to modify.
198 * @bits: Value to be wrote on each GPIO
199 *
200 * This function writes the specified values into the specified signals of the
201 * GPIO devices.
202 */
203static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
204 unsigned long *bits)
205{
206 DECLARE_BITMAP(hw_mask, 64);
207 DECLARE_BITMAP(hw_bits, 64);
208 DECLARE_BITMAP(state, 64);
209 unsigned long flags;
210 struct xgpio_instance *chip = gpiochip_get_data(gc);
211
212 bitmap_remap(hw_mask, mask, chip->sw_map, chip->hw_map, 64);
213 bitmap_remap(hw_bits, bits, chip->sw_map, chip->hw_map, 64);
214
215 spin_lock_irqsave(&chip->gpio_lock, flags);
216
217 bitmap_replace(state, chip->state, hw_bits, hw_mask, 64);
218
219 xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, state);
220
221 bitmap_copy(chip->state, state, 64);
222
223 spin_unlock_irqrestore(&chip->gpio_lock, flags);
224}
225
226/**
227 * xgpio_dir_in - Set the direction of the specified GPIO signal as input.
228 * @gc: Pointer to gpio_chip device structure.
229 * @gpio: GPIO signal number.
230 *
231 * Return:
232 * 0 - if direction of GPIO signals is set as input
233 * otherwise it returns negative error value.
234 */
235static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
236{
237 unsigned long flags;
238 struct xgpio_instance *chip = gpiochip_get_data(gc);
239 int bit = xgpio_to_bit(chip, gpio);
240
241 spin_lock_irqsave(&chip->gpio_lock, flags);
242
243 /* Set the GPIO bit in shadow register and set direction as input */
244 __set_bit(bit, chip->dir);
245 xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir);
246
247 spin_unlock_irqrestore(&chip->gpio_lock, flags);
248
249 return 0;
250}
251
252/**
253 * xgpio_dir_out - Set the direction of the specified GPIO signal as output.
254 * @gc: Pointer to gpio_chip device structure.
255 * @gpio: GPIO signal number.
256 * @val: Value to be written to specified signal.
257 *
258 * This function sets the direction of specified GPIO signal as output.
259 *
260 * Return:
261 * If all GPIO signals of GPIO chip is configured as input then it returns
262 * error otherwise it returns 0.
263 */
264static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
265{
266 unsigned long flags;
267 struct xgpio_instance *chip = gpiochip_get_data(gc);
268 int bit = xgpio_to_bit(chip, gpio);
269
270 spin_lock_irqsave(&chip->gpio_lock, flags);
271
272 /* Write state of GPIO signal */
273 __assign_bit(bit, chip->state, val);
274 xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state);
275
276 /* Clear the GPIO bit in shadow register and set direction as output */
277 __clear_bit(bit, chip->dir);
278 xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir);
279
280 spin_unlock_irqrestore(&chip->gpio_lock, flags);
281
282 return 0;
283}
284
285/**
286 * xgpio_save_regs - Set initial values of GPIO pins
287 * @chip: Pointer to GPIO instance
288 */
289static void xgpio_save_regs(struct xgpio_instance *chip)
290{
291 xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, chip->state);
292 xgpio_write_ch_all(chip, XGPIO_TRI_OFFSET, chip->dir);
293}
294
295static int xgpio_request(struct gpio_chip *chip, unsigned int offset)
296{
297 int ret;
298
299 ret = pm_runtime_get_sync(chip->parent);
300 /*
301 * If the device is already active pm_runtime_get() will return 1 on
302 * success, but gpio_request still needs to return 0.
303 */
304 return ret < 0 ? ret : 0;
305}
306
307static void xgpio_free(struct gpio_chip *chip, unsigned int offset)
308{
309 pm_runtime_put(chip->parent);
310}
311
312static int __maybe_unused xgpio_suspend(struct device *dev)
313{
314 struct xgpio_instance *gpio = dev_get_drvdata(dev);
315 struct irq_data *data = irq_get_irq_data(gpio->irq);
316
317 if (!data) {
318 dev_dbg(dev, "IRQ not connected\n");
319 return pm_runtime_force_suspend(dev);
320 }
321
322 if (!irqd_is_wakeup_set(data))
323 return pm_runtime_force_suspend(dev);
324
325 return 0;
326}
327
328/**
329 * xgpio_remove - Remove method for the GPIO device.
330 * @pdev: pointer to the platform device
331 *
332 * This function remove gpiochips and frees all the allocated resources.
333 *
334 * Return: 0 always
335 */
336static int xgpio_remove(struct platform_device *pdev)
337{
338 struct xgpio_instance *gpio = platform_get_drvdata(pdev);
339
340 pm_runtime_get_sync(&pdev->dev);
341 pm_runtime_put_noidle(&pdev->dev);
342 pm_runtime_disable(&pdev->dev);
343 clk_disable_unprepare(gpio->clk);
344
345 return 0;
346}
347
348/**
349 * xgpio_irq_ack - Acknowledge a child GPIO interrupt.
350 * @irq_data: per IRQ and chip data passed down to chip functions
351 * This currently does nothing, but irq_ack is unconditionally called by
352 * handle_edge_irq and therefore must be defined.
353 */
354static void xgpio_irq_ack(struct irq_data *irq_data)
355{
356}
357
358static int __maybe_unused xgpio_resume(struct device *dev)
359{
360 struct xgpio_instance *gpio = dev_get_drvdata(dev);
361 struct irq_data *data = irq_get_irq_data(gpio->irq);
362
363 if (!data) {
364 dev_dbg(dev, "IRQ not connected\n");
365 return pm_runtime_force_resume(dev);
366 }
367
368 if (!irqd_is_wakeup_set(data))
369 return pm_runtime_force_resume(dev);
370
371 return 0;
372}
373
374static int __maybe_unused xgpio_runtime_suspend(struct device *dev)
375{
376 struct xgpio_instance *gpio = dev_get_drvdata(dev);
377
378 clk_disable(gpio->clk);
379
380 return 0;
381}
382
383static int __maybe_unused xgpio_runtime_resume(struct device *dev)
384{
385 struct xgpio_instance *gpio = dev_get_drvdata(dev);
386
387 return clk_enable(gpio->clk);
388}
389
390static const struct dev_pm_ops xgpio_dev_pm_ops = {
391 SET_SYSTEM_SLEEP_PM_OPS(xgpio_suspend, xgpio_resume)
392 SET_RUNTIME_PM_OPS(xgpio_runtime_suspend,
393 xgpio_runtime_resume, NULL)
394};
395
396/**
397 * xgpio_irq_mask - Write the specified signal of the GPIO device.
398 * @irq_data: per IRQ and chip data passed down to chip functions
399 */
400static void xgpio_irq_mask(struct irq_data *irq_data)
401{
402 unsigned long flags;
403 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data);
404 int irq_offset = irqd_to_hwirq(irq_data);
405 int bit = xgpio_to_bit(chip, irq_offset);
406 u32 mask = BIT(bit / 32), temp;
407
408 spin_lock_irqsave(&chip->gpio_lock, flags);
409
410 __clear_bit(bit, chip->enable);
411
412 if (xgpio_get_value32(chip->enable, bit) == 0) {
413 /* Disable per channel interrupt */
414 temp = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET);
415 temp &= ~mask;
416 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, temp);
417 }
418 spin_unlock_irqrestore(&chip->gpio_lock, flags);
419}
420
421/**
422 * xgpio_irq_unmask - Write the specified signal of the GPIO device.
423 * @irq_data: per IRQ and chip data passed down to chip functions
424 */
425static void xgpio_irq_unmask(struct irq_data *irq_data)
426{
427 unsigned long flags;
428 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data);
429 int irq_offset = irqd_to_hwirq(irq_data);
430 int bit = xgpio_to_bit(chip, irq_offset);
431 u32 old_enable = xgpio_get_value32(chip->enable, bit);
432 u32 mask = BIT(bit / 32), val;
433
434 spin_lock_irqsave(&chip->gpio_lock, flags);
435
436 __set_bit(bit, chip->enable);
437
438 if (old_enable == 0) {
439 /* Clear any existing per-channel interrupts */
440 val = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
441 val &= mask;
442 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, val);
443
444 /* Update GPIO IRQ read data before enabling interrupt*/
445 xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, chip->last_irq_read);
446
447 /* Enable per channel interrupt */
448 val = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET);
449 val |= mask;
450 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, val);
451 }
452
453 spin_unlock_irqrestore(&chip->gpio_lock, flags);
454}
455
456/**
457 * xgpio_set_irq_type - Write the specified signal of the GPIO device.
458 * @irq_data: Per IRQ and chip data passed down to chip functions
459 * @type: Interrupt type that is to be set for the gpio pin
460 *
461 * Return:
462 * 0 if interrupt type is supported otherwise -EINVAL
463 */
464static int xgpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
465{
466 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data);
467 int irq_offset = irqd_to_hwirq(irq_data);
468 int bit = xgpio_to_bit(chip, irq_offset);
469
470 /*
471 * The Xilinx GPIO hardware provides a single interrupt status
472 * indication for any state change in a given GPIO channel (bank).
473 * Therefore, only rising edge or falling edge triggers are
474 * supported.
475 */
476 switch (type & IRQ_TYPE_SENSE_MASK) {
477 case IRQ_TYPE_EDGE_BOTH:
478 __set_bit(bit, chip->rising_edge);
479 __set_bit(bit, chip->falling_edge);
480 break;
481 case IRQ_TYPE_EDGE_RISING:
482 __set_bit(bit, chip->rising_edge);
483 __clear_bit(bit, chip->falling_edge);
484 break;
485 case IRQ_TYPE_EDGE_FALLING:
486 __clear_bit(bit, chip->rising_edge);
487 __set_bit(bit, chip->falling_edge);
488 break;
489 default:
490 return -EINVAL;
491 }
492
493 irq_set_handler_locked(irq_data, handle_edge_irq);
494 return 0;
495}
496
497/**
498 * xgpio_irqhandler - Gpio interrupt service routine
499 * @desc: Pointer to interrupt description
500 */
501static void xgpio_irqhandler(struct irq_desc *desc)
502{
503 struct xgpio_instance *chip = irq_desc_get_handler_data(desc);
504 struct gpio_chip *gc = &chip->gc;
505 struct irq_chip *irqchip = irq_desc_get_chip(desc);
506 DECLARE_BITMAP(rising, 64);
507 DECLARE_BITMAP(falling, 64);
508 DECLARE_BITMAP(all, 64);
509 int irq_offset;
510 u32 status;
511 u32 bit;
512
513 status = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
514 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, status);
515
516 chained_irq_enter(irqchip, desc);
517
518 spin_lock(&chip->gpio_lock);
519
520 xgpio_read_ch_all(chip, XGPIO_DATA_OFFSET, all);
521
522 bitmap_complement(rising, chip->last_irq_read, 64);
523 bitmap_and(rising, rising, all, 64);
524 bitmap_and(rising, rising, chip->enable, 64);
525 bitmap_and(rising, rising, chip->rising_edge, 64);
526
527 bitmap_complement(falling, all, 64);
528 bitmap_and(falling, falling, chip->last_irq_read, 64);
529 bitmap_and(falling, falling, chip->enable, 64);
530 bitmap_and(falling, falling, chip->falling_edge, 64);
531
532 bitmap_copy(chip->last_irq_read, all, 64);
533 bitmap_or(all, rising, falling, 64);
534
535 spin_unlock(&chip->gpio_lock);
536
537 dev_dbg(gc->parent, "IRQ rising %*pb falling %*pb\n", 64, rising, 64, falling);
538
539 for_each_set_bit(bit, all, 64) {
540 irq_offset = xgpio_from_bit(chip, bit);
541 generic_handle_domain_irq(gc->irq.domain, irq_offset);
542 }
543
544 chained_irq_exit(irqchip, desc);
545}
546
547/**
548 * xgpio_probe - Probe method for the GPIO device.
549 * @pdev: pointer to the platform device
550 *
551 * Return:
552 * It returns 0, if the driver is bound to the GPIO device, or
553 * a negative value if there is an error.
554 */
555static int xgpio_probe(struct platform_device *pdev)
556{
557 struct xgpio_instance *chip;
558 int status = 0;
559 struct device_node *np = pdev->dev.of_node;
560 u32 is_dual = 0;
561 u32 cells = 2;
562 u32 width[2];
563 u32 state[2];
564 u32 dir[2];
565 struct gpio_irq_chip *girq;
566 u32 temp;
567
568 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
569 if (!chip)
570 return -ENOMEM;
571
572 platform_set_drvdata(pdev, chip);
573
574 /* First, check if the device is dual-channel */
575 of_property_read_u32(np, "xlnx,is-dual", &is_dual);
576
577 /* Setup defaults */
578 memset32(width, 0, ARRAY_SIZE(width));
579 memset32(state, 0, ARRAY_SIZE(state));
580 memset32(dir, 0xFFFFFFFF, ARRAY_SIZE(dir));
581
582 /* Update GPIO state shadow register with default value */
583 of_property_read_u32(np, "xlnx,dout-default", &state[0]);
584 of_property_read_u32(np, "xlnx,dout-default-2", &state[1]);
585
586 bitmap_from_arr32(chip->state, state, 64);
587
588 /* Update GPIO direction shadow register with default value */
589 of_property_read_u32(np, "xlnx,tri-default", &dir[0]);
590 of_property_read_u32(np, "xlnx,tri-default-2", &dir[1]);
591
592 bitmap_from_arr32(chip->dir, dir, 64);
593
594 /* Update cells with gpio-cells value */
595 if (of_property_read_u32(np, "#gpio-cells", &cells))
596 dev_dbg(&pdev->dev, "Missing gpio-cells property\n");
597
598 if (cells != 2) {
599 dev_err(&pdev->dev, "#gpio-cells mismatch\n");
600 return -EINVAL;
601 }
602
603 /*
604 * Check device node and parent device node for device width
605 * and assume default width of 32
606 */
607 if (of_property_read_u32(np, "xlnx,gpio-width", &width[0]))
608 width[0] = 32;
609
610 if (width[0] > 32)
611 return -EINVAL;
612
613 if (is_dual && of_property_read_u32(np, "xlnx,gpio2-width", &width[1]))
614 width[1] = 32;
615
616 if (width[1] > 32)
617 return -EINVAL;
618
619 /* Setup software pin mapping */
620 bitmap_set(chip->sw_map, 0, width[0] + width[1]);
621
622 /* Setup hardware pin mapping */
623 bitmap_set(chip->hw_map, 0, width[0]);
624 bitmap_set(chip->hw_map, 32, width[1]);
625
626 spin_lock_init(&chip->gpio_lock);
627
628 chip->gc.base = -1;
629 chip->gc.ngpio = bitmap_weight(chip->hw_map, 64);
630 chip->gc.parent = &pdev->dev;
631 chip->gc.direction_input = xgpio_dir_in;
632 chip->gc.direction_output = xgpio_dir_out;
633 chip->gc.of_gpio_n_cells = cells;
634 chip->gc.get = xgpio_get;
635 chip->gc.set = xgpio_set;
636 chip->gc.request = xgpio_request;
637 chip->gc.free = xgpio_free;
638 chip->gc.set_multiple = xgpio_set_multiple;
639
640 chip->gc.label = dev_name(&pdev->dev);
641
642 chip->regs = devm_platform_ioremap_resource(pdev, 0);
643 if (IS_ERR(chip->regs)) {
644 dev_err(&pdev->dev, "failed to ioremap memory resource\n");
645 return PTR_ERR(chip->regs);
646 }
647
648 chip->clk = devm_clk_get_optional(&pdev->dev, NULL);
649 if (IS_ERR(chip->clk))
650 return dev_err_probe(&pdev->dev, PTR_ERR(chip->clk), "input clock not found.\n");
651
652 status = clk_prepare_enable(chip->clk);
653 if (status < 0) {
654 dev_err(&pdev->dev, "Failed to prepare clk\n");
655 return status;
656 }
657 pm_runtime_get_noresume(&pdev->dev);
658 pm_runtime_set_active(&pdev->dev);
659 pm_runtime_enable(&pdev->dev);
660
661 xgpio_save_regs(chip);
662
663 chip->irq = platform_get_irq_optional(pdev, 0);
664 if (chip->irq <= 0)
665 goto skip_irq;
666
667 chip->irqchip.name = "gpio-xilinx";
668 chip->irqchip.irq_ack = xgpio_irq_ack;
669 chip->irqchip.irq_mask = xgpio_irq_mask;
670 chip->irqchip.irq_unmask = xgpio_irq_unmask;
671 chip->irqchip.irq_set_type = xgpio_set_irq_type;
672
673 /* Disable per-channel interrupts */
674 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, 0);
675 /* Clear any existing per-channel interrupts */
676 temp = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
677 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, temp);
678 /* Enable global interrupts */
679 xgpio_writereg(chip->regs + XGPIO_GIER_OFFSET, XGPIO_GIER_IE);
680
681 girq = &chip->gc.irq;
682 girq->chip = &chip->irqchip;
683 girq->parent_handler = xgpio_irqhandler;
684 girq->num_parents = 1;
685 girq->parents = devm_kcalloc(&pdev->dev, 1,
686 sizeof(*girq->parents),
687 GFP_KERNEL);
688 if (!girq->parents) {
689 status = -ENOMEM;
690 goto err_pm_put;
691 }
692 girq->parents[0] = chip->irq;
693 girq->default_type = IRQ_TYPE_NONE;
694 girq->handler = handle_bad_irq;
695
696skip_irq:
697 status = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip);
698 if (status) {
699 dev_err(&pdev->dev, "failed to add GPIO chip\n");
700 goto err_pm_put;
701 }
702
703 pm_runtime_put(&pdev->dev);
704 return 0;
705
706err_pm_put:
707 pm_runtime_disable(&pdev->dev);
708 pm_runtime_put_noidle(&pdev->dev);
709 clk_disable_unprepare(chip->clk);
710 return status;
711}
712
713static const struct of_device_id xgpio_of_match[] = {
714 { .compatible = "xlnx,xps-gpio-1.00.a", },
715 { /* end of list */ },
716};
717
718MODULE_DEVICE_TABLE(of, xgpio_of_match);
719
720static struct platform_driver xgpio_plat_driver = {
721 .probe = xgpio_probe,
722 .remove = xgpio_remove,
723 .driver = {
724 .name = "gpio-xilinx",
725 .of_match_table = xgpio_of_match,
726 .pm = &xgpio_dev_pm_ops,
727 },
728};
729
730static int __init xgpio_init(void)
731{
732 return platform_driver_register(&xgpio_plat_driver);
733}
734
735subsys_initcall(xgpio_init);
736
737static void __exit xgpio_exit(void)
738{
739 platform_driver_unregister(&xgpio_plat_driver);
740}
741module_exit(xgpio_exit);
742
743MODULE_AUTHOR("Xilinx, Inc.");
744MODULE_DESCRIPTION("Xilinx GPIO driver");
745MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Xilinx gpio driver for xps/axi_gpio IP.
4 *
5 * Copyright 2008 - 2013 Xilinx, Inc.
6 */
7
8#include <linux/bitmap.h>
9#include <linux/bitops.h>
10#include <linux/clk.h>
11#include <linux/errno.h>
12#include <linux/gpio/driver.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/irq.h>
17#include <linux/module.h>
18#include <linux/platform_device.h>
19#include <linux/pm_runtime.h>
20#include <linux/property.h>
21#include <linux/slab.h>
22
23/* Register Offset Definitions */
24#define XGPIO_DATA_OFFSET (0x0) /* Data register */
25#define XGPIO_TRI_OFFSET (0x4) /* I/O direction register */
26
27#define XGPIO_CHANNEL0_OFFSET 0x0
28#define XGPIO_CHANNEL1_OFFSET 0x8
29
30#define XGPIO_GIER_OFFSET 0x11c /* Global Interrupt Enable */
31#define XGPIO_GIER_IE BIT(31)
32#define XGPIO_IPISR_OFFSET 0x120 /* IP Interrupt Status */
33#define XGPIO_IPIER_OFFSET 0x128 /* IP Interrupt Enable */
34
35/* Read/Write access to the GPIO registers */
36#if defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_X86)
37# define xgpio_readreg(offset) readl(offset)
38# define xgpio_writereg(offset, val) writel(val, offset)
39#else
40# define xgpio_readreg(offset) __raw_readl(offset)
41# define xgpio_writereg(offset, val) __raw_writel(val, offset)
42#endif
43
44/**
45 * struct xgpio_instance - Stores information about GPIO device
46 * @gc: GPIO chip
47 * @regs: register block
48 * @hw_map: GPIO pin mapping on hardware side
49 * @sw_map: GPIO pin mapping on software side
50 * @state: GPIO write state shadow register
51 * @last_irq_read: GPIO read state register from last interrupt
52 * @dir: GPIO direction shadow register
53 * @gpio_lock: Lock used for synchronization
54 * @irq: IRQ used by GPIO device
55 * @enable: GPIO IRQ enable/disable bitfield
56 * @rising_edge: GPIO IRQ rising edge enable/disable bitfield
57 * @falling_edge: GPIO IRQ falling edge enable/disable bitfield
58 * @clk: clock resource for this driver
59 */
60struct xgpio_instance {
61 struct gpio_chip gc;
62 void __iomem *regs;
63 DECLARE_BITMAP(hw_map, 64);
64 DECLARE_BITMAP(sw_map, 64);
65 DECLARE_BITMAP(state, 64);
66 DECLARE_BITMAP(last_irq_read, 64);
67 DECLARE_BITMAP(dir, 64);
68 raw_spinlock_t gpio_lock; /* For serializing operations */
69 int irq;
70 DECLARE_BITMAP(enable, 64);
71 DECLARE_BITMAP(rising_edge, 64);
72 DECLARE_BITMAP(falling_edge, 64);
73 struct clk *clk;
74};
75
76static inline int xgpio_from_bit(struct xgpio_instance *chip, int bit)
77{
78 return bitmap_bitremap(bit, chip->hw_map, chip->sw_map, 64);
79}
80
81static inline int xgpio_to_bit(struct xgpio_instance *chip, int gpio)
82{
83 return bitmap_bitremap(gpio, chip->sw_map, chip->hw_map, 64);
84}
85
86static inline u32 xgpio_get_value32(const unsigned long *map, int bit)
87{
88 const size_t index = BIT_WORD(bit);
89 const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5);
90
91 return (map[index] >> offset) & 0xFFFFFFFFul;
92}
93
94static inline void xgpio_set_value32(unsigned long *map, int bit, u32 v)
95{
96 const size_t index = BIT_WORD(bit);
97 const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5);
98
99 map[index] &= ~(0xFFFFFFFFul << offset);
100 map[index] |= (unsigned long)v << offset;
101}
102
103static inline int xgpio_regoffset(struct xgpio_instance *chip, int ch)
104{
105 switch (ch) {
106 case 0:
107 return XGPIO_CHANNEL0_OFFSET;
108 case 1:
109 return XGPIO_CHANNEL1_OFFSET;
110 default:
111 return -EINVAL;
112 }
113}
114
115static void xgpio_read_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a)
116{
117 void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32);
118
119 xgpio_set_value32(a, bit, xgpio_readreg(addr));
120}
121
122static void xgpio_write_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a)
123{
124 void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32);
125
126 xgpio_writereg(addr, xgpio_get_value32(a, bit));
127}
128
129static void xgpio_read_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a)
130{
131 int bit, lastbit = xgpio_to_bit(chip, chip->gc.ngpio - 1);
132
133 for (bit = 0; bit <= lastbit ; bit += 32)
134 xgpio_read_ch(chip, reg, bit, a);
135}
136
137static void xgpio_write_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a)
138{
139 int bit, lastbit = xgpio_to_bit(chip, chip->gc.ngpio - 1);
140
141 for (bit = 0; bit <= lastbit ; bit += 32)
142 xgpio_write_ch(chip, reg, bit, a);
143}
144
145/**
146 * xgpio_get - Read the specified signal of the GPIO device.
147 * @gc: Pointer to gpio_chip device structure.
148 * @gpio: GPIO signal number.
149 *
150 * This function reads the specified signal of the GPIO device.
151 *
152 * Return:
153 * 0 if direction of GPIO signals is set as input otherwise it
154 * returns negative error value.
155 */
156static int xgpio_get(struct gpio_chip *gc, unsigned int gpio)
157{
158 struct xgpio_instance *chip = gpiochip_get_data(gc);
159 int bit = xgpio_to_bit(chip, gpio);
160 DECLARE_BITMAP(state, 64);
161
162 xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, state);
163
164 return test_bit(bit, state);
165}
166
167/**
168 * xgpio_set - Write the specified signal of the GPIO device.
169 * @gc: Pointer to gpio_chip device structure.
170 * @gpio: GPIO signal number.
171 * @val: Value to be written to specified signal.
172 *
173 * This function writes the specified value in to the specified signal of the
174 * GPIO device.
175 */
176static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
177{
178 unsigned long flags;
179 struct xgpio_instance *chip = gpiochip_get_data(gc);
180 int bit = xgpio_to_bit(chip, gpio);
181
182 raw_spin_lock_irqsave(&chip->gpio_lock, flags);
183
184 /* Write to GPIO signal and set its direction to output */
185 __assign_bit(bit, chip->state, val);
186
187 xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state);
188
189 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
190}
191
192/**
193 * xgpio_set_multiple - Write the specified signals of the GPIO device.
194 * @gc: Pointer to gpio_chip device structure.
195 * @mask: Mask of the GPIOS to modify.
196 * @bits: Value to be wrote on each GPIO
197 *
198 * This function writes the specified values into the specified signals of the
199 * GPIO devices.
200 */
201static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
202 unsigned long *bits)
203{
204 DECLARE_BITMAP(hw_mask, 64);
205 DECLARE_BITMAP(hw_bits, 64);
206 DECLARE_BITMAP(state, 64);
207 unsigned long flags;
208 struct xgpio_instance *chip = gpiochip_get_data(gc);
209
210 bitmap_remap(hw_mask, mask, chip->sw_map, chip->hw_map, 64);
211 bitmap_remap(hw_bits, bits, chip->sw_map, chip->hw_map, 64);
212
213 raw_spin_lock_irqsave(&chip->gpio_lock, flags);
214
215 bitmap_replace(state, chip->state, hw_bits, hw_mask, 64);
216
217 xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, state);
218
219 bitmap_copy(chip->state, state, 64);
220
221 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
222}
223
224/**
225 * xgpio_dir_in - Set the direction of the specified GPIO signal as input.
226 * @gc: Pointer to gpio_chip device structure.
227 * @gpio: GPIO signal number.
228 *
229 * Return:
230 * 0 - if direction of GPIO signals is set as input
231 * otherwise it returns negative error value.
232 */
233static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
234{
235 unsigned long flags;
236 struct xgpio_instance *chip = gpiochip_get_data(gc);
237 int bit = xgpio_to_bit(chip, gpio);
238
239 raw_spin_lock_irqsave(&chip->gpio_lock, flags);
240
241 /* Set the GPIO bit in shadow register and set direction as input */
242 __set_bit(bit, chip->dir);
243 xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir);
244
245 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
246
247 return 0;
248}
249
250/**
251 * xgpio_dir_out - Set the direction of the specified GPIO signal as output.
252 * @gc: Pointer to gpio_chip device structure.
253 * @gpio: GPIO signal number.
254 * @val: Value to be written to specified signal.
255 *
256 * This function sets the direction of specified GPIO signal as output.
257 *
258 * Return:
259 * If all GPIO signals of GPIO chip is configured as input then it returns
260 * error otherwise it returns 0.
261 */
262static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
263{
264 unsigned long flags;
265 struct xgpio_instance *chip = gpiochip_get_data(gc);
266 int bit = xgpio_to_bit(chip, gpio);
267
268 raw_spin_lock_irqsave(&chip->gpio_lock, flags);
269
270 /* Write state of GPIO signal */
271 __assign_bit(bit, chip->state, val);
272 xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state);
273
274 /* Clear the GPIO bit in shadow register and set direction as output */
275 __clear_bit(bit, chip->dir);
276 xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir);
277
278 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
279
280 return 0;
281}
282
283/**
284 * xgpio_save_regs - Set initial values of GPIO pins
285 * @chip: Pointer to GPIO instance
286 */
287static void xgpio_save_regs(struct xgpio_instance *chip)
288{
289 xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, chip->state);
290 xgpio_write_ch_all(chip, XGPIO_TRI_OFFSET, chip->dir);
291}
292
293static int xgpio_request(struct gpio_chip *chip, unsigned int offset)
294{
295 int ret;
296
297 ret = pm_runtime_get_sync(chip->parent);
298 /*
299 * If the device is already active pm_runtime_get() will return 1 on
300 * success, but gpio_request still needs to return 0.
301 */
302 return ret < 0 ? ret : 0;
303}
304
305static void xgpio_free(struct gpio_chip *chip, unsigned int offset)
306{
307 pm_runtime_put(chip->parent);
308}
309
310static int __maybe_unused xgpio_suspend(struct device *dev)
311{
312 struct xgpio_instance *gpio = dev_get_drvdata(dev);
313 struct irq_data *data = irq_get_irq_data(gpio->irq);
314
315 if (!data) {
316 dev_dbg(dev, "IRQ not connected\n");
317 return pm_runtime_force_suspend(dev);
318 }
319
320 if (!irqd_is_wakeup_set(data))
321 return pm_runtime_force_suspend(dev);
322
323 return 0;
324}
325
326/**
327 * xgpio_remove - Remove method for the GPIO device.
328 * @pdev: pointer to the platform device
329 *
330 * This function remove gpiochips and frees all the allocated resources.
331 *
332 * Return: 0 always
333 */
334static void xgpio_remove(struct platform_device *pdev)
335{
336 pm_runtime_get_sync(&pdev->dev);
337 pm_runtime_put_noidle(&pdev->dev);
338 pm_runtime_disable(&pdev->dev);
339}
340
341/**
342 * xgpio_irq_ack - Acknowledge a child GPIO interrupt.
343 * @irq_data: per IRQ and chip data passed down to chip functions
344 * This currently does nothing, but irq_ack is unconditionally called by
345 * handle_edge_irq and therefore must be defined.
346 */
347static void xgpio_irq_ack(struct irq_data *irq_data)
348{
349}
350
351static int __maybe_unused xgpio_resume(struct device *dev)
352{
353 struct xgpio_instance *gpio = dev_get_drvdata(dev);
354 struct irq_data *data = irq_get_irq_data(gpio->irq);
355
356 if (!data) {
357 dev_dbg(dev, "IRQ not connected\n");
358 return pm_runtime_force_resume(dev);
359 }
360
361 if (!irqd_is_wakeup_set(data))
362 return pm_runtime_force_resume(dev);
363
364 return 0;
365}
366
367static int __maybe_unused xgpio_runtime_suspend(struct device *dev)
368{
369 struct xgpio_instance *gpio = dev_get_drvdata(dev);
370
371 clk_disable(gpio->clk);
372
373 return 0;
374}
375
376static int __maybe_unused xgpio_runtime_resume(struct device *dev)
377{
378 struct xgpio_instance *gpio = dev_get_drvdata(dev);
379
380 return clk_enable(gpio->clk);
381}
382
383static const struct dev_pm_ops xgpio_dev_pm_ops = {
384 SET_SYSTEM_SLEEP_PM_OPS(xgpio_suspend, xgpio_resume)
385 SET_RUNTIME_PM_OPS(xgpio_runtime_suspend,
386 xgpio_runtime_resume, NULL)
387};
388
389/**
390 * xgpio_irq_mask - Write the specified signal of the GPIO device.
391 * @irq_data: per IRQ and chip data passed down to chip functions
392 */
393static void xgpio_irq_mask(struct irq_data *irq_data)
394{
395 unsigned long flags;
396 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data);
397 int irq_offset = irqd_to_hwirq(irq_data);
398 int bit = xgpio_to_bit(chip, irq_offset);
399 u32 mask = BIT(bit / 32), temp;
400
401 raw_spin_lock_irqsave(&chip->gpio_lock, flags);
402
403 __clear_bit(bit, chip->enable);
404
405 if (xgpio_get_value32(chip->enable, bit) == 0) {
406 /* Disable per channel interrupt */
407 temp = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET);
408 temp &= ~mask;
409 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, temp);
410 }
411 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
412
413 gpiochip_disable_irq(&chip->gc, irq_offset);
414}
415
416/**
417 * xgpio_irq_unmask - Write the specified signal of the GPIO device.
418 * @irq_data: per IRQ and chip data passed down to chip functions
419 */
420static void xgpio_irq_unmask(struct irq_data *irq_data)
421{
422 unsigned long flags;
423 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data);
424 int irq_offset = irqd_to_hwirq(irq_data);
425 int bit = xgpio_to_bit(chip, irq_offset);
426 u32 old_enable = xgpio_get_value32(chip->enable, bit);
427 u32 mask = BIT(bit / 32), val;
428
429 gpiochip_enable_irq(&chip->gc, irq_offset);
430
431 raw_spin_lock_irqsave(&chip->gpio_lock, flags);
432
433 __set_bit(bit, chip->enable);
434
435 if (old_enable == 0) {
436 /* Clear any existing per-channel interrupts */
437 val = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
438 val &= mask;
439 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, val);
440
441 /* Update GPIO IRQ read data before enabling interrupt*/
442 xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, chip->last_irq_read);
443
444 /* Enable per channel interrupt */
445 val = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET);
446 val |= mask;
447 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, val);
448 }
449
450 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
451}
452
453/**
454 * xgpio_set_irq_type - Write the specified signal of the GPIO device.
455 * @irq_data: Per IRQ and chip data passed down to chip functions
456 * @type: Interrupt type that is to be set for the gpio pin
457 *
458 * Return:
459 * 0 if interrupt type is supported otherwise -EINVAL
460 */
461static int xgpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
462{
463 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data);
464 int irq_offset = irqd_to_hwirq(irq_data);
465 int bit = xgpio_to_bit(chip, irq_offset);
466
467 /*
468 * The Xilinx GPIO hardware provides a single interrupt status
469 * indication for any state change in a given GPIO channel (bank).
470 * Therefore, only rising edge or falling edge triggers are
471 * supported.
472 */
473 switch (type & IRQ_TYPE_SENSE_MASK) {
474 case IRQ_TYPE_EDGE_BOTH:
475 __set_bit(bit, chip->rising_edge);
476 __set_bit(bit, chip->falling_edge);
477 break;
478 case IRQ_TYPE_EDGE_RISING:
479 __set_bit(bit, chip->rising_edge);
480 __clear_bit(bit, chip->falling_edge);
481 break;
482 case IRQ_TYPE_EDGE_FALLING:
483 __clear_bit(bit, chip->rising_edge);
484 __set_bit(bit, chip->falling_edge);
485 break;
486 default:
487 return -EINVAL;
488 }
489
490 irq_set_handler_locked(irq_data, handle_edge_irq);
491 return 0;
492}
493
494/**
495 * xgpio_irqhandler - Gpio interrupt service routine
496 * @desc: Pointer to interrupt description
497 */
498static void xgpio_irqhandler(struct irq_desc *desc)
499{
500 struct xgpio_instance *chip = irq_desc_get_handler_data(desc);
501 struct gpio_chip *gc = &chip->gc;
502 struct irq_chip *irqchip = irq_desc_get_chip(desc);
503 DECLARE_BITMAP(rising, 64);
504 DECLARE_BITMAP(falling, 64);
505 DECLARE_BITMAP(all, 64);
506 int irq_offset;
507 u32 status;
508 u32 bit;
509
510 status = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
511 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, status);
512
513 chained_irq_enter(irqchip, desc);
514
515 raw_spin_lock(&chip->gpio_lock);
516
517 xgpio_read_ch_all(chip, XGPIO_DATA_OFFSET, all);
518
519 bitmap_complement(rising, chip->last_irq_read, 64);
520 bitmap_and(rising, rising, all, 64);
521 bitmap_and(rising, rising, chip->enable, 64);
522 bitmap_and(rising, rising, chip->rising_edge, 64);
523
524 bitmap_complement(falling, all, 64);
525 bitmap_and(falling, falling, chip->last_irq_read, 64);
526 bitmap_and(falling, falling, chip->enable, 64);
527 bitmap_and(falling, falling, chip->falling_edge, 64);
528
529 bitmap_copy(chip->last_irq_read, all, 64);
530 bitmap_or(all, rising, falling, 64);
531
532 raw_spin_unlock(&chip->gpio_lock);
533
534 dev_dbg(gc->parent, "IRQ rising %*pb falling %*pb\n", 64, rising, 64, falling);
535
536 for_each_set_bit(bit, all, 64) {
537 irq_offset = xgpio_from_bit(chip, bit);
538 generic_handle_domain_irq(gc->irq.domain, irq_offset);
539 }
540
541 chained_irq_exit(irqchip, desc);
542}
543
544static const struct irq_chip xgpio_irq_chip = {
545 .name = "gpio-xilinx",
546 .irq_ack = xgpio_irq_ack,
547 .irq_mask = xgpio_irq_mask,
548 .irq_unmask = xgpio_irq_unmask,
549 .irq_set_type = xgpio_set_irq_type,
550 .flags = IRQCHIP_IMMUTABLE,
551 GPIOCHIP_IRQ_RESOURCE_HELPERS,
552};
553
554/**
555 * xgpio_probe - Probe method for the GPIO device.
556 * @pdev: pointer to the platform device
557 *
558 * Return:
559 * It returns 0, if the driver is bound to the GPIO device, or
560 * a negative value if there is an error.
561 */
562static int xgpio_probe(struct platform_device *pdev)
563{
564 struct device *dev = &pdev->dev;
565 struct xgpio_instance *chip;
566 int status = 0;
567 u32 is_dual = 0;
568 u32 width[2];
569 u32 state[2];
570 u32 dir[2];
571 struct gpio_irq_chip *girq;
572 u32 temp;
573
574 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
575 if (!chip)
576 return -ENOMEM;
577
578 platform_set_drvdata(pdev, chip);
579
580 /* First, check if the device is dual-channel */
581 device_property_read_u32(dev, "xlnx,is-dual", &is_dual);
582
583 /* Setup defaults */
584 memset32(width, 0, ARRAY_SIZE(width));
585 memset32(state, 0, ARRAY_SIZE(state));
586 memset32(dir, 0xFFFFFFFF, ARRAY_SIZE(dir));
587
588 /* Update GPIO state shadow register with default value */
589 device_property_read_u32(dev, "xlnx,dout-default", &state[0]);
590 device_property_read_u32(dev, "xlnx,dout-default-2", &state[1]);
591
592 bitmap_from_arr32(chip->state, state, 64);
593
594 /* Update GPIO direction shadow register with default value */
595 device_property_read_u32(dev, "xlnx,tri-default", &dir[0]);
596 device_property_read_u32(dev, "xlnx,tri-default-2", &dir[1]);
597
598 bitmap_from_arr32(chip->dir, dir, 64);
599
600 /*
601 * Check device node and parent device node for device width
602 * and assume default width of 32
603 */
604 if (device_property_read_u32(dev, "xlnx,gpio-width", &width[0]))
605 width[0] = 32;
606
607 if (width[0] > 32)
608 return -EINVAL;
609
610 if (is_dual && device_property_read_u32(dev, "xlnx,gpio2-width", &width[1]))
611 width[1] = 32;
612
613 if (width[1] > 32)
614 return -EINVAL;
615
616 /* Setup software pin mapping */
617 bitmap_set(chip->sw_map, 0, width[0] + width[1]);
618
619 /* Setup hardware pin mapping */
620 bitmap_set(chip->hw_map, 0, width[0]);
621 bitmap_set(chip->hw_map, 32, width[1]);
622
623 raw_spin_lock_init(&chip->gpio_lock);
624
625 chip->gc.base = -1;
626 chip->gc.ngpio = bitmap_weight(chip->hw_map, 64);
627 chip->gc.parent = dev;
628 chip->gc.direction_input = xgpio_dir_in;
629 chip->gc.direction_output = xgpio_dir_out;
630 chip->gc.get = xgpio_get;
631 chip->gc.set = xgpio_set;
632 chip->gc.request = xgpio_request;
633 chip->gc.free = xgpio_free;
634 chip->gc.set_multiple = xgpio_set_multiple;
635
636 chip->gc.label = dev_name(dev);
637
638 chip->regs = devm_platform_ioremap_resource(pdev, 0);
639 if (IS_ERR(chip->regs)) {
640 dev_err(dev, "failed to ioremap memory resource\n");
641 return PTR_ERR(chip->regs);
642 }
643
644 chip->clk = devm_clk_get_optional_enabled(dev, NULL);
645 if (IS_ERR(chip->clk))
646 return dev_err_probe(dev, PTR_ERR(chip->clk), "input clock not found.\n");
647
648 pm_runtime_get_noresume(dev);
649 pm_runtime_set_active(dev);
650 pm_runtime_enable(dev);
651
652 xgpio_save_regs(chip);
653
654 chip->irq = platform_get_irq_optional(pdev, 0);
655 if (chip->irq <= 0)
656 goto skip_irq;
657
658 /* Disable per-channel interrupts */
659 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, 0);
660 /* Clear any existing per-channel interrupts */
661 temp = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
662 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, temp);
663 /* Enable global interrupts */
664 xgpio_writereg(chip->regs + XGPIO_GIER_OFFSET, XGPIO_GIER_IE);
665
666 girq = &chip->gc.irq;
667 gpio_irq_chip_set_chip(girq, &xgpio_irq_chip);
668 girq->parent_handler = xgpio_irqhandler;
669 girq->num_parents = 1;
670 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
671 GFP_KERNEL);
672 if (!girq->parents) {
673 status = -ENOMEM;
674 goto err_pm_put;
675 }
676 girq->parents[0] = chip->irq;
677 girq->default_type = IRQ_TYPE_NONE;
678 girq->handler = handle_bad_irq;
679
680skip_irq:
681 status = devm_gpiochip_add_data(dev, &chip->gc, chip);
682 if (status) {
683 dev_err(dev, "failed to add GPIO chip\n");
684 goto err_pm_put;
685 }
686
687 pm_runtime_put(dev);
688 return 0;
689
690err_pm_put:
691 pm_runtime_disable(dev);
692 pm_runtime_put_noidle(dev);
693 return status;
694}
695
696static const struct of_device_id xgpio_of_match[] = {
697 { .compatible = "xlnx,xps-gpio-1.00.a", },
698 { /* end of list */ },
699};
700
701MODULE_DEVICE_TABLE(of, xgpio_of_match);
702
703static struct platform_driver xgpio_plat_driver = {
704 .probe = xgpio_probe,
705 .remove = xgpio_remove,
706 .driver = {
707 .name = "gpio-xilinx",
708 .of_match_table = xgpio_of_match,
709 .pm = &xgpio_dev_pm_ops,
710 },
711};
712
713static int __init xgpio_init(void)
714{
715 return platform_driver_register(&xgpio_plat_driver);
716}
717
718subsys_initcall(xgpio_init);
719
720static void __exit xgpio_exit(void)
721{
722 platform_driver_unregister(&xgpio_plat_driver);
723}
724module_exit(xgpio_exit);
725
726MODULE_AUTHOR("Xilinx, Inc.");
727MODULE_DESCRIPTION("Xilinx GPIO driver");
728MODULE_LICENSE("GPL");