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1/*
2 * Driver for Amlogic Meson SPI communication controller (SPICC)
3 *
4 * Copyright (C) BayLibre, SAS
5 * Author: Neil Armstrong <narmstrong@baylibre.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#include <linux/bitfield.h>
11#include <linux/clk.h>
12#include <linux/clk-provider.h>
13#include <linux/device.h>
14#include <linux/io.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/of_device.h>
19#include <linux/platform_device.h>
20#include <linux/spi/spi.h>
21#include <linux/types.h>
22#include <linux/interrupt.h>
23#include <linux/reset.h>
24#include <linux/pinctrl/consumer.h>
25
26/*
27 * The Meson SPICC controller could support DMA based transfers, but is not
28 * implemented by the vendor code, and while having the registers documentation
29 * it has never worked on the GXL Hardware.
30 * The PIO mode is the only mode implemented, and due to badly designed HW :
31 * - all transfers are cutted in 16 words burst because the FIFO hangs on
32 * TX underflow, and there is no TX "Half-Empty" interrupt, so we go by
33 * FIFO max size chunk only
34 * - CS management is dumb, and goes UP between every burst, so is really a
35 * "Data Valid" signal than a Chip Select, GPIO link should be used instead
36 * to have a CS go down over the full transfer
37 */
38
39#define SPICC_MAX_BURST 128
40
41/* Register Map */
42#define SPICC_RXDATA 0x00
43
44#define SPICC_TXDATA 0x04
45
46#define SPICC_CONREG 0x08
47#define SPICC_ENABLE BIT(0)
48#define SPICC_MODE_MASTER BIT(1)
49#define SPICC_XCH BIT(2)
50#define SPICC_SMC BIT(3)
51#define SPICC_POL BIT(4)
52#define SPICC_PHA BIT(5)
53#define SPICC_SSCTL BIT(6)
54#define SPICC_SSPOL BIT(7)
55#define SPICC_DRCTL_MASK GENMASK(9, 8)
56#define SPICC_DRCTL_IGNORE 0
57#define SPICC_DRCTL_FALLING 1
58#define SPICC_DRCTL_LOWLEVEL 2
59#define SPICC_CS_MASK GENMASK(13, 12)
60#define SPICC_DATARATE_MASK GENMASK(18, 16)
61#define SPICC_DATARATE_DIV4 0
62#define SPICC_DATARATE_DIV8 1
63#define SPICC_DATARATE_DIV16 2
64#define SPICC_DATARATE_DIV32 3
65#define SPICC_BITLENGTH_MASK GENMASK(24, 19)
66#define SPICC_BURSTLENGTH_MASK GENMASK(31, 25)
67
68#define SPICC_INTREG 0x0c
69#define SPICC_TE_EN BIT(0) /* TX FIFO Empty Interrupt */
70#define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */
71#define SPICC_TF_EN BIT(2) /* TX FIFO Full Interrupt */
72#define SPICC_RR_EN BIT(3) /* RX FIFO Ready Interrupt */
73#define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */
74#define SPICC_RF_EN BIT(5) /* RX FIFO Full Interrupt */
75#define SPICC_RO_EN BIT(6) /* RX FIFO Overflow Interrupt */
76#define SPICC_TC_EN BIT(7) /* Transfert Complete Interrupt */
77
78#define SPICC_DMAREG 0x10
79#define SPICC_DMA_ENABLE BIT(0)
80#define SPICC_TXFIFO_THRESHOLD_MASK GENMASK(5, 1)
81#define SPICC_RXFIFO_THRESHOLD_MASK GENMASK(10, 6)
82#define SPICC_READ_BURST_MASK GENMASK(14, 11)
83#define SPICC_WRITE_BURST_MASK GENMASK(18, 15)
84#define SPICC_DMA_URGENT BIT(19)
85#define SPICC_DMA_THREADID_MASK GENMASK(25, 20)
86#define SPICC_DMA_BURSTNUM_MASK GENMASK(31, 26)
87
88#define SPICC_STATREG 0x14
89#define SPICC_TE BIT(0) /* TX FIFO Empty Interrupt */
90#define SPICC_TH BIT(1) /* TX FIFO Half-Full Interrupt */
91#define SPICC_TF BIT(2) /* TX FIFO Full Interrupt */
92#define SPICC_RR BIT(3) /* RX FIFO Ready Interrupt */
93#define SPICC_RH BIT(4) /* RX FIFO Half-Full Interrupt */
94#define SPICC_RF BIT(5) /* RX FIFO Full Interrupt */
95#define SPICC_RO BIT(6) /* RX FIFO Overflow Interrupt */
96#define SPICC_TC BIT(7) /* Transfert Complete Interrupt */
97
98#define SPICC_PERIODREG 0x18
99#define SPICC_PERIOD GENMASK(14, 0) /* Wait cycles */
100
101#define SPICC_TESTREG 0x1c
102#define SPICC_TXCNT_MASK GENMASK(4, 0) /* TX FIFO Counter */
103#define SPICC_RXCNT_MASK GENMASK(9, 5) /* RX FIFO Counter */
104#define SPICC_SMSTATUS_MASK GENMASK(12, 10) /* State Machine Status */
105#define SPICC_LBC_RO BIT(13) /* Loop Back Control Read-Only */
106#define SPICC_LBC_W1 BIT(14) /* Loop Back Control Write-Only */
107#define SPICC_SWAP_RO BIT(14) /* RX FIFO Data Swap Read-Only */
108#define SPICC_SWAP_W1 BIT(15) /* RX FIFO Data Swap Write-Only */
109#define SPICC_DLYCTL_RO_MASK GENMASK(20, 15) /* Delay Control Read-Only */
110#define SPICC_MO_DELAY_MASK GENMASK(17, 16) /* Master Output Delay */
111#define SPICC_MO_NO_DELAY 0
112#define SPICC_MO_DELAY_1_CYCLE 1
113#define SPICC_MO_DELAY_2_CYCLE 2
114#define SPICC_MO_DELAY_3_CYCLE 3
115#define SPICC_MI_DELAY_MASK GENMASK(19, 18) /* Master Input Delay */
116#define SPICC_MI_NO_DELAY 0
117#define SPICC_MI_DELAY_1_CYCLE 1
118#define SPICC_MI_DELAY_2_CYCLE 2
119#define SPICC_MI_DELAY_3_CYCLE 3
120#define SPICC_MI_CAP_DELAY_MASK GENMASK(21, 20) /* Master Capture Delay */
121#define SPICC_CAP_AHEAD_2_CYCLE 0
122#define SPICC_CAP_AHEAD_1_CYCLE 1
123#define SPICC_CAP_NO_DELAY 2
124#define SPICC_CAP_DELAY_1_CYCLE 3
125#define SPICC_FIFORST_RO_MASK GENMASK(22, 21) /* FIFO Softreset Read-Only */
126#define SPICC_FIFORST_W1_MASK GENMASK(23, 22) /* FIFO Softreset Write-Only */
127
128#define SPICC_DRADDR 0x20 /* Read Address of DMA */
129
130#define SPICC_DWADDR 0x24 /* Write Address of DMA */
131
132#define SPICC_ENH_CTL0 0x38 /* Enhanced Feature */
133#define SPICC_ENH_CLK_CS_DELAY_MASK GENMASK(15, 0)
134#define SPICC_ENH_DATARATE_MASK GENMASK(23, 16)
135#define SPICC_ENH_DATARATE_EN BIT(24)
136#define SPICC_ENH_MOSI_OEN BIT(25)
137#define SPICC_ENH_CLK_OEN BIT(26)
138#define SPICC_ENH_CS_OEN BIT(27)
139#define SPICC_ENH_CLK_CS_DELAY_EN BIT(28)
140#define SPICC_ENH_MAIN_CLK_AO BIT(29)
141
142#define writel_bits_relaxed(mask, val, addr) \
143 writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr)
144
145struct meson_spicc_data {
146 unsigned int max_speed_hz;
147 unsigned int min_speed_hz;
148 unsigned int fifo_size;
149 bool has_oen;
150 bool has_enhance_clk_div;
151 bool has_pclk;
152};
153
154struct meson_spicc_device {
155 struct spi_master *master;
156 struct platform_device *pdev;
157 void __iomem *base;
158 struct clk *core;
159 struct clk *pclk;
160 struct clk_divider pow2_div;
161 struct clk *clk;
162 struct spi_message *message;
163 struct spi_transfer *xfer;
164 struct completion done;
165 const struct meson_spicc_data *data;
166 u8 *tx_buf;
167 u8 *rx_buf;
168 unsigned int bytes_per_word;
169 unsigned long tx_remain;
170 unsigned long rx_remain;
171 unsigned long xfer_remain;
172 struct pinctrl *pinctrl;
173 struct pinctrl_state *pins_idle_high;
174 struct pinctrl_state *pins_idle_low;
175};
176
177#define pow2_clk_to_spicc(_div) container_of(_div, struct meson_spicc_device, pow2_div)
178
179static void meson_spicc_oen_enable(struct meson_spicc_device *spicc)
180{
181 u32 conf;
182
183 if (!spicc->data->has_oen) {
184 /* Try to get pinctrl states for idle high/low */
185 spicc->pins_idle_high = pinctrl_lookup_state(spicc->pinctrl,
186 "idle-high");
187 if (IS_ERR(spicc->pins_idle_high)) {
188 dev_warn(&spicc->pdev->dev, "can't get idle-high pinctrl\n");
189 spicc->pins_idle_high = NULL;
190 }
191 spicc->pins_idle_low = pinctrl_lookup_state(spicc->pinctrl,
192 "idle-low");
193 if (IS_ERR(spicc->pins_idle_low)) {
194 dev_warn(&spicc->pdev->dev, "can't get idle-low pinctrl\n");
195 spicc->pins_idle_low = NULL;
196 }
197 return;
198 }
199
200 conf = readl_relaxed(spicc->base + SPICC_ENH_CTL0) |
201 SPICC_ENH_MOSI_OEN | SPICC_ENH_CLK_OEN | SPICC_ENH_CS_OEN;
202
203 writel_relaxed(conf, spicc->base + SPICC_ENH_CTL0);
204}
205
206static inline bool meson_spicc_txfull(struct meson_spicc_device *spicc)
207{
208 return !!FIELD_GET(SPICC_TF,
209 readl_relaxed(spicc->base + SPICC_STATREG));
210}
211
212static inline bool meson_spicc_rxready(struct meson_spicc_device *spicc)
213{
214 return FIELD_GET(SPICC_RH | SPICC_RR | SPICC_RF,
215 readl_relaxed(spicc->base + SPICC_STATREG));
216}
217
218static inline u32 meson_spicc_pull_data(struct meson_spicc_device *spicc)
219{
220 unsigned int bytes = spicc->bytes_per_word;
221 unsigned int byte_shift = 0;
222 u32 data = 0;
223 u8 byte;
224
225 while (bytes--) {
226 byte = *spicc->tx_buf++;
227 data |= (byte & 0xff) << byte_shift;
228 byte_shift += 8;
229 }
230
231 spicc->tx_remain--;
232 return data;
233}
234
235static inline void meson_spicc_push_data(struct meson_spicc_device *spicc,
236 u32 data)
237{
238 unsigned int bytes = spicc->bytes_per_word;
239 unsigned int byte_shift = 0;
240 u8 byte;
241
242 while (bytes--) {
243 byte = (data >> byte_shift) & 0xff;
244 *spicc->rx_buf++ = byte;
245 byte_shift += 8;
246 }
247
248 spicc->rx_remain--;
249}
250
251static inline void meson_spicc_rx(struct meson_spicc_device *spicc)
252{
253 /* Empty RX FIFO */
254 while (spicc->rx_remain &&
255 meson_spicc_rxready(spicc))
256 meson_spicc_push_data(spicc,
257 readl_relaxed(spicc->base + SPICC_RXDATA));
258}
259
260static inline void meson_spicc_tx(struct meson_spicc_device *spicc)
261{
262 /* Fill Up TX FIFO */
263 while (spicc->tx_remain &&
264 !meson_spicc_txfull(spicc))
265 writel_relaxed(meson_spicc_pull_data(spicc),
266 spicc->base + SPICC_TXDATA);
267}
268
269static inline void meson_spicc_setup_burst(struct meson_spicc_device *spicc)
270{
271
272 unsigned int burst_len = min_t(unsigned int,
273 spicc->xfer_remain /
274 spicc->bytes_per_word,
275 spicc->data->fifo_size);
276 /* Setup Xfer variables */
277 spicc->tx_remain = burst_len;
278 spicc->rx_remain = burst_len;
279 spicc->xfer_remain -= burst_len * spicc->bytes_per_word;
280
281 /* Setup burst length */
282 writel_bits_relaxed(SPICC_BURSTLENGTH_MASK,
283 FIELD_PREP(SPICC_BURSTLENGTH_MASK,
284 burst_len - 1),
285 spicc->base + SPICC_CONREG);
286
287 /* Fill TX FIFO */
288 meson_spicc_tx(spicc);
289}
290
291static irqreturn_t meson_spicc_irq(int irq, void *data)
292{
293 struct meson_spicc_device *spicc = (void *) data;
294
295 writel_bits_relaxed(SPICC_TC, SPICC_TC, spicc->base + SPICC_STATREG);
296
297 /* Empty RX FIFO */
298 meson_spicc_rx(spicc);
299
300 if (!spicc->xfer_remain) {
301 /* Disable all IRQs */
302 writel(0, spicc->base + SPICC_INTREG);
303
304 complete(&spicc->done);
305
306 return IRQ_HANDLED;
307 }
308
309 /* Setup burst */
310 meson_spicc_setup_burst(spicc);
311
312 /* Start burst */
313 writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);
314
315 return IRQ_HANDLED;
316}
317
318static void meson_spicc_auto_io_delay(struct meson_spicc_device *spicc)
319{
320 u32 div, hz;
321 u32 mi_delay, cap_delay;
322 u32 conf;
323
324 if (spicc->data->has_enhance_clk_div) {
325 div = FIELD_GET(SPICC_ENH_DATARATE_MASK,
326 readl_relaxed(spicc->base + SPICC_ENH_CTL0));
327 div++;
328 div <<= 1;
329 } else {
330 div = FIELD_GET(SPICC_DATARATE_MASK,
331 readl_relaxed(spicc->base + SPICC_CONREG));
332 div += 2;
333 div = 1 << div;
334 }
335
336 mi_delay = SPICC_MI_NO_DELAY;
337 cap_delay = SPICC_CAP_AHEAD_2_CYCLE;
338 hz = clk_get_rate(spicc->clk);
339
340 if (hz >= 100000000)
341 cap_delay = SPICC_CAP_DELAY_1_CYCLE;
342 else if (hz >= 80000000)
343 cap_delay = SPICC_CAP_NO_DELAY;
344 else if (hz >= 40000000)
345 cap_delay = SPICC_CAP_AHEAD_1_CYCLE;
346 else if (div >= 16)
347 mi_delay = SPICC_MI_DELAY_3_CYCLE;
348 else if (div >= 8)
349 mi_delay = SPICC_MI_DELAY_2_CYCLE;
350 else if (div >= 6)
351 mi_delay = SPICC_MI_DELAY_1_CYCLE;
352
353 conf = readl_relaxed(spicc->base + SPICC_TESTREG);
354 conf &= ~(SPICC_MO_DELAY_MASK | SPICC_MI_DELAY_MASK
355 | SPICC_MI_CAP_DELAY_MASK);
356 conf |= FIELD_PREP(SPICC_MI_DELAY_MASK, mi_delay);
357 conf |= FIELD_PREP(SPICC_MI_CAP_DELAY_MASK, cap_delay);
358 writel_relaxed(conf, spicc->base + SPICC_TESTREG);
359}
360
361static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc,
362 struct spi_transfer *xfer)
363{
364 u32 conf, conf_orig;
365
366 /* Read original configuration */
367 conf = conf_orig = readl_relaxed(spicc->base + SPICC_CONREG);
368
369 /* Setup word width */
370 conf &= ~SPICC_BITLENGTH_MASK;
371 conf |= FIELD_PREP(SPICC_BITLENGTH_MASK,
372 (spicc->bytes_per_word << 3) - 1);
373
374 /* Ignore if unchanged */
375 if (conf != conf_orig)
376 writel_relaxed(conf, spicc->base + SPICC_CONREG);
377
378 clk_set_rate(spicc->clk, xfer->speed_hz);
379
380 meson_spicc_auto_io_delay(spicc);
381
382 writel_relaxed(0, spicc->base + SPICC_DMAREG);
383}
384
385static void meson_spicc_reset_fifo(struct meson_spicc_device *spicc)
386{
387 if (spicc->data->has_oen)
388 writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO,
389 SPICC_ENH_MAIN_CLK_AO,
390 spicc->base + SPICC_ENH_CTL0);
391
392 writel_bits_relaxed(SPICC_FIFORST_W1_MASK, SPICC_FIFORST_W1_MASK,
393 spicc->base + SPICC_TESTREG);
394
395 while (meson_spicc_rxready(spicc))
396 readl_relaxed(spicc->base + SPICC_RXDATA);
397
398 if (spicc->data->has_oen)
399 writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO, 0,
400 spicc->base + SPICC_ENH_CTL0);
401}
402
403static int meson_spicc_transfer_one(struct spi_master *master,
404 struct spi_device *spi,
405 struct spi_transfer *xfer)
406{
407 struct meson_spicc_device *spicc = spi_master_get_devdata(master);
408 uint64_t timeout;
409
410 /* Store current transfer */
411 spicc->xfer = xfer;
412
413 /* Setup transfer parameters */
414 spicc->tx_buf = (u8 *)xfer->tx_buf;
415 spicc->rx_buf = (u8 *)xfer->rx_buf;
416 spicc->xfer_remain = xfer->len;
417
418 /* Pre-calculate word size */
419 spicc->bytes_per_word =
420 DIV_ROUND_UP(spicc->xfer->bits_per_word, 8);
421
422 if (xfer->len % spicc->bytes_per_word)
423 return -EINVAL;
424
425 /* Setup transfer parameters */
426 meson_spicc_setup_xfer(spicc, xfer);
427
428 meson_spicc_reset_fifo(spicc);
429
430 /* Setup burst */
431 meson_spicc_setup_burst(spicc);
432
433 /* Setup wait for completion */
434 reinit_completion(&spicc->done);
435
436 /* For each byte we wait for 8 cycles of the SPI clock */
437 timeout = 8LL * MSEC_PER_SEC * xfer->len;
438 do_div(timeout, xfer->speed_hz);
439
440 /* Add 10us delay between each fifo bursts */
441 timeout += ((xfer->len >> 4) * 10) / MSEC_PER_SEC;
442
443 /* Increase it twice and add 200 ms tolerance */
444 timeout += timeout + 200;
445
446 /* Start burst */
447 writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);
448
449 /* Enable interrupts */
450 writel_relaxed(SPICC_TC_EN, spicc->base + SPICC_INTREG);
451
452 if (!wait_for_completion_timeout(&spicc->done, msecs_to_jiffies(timeout)))
453 return -ETIMEDOUT;
454
455 return 0;
456}
457
458static int meson_spicc_prepare_message(struct spi_master *master,
459 struct spi_message *message)
460{
461 struct meson_spicc_device *spicc = spi_master_get_devdata(master);
462 struct spi_device *spi = message->spi;
463 u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK;
464
465 /* Store current message */
466 spicc->message = message;
467
468 /* Enable Master */
469 conf |= SPICC_ENABLE;
470 conf |= SPICC_MODE_MASTER;
471
472 /* SMC = 0 */
473
474 /* Setup transfer mode */
475 if (spi->mode & SPI_CPOL)
476 conf |= SPICC_POL;
477 else
478 conf &= ~SPICC_POL;
479
480 if (!spicc->data->has_oen) {
481 if (spi->mode & SPI_CPOL) {
482 if (spicc->pins_idle_high)
483 pinctrl_select_state(spicc->pinctrl, spicc->pins_idle_high);
484 } else {
485 if (spicc->pins_idle_low)
486 pinctrl_select_state(spicc->pinctrl, spicc->pins_idle_low);
487 }
488 }
489
490 if (spi->mode & SPI_CPHA)
491 conf |= SPICC_PHA;
492 else
493 conf &= ~SPICC_PHA;
494
495 /* SSCTL = 0 */
496
497 if (spi->mode & SPI_CS_HIGH)
498 conf |= SPICC_SSPOL;
499 else
500 conf &= ~SPICC_SSPOL;
501
502 if (spi->mode & SPI_READY)
503 conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_LOWLEVEL);
504 else
505 conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_IGNORE);
506
507 /* Select CS */
508 conf |= FIELD_PREP(SPICC_CS_MASK, spi->chip_select);
509
510 /* Default 8bit word */
511 conf |= FIELD_PREP(SPICC_BITLENGTH_MASK, 8 - 1);
512
513 writel_relaxed(conf, spicc->base + SPICC_CONREG);
514
515 /* Setup no wait cycles by default */
516 writel_relaxed(0, spicc->base + SPICC_PERIODREG);
517
518 writel_bits_relaxed(SPICC_LBC_W1, 0, spicc->base + SPICC_TESTREG);
519
520 return 0;
521}
522
523static int meson_spicc_unprepare_transfer(struct spi_master *master)
524{
525 struct meson_spicc_device *spicc = spi_master_get_devdata(master);
526 u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK;
527
528 /* Disable all IRQs */
529 writel(0, spicc->base + SPICC_INTREG);
530
531 device_reset_optional(&spicc->pdev->dev);
532
533 /* Set default configuration, keeping datarate field */
534 writel_relaxed(conf, spicc->base + SPICC_CONREG);
535
536 if (!spicc->data->has_oen)
537 pinctrl_select_default_state(&spicc->pdev->dev);
538
539 return 0;
540}
541
542static int meson_spicc_setup(struct spi_device *spi)
543{
544 if (!spi->controller_state)
545 spi->controller_state = spi_master_get_devdata(spi->master);
546
547 return 0;
548}
549
550static void meson_spicc_cleanup(struct spi_device *spi)
551{
552 spi->controller_state = NULL;
553}
554
555/*
556 * The Clock Mux
557 * x-----------------x x------------x x------\
558 * |---| pow2 fixed div |---| pow2 div |----| |
559 * | x-----------------x x------------x | |
560 * src ---| | mux |-- out
561 * | x-----------------x x------------x | |
562 * |---| enh fixed div |---| enh div |0---| |
563 * x-----------------x x------------x x------/
564 *
565 * Clk path for GX series:
566 * src -> pow2 fixed div -> pow2 div -> out
567 *
568 * Clk path for AXG series:
569 * src -> pow2 fixed div -> pow2 div -> mux -> out
570 * src -> enh fixed div -> enh div -> mux -> out
571 *
572 * Clk path for G12A series:
573 * pclk -> pow2 fixed div -> pow2 div -> mux -> out
574 * pclk -> enh fixed div -> enh div -> mux -> out
575 *
576 * The pow2 divider is tied to the controller HW state, and the
577 * divider is only valid when the controller is initialized.
578 *
579 * A set of clock ops is added to make sure we don't read/set this
580 * clock rate while the controller is in an unknown state.
581 */
582
583static unsigned long meson_spicc_pow2_recalc_rate(struct clk_hw *hw,
584 unsigned long parent_rate)
585{
586 struct clk_divider *divider = to_clk_divider(hw);
587 struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
588
589 if (!spicc->master->cur_msg)
590 return 0;
591
592 return clk_divider_ops.recalc_rate(hw, parent_rate);
593}
594
595static int meson_spicc_pow2_determine_rate(struct clk_hw *hw,
596 struct clk_rate_request *req)
597{
598 struct clk_divider *divider = to_clk_divider(hw);
599 struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
600
601 if (!spicc->master->cur_msg)
602 return -EINVAL;
603
604 return clk_divider_ops.determine_rate(hw, req);
605}
606
607static int meson_spicc_pow2_set_rate(struct clk_hw *hw, unsigned long rate,
608 unsigned long parent_rate)
609{
610 struct clk_divider *divider = to_clk_divider(hw);
611 struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
612
613 if (!spicc->master->cur_msg)
614 return -EINVAL;
615
616 return clk_divider_ops.set_rate(hw, rate, parent_rate);
617}
618
619static const struct clk_ops meson_spicc_pow2_clk_ops = {
620 .recalc_rate = meson_spicc_pow2_recalc_rate,
621 .determine_rate = meson_spicc_pow2_determine_rate,
622 .set_rate = meson_spicc_pow2_set_rate,
623};
624
625static int meson_spicc_pow2_clk_init(struct meson_spicc_device *spicc)
626{
627 struct device *dev = &spicc->pdev->dev;
628 struct clk_fixed_factor *pow2_fixed_div;
629 struct clk_init_data init;
630 struct clk *clk;
631 struct clk_parent_data parent_data[2];
632 char name[64];
633
634 memset(&init, 0, sizeof(init));
635 memset(&parent_data, 0, sizeof(parent_data));
636
637 init.parent_data = parent_data;
638
639 /* algorithm for pow2 div: rate = freq / 4 / (2 ^ N) */
640
641 pow2_fixed_div = devm_kzalloc(dev, sizeof(*pow2_fixed_div), GFP_KERNEL);
642 if (!pow2_fixed_div)
643 return -ENOMEM;
644
645 snprintf(name, sizeof(name), "%s#pow2_fixed_div", dev_name(dev));
646 init.name = name;
647 init.ops = &clk_fixed_factor_ops;
648 init.flags = 0;
649 if (spicc->data->has_pclk)
650 parent_data[0].hw = __clk_get_hw(spicc->pclk);
651 else
652 parent_data[0].hw = __clk_get_hw(spicc->core);
653 init.num_parents = 1;
654
655 pow2_fixed_div->mult = 1,
656 pow2_fixed_div->div = 4,
657 pow2_fixed_div->hw.init = &init;
658
659 clk = devm_clk_register(dev, &pow2_fixed_div->hw);
660 if (WARN_ON(IS_ERR(clk)))
661 return PTR_ERR(clk);
662
663 snprintf(name, sizeof(name), "%s#pow2_div", dev_name(dev));
664 init.name = name;
665 init.ops = &meson_spicc_pow2_clk_ops;
666 /*
667 * Set NOCACHE here to make sure we read the actual HW value
668 * since we reset the HW after each transfer.
669 */
670 init.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE;
671 parent_data[0].hw = &pow2_fixed_div->hw;
672 init.num_parents = 1;
673
674 spicc->pow2_div.shift = 16,
675 spicc->pow2_div.width = 3,
676 spicc->pow2_div.flags = CLK_DIVIDER_POWER_OF_TWO,
677 spicc->pow2_div.reg = spicc->base + SPICC_CONREG;
678 spicc->pow2_div.hw.init = &init;
679
680 spicc->clk = devm_clk_register(dev, &spicc->pow2_div.hw);
681 if (WARN_ON(IS_ERR(spicc->clk)))
682 return PTR_ERR(spicc->clk);
683
684 return 0;
685}
686
687static int meson_spicc_enh_clk_init(struct meson_spicc_device *spicc)
688{
689 struct device *dev = &spicc->pdev->dev;
690 struct clk_fixed_factor *enh_fixed_div;
691 struct clk_divider *enh_div;
692 struct clk_mux *mux;
693 struct clk_init_data init;
694 struct clk *clk;
695 struct clk_parent_data parent_data[2];
696 char name[64];
697
698 memset(&init, 0, sizeof(init));
699 memset(&parent_data, 0, sizeof(parent_data));
700
701 init.parent_data = parent_data;
702
703 /* algorithm for enh div: rate = freq / 2 / (N + 1) */
704
705 enh_fixed_div = devm_kzalloc(dev, sizeof(*enh_fixed_div), GFP_KERNEL);
706 if (!enh_fixed_div)
707 return -ENOMEM;
708
709 snprintf(name, sizeof(name), "%s#enh_fixed_div", dev_name(dev));
710 init.name = name;
711 init.ops = &clk_fixed_factor_ops;
712 init.flags = 0;
713 if (spicc->data->has_pclk)
714 parent_data[0].hw = __clk_get_hw(spicc->pclk);
715 else
716 parent_data[0].hw = __clk_get_hw(spicc->core);
717 init.num_parents = 1;
718
719 enh_fixed_div->mult = 1,
720 enh_fixed_div->div = 2,
721 enh_fixed_div->hw.init = &init;
722
723 clk = devm_clk_register(dev, &enh_fixed_div->hw);
724 if (WARN_ON(IS_ERR(clk)))
725 return PTR_ERR(clk);
726
727 enh_div = devm_kzalloc(dev, sizeof(*enh_div), GFP_KERNEL);
728 if (!enh_div)
729 return -ENOMEM;
730
731 snprintf(name, sizeof(name), "%s#enh_div", dev_name(dev));
732 init.name = name;
733 init.ops = &clk_divider_ops;
734 init.flags = CLK_SET_RATE_PARENT;
735 parent_data[0].hw = &enh_fixed_div->hw;
736 init.num_parents = 1;
737
738 enh_div->shift = 16,
739 enh_div->width = 8,
740 enh_div->reg = spicc->base + SPICC_ENH_CTL0;
741 enh_div->hw.init = &init;
742
743 clk = devm_clk_register(dev, &enh_div->hw);
744 if (WARN_ON(IS_ERR(clk)))
745 return PTR_ERR(clk);
746
747 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
748 if (!mux)
749 return -ENOMEM;
750
751 snprintf(name, sizeof(name), "%s#sel", dev_name(dev));
752 init.name = name;
753 init.ops = &clk_mux_ops;
754 parent_data[0].hw = &spicc->pow2_div.hw;
755 parent_data[1].hw = &enh_div->hw;
756 init.num_parents = 2;
757 init.flags = CLK_SET_RATE_PARENT;
758
759 mux->mask = 0x1,
760 mux->shift = 24,
761 mux->reg = spicc->base + SPICC_ENH_CTL0;
762 mux->hw.init = &init;
763
764 spicc->clk = devm_clk_register(dev, &mux->hw);
765 if (WARN_ON(IS_ERR(spicc->clk)))
766 return PTR_ERR(spicc->clk);
767
768 return 0;
769}
770
771static int meson_spicc_probe(struct platform_device *pdev)
772{
773 struct spi_master *master;
774 struct meson_spicc_device *spicc;
775 int ret, irq;
776
777 master = spi_alloc_master(&pdev->dev, sizeof(*spicc));
778 if (!master) {
779 dev_err(&pdev->dev, "master allocation failed\n");
780 return -ENOMEM;
781 }
782 spicc = spi_master_get_devdata(master);
783 spicc->master = master;
784
785 spicc->data = of_device_get_match_data(&pdev->dev);
786 if (!spicc->data) {
787 dev_err(&pdev->dev, "failed to get match data\n");
788 ret = -EINVAL;
789 goto out_master;
790 }
791
792 spicc->pdev = pdev;
793 platform_set_drvdata(pdev, spicc);
794
795 init_completion(&spicc->done);
796
797 spicc->base = devm_platform_ioremap_resource(pdev, 0);
798 if (IS_ERR(spicc->base)) {
799 dev_err(&pdev->dev, "io resource mapping failed\n");
800 ret = PTR_ERR(spicc->base);
801 goto out_master;
802 }
803
804 /* Set master mode and enable controller */
805 writel_relaxed(SPICC_ENABLE | SPICC_MODE_MASTER,
806 spicc->base + SPICC_CONREG);
807
808 /* Disable all IRQs */
809 writel_relaxed(0, spicc->base + SPICC_INTREG);
810
811 irq = platform_get_irq(pdev, 0);
812 if (irq < 0) {
813 ret = irq;
814 goto out_master;
815 }
816
817 ret = devm_request_irq(&pdev->dev, irq, meson_spicc_irq,
818 0, NULL, spicc);
819 if (ret) {
820 dev_err(&pdev->dev, "irq request failed\n");
821 goto out_master;
822 }
823
824 spicc->core = devm_clk_get(&pdev->dev, "core");
825 if (IS_ERR(spicc->core)) {
826 dev_err(&pdev->dev, "core clock request failed\n");
827 ret = PTR_ERR(spicc->core);
828 goto out_master;
829 }
830
831 if (spicc->data->has_pclk) {
832 spicc->pclk = devm_clk_get(&pdev->dev, "pclk");
833 if (IS_ERR(spicc->pclk)) {
834 dev_err(&pdev->dev, "pclk clock request failed\n");
835 ret = PTR_ERR(spicc->pclk);
836 goto out_master;
837 }
838 }
839
840 ret = clk_prepare_enable(spicc->core);
841 if (ret) {
842 dev_err(&pdev->dev, "core clock enable failed\n");
843 goto out_master;
844 }
845
846 ret = clk_prepare_enable(spicc->pclk);
847 if (ret) {
848 dev_err(&pdev->dev, "pclk clock enable failed\n");
849 goto out_core_clk;
850 }
851
852 spicc->pinctrl = devm_pinctrl_get(&pdev->dev);
853 if (IS_ERR(spicc->pinctrl)) {
854 ret = PTR_ERR(spicc->pinctrl);
855 goto out_clk;
856 }
857
858 device_reset_optional(&pdev->dev);
859
860 master->num_chipselect = 4;
861 master->dev.of_node = pdev->dev.of_node;
862 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH;
863 master->bits_per_word_mask = SPI_BPW_MASK(32) |
864 SPI_BPW_MASK(24) |
865 SPI_BPW_MASK(16) |
866 SPI_BPW_MASK(8);
867 master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX);
868 master->min_speed_hz = spicc->data->min_speed_hz;
869 master->max_speed_hz = spicc->data->max_speed_hz;
870 master->setup = meson_spicc_setup;
871 master->cleanup = meson_spicc_cleanup;
872 master->prepare_message = meson_spicc_prepare_message;
873 master->unprepare_transfer_hardware = meson_spicc_unprepare_transfer;
874 master->transfer_one = meson_spicc_transfer_one;
875 master->use_gpio_descriptors = true;
876
877 meson_spicc_oen_enable(spicc);
878
879 ret = meson_spicc_pow2_clk_init(spicc);
880 if (ret) {
881 dev_err(&pdev->dev, "pow2 clock registration failed\n");
882 goto out_clk;
883 }
884
885 if (spicc->data->has_enhance_clk_div) {
886 ret = meson_spicc_enh_clk_init(spicc);
887 if (ret) {
888 dev_err(&pdev->dev, "clock registration failed\n");
889 goto out_clk;
890 }
891 }
892
893 ret = devm_spi_register_master(&pdev->dev, master);
894 if (ret) {
895 dev_err(&pdev->dev, "spi master registration failed\n");
896 goto out_clk;
897 }
898
899 return 0;
900
901out_clk:
902 clk_disable_unprepare(spicc->pclk);
903
904out_core_clk:
905 clk_disable_unprepare(spicc->core);
906
907out_master:
908 spi_master_put(master);
909
910 return ret;
911}
912
913static int meson_spicc_remove(struct platform_device *pdev)
914{
915 struct meson_spicc_device *spicc = platform_get_drvdata(pdev);
916
917 /* Disable SPI */
918 writel(0, spicc->base + SPICC_CONREG);
919
920 clk_disable_unprepare(spicc->core);
921 clk_disable_unprepare(spicc->pclk);
922
923 spi_master_put(spicc->master);
924
925 return 0;
926}
927
928static const struct meson_spicc_data meson_spicc_gx_data = {
929 .max_speed_hz = 30000000,
930 .min_speed_hz = 325000,
931 .fifo_size = 16,
932};
933
934static const struct meson_spicc_data meson_spicc_axg_data = {
935 .max_speed_hz = 80000000,
936 .min_speed_hz = 325000,
937 .fifo_size = 16,
938 .has_oen = true,
939 .has_enhance_clk_div = true,
940};
941
942static const struct meson_spicc_data meson_spicc_g12a_data = {
943 .max_speed_hz = 166666666,
944 .min_speed_hz = 50000,
945 .fifo_size = 15,
946 .has_oen = true,
947 .has_enhance_clk_div = true,
948 .has_pclk = true,
949};
950
951static const struct of_device_id meson_spicc_of_match[] = {
952 {
953 .compatible = "amlogic,meson-gx-spicc",
954 .data = &meson_spicc_gx_data,
955 },
956 {
957 .compatible = "amlogic,meson-axg-spicc",
958 .data = &meson_spicc_axg_data,
959 },
960 {
961 .compatible = "amlogic,meson-g12a-spicc",
962 .data = &meson_spicc_g12a_data,
963 },
964 { /* sentinel */ }
965};
966MODULE_DEVICE_TABLE(of, meson_spicc_of_match);
967
968static struct platform_driver meson_spicc_driver = {
969 .probe = meson_spicc_probe,
970 .remove = meson_spicc_remove,
971 .driver = {
972 .name = "meson-spicc",
973 .of_match_table = of_match_ptr(meson_spicc_of_match),
974 },
975};
976
977module_platform_driver(meson_spicc_driver);
978
979MODULE_DESCRIPTION("Meson SPI Communication Controller driver");
980MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
981MODULE_LICENSE("GPL");
1/*
2 * Driver for Amlogic Meson SPI communication controller (SPICC)
3 *
4 * Copyright (C) BayLibre, SAS
5 * Author: Neil Armstrong <narmstrong@baylibre.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#include <linux/bitfield.h>
11#include <linux/clk.h>
12#include <linux/clk-provider.h>
13#include <linux/device.h>
14#include <linux/io.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/of_device.h>
19#include <linux/platform_device.h>
20#include <linux/spi/spi.h>
21#include <linux/types.h>
22#include <linux/interrupt.h>
23#include <linux/reset.h>
24
25/*
26 * The Meson SPICC controller could support DMA based transfers, but is not
27 * implemented by the vendor code, and while having the registers documentation
28 * it has never worked on the GXL Hardware.
29 * The PIO mode is the only mode implemented, and due to badly designed HW :
30 * - all transfers are cutted in 16 words burst because the FIFO hangs on
31 * TX underflow, and there is no TX "Half-Empty" interrupt, so we go by
32 * FIFO max size chunk only
33 * - CS management is dumb, and goes UP between every burst, so is really a
34 * "Data Valid" signal than a Chip Select, GPIO link should be used instead
35 * to have a CS go down over the full transfer
36 */
37
38#define SPICC_MAX_BURST 128
39
40/* Register Map */
41#define SPICC_RXDATA 0x00
42
43#define SPICC_TXDATA 0x04
44
45#define SPICC_CONREG 0x08
46#define SPICC_ENABLE BIT(0)
47#define SPICC_MODE_MASTER BIT(1)
48#define SPICC_XCH BIT(2)
49#define SPICC_SMC BIT(3)
50#define SPICC_POL BIT(4)
51#define SPICC_PHA BIT(5)
52#define SPICC_SSCTL BIT(6)
53#define SPICC_SSPOL BIT(7)
54#define SPICC_DRCTL_MASK GENMASK(9, 8)
55#define SPICC_DRCTL_IGNORE 0
56#define SPICC_DRCTL_FALLING 1
57#define SPICC_DRCTL_LOWLEVEL 2
58#define SPICC_CS_MASK GENMASK(13, 12)
59#define SPICC_DATARATE_MASK GENMASK(18, 16)
60#define SPICC_DATARATE_DIV4 0
61#define SPICC_DATARATE_DIV8 1
62#define SPICC_DATARATE_DIV16 2
63#define SPICC_DATARATE_DIV32 3
64#define SPICC_BITLENGTH_MASK GENMASK(24, 19)
65#define SPICC_BURSTLENGTH_MASK GENMASK(31, 25)
66
67#define SPICC_INTREG 0x0c
68#define SPICC_TE_EN BIT(0) /* TX FIFO Empty Interrupt */
69#define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */
70#define SPICC_TF_EN BIT(2) /* TX FIFO Full Interrupt */
71#define SPICC_RR_EN BIT(3) /* RX FIFO Ready Interrupt */
72#define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */
73#define SPICC_RF_EN BIT(5) /* RX FIFO Full Interrupt */
74#define SPICC_RO_EN BIT(6) /* RX FIFO Overflow Interrupt */
75#define SPICC_TC_EN BIT(7) /* Transfert Complete Interrupt */
76
77#define SPICC_DMAREG 0x10
78#define SPICC_DMA_ENABLE BIT(0)
79#define SPICC_TXFIFO_THRESHOLD_MASK GENMASK(5, 1)
80#define SPICC_RXFIFO_THRESHOLD_MASK GENMASK(10, 6)
81#define SPICC_READ_BURST_MASK GENMASK(14, 11)
82#define SPICC_WRITE_BURST_MASK GENMASK(18, 15)
83#define SPICC_DMA_URGENT BIT(19)
84#define SPICC_DMA_THREADID_MASK GENMASK(25, 20)
85#define SPICC_DMA_BURSTNUM_MASK GENMASK(31, 26)
86
87#define SPICC_STATREG 0x14
88#define SPICC_TE BIT(0) /* TX FIFO Empty Interrupt */
89#define SPICC_TH BIT(1) /* TX FIFO Half-Full Interrupt */
90#define SPICC_TF BIT(2) /* TX FIFO Full Interrupt */
91#define SPICC_RR BIT(3) /* RX FIFO Ready Interrupt */
92#define SPICC_RH BIT(4) /* RX FIFO Half-Full Interrupt */
93#define SPICC_RF BIT(5) /* RX FIFO Full Interrupt */
94#define SPICC_RO BIT(6) /* RX FIFO Overflow Interrupt */
95#define SPICC_TC BIT(7) /* Transfert Complete Interrupt */
96
97#define SPICC_PERIODREG 0x18
98#define SPICC_PERIOD GENMASK(14, 0) /* Wait cycles */
99
100#define SPICC_TESTREG 0x1c
101#define SPICC_TXCNT_MASK GENMASK(4, 0) /* TX FIFO Counter */
102#define SPICC_RXCNT_MASK GENMASK(9, 5) /* RX FIFO Counter */
103#define SPICC_SMSTATUS_MASK GENMASK(12, 10) /* State Machine Status */
104#define SPICC_LBC_RO BIT(13) /* Loop Back Control Read-Only */
105#define SPICC_LBC_W1 BIT(14) /* Loop Back Control Write-Only */
106#define SPICC_SWAP_RO BIT(14) /* RX FIFO Data Swap Read-Only */
107#define SPICC_SWAP_W1 BIT(15) /* RX FIFO Data Swap Write-Only */
108#define SPICC_DLYCTL_RO_MASK GENMASK(20, 15) /* Delay Control Read-Only */
109#define SPICC_MO_DELAY_MASK GENMASK(17, 16) /* Master Output Delay */
110#define SPICC_MO_NO_DELAY 0
111#define SPICC_MO_DELAY_1_CYCLE 1
112#define SPICC_MO_DELAY_2_CYCLE 2
113#define SPICC_MO_DELAY_3_CYCLE 3
114#define SPICC_MI_DELAY_MASK GENMASK(19, 18) /* Master Input Delay */
115#define SPICC_MI_NO_DELAY 0
116#define SPICC_MI_DELAY_1_CYCLE 1
117#define SPICC_MI_DELAY_2_CYCLE 2
118#define SPICC_MI_DELAY_3_CYCLE 3
119#define SPICC_MI_CAP_DELAY_MASK GENMASK(21, 20) /* Master Capture Delay */
120#define SPICC_CAP_AHEAD_2_CYCLE 0
121#define SPICC_CAP_AHEAD_1_CYCLE 1
122#define SPICC_CAP_NO_DELAY 2
123#define SPICC_CAP_DELAY_1_CYCLE 3
124#define SPICC_FIFORST_RO_MASK GENMASK(22, 21) /* FIFO Softreset Read-Only */
125#define SPICC_FIFORST_W1_MASK GENMASK(23, 22) /* FIFO Softreset Write-Only */
126
127#define SPICC_DRADDR 0x20 /* Read Address of DMA */
128
129#define SPICC_DWADDR 0x24 /* Write Address of DMA */
130
131#define SPICC_ENH_CTL0 0x38 /* Enhanced Feature */
132#define SPICC_ENH_CLK_CS_DELAY_MASK GENMASK(15, 0)
133#define SPICC_ENH_DATARATE_MASK GENMASK(23, 16)
134#define SPICC_ENH_DATARATE_EN BIT(24)
135#define SPICC_ENH_MOSI_OEN BIT(25)
136#define SPICC_ENH_CLK_OEN BIT(26)
137#define SPICC_ENH_CS_OEN BIT(27)
138#define SPICC_ENH_CLK_CS_DELAY_EN BIT(28)
139#define SPICC_ENH_MAIN_CLK_AO BIT(29)
140
141#define writel_bits_relaxed(mask, val, addr) \
142 writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr)
143
144struct meson_spicc_data {
145 unsigned int max_speed_hz;
146 unsigned int min_speed_hz;
147 unsigned int fifo_size;
148 bool has_oen;
149 bool has_enhance_clk_div;
150 bool has_pclk;
151};
152
153struct meson_spicc_device {
154 struct spi_master *master;
155 struct platform_device *pdev;
156 void __iomem *base;
157 struct clk *core;
158 struct clk *pclk;
159 struct clk *clk;
160 struct spi_message *message;
161 struct spi_transfer *xfer;
162 const struct meson_spicc_data *data;
163 u8 *tx_buf;
164 u8 *rx_buf;
165 unsigned int bytes_per_word;
166 unsigned long tx_remain;
167 unsigned long rx_remain;
168 unsigned long xfer_remain;
169};
170
171static void meson_spicc_oen_enable(struct meson_spicc_device *spicc)
172{
173 u32 conf;
174
175 if (!spicc->data->has_oen)
176 return;
177
178 conf = readl_relaxed(spicc->base + SPICC_ENH_CTL0) |
179 SPICC_ENH_MOSI_OEN | SPICC_ENH_CLK_OEN | SPICC_ENH_CS_OEN;
180
181 writel_relaxed(conf, spicc->base + SPICC_ENH_CTL0);
182}
183
184static inline bool meson_spicc_txfull(struct meson_spicc_device *spicc)
185{
186 return !!FIELD_GET(SPICC_TF,
187 readl_relaxed(spicc->base + SPICC_STATREG));
188}
189
190static inline bool meson_spicc_rxready(struct meson_spicc_device *spicc)
191{
192 return FIELD_GET(SPICC_RH | SPICC_RR | SPICC_RF,
193 readl_relaxed(spicc->base + SPICC_STATREG));
194}
195
196static inline u32 meson_spicc_pull_data(struct meson_spicc_device *spicc)
197{
198 unsigned int bytes = spicc->bytes_per_word;
199 unsigned int byte_shift = 0;
200 u32 data = 0;
201 u8 byte;
202
203 while (bytes--) {
204 byte = *spicc->tx_buf++;
205 data |= (byte & 0xff) << byte_shift;
206 byte_shift += 8;
207 }
208
209 spicc->tx_remain--;
210 return data;
211}
212
213static inline void meson_spicc_push_data(struct meson_spicc_device *spicc,
214 u32 data)
215{
216 unsigned int bytes = spicc->bytes_per_word;
217 unsigned int byte_shift = 0;
218 u8 byte;
219
220 while (bytes--) {
221 byte = (data >> byte_shift) & 0xff;
222 *spicc->rx_buf++ = byte;
223 byte_shift += 8;
224 }
225
226 spicc->rx_remain--;
227}
228
229static inline void meson_spicc_rx(struct meson_spicc_device *spicc)
230{
231 /* Empty RX FIFO */
232 while (spicc->rx_remain &&
233 meson_spicc_rxready(spicc))
234 meson_spicc_push_data(spicc,
235 readl_relaxed(spicc->base + SPICC_RXDATA));
236}
237
238static inline void meson_spicc_tx(struct meson_spicc_device *spicc)
239{
240 /* Fill Up TX FIFO */
241 while (spicc->tx_remain &&
242 !meson_spicc_txfull(spicc))
243 writel_relaxed(meson_spicc_pull_data(spicc),
244 spicc->base + SPICC_TXDATA);
245}
246
247static inline void meson_spicc_setup_burst(struct meson_spicc_device *spicc)
248{
249
250 unsigned int burst_len = min_t(unsigned int,
251 spicc->xfer_remain /
252 spicc->bytes_per_word,
253 spicc->data->fifo_size);
254 /* Setup Xfer variables */
255 spicc->tx_remain = burst_len;
256 spicc->rx_remain = burst_len;
257 spicc->xfer_remain -= burst_len * spicc->bytes_per_word;
258
259 /* Setup burst length */
260 writel_bits_relaxed(SPICC_BURSTLENGTH_MASK,
261 FIELD_PREP(SPICC_BURSTLENGTH_MASK,
262 burst_len - 1),
263 spicc->base + SPICC_CONREG);
264
265 /* Fill TX FIFO */
266 meson_spicc_tx(spicc);
267}
268
269static irqreturn_t meson_spicc_irq(int irq, void *data)
270{
271 struct meson_spicc_device *spicc = (void *) data;
272
273 writel_bits_relaxed(SPICC_TC, SPICC_TC, spicc->base + SPICC_STATREG);
274
275 /* Empty RX FIFO */
276 meson_spicc_rx(spicc);
277
278 if (!spicc->xfer_remain) {
279 /* Disable all IRQs */
280 writel(0, spicc->base + SPICC_INTREG);
281
282 spi_finalize_current_transfer(spicc->master);
283
284 return IRQ_HANDLED;
285 }
286
287 /* Setup burst */
288 meson_spicc_setup_burst(spicc);
289
290 /* Start burst */
291 writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);
292
293 return IRQ_HANDLED;
294}
295
296static void meson_spicc_auto_io_delay(struct meson_spicc_device *spicc)
297{
298 u32 div, hz;
299 u32 mi_delay, cap_delay;
300 u32 conf;
301
302 if (spicc->data->has_enhance_clk_div) {
303 div = FIELD_GET(SPICC_ENH_DATARATE_MASK,
304 readl_relaxed(spicc->base + SPICC_ENH_CTL0));
305 div++;
306 div <<= 1;
307 } else {
308 div = FIELD_GET(SPICC_DATARATE_MASK,
309 readl_relaxed(spicc->base + SPICC_CONREG));
310 div += 2;
311 div = 1 << div;
312 }
313
314 mi_delay = SPICC_MI_NO_DELAY;
315 cap_delay = SPICC_CAP_AHEAD_2_CYCLE;
316 hz = clk_get_rate(spicc->clk);
317
318 if (hz >= 100000000)
319 cap_delay = SPICC_CAP_DELAY_1_CYCLE;
320 else if (hz >= 80000000)
321 cap_delay = SPICC_CAP_NO_DELAY;
322 else if (hz >= 40000000)
323 cap_delay = SPICC_CAP_AHEAD_1_CYCLE;
324 else if (div >= 16)
325 mi_delay = SPICC_MI_DELAY_3_CYCLE;
326 else if (div >= 8)
327 mi_delay = SPICC_MI_DELAY_2_CYCLE;
328 else if (div >= 6)
329 mi_delay = SPICC_MI_DELAY_1_CYCLE;
330
331 conf = readl_relaxed(spicc->base + SPICC_TESTREG);
332 conf &= ~(SPICC_MO_DELAY_MASK | SPICC_MI_DELAY_MASK
333 | SPICC_MI_CAP_DELAY_MASK);
334 conf |= FIELD_PREP(SPICC_MI_DELAY_MASK, mi_delay);
335 conf |= FIELD_PREP(SPICC_MI_CAP_DELAY_MASK, cap_delay);
336 writel_relaxed(conf, spicc->base + SPICC_TESTREG);
337}
338
339static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc,
340 struct spi_transfer *xfer)
341{
342 u32 conf, conf_orig;
343
344 /* Read original configuration */
345 conf = conf_orig = readl_relaxed(spicc->base + SPICC_CONREG);
346
347 /* Setup word width */
348 conf &= ~SPICC_BITLENGTH_MASK;
349 conf |= FIELD_PREP(SPICC_BITLENGTH_MASK,
350 (spicc->bytes_per_word << 3) - 1);
351
352 /* Ignore if unchanged */
353 if (conf != conf_orig)
354 writel_relaxed(conf, spicc->base + SPICC_CONREG);
355
356 clk_set_rate(spicc->clk, xfer->speed_hz);
357
358 meson_spicc_auto_io_delay(spicc);
359
360 writel_relaxed(0, spicc->base + SPICC_DMAREG);
361}
362
363static void meson_spicc_reset_fifo(struct meson_spicc_device *spicc)
364{
365 if (spicc->data->has_oen)
366 writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO,
367 SPICC_ENH_MAIN_CLK_AO,
368 spicc->base + SPICC_ENH_CTL0);
369
370 writel_bits_relaxed(SPICC_FIFORST_W1_MASK, SPICC_FIFORST_W1_MASK,
371 spicc->base + SPICC_TESTREG);
372
373 while (meson_spicc_rxready(spicc))
374 readl_relaxed(spicc->base + SPICC_RXDATA);
375
376 if (spicc->data->has_oen)
377 writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO, 0,
378 spicc->base + SPICC_ENH_CTL0);
379}
380
381static int meson_spicc_transfer_one(struct spi_master *master,
382 struct spi_device *spi,
383 struct spi_transfer *xfer)
384{
385 struct meson_spicc_device *spicc = spi_master_get_devdata(master);
386
387 /* Store current transfer */
388 spicc->xfer = xfer;
389
390 /* Setup transfer parameters */
391 spicc->tx_buf = (u8 *)xfer->tx_buf;
392 spicc->rx_buf = (u8 *)xfer->rx_buf;
393 spicc->xfer_remain = xfer->len;
394
395 /* Pre-calculate word size */
396 spicc->bytes_per_word =
397 DIV_ROUND_UP(spicc->xfer->bits_per_word, 8);
398
399 if (xfer->len % spicc->bytes_per_word)
400 return -EINVAL;
401
402 /* Setup transfer parameters */
403 meson_spicc_setup_xfer(spicc, xfer);
404
405 meson_spicc_reset_fifo(spicc);
406
407 /* Setup burst */
408 meson_spicc_setup_burst(spicc);
409
410 /* Start burst */
411 writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);
412
413 /* Enable interrupts */
414 writel_relaxed(SPICC_TC_EN, spicc->base + SPICC_INTREG);
415
416 return 1;
417}
418
419static int meson_spicc_prepare_message(struct spi_master *master,
420 struct spi_message *message)
421{
422 struct meson_spicc_device *spicc = spi_master_get_devdata(master);
423 struct spi_device *spi = message->spi;
424 u32 conf = 0;
425
426 /* Store current message */
427 spicc->message = message;
428
429 /* Enable Master */
430 conf |= SPICC_ENABLE;
431 conf |= SPICC_MODE_MASTER;
432
433 /* SMC = 0 */
434
435 /* Setup transfer mode */
436 if (spi->mode & SPI_CPOL)
437 conf |= SPICC_POL;
438 else
439 conf &= ~SPICC_POL;
440
441 if (spi->mode & SPI_CPHA)
442 conf |= SPICC_PHA;
443 else
444 conf &= ~SPICC_PHA;
445
446 /* SSCTL = 0 */
447
448 if (spi->mode & SPI_CS_HIGH)
449 conf |= SPICC_SSPOL;
450 else
451 conf &= ~SPICC_SSPOL;
452
453 if (spi->mode & SPI_READY)
454 conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_LOWLEVEL);
455 else
456 conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_IGNORE);
457
458 /* Select CS */
459 conf |= FIELD_PREP(SPICC_CS_MASK, spi->chip_select);
460
461 /* Default Clock rate core/4 */
462
463 /* Default 8bit word */
464 conf |= FIELD_PREP(SPICC_BITLENGTH_MASK, 8 - 1);
465
466 writel_relaxed(conf, spicc->base + SPICC_CONREG);
467
468 /* Setup no wait cycles by default */
469 writel_relaxed(0, spicc->base + SPICC_PERIODREG);
470
471 writel_bits_relaxed(SPICC_LBC_W1, 0, spicc->base + SPICC_TESTREG);
472
473 return 0;
474}
475
476static int meson_spicc_unprepare_transfer(struct spi_master *master)
477{
478 struct meson_spicc_device *spicc = spi_master_get_devdata(master);
479
480 /* Disable all IRQs */
481 writel(0, spicc->base + SPICC_INTREG);
482
483 device_reset_optional(&spicc->pdev->dev);
484
485 return 0;
486}
487
488static int meson_spicc_setup(struct spi_device *spi)
489{
490 if (!spi->controller_state)
491 spi->controller_state = spi_master_get_devdata(spi->master);
492
493 return 0;
494}
495
496static void meson_spicc_cleanup(struct spi_device *spi)
497{
498 spi->controller_state = NULL;
499}
500
501/*
502 * The Clock Mux
503 * x-----------------x x------------x x------\
504 * |---| pow2 fixed div |---| pow2 div |----| |
505 * | x-----------------x x------------x | |
506 * src ---| | mux |-- out
507 * | x-----------------x x------------x | |
508 * |---| enh fixed div |---| enh div |0---| |
509 * x-----------------x x------------x x------/
510 *
511 * Clk path for GX series:
512 * src -> pow2 fixed div -> pow2 div -> out
513 *
514 * Clk path for AXG series:
515 * src -> pow2 fixed div -> pow2 div -> mux -> out
516 * src -> enh fixed div -> enh div -> mux -> out
517 *
518 * Clk path for G12A series:
519 * pclk -> pow2 fixed div -> pow2 div -> mux -> out
520 * pclk -> enh fixed div -> enh div -> mux -> out
521 */
522
523static int meson_spicc_clk_init(struct meson_spicc_device *spicc)
524{
525 struct device *dev = &spicc->pdev->dev;
526 struct clk_fixed_factor *pow2_fixed_div, *enh_fixed_div;
527 struct clk_divider *pow2_div, *enh_div;
528 struct clk_mux *mux;
529 struct clk_init_data init;
530 struct clk *clk;
531 struct clk_parent_data parent_data[2];
532 char name[64];
533
534 memset(&init, 0, sizeof(init));
535 memset(&parent_data, 0, sizeof(parent_data));
536
537 init.parent_data = parent_data;
538
539 /* algorithm for pow2 div: rate = freq / 4 / (2 ^ N) */
540
541 pow2_fixed_div = devm_kzalloc(dev, sizeof(*pow2_fixed_div), GFP_KERNEL);
542 if (!pow2_fixed_div)
543 return -ENOMEM;
544
545 snprintf(name, sizeof(name), "%s#pow2_fixed_div", dev_name(dev));
546 init.name = name;
547 init.ops = &clk_fixed_factor_ops;
548 init.flags = 0;
549 if (spicc->data->has_pclk)
550 parent_data[0].hw = __clk_get_hw(spicc->pclk);
551 else
552 parent_data[0].hw = __clk_get_hw(spicc->core);
553 init.num_parents = 1;
554
555 pow2_fixed_div->mult = 1,
556 pow2_fixed_div->div = 4,
557 pow2_fixed_div->hw.init = &init;
558
559 clk = devm_clk_register(dev, &pow2_fixed_div->hw);
560 if (WARN_ON(IS_ERR(clk)))
561 return PTR_ERR(clk);
562
563 pow2_div = devm_kzalloc(dev, sizeof(*pow2_div), GFP_KERNEL);
564 if (!pow2_div)
565 return -ENOMEM;
566
567 snprintf(name, sizeof(name), "%s#pow2_div", dev_name(dev));
568 init.name = name;
569 init.ops = &clk_divider_ops;
570 init.flags = CLK_SET_RATE_PARENT;
571 parent_data[0].hw = &pow2_fixed_div->hw;
572 init.num_parents = 1;
573
574 pow2_div->shift = 16,
575 pow2_div->width = 3,
576 pow2_div->flags = CLK_DIVIDER_POWER_OF_TWO,
577 pow2_div->reg = spicc->base + SPICC_CONREG;
578 pow2_div->hw.init = &init;
579
580 clk = devm_clk_register(dev, &pow2_div->hw);
581 if (WARN_ON(IS_ERR(clk)))
582 return PTR_ERR(clk);
583
584 if (!spicc->data->has_enhance_clk_div) {
585 spicc->clk = clk;
586 return 0;
587 }
588
589 /* algorithm for enh div: rate = freq / 2 / (N + 1) */
590
591 enh_fixed_div = devm_kzalloc(dev, sizeof(*enh_fixed_div), GFP_KERNEL);
592 if (!enh_fixed_div)
593 return -ENOMEM;
594
595 snprintf(name, sizeof(name), "%s#enh_fixed_div", dev_name(dev));
596 init.name = name;
597 init.ops = &clk_fixed_factor_ops;
598 init.flags = 0;
599 if (spicc->data->has_pclk)
600 parent_data[0].hw = __clk_get_hw(spicc->pclk);
601 else
602 parent_data[0].hw = __clk_get_hw(spicc->core);
603 init.num_parents = 1;
604
605 enh_fixed_div->mult = 1,
606 enh_fixed_div->div = 2,
607 enh_fixed_div->hw.init = &init;
608
609 clk = devm_clk_register(dev, &enh_fixed_div->hw);
610 if (WARN_ON(IS_ERR(clk)))
611 return PTR_ERR(clk);
612
613 enh_div = devm_kzalloc(dev, sizeof(*enh_div), GFP_KERNEL);
614 if (!enh_div)
615 return -ENOMEM;
616
617 snprintf(name, sizeof(name), "%s#enh_div", dev_name(dev));
618 init.name = name;
619 init.ops = &clk_divider_ops;
620 init.flags = CLK_SET_RATE_PARENT;
621 parent_data[0].hw = &enh_fixed_div->hw;
622 init.num_parents = 1;
623
624 enh_div->shift = 16,
625 enh_div->width = 8,
626 enh_div->reg = spicc->base + SPICC_ENH_CTL0;
627 enh_div->hw.init = &init;
628
629 clk = devm_clk_register(dev, &enh_div->hw);
630 if (WARN_ON(IS_ERR(clk)))
631 return PTR_ERR(clk);
632
633 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
634 if (!mux)
635 return -ENOMEM;
636
637 snprintf(name, sizeof(name), "%s#sel", dev_name(dev));
638 init.name = name;
639 init.ops = &clk_mux_ops;
640 parent_data[0].hw = &pow2_div->hw;
641 parent_data[1].hw = &enh_div->hw;
642 init.num_parents = 2;
643 init.flags = CLK_SET_RATE_PARENT;
644
645 mux->mask = 0x1,
646 mux->shift = 24,
647 mux->reg = spicc->base + SPICC_ENH_CTL0;
648 mux->hw.init = &init;
649
650 spicc->clk = devm_clk_register(dev, &mux->hw);
651 if (WARN_ON(IS_ERR(spicc->clk)))
652 return PTR_ERR(spicc->clk);
653
654 return 0;
655}
656
657static int meson_spicc_probe(struct platform_device *pdev)
658{
659 struct spi_master *master;
660 struct meson_spicc_device *spicc;
661 int ret, irq;
662
663 master = spi_alloc_master(&pdev->dev, sizeof(*spicc));
664 if (!master) {
665 dev_err(&pdev->dev, "master allocation failed\n");
666 return -ENOMEM;
667 }
668 spicc = spi_master_get_devdata(master);
669 spicc->master = master;
670
671 spicc->data = of_device_get_match_data(&pdev->dev);
672 if (!spicc->data) {
673 dev_err(&pdev->dev, "failed to get match data\n");
674 ret = -EINVAL;
675 goto out_master;
676 }
677
678 spicc->pdev = pdev;
679 platform_set_drvdata(pdev, spicc);
680
681 spicc->base = devm_platform_ioremap_resource(pdev, 0);
682 if (IS_ERR(spicc->base)) {
683 dev_err(&pdev->dev, "io resource mapping failed\n");
684 ret = PTR_ERR(spicc->base);
685 goto out_master;
686 }
687
688 /* Set master mode and enable controller */
689 writel_relaxed(SPICC_ENABLE | SPICC_MODE_MASTER,
690 spicc->base + SPICC_CONREG);
691
692 /* Disable all IRQs */
693 writel_relaxed(0, spicc->base + SPICC_INTREG);
694
695 irq = platform_get_irq(pdev, 0);
696 ret = devm_request_irq(&pdev->dev, irq, meson_spicc_irq,
697 0, NULL, spicc);
698 if (ret) {
699 dev_err(&pdev->dev, "irq request failed\n");
700 goto out_master;
701 }
702
703 spicc->core = devm_clk_get(&pdev->dev, "core");
704 if (IS_ERR(spicc->core)) {
705 dev_err(&pdev->dev, "core clock request failed\n");
706 ret = PTR_ERR(spicc->core);
707 goto out_master;
708 }
709
710 if (spicc->data->has_pclk) {
711 spicc->pclk = devm_clk_get(&pdev->dev, "pclk");
712 if (IS_ERR(spicc->pclk)) {
713 dev_err(&pdev->dev, "pclk clock request failed\n");
714 ret = PTR_ERR(spicc->pclk);
715 goto out_master;
716 }
717 }
718
719 ret = clk_prepare_enable(spicc->core);
720 if (ret) {
721 dev_err(&pdev->dev, "core clock enable failed\n");
722 goto out_master;
723 }
724
725 ret = clk_prepare_enable(spicc->pclk);
726 if (ret) {
727 dev_err(&pdev->dev, "pclk clock enable failed\n");
728 goto out_master;
729 }
730
731 device_reset_optional(&pdev->dev);
732
733 master->num_chipselect = 4;
734 master->dev.of_node = pdev->dev.of_node;
735 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH;
736 master->bits_per_word_mask = SPI_BPW_MASK(32) |
737 SPI_BPW_MASK(24) |
738 SPI_BPW_MASK(16) |
739 SPI_BPW_MASK(8);
740 master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX);
741 master->min_speed_hz = spicc->data->min_speed_hz;
742 master->max_speed_hz = spicc->data->max_speed_hz;
743 master->setup = meson_spicc_setup;
744 master->cleanup = meson_spicc_cleanup;
745 master->prepare_message = meson_spicc_prepare_message;
746 master->unprepare_transfer_hardware = meson_spicc_unprepare_transfer;
747 master->transfer_one = meson_spicc_transfer_one;
748 master->use_gpio_descriptors = true;
749
750 meson_spicc_oen_enable(spicc);
751
752 ret = meson_spicc_clk_init(spicc);
753 if (ret) {
754 dev_err(&pdev->dev, "clock registration failed\n");
755 goto out_master;
756 }
757
758 ret = devm_spi_register_master(&pdev->dev, master);
759 if (ret) {
760 dev_err(&pdev->dev, "spi master registration failed\n");
761 goto out_clk;
762 }
763
764 return 0;
765
766out_clk:
767 clk_disable_unprepare(spicc->core);
768 clk_disable_unprepare(spicc->pclk);
769
770out_master:
771 spi_master_put(master);
772
773 return ret;
774}
775
776static int meson_spicc_remove(struct platform_device *pdev)
777{
778 struct meson_spicc_device *spicc = platform_get_drvdata(pdev);
779
780 /* Disable SPI */
781 writel(0, spicc->base + SPICC_CONREG);
782
783 clk_disable_unprepare(spicc->core);
784 clk_disable_unprepare(spicc->pclk);
785
786 return 0;
787}
788
789static const struct meson_spicc_data meson_spicc_gx_data = {
790 .max_speed_hz = 30000000,
791 .min_speed_hz = 325000,
792 .fifo_size = 16,
793};
794
795static const struct meson_spicc_data meson_spicc_axg_data = {
796 .max_speed_hz = 80000000,
797 .min_speed_hz = 325000,
798 .fifo_size = 16,
799 .has_oen = true,
800 .has_enhance_clk_div = true,
801};
802
803static const struct meson_spicc_data meson_spicc_g12a_data = {
804 .max_speed_hz = 166666666,
805 .min_speed_hz = 50000,
806 .fifo_size = 15,
807 .has_oen = true,
808 .has_enhance_clk_div = true,
809 .has_pclk = true,
810};
811
812static const struct of_device_id meson_spicc_of_match[] = {
813 {
814 .compatible = "amlogic,meson-gx-spicc",
815 .data = &meson_spicc_gx_data,
816 },
817 {
818 .compatible = "amlogic,meson-axg-spicc",
819 .data = &meson_spicc_axg_data,
820 },
821 {
822 .compatible = "amlogic,meson-g12a-spicc",
823 .data = &meson_spicc_g12a_data,
824 },
825 { /* sentinel */ }
826};
827MODULE_DEVICE_TABLE(of, meson_spicc_of_match);
828
829static struct platform_driver meson_spicc_driver = {
830 .probe = meson_spicc_probe,
831 .remove = meson_spicc_remove,
832 .driver = {
833 .name = "meson-spicc",
834 .of_match_table = of_match_ptr(meson_spicc_of_match),
835 },
836};
837
838module_platform_driver(meson_spicc_driver);
839
840MODULE_DESCRIPTION("Meson SPI Communication Controller driver");
841MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
842MODULE_LICENSE("GPL");