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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
4 */
5
6#include <linux/delay.h>
7#include <linux/io.h>
8#include <linux/module.h>
9#include <linux/of.h>
10#include <linux/phy/phy.h>
11#include <linux/regulator/consumer.h>
12#include <linux/platform_device.h>
13#include <linux/clk.h>
14#include <linux/slab.h>
15
16#include <soc/tegra/fuse.h>
17
18#include "xusb.h"
19
20/* FUSE USB_CALIB registers */
21#define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
22#define HS_CURR_LEVEL_PAD_MASK 0x3f
23#define HS_TERM_RANGE_ADJ_SHIFT 7
24#define HS_TERM_RANGE_ADJ_MASK 0xf
25#define HS_SQUELCH_SHIFT 29
26#define HS_SQUELCH_MASK 0x7
27
28#define RPD_CTRL_SHIFT 0
29#define RPD_CTRL_MASK 0x1f
30
31/* XUSB PADCTL registers */
32#define XUSB_PADCTL_USB2_PAD_MUX 0x4
33#define USB2_PORT_SHIFT(x) ((x) * 2)
34#define USB2_PORT_MASK 0x3
35#define PORT_XUSB 1
36#define HSIC_PORT_SHIFT(x) ((x) + 20)
37#define HSIC_PORT_MASK 0x1
38#define PORT_HSIC 0
39
40#define XUSB_PADCTL_USB2_PORT_CAP 0x8
41#define XUSB_PADCTL_SS_PORT_CAP 0xc
42#define PORTX_CAP_SHIFT(x) ((x) * 4)
43#define PORT_CAP_MASK 0x3
44#define PORT_CAP_DISABLED 0x0
45#define PORT_CAP_HOST 0x1
46#define PORT_CAP_DEVICE 0x2
47#define PORT_CAP_OTG 0x3
48
49#define XUSB_PADCTL_ELPG_PROGRAM 0x20
50#define USB2_PORT_WAKE_INTERRUPT_ENABLE(x) BIT(x)
51#define USB2_PORT_WAKEUP_EVENT(x) BIT((x) + 7)
52#define SS_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 14)
53#define SS_PORT_WAKEUP_EVENT(x) BIT((x) + 21)
54#define USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 28)
55#define USB2_HSIC_PORT_WAKEUP_EVENT(x) BIT((x) + 30)
56#define ALL_WAKE_EVENTS \
57 (USB2_PORT_WAKEUP_EVENT(0) | USB2_PORT_WAKEUP_EVENT(1) | \
58 USB2_PORT_WAKEUP_EVENT(2) | SS_PORT_WAKEUP_EVENT(0) | \
59 SS_PORT_WAKEUP_EVENT(1) | SS_PORT_WAKEUP_EVENT(2) | \
60 USB2_HSIC_PORT_WAKEUP_EVENT(0))
61
62#define XUSB_PADCTL_ELPG_PROGRAM_1 0x24
63#define SSPX_ELPG_CLAMP_EN(x) BIT(0 + (x) * 3)
64#define SSPX_ELPG_CLAMP_EN_EARLY(x) BIT(1 + (x) * 3)
65#define SSPX_ELPG_VCORE_DOWN(x) BIT(2 + (x) * 3)
66#define XUSB_PADCTL_SS_PORT_CFG 0x2c
67#define PORTX_SPEED_SUPPORT_SHIFT(x) ((x) * 4)
68#define PORTX_SPEED_SUPPORT_MASK (0x3)
69#define PORT_SPEED_SUPPORT_GEN1 (0x0)
70
71#define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x88 + (x) * 0x40)
72#define HS_CURR_LEVEL(x) ((x) & 0x3f)
73#define TERM_SEL BIT(25)
74#define USB2_OTG_PD BIT(26)
75#define USB2_OTG_PD2 BIT(27)
76#define USB2_OTG_PD2_OVRD_EN BIT(28)
77#define USB2_OTG_PD_ZI BIT(29)
78
79#define XUSB_PADCTL_USB2_OTG_PADX_CTL1(x) (0x8c + (x) * 0x40)
80#define USB2_OTG_PD_DR BIT(2)
81#define TERM_RANGE_ADJ(x) (((x) & 0xf) << 3)
82#define RPD_CTRL(x) (((x) & 0x1f) << 26)
83
84#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x284
85#define BIAS_PAD_PD BIT(11)
86#define HS_SQUELCH_LEVEL(x) (((x) & 0x7) << 0)
87
88#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1 0x288
89#define USB2_TRK_START_TIMER(x) (((x) & 0x7f) << 12)
90#define USB2_TRK_DONE_RESET_TIMER(x) (((x) & 0x7f) << 19)
91#define USB2_PD_TRK BIT(26)
92
93#define XUSB_PADCTL_HSIC_PADX_CTL0(x) (0x300 + (x) * 0x20)
94#define HSIC_PD_TX_DATA0 BIT(1)
95#define HSIC_PD_TX_STROBE BIT(3)
96#define HSIC_PD_RX_DATA0 BIT(4)
97#define HSIC_PD_RX_STROBE BIT(6)
98#define HSIC_PD_ZI_DATA0 BIT(7)
99#define HSIC_PD_ZI_STROBE BIT(9)
100#define HSIC_RPD_DATA0 BIT(13)
101#define HSIC_RPD_STROBE BIT(15)
102#define HSIC_RPU_DATA0 BIT(16)
103#define HSIC_RPU_STROBE BIT(18)
104
105#define XUSB_PADCTL_HSIC_PAD_TRK_CTL0 0x340
106#define HSIC_TRK_START_TIMER(x) (((x) & 0x7f) << 5)
107#define HSIC_TRK_DONE_RESET_TIMER(x) (((x) & 0x7f) << 12)
108#define HSIC_PD_TRK BIT(19)
109
110#define USB2_VBUS_ID 0x360
111#define VBUS_OVERRIDE BIT(14)
112#define ID_OVERRIDE(x) (((x) & 0xf) << 18)
113#define ID_OVERRIDE_FLOATING ID_OVERRIDE(8)
114#define ID_OVERRIDE_GROUNDED ID_OVERRIDE(0)
115
116/* XUSB AO registers */
117#define XUSB_AO_USB_DEBOUNCE_DEL (0x4)
118#define UHSIC_LINE_DEB_CNT(x) (((x) & 0xf) << 4)
119#define UTMIP_LINE_DEB_CNT(x) ((x) & 0xf)
120
121#define XUSB_AO_UTMIP_TRIGGERS(x) (0x40 + (x) * 4)
122#define CLR_WALK_PTR BIT(0)
123#define CAP_CFG BIT(1)
124#define CLR_WAKE_ALARM BIT(3)
125
126#define XUSB_AO_UHSIC_TRIGGERS(x) (0x60 + (x) * 4)
127#define HSIC_CLR_WALK_PTR BIT(0)
128#define HSIC_CLR_WAKE_ALARM BIT(3)
129#define HSIC_CAP_CFG BIT(4)
130
131#define XUSB_AO_UTMIP_SAVED_STATE(x) (0x70 + (x) * 4)
132#define SPEED(x) ((x) & 0x3)
133#define UTMI_HS SPEED(0)
134#define UTMI_FS SPEED(1)
135#define UTMI_LS SPEED(2)
136#define UTMI_RST SPEED(3)
137
138#define XUSB_AO_UHSIC_SAVED_STATE(x) (0x90 + (x) * 4)
139#define MODE(x) ((x) & 0x1)
140#define MODE_HS MODE(0)
141#define MODE_RST MODE(1)
142
143#define XUSB_AO_UTMIP_SLEEPWALK_CFG(x) (0xd0 + (x) * 4)
144#define XUSB_AO_UHSIC_SLEEPWALK_CFG(x) (0xf0 + (x) * 4)
145#define FAKE_USBOP_VAL BIT(0)
146#define FAKE_USBON_VAL BIT(1)
147#define FAKE_USBOP_EN BIT(2)
148#define FAKE_USBON_EN BIT(3)
149#define FAKE_STROBE_VAL BIT(0)
150#define FAKE_DATA_VAL BIT(1)
151#define FAKE_STROBE_EN BIT(2)
152#define FAKE_DATA_EN BIT(3)
153#define WAKE_WALK_EN BIT(14)
154#define MASTER_ENABLE BIT(15)
155#define LINEVAL_WALK_EN BIT(16)
156#define WAKE_VAL(x) (((x) & 0xf) << 17)
157#define WAKE_VAL_NONE WAKE_VAL(12)
158#define WAKE_VAL_ANY WAKE_VAL(15)
159#define WAKE_VAL_DS10 WAKE_VAL(2)
160#define LINE_WAKEUP_EN BIT(21)
161#define MASTER_CFG_SEL BIT(22)
162
163#define XUSB_AO_UTMIP_SLEEPWALK(x) (0x100 + (x) * 4)
164/* phase A */
165#define USBOP_RPD_A BIT(0)
166#define USBON_RPD_A BIT(1)
167#define AP_A BIT(4)
168#define AN_A BIT(5)
169#define HIGHZ_A BIT(6)
170/* phase B */
171#define USBOP_RPD_B BIT(8)
172#define USBON_RPD_B BIT(9)
173#define AP_B BIT(12)
174#define AN_B BIT(13)
175#define HIGHZ_B BIT(14)
176/* phase C */
177#define USBOP_RPD_C BIT(16)
178#define USBON_RPD_C BIT(17)
179#define AP_C BIT(20)
180#define AN_C BIT(21)
181#define HIGHZ_C BIT(22)
182/* phase D */
183#define USBOP_RPD_D BIT(24)
184#define USBON_RPD_D BIT(25)
185#define AP_D BIT(28)
186#define AN_D BIT(29)
187#define HIGHZ_D BIT(30)
188
189#define XUSB_AO_UHSIC_SLEEPWALK(x) (0x120 + (x) * 4)
190/* phase A */
191#define RPD_STROBE_A BIT(0)
192#define RPD_DATA0_A BIT(1)
193#define RPU_STROBE_A BIT(2)
194#define RPU_DATA0_A BIT(3)
195/* phase B */
196#define RPD_STROBE_B BIT(8)
197#define RPD_DATA0_B BIT(9)
198#define RPU_STROBE_B BIT(10)
199#define RPU_DATA0_B BIT(11)
200/* phase C */
201#define RPD_STROBE_C BIT(16)
202#define RPD_DATA0_C BIT(17)
203#define RPU_STROBE_C BIT(18)
204#define RPU_DATA0_C BIT(19)
205/* phase D */
206#define RPD_STROBE_D BIT(24)
207#define RPD_DATA0_D BIT(25)
208#define RPU_STROBE_D BIT(26)
209#define RPU_DATA0_D BIT(27)
210
211#define XUSB_AO_UTMIP_PAD_CFG(x) (0x130 + (x) * 4)
212#define FSLS_USE_XUSB_AO BIT(3)
213#define TRK_CTRL_USE_XUSB_AO BIT(4)
214#define RPD_CTRL_USE_XUSB_AO BIT(5)
215#define RPU_USE_XUSB_AO BIT(6)
216#define VREG_USE_XUSB_AO BIT(7)
217#define USBOP_VAL_PD BIT(8)
218#define USBON_VAL_PD BIT(9)
219#define E_DPD_OVRD_EN BIT(10)
220#define E_DPD_OVRD_VAL BIT(11)
221
222#define XUSB_AO_UHSIC_PAD_CFG(x) (0x150 + (x) * 4)
223#define STROBE_VAL_PD BIT(0)
224#define DATA0_VAL_PD BIT(1)
225#define USE_XUSB_AO BIT(4)
226
227#define TEGRA186_LANE(_name, _offset, _shift, _mask, _type) \
228 { \
229 .name = _name, \
230 .offset = _offset, \
231 .shift = _shift, \
232 .mask = _mask, \
233 .num_funcs = ARRAY_SIZE(tegra186_##_type##_functions), \
234 .funcs = tegra186_##_type##_functions, \
235 }
236
237struct tegra_xusb_fuse_calibration {
238 u32 *hs_curr_level;
239 u32 hs_squelch;
240 u32 hs_term_range_adj;
241 u32 rpd_ctrl;
242};
243
244struct tegra186_xusb_padctl_context {
245 u32 vbus_id;
246 u32 usb2_pad_mux;
247 u32 usb2_port_cap;
248 u32 ss_port_cap;
249};
250
251struct tegra186_xusb_padctl {
252 struct tegra_xusb_padctl base;
253 void __iomem *ao_regs;
254
255 struct tegra_xusb_fuse_calibration calib;
256
257 /* UTMI bias and tracking */
258 struct clk *usb2_trk_clk;
259 unsigned int bias_pad_enable;
260
261 /* padctl context */
262 struct tegra186_xusb_padctl_context context;
263};
264
265static inline void ao_writel(struct tegra186_xusb_padctl *priv, u32 value, unsigned int offset)
266{
267 writel(value, priv->ao_regs + offset);
268}
269
270static inline u32 ao_readl(struct tegra186_xusb_padctl *priv, unsigned int offset)
271{
272 return readl(priv->ao_regs + offset);
273}
274
275static inline struct tegra186_xusb_padctl *
276to_tegra186_xusb_padctl(struct tegra_xusb_padctl *padctl)
277{
278 return container_of(padctl, struct tegra186_xusb_padctl, base);
279}
280
281/* USB 2.0 UTMI PHY support */
282static struct tegra_xusb_lane *
283tegra186_usb2_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
284 unsigned int index)
285{
286 struct tegra_xusb_usb2_lane *usb2;
287 int err;
288
289 usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);
290 if (!usb2)
291 return ERR_PTR(-ENOMEM);
292
293 INIT_LIST_HEAD(&usb2->base.list);
294 usb2->base.soc = &pad->soc->lanes[index];
295 usb2->base.index = index;
296 usb2->base.pad = pad;
297 usb2->base.np = np;
298
299 err = tegra_xusb_lane_parse_dt(&usb2->base, np);
300 if (err < 0) {
301 kfree(usb2);
302 return ERR_PTR(err);
303 }
304
305 return &usb2->base;
306}
307
308static void tegra186_usb2_lane_remove(struct tegra_xusb_lane *lane)
309{
310 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
311
312 kfree(usb2);
313}
314
315static int tegra186_utmi_enable_phy_sleepwalk(struct tegra_xusb_lane *lane,
316 enum usb_device_speed speed)
317{
318 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
319 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
320 unsigned int index = lane->index;
321 u32 value;
322
323 mutex_lock(&padctl->lock);
324
325 /* ensure sleepwalk logic is disabled */
326 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
327 value &= ~MASTER_ENABLE;
328 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
329
330 /* ensure sleepwalk logics are in low power mode */
331 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
332 value |= MASTER_CFG_SEL;
333 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
334
335 /* set debounce time */
336 value = ao_readl(priv, XUSB_AO_USB_DEBOUNCE_DEL);
337 value &= ~UTMIP_LINE_DEB_CNT(~0);
338 value |= UTMIP_LINE_DEB_CNT(1);
339 ao_writel(priv, value, XUSB_AO_USB_DEBOUNCE_DEL);
340
341 /* ensure fake events of sleepwalk logic are desiabled */
342 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
343 value &= ~(FAKE_USBOP_VAL | FAKE_USBON_VAL |
344 FAKE_USBOP_EN | FAKE_USBON_EN);
345 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
346
347 /* ensure wake events of sleepwalk logic are not latched */
348 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
349 value &= ~LINE_WAKEUP_EN;
350 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
351
352 /* disable wake event triggers of sleepwalk logic */
353 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
354 value &= ~WAKE_VAL(~0);
355 value |= WAKE_VAL_NONE;
356 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
357
358 /* power down the line state detectors of the pad */
359 value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
360 value |= (USBOP_VAL_PD | USBON_VAL_PD);
361 ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
362
363 /* save state per speed */
364 value = ao_readl(priv, XUSB_AO_UTMIP_SAVED_STATE(index));
365 value &= ~SPEED(~0);
366
367 switch (speed) {
368 case USB_SPEED_HIGH:
369 value |= UTMI_HS;
370 break;
371
372 case USB_SPEED_FULL:
373 value |= UTMI_FS;
374 break;
375
376 case USB_SPEED_LOW:
377 value |= UTMI_LS;
378 break;
379
380 default:
381 value |= UTMI_RST;
382 break;
383 }
384
385 ao_writel(priv, value, XUSB_AO_UTMIP_SAVED_STATE(index));
386
387 /* enable the trigger of the sleepwalk logic */
388 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
389 value |= LINEVAL_WALK_EN;
390 value &= ~WAKE_WALK_EN;
391 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
392
393 /* reset the walk pointer and clear the alarm of the sleepwalk logic,
394 * as well as capture the configuration of the USB2.0 pad
395 */
396 value = ao_readl(priv, XUSB_AO_UTMIP_TRIGGERS(index));
397 value |= (CLR_WALK_PTR | CLR_WAKE_ALARM | CAP_CFG);
398 ao_writel(priv, value, XUSB_AO_UTMIP_TRIGGERS(index));
399
400 /* setup the pull-ups and pull-downs of the signals during the four
401 * stages of sleepwalk.
402 * if device is connected, program sleepwalk logic to maintain a J and
403 * keep driving K upon seeing remote wake.
404 */
405 value = USBOP_RPD_A | USBOP_RPD_B | USBOP_RPD_C | USBOP_RPD_D;
406 value |= USBON_RPD_A | USBON_RPD_B | USBON_RPD_C | USBON_RPD_D;
407
408 switch (speed) {
409 case USB_SPEED_HIGH:
410 case USB_SPEED_FULL:
411 /* J state: D+/D- = high/low, K state: D+/D- = low/high */
412 value |= HIGHZ_A;
413 value |= AP_A;
414 value |= AN_B | AN_C | AN_D;
415 break;
416
417 case USB_SPEED_LOW:
418 /* J state: D+/D- = low/high, K state: D+/D- = high/low */
419 value |= HIGHZ_A;
420 value |= AN_A;
421 value |= AP_B | AP_C | AP_D;
422 break;
423
424 default:
425 value |= HIGHZ_A | HIGHZ_B | HIGHZ_C | HIGHZ_D;
426 break;
427 }
428
429 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK(index));
430
431 /* power up the line state detectors of the pad */
432 value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
433 value &= ~(USBOP_VAL_PD | USBON_VAL_PD);
434 ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
435
436 usleep_range(150, 200);
437
438 /* switch the electric control of the USB2.0 pad to XUSB_AO */
439 value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
440 value |= FSLS_USE_XUSB_AO | TRK_CTRL_USE_XUSB_AO | RPD_CTRL_USE_XUSB_AO |
441 RPU_USE_XUSB_AO | VREG_USE_XUSB_AO;
442 ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
443
444 /* set the wake signaling trigger events */
445 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
446 value &= ~WAKE_VAL(~0);
447 value |= WAKE_VAL_ANY;
448 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
449
450 /* enable the wake detection */
451 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
452 value |= MASTER_ENABLE | LINE_WAKEUP_EN;
453 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
454
455 mutex_unlock(&padctl->lock);
456
457 return 0;
458}
459
460static int tegra186_utmi_disable_phy_sleepwalk(struct tegra_xusb_lane *lane)
461{
462 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
463 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
464 unsigned int index = lane->index;
465 u32 value;
466
467 mutex_lock(&padctl->lock);
468
469 /* disable the wake detection */
470 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
471 value &= ~(MASTER_ENABLE | LINE_WAKEUP_EN);
472 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
473
474 /* switch the electric control of the USB2.0 pad to XUSB vcore logic */
475 value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
476 value &= ~(FSLS_USE_XUSB_AO | TRK_CTRL_USE_XUSB_AO | RPD_CTRL_USE_XUSB_AO |
477 RPU_USE_XUSB_AO | VREG_USE_XUSB_AO);
478 ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
479
480 /* disable wake event triggers of sleepwalk logic */
481 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
482 value &= ~WAKE_VAL(~0);
483 value |= WAKE_VAL_NONE;
484 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
485
486 /* power down the line state detectors of the port */
487 value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
488 value |= USBOP_VAL_PD | USBON_VAL_PD;
489 ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
490
491 /* clear alarm of the sleepwalk logic */
492 value = ao_readl(priv, XUSB_AO_UTMIP_TRIGGERS(index));
493 value |= CLR_WAKE_ALARM;
494 ao_writel(priv, value, XUSB_AO_UTMIP_TRIGGERS(index));
495
496 mutex_unlock(&padctl->lock);
497
498 return 0;
499}
500
501static int tegra186_utmi_enable_phy_wake(struct tegra_xusb_lane *lane)
502{
503 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
504 unsigned int index = lane->index;
505 u32 value;
506
507 mutex_lock(&padctl->lock);
508
509 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
510 value &= ~ALL_WAKE_EVENTS;
511 value |= USB2_PORT_WAKEUP_EVENT(index);
512 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
513
514 usleep_range(10, 20);
515
516 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
517 value &= ~ALL_WAKE_EVENTS;
518 value |= USB2_PORT_WAKE_INTERRUPT_ENABLE(index);
519 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
520
521 mutex_unlock(&padctl->lock);
522
523 return 0;
524}
525
526static int tegra186_utmi_disable_phy_wake(struct tegra_xusb_lane *lane)
527{
528 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
529 unsigned int index = lane->index;
530 u32 value;
531
532 mutex_lock(&padctl->lock);
533
534 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
535 value &= ~ALL_WAKE_EVENTS;
536 value &= ~USB2_PORT_WAKE_INTERRUPT_ENABLE(index);
537 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
538
539 usleep_range(10, 20);
540
541 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
542 value &= ~ALL_WAKE_EVENTS;
543 value |= USB2_PORT_WAKEUP_EVENT(index);
544 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
545
546 mutex_unlock(&padctl->lock);
547
548 return 0;
549}
550
551static bool tegra186_utmi_phy_remote_wake_detected(struct tegra_xusb_lane *lane)
552{
553 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
554 unsigned int index = lane->index;
555 u32 value;
556
557 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
558 if ((value & USB2_PORT_WAKE_INTERRUPT_ENABLE(index)) &&
559 (value & USB2_PORT_WAKEUP_EVENT(index)))
560 return true;
561
562 return false;
563}
564
565static const struct tegra_xusb_lane_ops tegra186_usb2_lane_ops = {
566 .probe = tegra186_usb2_lane_probe,
567 .remove = tegra186_usb2_lane_remove,
568 .enable_phy_sleepwalk = tegra186_utmi_enable_phy_sleepwalk,
569 .disable_phy_sleepwalk = tegra186_utmi_disable_phy_sleepwalk,
570 .enable_phy_wake = tegra186_utmi_enable_phy_wake,
571 .disable_phy_wake = tegra186_utmi_disable_phy_wake,
572 .remote_wake_detected = tegra186_utmi_phy_remote_wake_detected,
573};
574
575static void tegra186_utmi_bias_pad_power_on(struct tegra_xusb_padctl *padctl)
576{
577 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
578 struct device *dev = padctl->dev;
579 u32 value;
580 int err;
581
582 mutex_lock(&padctl->lock);
583
584 if (priv->bias_pad_enable++ > 0) {
585 mutex_unlock(&padctl->lock);
586 return;
587 }
588
589 err = clk_prepare_enable(priv->usb2_trk_clk);
590 if (err < 0)
591 dev_warn(dev, "failed to enable USB2 trk clock: %d\n", err);
592
593 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
594 value &= ~USB2_TRK_START_TIMER(~0);
595 value |= USB2_TRK_START_TIMER(0x1e);
596 value &= ~USB2_TRK_DONE_RESET_TIMER(~0);
597 value |= USB2_TRK_DONE_RESET_TIMER(0xa);
598 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
599
600 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
601 value &= ~BIAS_PAD_PD;
602 value &= ~HS_SQUELCH_LEVEL(~0);
603 value |= HS_SQUELCH_LEVEL(priv->calib.hs_squelch);
604 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
605
606 udelay(1);
607
608 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
609 value &= ~USB2_PD_TRK;
610 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
611
612 mutex_unlock(&padctl->lock);
613}
614
615static void tegra186_utmi_bias_pad_power_off(struct tegra_xusb_padctl *padctl)
616{
617 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
618 u32 value;
619
620 mutex_lock(&padctl->lock);
621
622 if (WARN_ON(priv->bias_pad_enable == 0)) {
623 mutex_unlock(&padctl->lock);
624 return;
625 }
626
627 if (--priv->bias_pad_enable > 0) {
628 mutex_unlock(&padctl->lock);
629 return;
630 }
631
632 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
633 value |= USB2_PD_TRK;
634 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
635
636 clk_disable_unprepare(priv->usb2_trk_clk);
637
638 mutex_unlock(&padctl->lock);
639}
640
641static void tegra186_utmi_pad_power_on(struct phy *phy)
642{
643 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
644 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
645 struct tegra_xusb_usb2_port *port;
646 struct device *dev = padctl->dev;
647 unsigned int index = lane->index;
648 u32 value;
649
650 if (!phy)
651 return;
652
653 port = tegra_xusb_find_usb2_port(padctl, index);
654 if (!port) {
655 dev_err(dev, "no port found for USB2 lane %u\n", index);
656 return;
657 }
658
659 dev_dbg(dev, "power on UTMI pad %u\n", index);
660
661 tegra186_utmi_bias_pad_power_on(padctl);
662
663 udelay(2);
664
665 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
666 value &= ~USB2_OTG_PD;
667 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
668
669 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
670 value &= ~USB2_OTG_PD_DR;
671 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
672}
673
674static void tegra186_utmi_pad_power_down(struct phy *phy)
675{
676 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
677 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
678 unsigned int index = lane->index;
679 u32 value;
680
681 if (!phy)
682 return;
683
684 dev_dbg(padctl->dev, "power down UTMI pad %u\n", index);
685
686 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
687 value |= USB2_OTG_PD;
688 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
689
690 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
691 value |= USB2_OTG_PD_DR;
692 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
693
694 udelay(2);
695
696 tegra186_utmi_bias_pad_power_off(padctl);
697}
698
699static int tegra186_xusb_padctl_vbus_override(struct tegra_xusb_padctl *padctl,
700 bool status)
701{
702 u32 value;
703
704 dev_dbg(padctl->dev, "%s vbus override\n", status ? "set" : "clear");
705
706 value = padctl_readl(padctl, USB2_VBUS_ID);
707
708 if (status) {
709 value |= VBUS_OVERRIDE;
710 value &= ~ID_OVERRIDE(~0);
711 value |= ID_OVERRIDE_FLOATING;
712 } else {
713 value &= ~VBUS_OVERRIDE;
714 }
715
716 padctl_writel(padctl, value, USB2_VBUS_ID);
717
718 return 0;
719}
720
721static int tegra186_xusb_padctl_id_override(struct tegra_xusb_padctl *padctl,
722 bool status)
723{
724 u32 value;
725
726 dev_dbg(padctl->dev, "%s id override\n", status ? "set" : "clear");
727
728 value = padctl_readl(padctl, USB2_VBUS_ID);
729
730 if (status) {
731 if (value & VBUS_OVERRIDE) {
732 value &= ~VBUS_OVERRIDE;
733 padctl_writel(padctl, value, USB2_VBUS_ID);
734 usleep_range(1000, 2000);
735
736 value = padctl_readl(padctl, USB2_VBUS_ID);
737 }
738
739 value &= ~ID_OVERRIDE(~0);
740 value |= ID_OVERRIDE_GROUNDED;
741 } else {
742 value &= ~ID_OVERRIDE(~0);
743 value |= ID_OVERRIDE_FLOATING;
744 }
745
746 padctl_writel(padctl, value, USB2_VBUS_ID);
747
748 return 0;
749}
750
751static int tegra186_utmi_phy_set_mode(struct phy *phy, enum phy_mode mode,
752 int submode)
753{
754 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
755 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
756 struct tegra_xusb_usb2_port *port = tegra_xusb_find_usb2_port(padctl,
757 lane->index);
758 int err = 0;
759
760 mutex_lock(&padctl->lock);
761
762 dev_dbg(&port->base.dev, "%s: mode %d", __func__, mode);
763
764 if (mode == PHY_MODE_USB_OTG) {
765 if (submode == USB_ROLE_HOST) {
766 tegra186_xusb_padctl_id_override(padctl, true);
767
768 err = regulator_enable(port->supply);
769 } else if (submode == USB_ROLE_DEVICE) {
770 tegra186_xusb_padctl_vbus_override(padctl, true);
771 } else if (submode == USB_ROLE_NONE) {
772 /*
773 * When port is peripheral only or role transitions to
774 * USB_ROLE_NONE from USB_ROLE_DEVICE, regulator is not
775 * enabled.
776 */
777 if (regulator_is_enabled(port->supply))
778 regulator_disable(port->supply);
779
780 tegra186_xusb_padctl_id_override(padctl, false);
781 tegra186_xusb_padctl_vbus_override(padctl, false);
782 }
783 }
784
785 mutex_unlock(&padctl->lock);
786
787 return err;
788}
789
790static int tegra186_utmi_phy_power_on(struct phy *phy)
791{
792 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
793 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
794 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
795 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
796 struct tegra_xusb_usb2_port *port;
797 unsigned int index = lane->index;
798 struct device *dev = padctl->dev;
799 u32 value;
800
801 port = tegra_xusb_find_usb2_port(padctl, index);
802 if (!port) {
803 dev_err(dev, "no port found for USB2 lane %u\n", index);
804 return -ENODEV;
805 }
806
807 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
808 value &= ~(USB2_PORT_MASK << USB2_PORT_SHIFT(index));
809 value |= (PORT_XUSB << USB2_PORT_SHIFT(index));
810 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX);
811
812 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
813 value &= ~(PORT_CAP_MASK << PORTX_CAP_SHIFT(index));
814
815 if (port->mode == USB_DR_MODE_UNKNOWN)
816 value |= (PORT_CAP_DISABLED << PORTX_CAP_SHIFT(index));
817 else if (port->mode == USB_DR_MODE_PERIPHERAL)
818 value |= (PORT_CAP_DEVICE << PORTX_CAP_SHIFT(index));
819 else if (port->mode == USB_DR_MODE_HOST)
820 value |= (PORT_CAP_HOST << PORTX_CAP_SHIFT(index));
821 else if (port->mode == USB_DR_MODE_OTG)
822 value |= (PORT_CAP_OTG << PORTX_CAP_SHIFT(index));
823
824 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP);
825
826 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
827 value &= ~USB2_OTG_PD_ZI;
828 value |= TERM_SEL;
829 value &= ~HS_CURR_LEVEL(~0);
830
831 if (usb2->hs_curr_level_offset) {
832 int hs_current_level;
833
834 hs_current_level = (int)priv->calib.hs_curr_level[index] +
835 usb2->hs_curr_level_offset;
836
837 if (hs_current_level < 0)
838 hs_current_level = 0;
839 if (hs_current_level > 0x3f)
840 hs_current_level = 0x3f;
841
842 value |= HS_CURR_LEVEL(hs_current_level);
843 } else {
844 value |= HS_CURR_LEVEL(priv->calib.hs_curr_level[index]);
845 }
846
847 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
848
849 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
850 value &= ~TERM_RANGE_ADJ(~0);
851 value |= TERM_RANGE_ADJ(priv->calib.hs_term_range_adj);
852 value &= ~RPD_CTRL(~0);
853 value |= RPD_CTRL(priv->calib.rpd_ctrl);
854 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
855
856 tegra186_utmi_pad_power_on(phy);
857
858 return 0;
859}
860
861static int tegra186_utmi_phy_power_off(struct phy *phy)
862{
863 tegra186_utmi_pad_power_down(phy);
864
865 return 0;
866}
867
868static int tegra186_utmi_phy_init(struct phy *phy)
869{
870 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
871 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
872 struct tegra_xusb_usb2_port *port;
873 unsigned int index = lane->index;
874 struct device *dev = padctl->dev;
875 int err;
876
877 port = tegra_xusb_find_usb2_port(padctl, index);
878 if (!port) {
879 dev_err(dev, "no port found for USB2 lane %u\n", index);
880 return -ENODEV;
881 }
882
883 if (port->supply && port->mode == USB_DR_MODE_HOST) {
884 err = regulator_enable(port->supply);
885 if (err) {
886 dev_err(dev, "failed to enable port %u VBUS: %d\n",
887 index, err);
888 return err;
889 }
890 }
891
892 return 0;
893}
894
895static int tegra186_utmi_phy_exit(struct phy *phy)
896{
897 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
898 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
899 struct tegra_xusb_usb2_port *port;
900 unsigned int index = lane->index;
901 struct device *dev = padctl->dev;
902 int err;
903
904 port = tegra_xusb_find_usb2_port(padctl, index);
905 if (!port) {
906 dev_err(dev, "no port found for USB2 lane %u\n", index);
907 return -ENODEV;
908 }
909
910 if (port->supply && port->mode == USB_DR_MODE_HOST) {
911 err = regulator_disable(port->supply);
912 if (err) {
913 dev_err(dev, "failed to disable port %u VBUS: %d\n",
914 index, err);
915 return err;
916 }
917 }
918
919 return 0;
920}
921
922static const struct phy_ops utmi_phy_ops = {
923 .init = tegra186_utmi_phy_init,
924 .exit = tegra186_utmi_phy_exit,
925 .power_on = tegra186_utmi_phy_power_on,
926 .power_off = tegra186_utmi_phy_power_off,
927 .set_mode = tegra186_utmi_phy_set_mode,
928 .owner = THIS_MODULE,
929};
930
931static struct tegra_xusb_pad *
932tegra186_usb2_pad_probe(struct tegra_xusb_padctl *padctl,
933 const struct tegra_xusb_pad_soc *soc,
934 struct device_node *np)
935{
936 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
937 struct tegra_xusb_usb2_pad *usb2;
938 struct tegra_xusb_pad *pad;
939 int err;
940
941 usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);
942 if (!usb2)
943 return ERR_PTR(-ENOMEM);
944
945 pad = &usb2->base;
946 pad->ops = &tegra186_usb2_lane_ops;
947 pad->soc = soc;
948
949 err = tegra_xusb_pad_init(pad, padctl, np);
950 if (err < 0) {
951 kfree(usb2);
952 goto out;
953 }
954
955 priv->usb2_trk_clk = devm_clk_get(&pad->dev, "trk");
956 if (IS_ERR(priv->usb2_trk_clk)) {
957 err = PTR_ERR(priv->usb2_trk_clk);
958 dev_dbg(&pad->dev, "failed to get usb2 trk clock: %d\n", err);
959 goto unregister;
960 }
961
962 err = tegra_xusb_pad_register(pad, &utmi_phy_ops);
963 if (err < 0)
964 goto unregister;
965
966 dev_set_drvdata(&pad->dev, pad);
967
968 return pad;
969
970unregister:
971 device_unregister(&pad->dev);
972out:
973 return ERR_PTR(err);
974}
975
976static void tegra186_usb2_pad_remove(struct tegra_xusb_pad *pad)
977{
978 struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad);
979
980 kfree(usb2);
981}
982
983static const struct tegra_xusb_pad_ops tegra186_usb2_pad_ops = {
984 .probe = tegra186_usb2_pad_probe,
985 .remove = tegra186_usb2_pad_remove,
986};
987
988static const char * const tegra186_usb2_functions[] = {
989 "xusb",
990};
991
992static int tegra186_usb2_port_enable(struct tegra_xusb_port *port)
993{
994 return 0;
995}
996
997static void tegra186_usb2_port_disable(struct tegra_xusb_port *port)
998{
999}
1000
1001static struct tegra_xusb_lane *
1002tegra186_usb2_port_map(struct tegra_xusb_port *port)
1003{
1004 return tegra_xusb_find_lane(port->padctl, "usb2", port->index);
1005}
1006
1007static const struct tegra_xusb_port_ops tegra186_usb2_port_ops = {
1008 .release = tegra_xusb_usb2_port_release,
1009 .remove = tegra_xusb_usb2_port_remove,
1010 .enable = tegra186_usb2_port_enable,
1011 .disable = tegra186_usb2_port_disable,
1012 .map = tegra186_usb2_port_map,
1013};
1014
1015/* SuperSpeed PHY support */
1016static struct tegra_xusb_lane *
1017tegra186_usb3_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
1018 unsigned int index)
1019{
1020 struct tegra_xusb_usb3_lane *usb3;
1021 int err;
1022
1023 usb3 = kzalloc(sizeof(*usb3), GFP_KERNEL);
1024 if (!usb3)
1025 return ERR_PTR(-ENOMEM);
1026
1027 INIT_LIST_HEAD(&usb3->base.list);
1028 usb3->base.soc = &pad->soc->lanes[index];
1029 usb3->base.index = index;
1030 usb3->base.pad = pad;
1031 usb3->base.np = np;
1032
1033 err = tegra_xusb_lane_parse_dt(&usb3->base, np);
1034 if (err < 0) {
1035 kfree(usb3);
1036 return ERR_PTR(err);
1037 }
1038
1039 return &usb3->base;
1040}
1041
1042static void tegra186_usb3_lane_remove(struct tegra_xusb_lane *lane)
1043{
1044 struct tegra_xusb_usb3_lane *usb3 = to_usb3_lane(lane);
1045
1046 kfree(usb3);
1047}
1048
1049static int tegra186_usb3_enable_phy_sleepwalk(struct tegra_xusb_lane *lane,
1050 enum usb_device_speed speed)
1051{
1052 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1053 unsigned int index = lane->index;
1054 u32 value;
1055
1056 mutex_lock(&padctl->lock);
1057
1058 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1059 value |= SSPX_ELPG_CLAMP_EN_EARLY(index);
1060 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1061
1062 usleep_range(100, 200);
1063
1064 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1065 value |= SSPX_ELPG_CLAMP_EN(index);
1066 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1067
1068 usleep_range(250, 350);
1069
1070 mutex_unlock(&padctl->lock);
1071
1072 return 0;
1073}
1074
1075static int tegra186_usb3_disable_phy_sleepwalk(struct tegra_xusb_lane *lane)
1076{
1077 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1078 unsigned int index = lane->index;
1079 u32 value;
1080
1081 mutex_lock(&padctl->lock);
1082
1083 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1084 value &= ~SSPX_ELPG_CLAMP_EN_EARLY(index);
1085 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1086
1087 usleep_range(100, 200);
1088
1089 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1090 value &= ~SSPX_ELPG_CLAMP_EN(index);
1091 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1092
1093 mutex_unlock(&padctl->lock);
1094
1095 return 0;
1096}
1097
1098static int tegra186_usb3_enable_phy_wake(struct tegra_xusb_lane *lane)
1099{
1100 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1101 unsigned int index = lane->index;
1102 u32 value;
1103
1104 mutex_lock(&padctl->lock);
1105
1106 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1107 value &= ~ALL_WAKE_EVENTS;
1108 value |= SS_PORT_WAKEUP_EVENT(index);
1109 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1110
1111 usleep_range(10, 20);
1112
1113 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1114 value &= ~ALL_WAKE_EVENTS;
1115 value |= SS_PORT_WAKE_INTERRUPT_ENABLE(index);
1116 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1117
1118 mutex_unlock(&padctl->lock);
1119
1120 return 0;
1121}
1122
1123static int tegra186_usb3_disable_phy_wake(struct tegra_xusb_lane *lane)
1124{
1125 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1126 unsigned int index = lane->index;
1127 u32 value;
1128
1129 mutex_lock(&padctl->lock);
1130
1131 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1132 value &= ~ALL_WAKE_EVENTS;
1133 value &= ~SS_PORT_WAKE_INTERRUPT_ENABLE(index);
1134 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1135
1136 usleep_range(10, 20);
1137
1138 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1139 value &= ~ALL_WAKE_EVENTS;
1140 value |= SS_PORT_WAKEUP_EVENT(index);
1141 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1142
1143 mutex_unlock(&padctl->lock);
1144
1145 return 0;
1146}
1147
1148static bool tegra186_usb3_phy_remote_wake_detected(struct tegra_xusb_lane *lane)
1149{
1150 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1151 unsigned int index = lane->index;
1152 u32 value;
1153
1154 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1155 if ((value & SS_PORT_WAKE_INTERRUPT_ENABLE(index)) && (value & SS_PORT_WAKEUP_EVENT(index)))
1156 return true;
1157
1158 return false;
1159}
1160
1161static const struct tegra_xusb_lane_ops tegra186_usb3_lane_ops = {
1162 .probe = tegra186_usb3_lane_probe,
1163 .remove = tegra186_usb3_lane_remove,
1164 .enable_phy_sleepwalk = tegra186_usb3_enable_phy_sleepwalk,
1165 .disable_phy_sleepwalk = tegra186_usb3_disable_phy_sleepwalk,
1166 .enable_phy_wake = tegra186_usb3_enable_phy_wake,
1167 .disable_phy_wake = tegra186_usb3_disable_phy_wake,
1168 .remote_wake_detected = tegra186_usb3_phy_remote_wake_detected,
1169};
1170
1171static int tegra186_usb3_port_enable(struct tegra_xusb_port *port)
1172{
1173 return 0;
1174}
1175
1176static void tegra186_usb3_port_disable(struct tegra_xusb_port *port)
1177{
1178}
1179
1180static struct tegra_xusb_lane *
1181tegra186_usb3_port_map(struct tegra_xusb_port *port)
1182{
1183 return tegra_xusb_find_lane(port->padctl, "usb3", port->index);
1184}
1185
1186static const struct tegra_xusb_port_ops tegra186_usb3_port_ops = {
1187 .release = tegra_xusb_usb3_port_release,
1188 .enable = tegra186_usb3_port_enable,
1189 .disable = tegra186_usb3_port_disable,
1190 .map = tegra186_usb3_port_map,
1191};
1192
1193static int tegra186_usb3_phy_power_on(struct phy *phy)
1194{
1195 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1196 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1197 struct tegra_xusb_usb3_port *port;
1198 struct tegra_xusb_usb2_port *usb2;
1199 unsigned int index = lane->index;
1200 struct device *dev = padctl->dev;
1201 u32 value;
1202
1203 port = tegra_xusb_find_usb3_port(padctl, index);
1204 if (!port) {
1205 dev_err(dev, "no port found for USB3 lane %u\n", index);
1206 return -ENODEV;
1207 }
1208
1209 usb2 = tegra_xusb_find_usb2_port(padctl, port->port);
1210 if (!usb2) {
1211 dev_err(dev, "no companion port found for USB3 lane %u\n",
1212 index);
1213 return -ENODEV;
1214 }
1215
1216 mutex_lock(&padctl->lock);
1217
1218 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CAP);
1219 value &= ~(PORT_CAP_MASK << PORTX_CAP_SHIFT(index));
1220
1221 if (usb2->mode == USB_DR_MODE_UNKNOWN)
1222 value |= (PORT_CAP_DISABLED << PORTX_CAP_SHIFT(index));
1223 else if (usb2->mode == USB_DR_MODE_PERIPHERAL)
1224 value |= (PORT_CAP_DEVICE << PORTX_CAP_SHIFT(index));
1225 else if (usb2->mode == USB_DR_MODE_HOST)
1226 value |= (PORT_CAP_HOST << PORTX_CAP_SHIFT(index));
1227 else if (usb2->mode == USB_DR_MODE_OTG)
1228 value |= (PORT_CAP_OTG << PORTX_CAP_SHIFT(index));
1229
1230 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CAP);
1231
1232 if (padctl->soc->supports_gen2 && port->disable_gen2) {
1233 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CFG);
1234 value &= ~(PORTX_SPEED_SUPPORT_MASK <<
1235 PORTX_SPEED_SUPPORT_SHIFT(index));
1236 value |= (PORT_SPEED_SUPPORT_GEN1 <<
1237 PORTX_SPEED_SUPPORT_SHIFT(index));
1238 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CFG);
1239 }
1240
1241 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1242 value &= ~SSPX_ELPG_VCORE_DOWN(index);
1243 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1244
1245 usleep_range(100, 200);
1246
1247 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1248 value &= ~SSPX_ELPG_CLAMP_EN_EARLY(index);
1249 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1250
1251 usleep_range(100, 200);
1252
1253 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1254 value &= ~SSPX_ELPG_CLAMP_EN(index);
1255 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1256
1257 mutex_unlock(&padctl->lock);
1258
1259 return 0;
1260}
1261
1262static int tegra186_usb3_phy_power_off(struct phy *phy)
1263{
1264 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1265 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1266 struct tegra_xusb_usb3_port *port;
1267 unsigned int index = lane->index;
1268 struct device *dev = padctl->dev;
1269 u32 value;
1270
1271 port = tegra_xusb_find_usb3_port(padctl, index);
1272 if (!port) {
1273 dev_err(dev, "no port found for USB3 lane %u\n", index);
1274 return -ENODEV;
1275 }
1276
1277 mutex_lock(&padctl->lock);
1278
1279 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1280 value |= SSPX_ELPG_CLAMP_EN_EARLY(index);
1281 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1282
1283 usleep_range(100, 200);
1284
1285 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1286 value |= SSPX_ELPG_CLAMP_EN(index);
1287 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1288
1289 usleep_range(250, 350);
1290
1291 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1292 value |= SSPX_ELPG_VCORE_DOWN(index);
1293 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1294
1295 mutex_unlock(&padctl->lock);
1296
1297 return 0;
1298}
1299
1300static int tegra186_usb3_phy_init(struct phy *phy)
1301{
1302 return 0;
1303}
1304
1305static int tegra186_usb3_phy_exit(struct phy *phy)
1306{
1307 return 0;
1308}
1309
1310static const struct phy_ops usb3_phy_ops = {
1311 .init = tegra186_usb3_phy_init,
1312 .exit = tegra186_usb3_phy_exit,
1313 .power_on = tegra186_usb3_phy_power_on,
1314 .power_off = tegra186_usb3_phy_power_off,
1315 .owner = THIS_MODULE,
1316};
1317
1318static struct tegra_xusb_pad *
1319tegra186_usb3_pad_probe(struct tegra_xusb_padctl *padctl,
1320 const struct tegra_xusb_pad_soc *soc,
1321 struct device_node *np)
1322{
1323 struct tegra_xusb_usb3_pad *usb3;
1324 struct tegra_xusb_pad *pad;
1325 int err;
1326
1327 usb3 = kzalloc(sizeof(*usb3), GFP_KERNEL);
1328 if (!usb3)
1329 return ERR_PTR(-ENOMEM);
1330
1331 pad = &usb3->base;
1332 pad->ops = &tegra186_usb3_lane_ops;
1333 pad->soc = soc;
1334
1335 err = tegra_xusb_pad_init(pad, padctl, np);
1336 if (err < 0) {
1337 kfree(usb3);
1338 goto out;
1339 }
1340
1341 err = tegra_xusb_pad_register(pad, &usb3_phy_ops);
1342 if (err < 0)
1343 goto unregister;
1344
1345 dev_set_drvdata(&pad->dev, pad);
1346
1347 return pad;
1348
1349unregister:
1350 device_unregister(&pad->dev);
1351out:
1352 return ERR_PTR(err);
1353}
1354
1355static void tegra186_usb3_pad_remove(struct tegra_xusb_pad *pad)
1356{
1357 struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad);
1358
1359 kfree(usb2);
1360}
1361
1362static const struct tegra_xusb_pad_ops tegra186_usb3_pad_ops = {
1363 .probe = tegra186_usb3_pad_probe,
1364 .remove = tegra186_usb3_pad_remove,
1365};
1366
1367static const char * const tegra186_usb3_functions[] = {
1368 "xusb",
1369};
1370
1371static int
1372tegra186_xusb_read_fuse_calibration(struct tegra186_xusb_padctl *padctl)
1373{
1374 struct device *dev = padctl->base.dev;
1375 unsigned int i, count;
1376 u32 value, *level;
1377 int err;
1378
1379 count = padctl->base.soc->ports.usb2.count;
1380
1381 level = devm_kcalloc(dev, count, sizeof(u32), GFP_KERNEL);
1382 if (!level)
1383 return -ENOMEM;
1384
1385 err = tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0, &value);
1386 if (err)
1387 return dev_err_probe(dev, err,
1388 "failed to read calibration fuse\n");
1389
1390 dev_dbg(dev, "FUSE_USB_CALIB_0 %#x\n", value);
1391
1392 for (i = 0; i < count; i++)
1393 level[i] = (value >> HS_CURR_LEVEL_PADX_SHIFT(i)) &
1394 HS_CURR_LEVEL_PAD_MASK;
1395
1396 padctl->calib.hs_curr_level = level;
1397
1398 padctl->calib.hs_squelch = (value >> HS_SQUELCH_SHIFT) &
1399 HS_SQUELCH_MASK;
1400 padctl->calib.hs_term_range_adj = (value >> HS_TERM_RANGE_ADJ_SHIFT) &
1401 HS_TERM_RANGE_ADJ_MASK;
1402
1403 err = tegra_fuse_readl(TEGRA_FUSE_USB_CALIB_EXT_0, &value);
1404 if (err) {
1405 dev_err(dev, "failed to read calibration fuse: %d\n", err);
1406 return err;
1407 }
1408
1409 dev_dbg(dev, "FUSE_USB_CALIB_EXT_0 %#x\n", value);
1410
1411 padctl->calib.rpd_ctrl = (value >> RPD_CTRL_SHIFT) & RPD_CTRL_MASK;
1412
1413 return 0;
1414}
1415
1416static struct tegra_xusb_padctl *
1417tegra186_xusb_padctl_probe(struct device *dev,
1418 const struct tegra_xusb_padctl_soc *soc)
1419{
1420 struct platform_device *pdev = to_platform_device(dev);
1421 struct tegra186_xusb_padctl *priv;
1422 struct resource *res;
1423 int err;
1424
1425 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1426 if (!priv)
1427 return ERR_PTR(-ENOMEM);
1428
1429 priv->base.dev = dev;
1430 priv->base.soc = soc;
1431
1432 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ao");
1433 priv->ao_regs = devm_ioremap_resource(dev, res);
1434 if (IS_ERR(priv->ao_regs))
1435 return ERR_CAST(priv->ao_regs);
1436
1437 err = tegra186_xusb_read_fuse_calibration(priv);
1438 if (err < 0)
1439 return ERR_PTR(err);
1440
1441 return &priv->base;
1442}
1443
1444static void tegra186_xusb_padctl_save(struct tegra_xusb_padctl *padctl)
1445{
1446 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
1447
1448 priv->context.vbus_id = padctl_readl(padctl, USB2_VBUS_ID);
1449 priv->context.usb2_pad_mux = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
1450 priv->context.usb2_port_cap = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
1451 priv->context.ss_port_cap = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CAP);
1452}
1453
1454static void tegra186_xusb_padctl_restore(struct tegra_xusb_padctl *padctl)
1455{
1456 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
1457
1458 padctl_writel(padctl, priv->context.usb2_pad_mux, XUSB_PADCTL_USB2_PAD_MUX);
1459 padctl_writel(padctl, priv->context.usb2_port_cap, XUSB_PADCTL_USB2_PORT_CAP);
1460 padctl_writel(padctl, priv->context.ss_port_cap, XUSB_PADCTL_SS_PORT_CAP);
1461 padctl_writel(padctl, priv->context.vbus_id, USB2_VBUS_ID);
1462}
1463
1464static int tegra186_xusb_padctl_suspend_noirq(struct tegra_xusb_padctl *padctl)
1465{
1466 tegra186_xusb_padctl_save(padctl);
1467
1468 return 0;
1469}
1470
1471static int tegra186_xusb_padctl_resume_noirq(struct tegra_xusb_padctl *padctl)
1472{
1473 tegra186_xusb_padctl_restore(padctl);
1474
1475 return 0;
1476}
1477
1478static void tegra186_xusb_padctl_remove(struct tegra_xusb_padctl *padctl)
1479{
1480}
1481
1482static const struct tegra_xusb_padctl_ops tegra186_xusb_padctl_ops = {
1483 .probe = tegra186_xusb_padctl_probe,
1484 .remove = tegra186_xusb_padctl_remove,
1485 .suspend_noirq = tegra186_xusb_padctl_suspend_noirq,
1486 .resume_noirq = tegra186_xusb_padctl_resume_noirq,
1487 .vbus_override = tegra186_xusb_padctl_vbus_override,
1488 .utmi_pad_power_on = tegra186_utmi_pad_power_on,
1489 .utmi_pad_power_down = tegra186_utmi_pad_power_down,
1490};
1491
1492#if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
1493static const char * const tegra186_xusb_padctl_supply_names[] = {
1494 "avdd-pll-erefeut",
1495 "avdd-usb",
1496 "vclamp-usb",
1497 "vddio-hsic",
1498};
1499
1500static const struct tegra_xusb_lane_soc tegra186_usb2_lanes[] = {
1501 TEGRA186_LANE("usb2-0", 0, 0, 0, usb2),
1502 TEGRA186_LANE("usb2-1", 0, 0, 0, usb2),
1503 TEGRA186_LANE("usb2-2", 0, 0, 0, usb2),
1504};
1505
1506static const struct tegra_xusb_pad_soc tegra186_usb2_pad = {
1507 .name = "usb2",
1508 .num_lanes = ARRAY_SIZE(tegra186_usb2_lanes),
1509 .lanes = tegra186_usb2_lanes,
1510 .ops = &tegra186_usb2_pad_ops,
1511};
1512
1513static const struct tegra_xusb_lane_soc tegra186_usb3_lanes[] = {
1514 TEGRA186_LANE("usb3-0", 0, 0, 0, usb3),
1515 TEGRA186_LANE("usb3-1", 0, 0, 0, usb3),
1516 TEGRA186_LANE("usb3-2", 0, 0, 0, usb3),
1517};
1518
1519static const struct tegra_xusb_pad_soc tegra186_usb3_pad = {
1520 .name = "usb3",
1521 .num_lanes = ARRAY_SIZE(tegra186_usb3_lanes),
1522 .lanes = tegra186_usb3_lanes,
1523 .ops = &tegra186_usb3_pad_ops,
1524};
1525
1526static const struct tegra_xusb_pad_soc * const tegra186_pads[] = {
1527 &tegra186_usb2_pad,
1528 &tegra186_usb3_pad,
1529#if 0 /* TODO implement */
1530 &tegra186_hsic_pad,
1531#endif
1532};
1533
1534const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc = {
1535 .num_pads = ARRAY_SIZE(tegra186_pads),
1536 .pads = tegra186_pads,
1537 .ports = {
1538 .usb2 = {
1539 .ops = &tegra186_usb2_port_ops,
1540 .count = 3,
1541 },
1542#if 0 /* TODO implement */
1543 .hsic = {
1544 .ops = &tegra186_hsic_port_ops,
1545 .count = 1,
1546 },
1547#endif
1548 .usb3 = {
1549 .ops = &tegra186_usb3_port_ops,
1550 .count = 3,
1551 },
1552 },
1553 .ops = &tegra186_xusb_padctl_ops,
1554 .supply_names = tegra186_xusb_padctl_supply_names,
1555 .num_supplies = ARRAY_SIZE(tegra186_xusb_padctl_supply_names),
1556};
1557EXPORT_SYMBOL_GPL(tegra186_xusb_padctl_soc);
1558#endif
1559
1560#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC)
1561static const char * const tegra194_xusb_padctl_supply_names[] = {
1562 "avdd-usb",
1563 "vclamp-usb",
1564};
1565
1566static const struct tegra_xusb_lane_soc tegra194_usb2_lanes[] = {
1567 TEGRA186_LANE("usb2-0", 0, 0, 0, usb2),
1568 TEGRA186_LANE("usb2-1", 0, 0, 0, usb2),
1569 TEGRA186_LANE("usb2-2", 0, 0, 0, usb2),
1570 TEGRA186_LANE("usb2-3", 0, 0, 0, usb2),
1571};
1572
1573static const struct tegra_xusb_pad_soc tegra194_usb2_pad = {
1574 .name = "usb2",
1575 .num_lanes = ARRAY_SIZE(tegra194_usb2_lanes),
1576 .lanes = tegra194_usb2_lanes,
1577 .ops = &tegra186_usb2_pad_ops,
1578};
1579
1580static const struct tegra_xusb_lane_soc tegra194_usb3_lanes[] = {
1581 TEGRA186_LANE("usb3-0", 0, 0, 0, usb3),
1582 TEGRA186_LANE("usb3-1", 0, 0, 0, usb3),
1583 TEGRA186_LANE("usb3-2", 0, 0, 0, usb3),
1584 TEGRA186_LANE("usb3-3", 0, 0, 0, usb3),
1585};
1586
1587static const struct tegra_xusb_pad_soc tegra194_usb3_pad = {
1588 .name = "usb3",
1589 .num_lanes = ARRAY_SIZE(tegra194_usb3_lanes),
1590 .lanes = tegra194_usb3_lanes,
1591 .ops = &tegra186_usb3_pad_ops,
1592};
1593
1594static const struct tegra_xusb_pad_soc * const tegra194_pads[] = {
1595 &tegra194_usb2_pad,
1596 &tegra194_usb3_pad,
1597};
1598
1599const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc = {
1600 .num_pads = ARRAY_SIZE(tegra194_pads),
1601 .pads = tegra194_pads,
1602 .ports = {
1603 .usb2 = {
1604 .ops = &tegra186_usb2_port_ops,
1605 .count = 4,
1606 },
1607 .usb3 = {
1608 .ops = &tegra186_usb3_port_ops,
1609 .count = 4,
1610 },
1611 },
1612 .ops = &tegra186_xusb_padctl_ops,
1613 .supply_names = tegra194_xusb_padctl_supply_names,
1614 .num_supplies = ARRAY_SIZE(tegra194_xusb_padctl_supply_names),
1615 .supports_gen2 = true,
1616};
1617EXPORT_SYMBOL_GPL(tegra194_xusb_padctl_soc);
1618#endif
1619
1620MODULE_AUTHOR("JC Kuo <jckuo@nvidia.com>");
1621MODULE_DESCRIPTION("NVIDIA Tegra186 XUSB Pad Controller driver");
1622MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
4 */
5
6#include <linux/delay.h>
7#include <linux/io.h>
8#include <linux/module.h>
9#include <linux/of.h>
10#include <linux/phy/phy.h>
11#include <linux/regulator/consumer.h>
12#include <linux/platform_device.h>
13#include <linux/clk.h>
14#include <linux/slab.h>
15
16#include <soc/tegra/fuse.h>
17
18#include "xusb.h"
19
20/* FUSE USB_CALIB registers */
21#define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
22#define HS_CURR_LEVEL_PAD_MASK 0x3f
23#define HS_TERM_RANGE_ADJ_SHIFT 7
24#define HS_TERM_RANGE_ADJ_MASK 0xf
25#define HS_SQUELCH_SHIFT 29
26#define HS_SQUELCH_MASK 0x7
27
28#define RPD_CTRL_SHIFT 0
29#define RPD_CTRL_MASK 0x1f
30
31/* XUSB PADCTL registers */
32#define XUSB_PADCTL_USB2_PAD_MUX 0x4
33#define USB2_PORT_SHIFT(x) ((x) * 2)
34#define USB2_PORT_MASK 0x3
35#define PORT_XUSB 1
36#define HSIC_PORT_SHIFT(x) ((x) + 20)
37#define HSIC_PORT_MASK 0x1
38#define PORT_HSIC 0
39
40#define XUSB_PADCTL_USB2_PORT_CAP 0x8
41#define XUSB_PADCTL_SS_PORT_CAP 0xc
42#define PORTX_CAP_SHIFT(x) ((x) * 4)
43#define PORT_CAP_MASK 0x3
44#define PORT_CAP_DISABLED 0x0
45#define PORT_CAP_HOST 0x1
46#define PORT_CAP_DEVICE 0x2
47#define PORT_CAP_OTG 0x3
48
49#define XUSB_PADCTL_ELPG_PROGRAM 0x20
50#define USB2_PORT_WAKE_INTERRUPT_ENABLE(x) BIT(x)
51#define USB2_PORT_WAKEUP_EVENT(x) BIT((x) + 7)
52#define SS_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 14)
53#define SS_PORT_WAKEUP_EVENT(x) BIT((x) + 21)
54#define USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 28)
55#define USB2_HSIC_PORT_WAKEUP_EVENT(x) BIT((x) + 30)
56#define ALL_WAKE_EVENTS \
57 (USB2_PORT_WAKEUP_EVENT(0) | USB2_PORT_WAKEUP_EVENT(1) | \
58 USB2_PORT_WAKEUP_EVENT(2) | SS_PORT_WAKEUP_EVENT(0) | \
59 SS_PORT_WAKEUP_EVENT(1) | SS_PORT_WAKEUP_EVENT(2) | \
60 USB2_HSIC_PORT_WAKEUP_EVENT(0))
61
62#define XUSB_PADCTL_ELPG_PROGRAM_1 0x24
63#define SSPX_ELPG_CLAMP_EN(x) BIT(0 + (x) * 3)
64#define SSPX_ELPG_CLAMP_EN_EARLY(x) BIT(1 + (x) * 3)
65#define SSPX_ELPG_VCORE_DOWN(x) BIT(2 + (x) * 3)
66#define XUSB_PADCTL_SS_PORT_CFG 0x2c
67#define PORTX_SPEED_SUPPORT_SHIFT(x) ((x) * 4)
68#define PORTX_SPEED_SUPPORT_MASK (0x3)
69#define PORT_SPEED_SUPPORT_GEN1 (0x0)
70
71#define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x88 + (x) * 0x40)
72#define HS_CURR_LEVEL(x) ((x) & 0x3f)
73#define TERM_SEL BIT(25)
74#define USB2_OTG_PD BIT(26)
75#define USB2_OTG_PD2 BIT(27)
76#define USB2_OTG_PD2_OVRD_EN BIT(28)
77#define USB2_OTG_PD_ZI BIT(29)
78
79#define XUSB_PADCTL_USB2_OTG_PADX_CTL1(x) (0x8c + (x) * 0x40)
80#define USB2_OTG_PD_DR BIT(2)
81#define TERM_RANGE_ADJ(x) (((x) & 0xf) << 3)
82#define RPD_CTRL(x) (((x) & 0x1f) << 26)
83
84#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x284
85#define BIAS_PAD_PD BIT(11)
86#define HS_SQUELCH_LEVEL(x) (((x) & 0x7) << 0)
87
88#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1 0x288
89#define USB2_TRK_START_TIMER(x) (((x) & 0x7f) << 12)
90#define USB2_TRK_DONE_RESET_TIMER(x) (((x) & 0x7f) << 19)
91#define USB2_PD_TRK BIT(26)
92
93#define XUSB_PADCTL_HSIC_PADX_CTL0(x) (0x300 + (x) * 0x20)
94#define HSIC_PD_TX_DATA0 BIT(1)
95#define HSIC_PD_TX_STROBE BIT(3)
96#define HSIC_PD_RX_DATA0 BIT(4)
97#define HSIC_PD_RX_STROBE BIT(6)
98#define HSIC_PD_ZI_DATA0 BIT(7)
99#define HSIC_PD_ZI_STROBE BIT(9)
100#define HSIC_RPD_DATA0 BIT(13)
101#define HSIC_RPD_STROBE BIT(15)
102#define HSIC_RPU_DATA0 BIT(16)
103#define HSIC_RPU_STROBE BIT(18)
104
105#define XUSB_PADCTL_HSIC_PAD_TRK_CTL0 0x340
106#define HSIC_TRK_START_TIMER(x) (((x) & 0x7f) << 5)
107#define HSIC_TRK_DONE_RESET_TIMER(x) (((x) & 0x7f) << 12)
108#define HSIC_PD_TRK BIT(19)
109
110#define USB2_VBUS_ID 0x360
111#define VBUS_OVERRIDE BIT(14)
112#define ID_OVERRIDE(x) (((x) & 0xf) << 18)
113#define ID_OVERRIDE_FLOATING ID_OVERRIDE(8)
114#define ID_OVERRIDE_GROUNDED ID_OVERRIDE(0)
115
116#define TEGRA186_LANE(_name, _offset, _shift, _mask, _type) \
117 { \
118 .name = _name, \
119 .offset = _offset, \
120 .shift = _shift, \
121 .mask = _mask, \
122 .num_funcs = ARRAY_SIZE(tegra186_##_type##_functions), \
123 .funcs = tegra186_##_type##_functions, \
124 }
125
126struct tegra_xusb_fuse_calibration {
127 u32 *hs_curr_level;
128 u32 hs_squelch;
129 u32 hs_term_range_adj;
130 u32 rpd_ctrl;
131};
132
133struct tegra186_xusb_padctl {
134 struct tegra_xusb_padctl base;
135
136 struct tegra_xusb_fuse_calibration calib;
137
138 /* UTMI bias and tracking */
139 struct clk *usb2_trk_clk;
140 unsigned int bias_pad_enable;
141};
142
143static inline struct tegra186_xusb_padctl *
144to_tegra186_xusb_padctl(struct tegra_xusb_padctl *padctl)
145{
146 return container_of(padctl, struct tegra186_xusb_padctl, base);
147}
148
149/* USB 2.0 UTMI PHY support */
150static struct tegra_xusb_lane *
151tegra186_usb2_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
152 unsigned int index)
153{
154 struct tegra_xusb_usb2_lane *usb2;
155 int err;
156
157 usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);
158 if (!usb2)
159 return ERR_PTR(-ENOMEM);
160
161 INIT_LIST_HEAD(&usb2->base.list);
162 usb2->base.soc = &pad->soc->lanes[index];
163 usb2->base.index = index;
164 usb2->base.pad = pad;
165 usb2->base.np = np;
166
167 err = tegra_xusb_lane_parse_dt(&usb2->base, np);
168 if (err < 0) {
169 kfree(usb2);
170 return ERR_PTR(err);
171 }
172
173 return &usb2->base;
174}
175
176static void tegra186_usb2_lane_remove(struct tegra_xusb_lane *lane)
177{
178 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
179
180 kfree(usb2);
181}
182
183static const struct tegra_xusb_lane_ops tegra186_usb2_lane_ops = {
184 .probe = tegra186_usb2_lane_probe,
185 .remove = tegra186_usb2_lane_remove,
186};
187
188static void tegra186_utmi_bias_pad_power_on(struct tegra_xusb_padctl *padctl)
189{
190 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
191 struct device *dev = padctl->dev;
192 u32 value;
193 int err;
194
195 mutex_lock(&padctl->lock);
196
197 if (priv->bias_pad_enable++ > 0) {
198 mutex_unlock(&padctl->lock);
199 return;
200 }
201
202 err = clk_prepare_enable(priv->usb2_trk_clk);
203 if (err < 0)
204 dev_warn(dev, "failed to enable USB2 trk clock: %d\n", err);
205
206 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
207 value &= ~USB2_TRK_START_TIMER(~0);
208 value |= USB2_TRK_START_TIMER(0x1e);
209 value &= ~USB2_TRK_DONE_RESET_TIMER(~0);
210 value |= USB2_TRK_DONE_RESET_TIMER(0xa);
211 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
212
213 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
214 value &= ~BIAS_PAD_PD;
215 value &= ~HS_SQUELCH_LEVEL(~0);
216 value |= HS_SQUELCH_LEVEL(priv->calib.hs_squelch);
217 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
218
219 udelay(1);
220
221 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
222 value &= ~USB2_PD_TRK;
223 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
224
225 mutex_unlock(&padctl->lock);
226}
227
228static void tegra186_utmi_bias_pad_power_off(struct tegra_xusb_padctl *padctl)
229{
230 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
231 u32 value;
232
233 mutex_lock(&padctl->lock);
234
235 if (WARN_ON(priv->bias_pad_enable == 0)) {
236 mutex_unlock(&padctl->lock);
237 return;
238 }
239
240 if (--priv->bias_pad_enable > 0) {
241 mutex_unlock(&padctl->lock);
242 return;
243 }
244
245 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
246 value |= USB2_PD_TRK;
247 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
248
249 clk_disable_unprepare(priv->usb2_trk_clk);
250
251 mutex_unlock(&padctl->lock);
252}
253
254static void tegra_phy_xusb_utmi_pad_power_on(struct phy *phy)
255{
256 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
257 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
258 struct tegra_xusb_usb2_port *port;
259 struct device *dev = padctl->dev;
260 unsigned int index = lane->index;
261 u32 value;
262
263 if (!phy)
264 return;
265
266 port = tegra_xusb_find_usb2_port(padctl, index);
267 if (!port) {
268 dev_err(dev, "no port found for USB2 lane %u\n", index);
269 return;
270 }
271
272 tegra186_utmi_bias_pad_power_on(padctl);
273
274 udelay(2);
275
276 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
277 value &= ~USB2_OTG_PD;
278 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
279
280 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
281 value &= ~USB2_OTG_PD_DR;
282 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
283}
284
285static void tegra_phy_xusb_utmi_pad_power_down(struct phy *phy)
286{
287 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
288 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
289 unsigned int index = lane->index;
290 u32 value;
291
292 if (!phy)
293 return;
294
295 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
296 value |= USB2_OTG_PD;
297 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
298
299 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
300 value |= USB2_OTG_PD_DR;
301 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
302
303 udelay(2);
304
305 tegra186_utmi_bias_pad_power_off(padctl);
306}
307
308static int tegra186_xusb_padctl_vbus_override(struct tegra_xusb_padctl *padctl,
309 bool status)
310{
311 u32 value;
312
313 dev_dbg(padctl->dev, "%s vbus override\n", status ? "set" : "clear");
314
315 value = padctl_readl(padctl, USB2_VBUS_ID);
316
317 if (status) {
318 value |= VBUS_OVERRIDE;
319 value &= ~ID_OVERRIDE(~0);
320 value |= ID_OVERRIDE_FLOATING;
321 } else {
322 value &= ~VBUS_OVERRIDE;
323 }
324
325 padctl_writel(padctl, value, USB2_VBUS_ID);
326
327 return 0;
328}
329
330static int tegra186_xusb_padctl_id_override(struct tegra_xusb_padctl *padctl,
331 bool status)
332{
333 u32 value;
334
335 dev_dbg(padctl->dev, "%s id override\n", status ? "set" : "clear");
336
337 value = padctl_readl(padctl, USB2_VBUS_ID);
338
339 if (status) {
340 if (value & VBUS_OVERRIDE) {
341 value &= ~VBUS_OVERRIDE;
342 padctl_writel(padctl, value, USB2_VBUS_ID);
343 usleep_range(1000, 2000);
344
345 value = padctl_readl(padctl, USB2_VBUS_ID);
346 }
347
348 value &= ~ID_OVERRIDE(~0);
349 value |= ID_OVERRIDE_GROUNDED;
350 } else {
351 value &= ~ID_OVERRIDE(~0);
352 value |= ID_OVERRIDE_FLOATING;
353 }
354
355 padctl_writel(padctl, value, USB2_VBUS_ID);
356
357 return 0;
358}
359
360static int tegra186_utmi_phy_set_mode(struct phy *phy, enum phy_mode mode,
361 int submode)
362{
363 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
364 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
365 struct tegra_xusb_usb2_port *port = tegra_xusb_find_usb2_port(padctl,
366 lane->index);
367 int err = 0;
368
369 mutex_lock(&padctl->lock);
370
371 dev_dbg(&port->base.dev, "%s: mode %d", __func__, mode);
372
373 if (mode == PHY_MODE_USB_OTG) {
374 if (submode == USB_ROLE_HOST) {
375 tegra186_xusb_padctl_id_override(padctl, true);
376
377 err = regulator_enable(port->supply);
378 } else if (submode == USB_ROLE_DEVICE) {
379 tegra186_xusb_padctl_vbus_override(padctl, true);
380 } else if (submode == USB_ROLE_NONE) {
381 /*
382 * When port is peripheral only or role transitions to
383 * USB_ROLE_NONE from USB_ROLE_DEVICE, regulator is not
384 * enabled.
385 */
386 if (regulator_is_enabled(port->supply))
387 regulator_disable(port->supply);
388
389 tegra186_xusb_padctl_id_override(padctl, false);
390 tegra186_xusb_padctl_vbus_override(padctl, false);
391 }
392 }
393
394 mutex_unlock(&padctl->lock);
395
396 return err;
397}
398
399static int tegra186_utmi_phy_power_on(struct phy *phy)
400{
401 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
402 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
403 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
404 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
405 struct tegra_xusb_usb2_port *port;
406 unsigned int index = lane->index;
407 struct device *dev = padctl->dev;
408 u32 value;
409
410 port = tegra_xusb_find_usb2_port(padctl, index);
411 if (!port) {
412 dev_err(dev, "no port found for USB2 lane %u\n", index);
413 return -ENODEV;
414 }
415
416 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
417 value &= ~(USB2_PORT_MASK << USB2_PORT_SHIFT(index));
418 value |= (PORT_XUSB << USB2_PORT_SHIFT(index));
419 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX);
420
421 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
422 value &= ~(PORT_CAP_MASK << PORTX_CAP_SHIFT(index));
423
424 if (port->mode == USB_DR_MODE_UNKNOWN)
425 value |= (PORT_CAP_DISABLED << PORTX_CAP_SHIFT(index));
426 else if (port->mode == USB_DR_MODE_PERIPHERAL)
427 value |= (PORT_CAP_DEVICE << PORTX_CAP_SHIFT(index));
428 else if (port->mode == USB_DR_MODE_HOST)
429 value |= (PORT_CAP_HOST << PORTX_CAP_SHIFT(index));
430 else if (port->mode == USB_DR_MODE_OTG)
431 value |= (PORT_CAP_OTG << PORTX_CAP_SHIFT(index));
432
433 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP);
434
435 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
436 value &= ~USB2_OTG_PD_ZI;
437 value |= TERM_SEL;
438 value &= ~HS_CURR_LEVEL(~0);
439
440 if (usb2->hs_curr_level_offset) {
441 int hs_current_level;
442
443 hs_current_level = (int)priv->calib.hs_curr_level[index] +
444 usb2->hs_curr_level_offset;
445
446 if (hs_current_level < 0)
447 hs_current_level = 0;
448 if (hs_current_level > 0x3f)
449 hs_current_level = 0x3f;
450
451 value |= HS_CURR_LEVEL(hs_current_level);
452 } else {
453 value |= HS_CURR_LEVEL(priv->calib.hs_curr_level[index]);
454 }
455
456 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
457
458 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
459 value &= ~TERM_RANGE_ADJ(~0);
460 value |= TERM_RANGE_ADJ(priv->calib.hs_term_range_adj);
461 value &= ~RPD_CTRL(~0);
462 value |= RPD_CTRL(priv->calib.rpd_ctrl);
463 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
464
465 /* TODO: pad power saving */
466 tegra_phy_xusb_utmi_pad_power_on(phy);
467 return 0;
468}
469
470static int tegra186_utmi_phy_power_off(struct phy *phy)
471{
472 /* TODO: pad power saving */
473 tegra_phy_xusb_utmi_pad_power_down(phy);
474
475 return 0;
476}
477
478static int tegra186_utmi_phy_init(struct phy *phy)
479{
480 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
481 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
482 struct tegra_xusb_usb2_port *port;
483 unsigned int index = lane->index;
484 struct device *dev = padctl->dev;
485 int err;
486
487 port = tegra_xusb_find_usb2_port(padctl, index);
488 if (!port) {
489 dev_err(dev, "no port found for USB2 lane %u\n", index);
490 return -ENODEV;
491 }
492
493 if (port->supply && port->mode == USB_DR_MODE_HOST) {
494 err = regulator_enable(port->supply);
495 if (err) {
496 dev_err(dev, "failed to enable port %u VBUS: %d\n",
497 index, err);
498 return err;
499 }
500 }
501
502 return 0;
503}
504
505static int tegra186_utmi_phy_exit(struct phy *phy)
506{
507 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
508 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
509 struct tegra_xusb_usb2_port *port;
510 unsigned int index = lane->index;
511 struct device *dev = padctl->dev;
512 int err;
513
514 port = tegra_xusb_find_usb2_port(padctl, index);
515 if (!port) {
516 dev_err(dev, "no port found for USB2 lane %u\n", index);
517 return -ENODEV;
518 }
519
520 if (port->supply && port->mode == USB_DR_MODE_HOST) {
521 err = regulator_disable(port->supply);
522 if (err) {
523 dev_err(dev, "failed to disable port %u VBUS: %d\n",
524 index, err);
525 return err;
526 }
527 }
528
529 return 0;
530}
531
532static const struct phy_ops utmi_phy_ops = {
533 .init = tegra186_utmi_phy_init,
534 .exit = tegra186_utmi_phy_exit,
535 .power_on = tegra186_utmi_phy_power_on,
536 .power_off = tegra186_utmi_phy_power_off,
537 .set_mode = tegra186_utmi_phy_set_mode,
538 .owner = THIS_MODULE,
539};
540
541static struct tegra_xusb_pad *
542tegra186_usb2_pad_probe(struct tegra_xusb_padctl *padctl,
543 const struct tegra_xusb_pad_soc *soc,
544 struct device_node *np)
545{
546 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
547 struct tegra_xusb_usb2_pad *usb2;
548 struct tegra_xusb_pad *pad;
549 int err;
550
551 usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);
552 if (!usb2)
553 return ERR_PTR(-ENOMEM);
554
555 pad = &usb2->base;
556 pad->ops = &tegra186_usb2_lane_ops;
557 pad->soc = soc;
558
559 err = tegra_xusb_pad_init(pad, padctl, np);
560 if (err < 0) {
561 kfree(usb2);
562 goto out;
563 }
564
565 priv->usb2_trk_clk = devm_clk_get(&pad->dev, "trk");
566 if (IS_ERR(priv->usb2_trk_clk)) {
567 err = PTR_ERR(priv->usb2_trk_clk);
568 dev_dbg(&pad->dev, "failed to get usb2 trk clock: %d\n", err);
569 goto unregister;
570 }
571
572 err = tegra_xusb_pad_register(pad, &utmi_phy_ops);
573 if (err < 0)
574 goto unregister;
575
576 dev_set_drvdata(&pad->dev, pad);
577
578 return pad;
579
580unregister:
581 device_unregister(&pad->dev);
582out:
583 return ERR_PTR(err);
584}
585
586static void tegra186_usb2_pad_remove(struct tegra_xusb_pad *pad)
587{
588 struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad);
589
590 kfree(usb2);
591}
592
593static const struct tegra_xusb_pad_ops tegra186_usb2_pad_ops = {
594 .probe = tegra186_usb2_pad_probe,
595 .remove = tegra186_usb2_pad_remove,
596};
597
598static const char * const tegra186_usb2_functions[] = {
599 "xusb",
600};
601
602static int tegra186_usb2_port_enable(struct tegra_xusb_port *port)
603{
604 return 0;
605}
606
607static void tegra186_usb2_port_disable(struct tegra_xusb_port *port)
608{
609}
610
611static struct tegra_xusb_lane *
612tegra186_usb2_port_map(struct tegra_xusb_port *port)
613{
614 return tegra_xusb_find_lane(port->padctl, "usb2", port->index);
615}
616
617static const struct tegra_xusb_port_ops tegra186_usb2_port_ops = {
618 .release = tegra_xusb_usb2_port_release,
619 .remove = tegra_xusb_usb2_port_remove,
620 .enable = tegra186_usb2_port_enable,
621 .disable = tegra186_usb2_port_disable,
622 .map = tegra186_usb2_port_map,
623};
624
625/* SuperSpeed PHY support */
626static struct tegra_xusb_lane *
627tegra186_usb3_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
628 unsigned int index)
629{
630 struct tegra_xusb_usb3_lane *usb3;
631 int err;
632
633 usb3 = kzalloc(sizeof(*usb3), GFP_KERNEL);
634 if (!usb3)
635 return ERR_PTR(-ENOMEM);
636
637 INIT_LIST_HEAD(&usb3->base.list);
638 usb3->base.soc = &pad->soc->lanes[index];
639 usb3->base.index = index;
640 usb3->base.pad = pad;
641 usb3->base.np = np;
642
643 err = tegra_xusb_lane_parse_dt(&usb3->base, np);
644 if (err < 0) {
645 kfree(usb3);
646 return ERR_PTR(err);
647 }
648
649 return &usb3->base;
650}
651
652static void tegra186_usb3_lane_remove(struct tegra_xusb_lane *lane)
653{
654 struct tegra_xusb_usb3_lane *usb3 = to_usb3_lane(lane);
655
656 kfree(usb3);
657}
658
659static const struct tegra_xusb_lane_ops tegra186_usb3_lane_ops = {
660 .probe = tegra186_usb3_lane_probe,
661 .remove = tegra186_usb3_lane_remove,
662};
663static int tegra186_usb3_port_enable(struct tegra_xusb_port *port)
664{
665 return 0;
666}
667
668static void tegra186_usb3_port_disable(struct tegra_xusb_port *port)
669{
670}
671
672static struct tegra_xusb_lane *
673tegra186_usb3_port_map(struct tegra_xusb_port *port)
674{
675 return tegra_xusb_find_lane(port->padctl, "usb3", port->index);
676}
677
678static const struct tegra_xusb_port_ops tegra186_usb3_port_ops = {
679 .release = tegra_xusb_usb3_port_release,
680 .remove = tegra_xusb_usb3_port_remove,
681 .enable = tegra186_usb3_port_enable,
682 .disable = tegra186_usb3_port_disable,
683 .map = tegra186_usb3_port_map,
684};
685
686static int tegra186_usb3_phy_power_on(struct phy *phy)
687{
688 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
689 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
690 struct tegra_xusb_usb3_port *port;
691 struct tegra_xusb_usb2_port *usb2;
692 unsigned int index = lane->index;
693 struct device *dev = padctl->dev;
694 u32 value;
695
696 port = tegra_xusb_find_usb3_port(padctl, index);
697 if (!port) {
698 dev_err(dev, "no port found for USB3 lane %u\n", index);
699 return -ENODEV;
700 }
701
702 usb2 = tegra_xusb_find_usb2_port(padctl, port->port);
703 if (!usb2) {
704 dev_err(dev, "no companion port found for USB3 lane %u\n",
705 index);
706 return -ENODEV;
707 }
708
709 mutex_lock(&padctl->lock);
710
711 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CAP);
712 value &= ~(PORT_CAP_MASK << PORTX_CAP_SHIFT(index));
713
714 if (usb2->mode == USB_DR_MODE_UNKNOWN)
715 value |= (PORT_CAP_DISABLED << PORTX_CAP_SHIFT(index));
716 else if (usb2->mode == USB_DR_MODE_PERIPHERAL)
717 value |= (PORT_CAP_DEVICE << PORTX_CAP_SHIFT(index));
718 else if (usb2->mode == USB_DR_MODE_HOST)
719 value |= (PORT_CAP_HOST << PORTX_CAP_SHIFT(index));
720 else if (usb2->mode == USB_DR_MODE_OTG)
721 value |= (PORT_CAP_OTG << PORTX_CAP_SHIFT(index));
722
723 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CAP);
724
725 if (padctl->soc->supports_gen2 && port->disable_gen2) {
726 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CFG);
727 value &= ~(PORTX_SPEED_SUPPORT_MASK <<
728 PORTX_SPEED_SUPPORT_SHIFT(index));
729 value |= (PORT_SPEED_SUPPORT_GEN1 <<
730 PORTX_SPEED_SUPPORT_SHIFT(index));
731 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CFG);
732 }
733
734 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
735 value &= ~SSPX_ELPG_VCORE_DOWN(index);
736 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
737
738 usleep_range(100, 200);
739
740 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
741 value &= ~SSPX_ELPG_CLAMP_EN_EARLY(index);
742 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
743
744 usleep_range(100, 200);
745
746 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
747 value &= ~SSPX_ELPG_CLAMP_EN(index);
748 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
749
750 mutex_unlock(&padctl->lock);
751
752 return 0;
753}
754
755static int tegra186_usb3_phy_power_off(struct phy *phy)
756{
757 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
758 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
759 struct tegra_xusb_usb3_port *port;
760 unsigned int index = lane->index;
761 struct device *dev = padctl->dev;
762 u32 value;
763
764 port = tegra_xusb_find_usb3_port(padctl, index);
765 if (!port) {
766 dev_err(dev, "no port found for USB3 lane %u\n", index);
767 return -ENODEV;
768 }
769
770 mutex_lock(&padctl->lock);
771
772 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
773 value |= SSPX_ELPG_CLAMP_EN_EARLY(index);
774 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
775
776 usleep_range(100, 200);
777
778 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
779 value |= SSPX_ELPG_CLAMP_EN(index);
780 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
781
782 usleep_range(250, 350);
783
784 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
785 value |= SSPX_ELPG_VCORE_DOWN(index);
786 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
787
788 mutex_unlock(&padctl->lock);
789
790 return 0;
791}
792
793static int tegra186_usb3_phy_init(struct phy *phy)
794{
795 return 0;
796}
797
798static int tegra186_usb3_phy_exit(struct phy *phy)
799{
800 return 0;
801}
802
803static const struct phy_ops usb3_phy_ops = {
804 .init = tegra186_usb3_phy_init,
805 .exit = tegra186_usb3_phy_exit,
806 .power_on = tegra186_usb3_phy_power_on,
807 .power_off = tegra186_usb3_phy_power_off,
808 .owner = THIS_MODULE,
809};
810
811static struct tegra_xusb_pad *
812tegra186_usb3_pad_probe(struct tegra_xusb_padctl *padctl,
813 const struct tegra_xusb_pad_soc *soc,
814 struct device_node *np)
815{
816 struct tegra_xusb_usb3_pad *usb3;
817 struct tegra_xusb_pad *pad;
818 int err;
819
820 usb3 = kzalloc(sizeof(*usb3), GFP_KERNEL);
821 if (!usb3)
822 return ERR_PTR(-ENOMEM);
823
824 pad = &usb3->base;
825 pad->ops = &tegra186_usb3_lane_ops;
826 pad->soc = soc;
827
828 err = tegra_xusb_pad_init(pad, padctl, np);
829 if (err < 0) {
830 kfree(usb3);
831 goto out;
832 }
833
834 err = tegra_xusb_pad_register(pad, &usb3_phy_ops);
835 if (err < 0)
836 goto unregister;
837
838 dev_set_drvdata(&pad->dev, pad);
839
840 return pad;
841
842unregister:
843 device_unregister(&pad->dev);
844out:
845 return ERR_PTR(err);
846}
847
848static void tegra186_usb3_pad_remove(struct tegra_xusb_pad *pad)
849{
850 struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad);
851
852 kfree(usb2);
853}
854
855static const struct tegra_xusb_pad_ops tegra186_usb3_pad_ops = {
856 .probe = tegra186_usb3_pad_probe,
857 .remove = tegra186_usb3_pad_remove,
858};
859
860static const char * const tegra186_usb3_functions[] = {
861 "xusb",
862};
863
864static int
865tegra186_xusb_read_fuse_calibration(struct tegra186_xusb_padctl *padctl)
866{
867 struct device *dev = padctl->base.dev;
868 unsigned int i, count;
869 u32 value, *level;
870 int err;
871
872 count = padctl->base.soc->ports.usb2.count;
873
874 level = devm_kcalloc(dev, count, sizeof(u32), GFP_KERNEL);
875 if (!level)
876 return -ENOMEM;
877
878 err = tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0, &value);
879 if (err) {
880 if (err != -EPROBE_DEFER)
881 dev_err(dev, "failed to read calibration fuse: %d\n",
882 err);
883 return err;
884 }
885
886 dev_dbg(dev, "FUSE_USB_CALIB_0 %#x\n", value);
887
888 for (i = 0; i < count; i++)
889 level[i] = (value >> HS_CURR_LEVEL_PADX_SHIFT(i)) &
890 HS_CURR_LEVEL_PAD_MASK;
891
892 padctl->calib.hs_curr_level = level;
893
894 padctl->calib.hs_squelch = (value >> HS_SQUELCH_SHIFT) &
895 HS_SQUELCH_MASK;
896 padctl->calib.hs_term_range_adj = (value >> HS_TERM_RANGE_ADJ_SHIFT) &
897 HS_TERM_RANGE_ADJ_MASK;
898
899 err = tegra_fuse_readl(TEGRA_FUSE_USB_CALIB_EXT_0, &value);
900 if (err) {
901 dev_err(dev, "failed to read calibration fuse: %d\n", err);
902 return err;
903 }
904
905 dev_dbg(dev, "FUSE_USB_CALIB_EXT_0 %#x\n", value);
906
907 padctl->calib.rpd_ctrl = (value >> RPD_CTRL_SHIFT) & RPD_CTRL_MASK;
908
909 return 0;
910}
911
912static struct tegra_xusb_padctl *
913tegra186_xusb_padctl_probe(struct device *dev,
914 const struct tegra_xusb_padctl_soc *soc)
915{
916 struct tegra186_xusb_padctl *priv;
917 int err;
918
919 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
920 if (!priv)
921 return ERR_PTR(-ENOMEM);
922
923 priv->base.dev = dev;
924 priv->base.soc = soc;
925
926 err = tegra186_xusb_read_fuse_calibration(priv);
927 if (err < 0)
928 return ERR_PTR(err);
929
930 return &priv->base;
931}
932
933static void tegra186_xusb_padctl_remove(struct tegra_xusb_padctl *padctl)
934{
935}
936
937static const struct tegra_xusb_padctl_ops tegra186_xusb_padctl_ops = {
938 .probe = tegra186_xusb_padctl_probe,
939 .remove = tegra186_xusb_padctl_remove,
940 .vbus_override = tegra186_xusb_padctl_vbus_override,
941};
942
943#if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
944static const char * const tegra186_xusb_padctl_supply_names[] = {
945 "avdd-pll-erefeut",
946 "avdd-usb",
947 "vclamp-usb",
948 "vddio-hsic",
949};
950
951static const struct tegra_xusb_lane_soc tegra186_usb2_lanes[] = {
952 TEGRA186_LANE("usb2-0", 0, 0, 0, usb2),
953 TEGRA186_LANE("usb2-1", 0, 0, 0, usb2),
954 TEGRA186_LANE("usb2-2", 0, 0, 0, usb2),
955};
956
957static const struct tegra_xusb_pad_soc tegra186_usb2_pad = {
958 .name = "usb2",
959 .num_lanes = ARRAY_SIZE(tegra186_usb2_lanes),
960 .lanes = tegra186_usb2_lanes,
961 .ops = &tegra186_usb2_pad_ops,
962};
963
964static const struct tegra_xusb_lane_soc tegra186_usb3_lanes[] = {
965 TEGRA186_LANE("usb3-0", 0, 0, 0, usb3),
966 TEGRA186_LANE("usb3-1", 0, 0, 0, usb3),
967 TEGRA186_LANE("usb3-2", 0, 0, 0, usb3),
968};
969
970static const struct tegra_xusb_pad_soc tegra186_usb3_pad = {
971 .name = "usb3",
972 .num_lanes = ARRAY_SIZE(tegra186_usb3_lanes),
973 .lanes = tegra186_usb3_lanes,
974 .ops = &tegra186_usb3_pad_ops,
975};
976
977static const struct tegra_xusb_pad_soc * const tegra186_pads[] = {
978 &tegra186_usb2_pad,
979 &tegra186_usb3_pad,
980#if 0 /* TODO implement */
981 &tegra186_hsic_pad,
982#endif
983};
984
985const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc = {
986 .num_pads = ARRAY_SIZE(tegra186_pads),
987 .pads = tegra186_pads,
988 .ports = {
989 .usb2 = {
990 .ops = &tegra186_usb2_port_ops,
991 .count = 3,
992 },
993#if 0 /* TODO implement */
994 .hsic = {
995 .ops = &tegra186_hsic_port_ops,
996 .count = 1,
997 },
998#endif
999 .usb3 = {
1000 .ops = &tegra186_usb3_port_ops,
1001 .count = 3,
1002 },
1003 },
1004 .ops = &tegra186_xusb_padctl_ops,
1005 .supply_names = tegra186_xusb_padctl_supply_names,
1006 .num_supplies = ARRAY_SIZE(tegra186_xusb_padctl_supply_names),
1007};
1008EXPORT_SYMBOL_GPL(tegra186_xusb_padctl_soc);
1009#endif
1010
1011#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC)
1012static const char * const tegra194_xusb_padctl_supply_names[] = {
1013 "avdd-usb",
1014 "vclamp-usb",
1015};
1016
1017static const struct tegra_xusb_lane_soc tegra194_usb2_lanes[] = {
1018 TEGRA186_LANE("usb2-0", 0, 0, 0, usb2),
1019 TEGRA186_LANE("usb2-1", 0, 0, 0, usb2),
1020 TEGRA186_LANE("usb2-2", 0, 0, 0, usb2),
1021 TEGRA186_LANE("usb2-3", 0, 0, 0, usb2),
1022};
1023
1024static const struct tegra_xusb_pad_soc tegra194_usb2_pad = {
1025 .name = "usb2",
1026 .num_lanes = ARRAY_SIZE(tegra194_usb2_lanes),
1027 .lanes = tegra194_usb2_lanes,
1028 .ops = &tegra186_usb2_pad_ops,
1029};
1030
1031static const struct tegra_xusb_lane_soc tegra194_usb3_lanes[] = {
1032 TEGRA186_LANE("usb3-0", 0, 0, 0, usb3),
1033 TEGRA186_LANE("usb3-1", 0, 0, 0, usb3),
1034 TEGRA186_LANE("usb3-2", 0, 0, 0, usb3),
1035 TEGRA186_LANE("usb3-3", 0, 0, 0, usb3),
1036};
1037
1038static const struct tegra_xusb_pad_soc tegra194_usb3_pad = {
1039 .name = "usb3",
1040 .num_lanes = ARRAY_SIZE(tegra194_usb3_lanes),
1041 .lanes = tegra194_usb3_lanes,
1042 .ops = &tegra186_usb3_pad_ops,
1043};
1044
1045static const struct tegra_xusb_pad_soc * const tegra194_pads[] = {
1046 &tegra194_usb2_pad,
1047 &tegra194_usb3_pad,
1048};
1049
1050const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc = {
1051 .num_pads = ARRAY_SIZE(tegra194_pads),
1052 .pads = tegra194_pads,
1053 .ports = {
1054 .usb2 = {
1055 .ops = &tegra186_usb2_port_ops,
1056 .count = 4,
1057 },
1058 .usb3 = {
1059 .ops = &tegra186_usb3_port_ops,
1060 .count = 4,
1061 },
1062 },
1063 .ops = &tegra186_xusb_padctl_ops,
1064 .supply_names = tegra194_xusb_padctl_supply_names,
1065 .num_supplies = ARRAY_SIZE(tegra194_xusb_padctl_supply_names),
1066 .supports_gen2 = true,
1067};
1068EXPORT_SYMBOL_GPL(tegra194_xusb_padctl_soc);
1069#endif
1070
1071MODULE_AUTHOR("JC Kuo <jckuo@nvidia.com>");
1072MODULE_DESCRIPTION("NVIDIA Tegra186 XUSB Pad Controller driver");
1073MODULE_LICENSE("GPL v2");