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1/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2/* Copyright(c) 2020 Intel Corporation. All rights reserved. */
3#ifndef _NTB_INTEL_GEN4_H_
4#define _NTB_INTEL_GEN4_H_
5
6#include "ntb_hw_intel.h"
7
8/* Supported PCI device revision range for ICX */
9#define PCI_DEVICE_REVISION_ICX_MIN 0x2
10#define PCI_DEVICE_REVISION_ICX_MAX 0xF
11
12/* Intel Gen4 NTB hardware */
13/* PCIe config space */
14#define GEN4_IMBAR23SZ_OFFSET 0x00c4
15#define GEN4_IMBAR45SZ_OFFSET 0x00c5
16#define GEN4_EMBAR23SZ_OFFSET 0x00c6
17#define GEN4_EMBAR45SZ_OFFSET 0x00c7
18#define GEN4_DEVCTRL_OFFSET 0x0048
19#define GEN4_DEVSTS_OFFSET 0x004a
20#define GEN4_UNCERRSTS_OFFSET 0x0104
21#define GEN4_CORERRSTS_OFFSET 0x0110
22
23/* BAR0 MMIO */
24#define GEN4_NTBCNTL_OFFSET 0x0000
25#define GEN4_IM23XBASE_OFFSET 0x0010 /* IMBAR1XBASE */
26#define GEN4_IM23XLMT_OFFSET 0x0018 /* IMBAR1XLMT */
27#define GEN4_IM45XBASE_OFFSET 0x0020 /* IMBAR2XBASE */
28#define GEN4_IM45XLMT_OFFSET 0x0028 /* IMBAR2XLMT */
29#define GEN4_IM_INT_STATUS_OFFSET 0x0040
30#define GEN4_IM_INT_DISABLE_OFFSET 0x0048
31#define GEN4_INTVEC_OFFSET 0x0050 /* 0-32 vecs */
32#define GEN4_IM23XBASEIDX_OFFSET 0x0074
33#define GEN4_IM45XBASEIDX_OFFSET 0x0076
34#define GEN4_IM_SPAD_OFFSET 0x0080 /* 0-15 SPADs */
35#define GEN4_IM_SPAD_SEM_OFFSET 0x00c0 /* SPAD hw semaphore */
36#define GEN4_IM_SPAD_STICKY_OFFSET 0x00c4 /* sticky SPAD */
37#define GEN4_IM_DOORBELL_OFFSET 0x0100 /* 0-31 doorbells */
38#define GEN4_LTR_SWSEL_OFFSET 0x30ec
39#define GEN4_LTR_ACTIVE_OFFSET 0x30f0
40#define GEN4_LTR_IDLE_OFFSET 0x30f4
41#define GEN4_EM_SPAD_OFFSET 0x8080
42/* note, link status is now in MMIO and not config space for NTB */
43#define GEN4_LINK_CTRL_OFFSET 0xb050
44#define GEN4_LINK_STATUS_OFFSET 0xb052
45#define GEN4_PPD0_OFFSET 0xb0d4
46#define GEN4_PPD1_OFFSET 0xb4c0
47#define GEN4_LTSSMSTATEJMP 0xf040
48
49#define GEN4_PPD_CLEAR_TRN 0x0001
50#define GEN4_PPD_LINKTRN 0x0008
51#define GEN4_PPD_CONN_MASK 0x0300
52#define SPR_PPD_CONN_MASK 0x0700
53#define GEN4_PPD_CONN_B2B 0x0200
54#define GEN4_PPD_DEV_MASK 0x1000
55#define GEN4_PPD_DEV_DSD 0x1000
56#define GEN4_PPD_DEV_USD 0x0000
57#define SPR_PPD_DEV_MASK 0x4000
58#define SPR_PPD_DEV_DSD 0x4000
59#define SPR_PPD_DEV_USD 0x0000
60#define GEN4_LINK_CTRL_LINK_DISABLE 0x0010
61
62#define GEN4_SLOTSTS 0xb05a
63#define GEN4_SLOTSTS_DLLSCS 0x100
64
65#define GEN4_PPD_TOPO_MASK (GEN4_PPD_CONN_MASK | GEN4_PPD_DEV_MASK)
66#define GEN4_PPD_TOPO_B2B_USD (GEN4_PPD_CONN_B2B | GEN4_PPD_DEV_USD)
67#define GEN4_PPD_TOPO_B2B_DSD (GEN4_PPD_CONN_B2B | GEN4_PPD_DEV_DSD)
68
69#define SPR_PPD_TOPO_MASK (SPR_PPD_CONN_MASK | SPR_PPD_DEV_MASK)
70#define SPR_PPD_TOPO_B2B_USD (GEN4_PPD_CONN_B2B | SPR_PPD_DEV_USD)
71#define SPR_PPD_TOPO_B2B_DSD (GEN4_PPD_CONN_B2B | SPR_PPD_DEV_DSD)
72
73#define GEN4_DB_COUNT 32
74#define GEN4_DB_LINK 32
75#define GEN4_DB_LINK_BIT BIT_ULL(GEN4_DB_LINK)
76#define GEN4_DB_MSIX_VECTOR_COUNT 33
77#define GEN4_DB_MSIX_VECTOR_SHIFT 1
78#define GEN4_DB_TOTAL_SHIFT 33
79#define GEN4_SPAD_COUNT 16
80
81#define NTB_CTL_E2I_BAR23_SNOOP 0x000004
82#define NTB_CTL_E2I_BAR23_NOSNOOP 0x000008
83#define NTB_CTL_I2E_BAR23_SNOOP 0x000010
84#define NTB_CTL_I2E_BAR23_NOSNOOP 0x000020
85#define NTB_CTL_E2I_BAR45_SNOOP 0x000040
86#define NTB_CTL_E2I_BAR45_NOSNOO 0x000080
87#define NTB_CTL_I2E_BAR45_SNOOP 0x000100
88#define NTB_CTL_I2E_BAR45_NOSNOOP 0x000200
89#define NTB_CTL_BUSNO_DIS_INC 0x000400
90#define NTB_CTL_LINK_DOWN 0x010000
91
92#define NTB_SJC_FORCEDETECT 0x000004
93
94#define NTB_LTR_SWSEL_ACTIVE 0x0
95#define NTB_LTR_SWSEL_IDLE 0x1
96
97#define NTB_LTR_NS_SHIFT 16
98#define NTB_LTR_ACTIVE_VAL 0x0000 /* 0 us */
99#define NTB_LTR_ACTIVE_LATSCALE 0x0800 /* 1us scale */
100#define NTB_LTR_ACTIVE_REQMNT 0x8000 /* snoop req enable */
101
102#define NTB_LTR_IDLE_VAL 0x0258 /* 600 us */
103#define NTB_LTR_IDLE_LATSCALE 0x0800 /* 1us scale */
104#define NTB_LTR_IDLE_REQMNT 0x8000 /* snoop req enable */
105
106ssize_t ndev_ntb4_debugfs_read(struct file *filp, char __user *ubuf,
107 size_t count, loff_t *offp);
108int gen4_init_dev(struct intel_ntb_dev *ndev);
109ssize_t ndev_ntb4_debugfs_read(struct file *filp, char __user *ubuf,
110 size_t count, loff_t *offp);
111
112extern const struct ntb_dev_ops intel_ntb4_ops;
113
114static inline int pdev_is_ICX(struct pci_dev *pdev)
115{
116 if (pdev_is_gen4(pdev) &&
117 pdev->revision >= PCI_DEVICE_REVISION_ICX_MIN &&
118 pdev->revision <= PCI_DEVICE_REVISION_ICX_MAX)
119 return 1;
120 return 0;
121}
122
123static inline int pdev_is_SPR(struct pci_dev *pdev)
124{
125 if (pdev_is_gen4(pdev) &&
126 pdev->revision > PCI_DEVICE_REVISION_ICX_MAX)
127 return 1;
128 return 0;
129}
130
131#endif
1/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2/* Copyright(c) 2020 Intel Corporation. All rights reserved. */
3#ifndef _NTB_INTEL_GEN4_H_
4#define _NTB_INTEL_GEN4_H_
5
6#include "ntb_hw_intel.h"
7
8/* Supported PCI device revision range for ICX */
9#define PCI_DEVICE_REVISION_ICX_MIN 0x2
10#define PCI_DEVICE_REVISION_ICX_MAX 0xF
11
12/* Intel Gen4 NTB hardware */
13/* PCIe config space */
14#define GEN4_IMBAR23SZ_OFFSET 0x00c4
15#define GEN4_IMBAR45SZ_OFFSET 0x00c5
16#define GEN4_EMBAR23SZ_OFFSET 0x00c6
17#define GEN4_EMBAR45SZ_OFFSET 0x00c7
18#define GEN4_DEVCTRL_OFFSET 0x0048
19#define GEN4_DEVSTS_OFFSET 0x004a
20#define GEN4_UNCERRSTS_OFFSET 0x0104
21#define GEN4_CORERRSTS_OFFSET 0x0110
22
23/* BAR0 MMIO */
24#define GEN4_NTBCNTL_OFFSET 0x0000
25#define GEN4_IM23XBASE_OFFSET 0x0010 /* IMBAR1XBASE */
26#define GEN4_IM23XLMT_OFFSET 0x0018 /* IMBAR1XLMT */
27#define GEN4_IM45XBASE_OFFSET 0x0020 /* IMBAR2XBASE */
28#define GEN4_IM45XLMT_OFFSET 0x0028 /* IMBAR2XLMT */
29#define GEN4_IM_INT_STATUS_OFFSET 0x0040
30#define GEN4_IM_INT_DISABLE_OFFSET 0x0048
31#define GEN4_INTVEC_OFFSET 0x0050 /* 0-32 vecs */
32#define GEN4_IM23XBASEIDX_OFFSET 0x0074
33#define GEN4_IM45XBASEIDX_OFFSET 0x0076
34#define GEN4_IM_SPAD_OFFSET 0x0080 /* 0-15 SPADs */
35#define GEN4_IM_SPAD_SEM_OFFSET 0x00c0 /* SPAD hw semaphore */
36#define GEN4_IM_SPAD_STICKY_OFFSET 0x00c4 /* sticky SPAD */
37#define GEN4_IM_DOORBELL_OFFSET 0x0100 /* 0-31 doorbells */
38#define GEN4_EM_SPAD_OFFSET 0x8080
39/* note, link status is now in MMIO and not config space for NTB */
40#define GEN4_LINK_CTRL_OFFSET 0xb050
41#define GEN4_LINK_STATUS_OFFSET 0xb052
42#define GEN4_PPD0_OFFSET 0xb0d4
43#define GEN4_PPD1_OFFSET 0xb4c0
44#define GEN4_LTSSMSTATEJMP 0xf040
45
46#define GEN4_PPD_CLEAR_TRN 0x0001
47#define GEN4_PPD_LINKTRN 0x0008
48#define GEN4_PPD_CONN_MASK 0x0300
49#define GEN4_PPD_CONN_B2B 0x0200
50#define GEN4_PPD_DEV_MASK 0x1000
51#define GEN4_PPD_DEV_DSD 0x1000
52#define GEN4_PPD_DEV_USD 0x0000
53#define GEN4_LINK_CTRL_LINK_DISABLE 0x0010
54
55#define GEN4_SLOTSTS 0xb05a
56#define GEN4_SLOTSTS_DLLSCS 0x100
57
58#define GEN4_PPD_TOPO_MASK (GEN4_PPD_CONN_MASK | GEN4_PPD_DEV_MASK)
59#define GEN4_PPD_TOPO_B2B_USD (GEN4_PPD_CONN_B2B | GEN4_PPD_DEV_USD)
60#define GEN4_PPD_TOPO_B2B_DSD (GEN4_PPD_CONN_B2B | GEN4_PPD_DEV_DSD)
61
62#define GEN4_DB_COUNT 32
63#define GEN4_DB_LINK 32
64#define GEN4_DB_LINK_BIT BIT_ULL(GEN4_DB_LINK)
65#define GEN4_DB_MSIX_VECTOR_COUNT 33
66#define GEN4_DB_MSIX_VECTOR_SHIFT 1
67#define GEN4_DB_TOTAL_SHIFT 33
68#define GEN4_SPAD_COUNT 16
69
70#define NTB_CTL_E2I_BAR23_SNOOP 0x000004
71#define NTB_CTL_E2I_BAR23_NOSNOOP 0x000008
72#define NTB_CTL_I2E_BAR23_SNOOP 0x000010
73#define NTB_CTL_I2E_BAR23_NOSNOOP 0x000020
74#define NTB_CTL_E2I_BAR45_SNOOP 0x000040
75#define NTB_CTL_E2I_BAR45_NOSNOO 0x000080
76#define NTB_CTL_I2E_BAR45_SNOOP 0x000100
77#define NTB_CTL_I2E_BAR45_NOSNOOP 0x000200
78#define NTB_CTL_BUSNO_DIS_INC 0x000400
79#define NTB_CTL_LINK_DOWN 0x010000
80
81#define NTB_SJC_FORCEDETECT 0x000004
82
83ssize_t ndev_ntb4_debugfs_read(struct file *filp, char __user *ubuf,
84 size_t count, loff_t *offp);
85int gen4_init_dev(struct intel_ntb_dev *ndev);
86ssize_t ndev_ntb4_debugfs_read(struct file *filp, char __user *ubuf,
87 size_t count, loff_t *offp);
88
89extern const struct ntb_dev_ops intel_ntb4_ops;
90
91static inline int pdev_is_ICX(struct pci_dev *pdev)
92{
93 if (pdev_is_gen4(pdev) &&
94 pdev->revision >= PCI_DEVICE_REVISION_ICX_MIN &&
95 pdev->revision <= PCI_DEVICE_REVISION_ICX_MAX)
96 return 1;
97 return 0;
98}
99
100#endif