Loading...
1/*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright(c) 2012-2017 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * BSD LICENSE
14 *
15 * Copyright(c) 2012-2017 Intel Corporation. All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
19 * are met:
20 *
21 * * Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * * Redistributions in binary form must reproduce the above copy
24 * notice, this list of conditions and the following disclaimer in
25 * the documentation and/or other materials provided with the
26 * distribution.
27 * * Neither the name of Intel Corporation nor the names of its
28 * contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
30 *
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
35 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
36 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
37 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 */
43
44#ifndef _NTB_INTEL_GEN3_H_
45#define _NTB_INTEL_GEN3_H_
46
47#include "ntb_hw_intel.h"
48
49/* Intel Skylake Xeon hardware */
50#define GEN3_IMBAR1SZ_OFFSET 0x00d0
51#define GEN3_IMBAR2SZ_OFFSET 0x00d1
52#define GEN3_EMBAR1SZ_OFFSET 0x00d2
53#define GEN3_EMBAR2SZ_OFFSET 0x00d3
54#define GEN3_DEVCTRL_OFFSET 0x0098
55#define GEN3_DEVSTS_OFFSET 0x009a
56#define GEN3_UNCERRSTS_OFFSET 0x014c
57#define GEN3_CORERRSTS_OFFSET 0x0158
58#define GEN3_LINK_STATUS_OFFSET 0x01a2
59
60#define GEN3_NTBCNTL_OFFSET 0x0000
61#define GEN3_IMBAR1XBASE_OFFSET 0x0010 /* SBAR2XLAT */
62#define GEN3_IMBAR1XLMT_OFFSET 0x0018 /* SBAR2LMT */
63#define GEN3_IMBAR2XBASE_OFFSET 0x0020 /* SBAR4XLAT */
64#define GEN3_IMBAR2XLMT_OFFSET 0x0028 /* SBAR4LMT */
65#define GEN3_IM_INT_STATUS_OFFSET 0x0040
66#define GEN3_IM_INT_DISABLE_OFFSET 0x0048
67#define GEN3_IM_SPAD_OFFSET 0x0080 /* SPAD */
68#define GEN3_USMEMMISS_OFFSET 0x0070
69#define GEN3_INTVEC_OFFSET 0x00d0
70#define GEN3_IM_DOORBELL_OFFSET 0x0100 /* SDOORBELL0 */
71#define GEN3_B2B_SPAD_OFFSET 0x0180 /* B2B SPAD */
72#define GEN3_EMBAR0XBASE_OFFSET 0x4008 /* B2B_XLAT */
73#define GEN3_EMBAR1XBASE_OFFSET 0x4010 /* PBAR2XLAT */
74#define GEN3_EMBAR1XLMT_OFFSET 0x4018 /* PBAR2LMT */
75#define GEN3_EMBAR2XBASE_OFFSET 0x4020 /* PBAR4XLAT */
76#define GEN3_EMBAR2XLMT_OFFSET 0x4028 /* PBAR4LMT */
77#define GEN3_EM_INT_STATUS_OFFSET 0x4040
78#define GEN3_EM_INT_DISABLE_OFFSET 0x4048
79#define GEN3_EM_SPAD_OFFSET 0x4080 /* remote SPAD */
80#define GEN3_EM_DOORBELL_OFFSET 0x4100 /* PDOORBELL0 */
81#define GEN3_SPCICMD_OFFSET 0x4504 /* SPCICMD */
82#define GEN3_EMBAR0_OFFSET 0x4510 /* SBAR0BASE */
83#define GEN3_EMBAR1_OFFSET 0x4518 /* SBAR23BASE */
84#define GEN3_EMBAR2_OFFSET 0x4520 /* SBAR45BASE */
85
86#define GEN3_DB_COUNT 32
87#define GEN3_DB_LINK 32
88#define GEN3_DB_LINK_BIT BIT_ULL(GEN3_DB_LINK)
89#define GEN3_DB_MSIX_VECTOR_COUNT 33
90#define GEN3_DB_MSIX_VECTOR_SHIFT 1
91#define GEN3_DB_TOTAL_SHIFT 33
92#define GEN3_SPAD_COUNT 16
93
94static inline u64 gen3_db_ioread(const void __iomem *mmio)
95{
96 return ioread64(mmio);
97}
98
99static inline void gen3_db_iowrite(u64 bits, void __iomem *mmio)
100{
101 iowrite64(bits, mmio);
102}
103
104ssize_t ndev_ntb3_debugfs_read(struct file *filp, char __user *ubuf,
105 size_t count, loff_t *offp);
106int gen3_init_dev(struct intel_ntb_dev *ndev);
107int intel_ntb3_link_enable(struct ntb_dev *ntb, enum ntb_speed max_speed,
108 enum ntb_width max_width);
109u64 intel_ntb3_db_read(struct ntb_dev *ntb);
110int intel_ntb3_db_clear(struct ntb_dev *ntb, u64 db_bits);
111int intel_ntb3_peer_db_set(struct ntb_dev *ntb, u64 db_bits);
112int intel_ntb3_peer_db_addr(struct ntb_dev *ntb, phys_addr_t *db_addr,
113 resource_size_t *db_size,
114 u64 *db_data, int db_bit);
115
116extern const struct ntb_dev_ops intel_ntb3_ops;
117
118#endif
1/*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright(c) 2012-2017 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * BSD LICENSE
14 *
15 * Copyright(c) 2012-2017 Intel Corporation. All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
19 * are met:
20 *
21 * * Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * * Redistributions in binary form must reproduce the above copy
24 * notice, this list of conditions and the following disclaimer in
25 * the documentation and/or other materials provided with the
26 * distribution.
27 * * Neither the name of Intel Corporation nor the names of its
28 * contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
30 *
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
35 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
36 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
37 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 */
43
44#ifndef _NTB_INTEL_GEN3_H_
45#define _NTB_INTEL_GEN3_H_
46
47#include "ntb_hw_intel.h"
48
49/* Intel Skylake Xeon hardware */
50#define GEN3_IMBAR1SZ_OFFSET 0x00d0
51#define GEN3_IMBAR2SZ_OFFSET 0x00d1
52#define GEN3_EMBAR1SZ_OFFSET 0x00d2
53#define GEN3_EMBAR2SZ_OFFSET 0x00d3
54#define GEN3_DEVCTRL_OFFSET 0x0098
55#define GEN3_DEVSTS_OFFSET 0x009a
56#define GEN3_UNCERRSTS_OFFSET 0x014c
57#define GEN3_CORERRSTS_OFFSET 0x0158
58#define GEN3_LINK_STATUS_OFFSET 0x01a2
59
60#define GEN3_NTBCNTL_OFFSET 0x0000
61#define GEN3_IMBAR1XBASE_OFFSET 0x0010 /* SBAR2XLAT */
62#define GEN3_IMBAR1XLMT_OFFSET 0x0018 /* SBAR2LMT */
63#define GEN3_IMBAR2XBASE_OFFSET 0x0020 /* SBAR4XLAT */
64#define GEN3_IMBAR2XLMT_OFFSET 0x0028 /* SBAR4LMT */
65#define GEN3_IM_INT_STATUS_OFFSET 0x0040
66#define GEN3_IM_INT_DISABLE_OFFSET 0x0048
67#define GEN3_IM_SPAD_OFFSET 0x0080 /* SPAD */
68#define GEN3_USMEMMISS_OFFSET 0x0070
69#define GEN3_INTVEC_OFFSET 0x00d0
70#define GEN3_IM_DOORBELL_OFFSET 0x0100 /* SDOORBELL0 */
71#define GEN3_B2B_SPAD_OFFSET 0x0180 /* B2B SPAD */
72#define GEN3_EMBAR0XBASE_OFFSET 0x4008 /* B2B_XLAT */
73#define GEN3_EMBAR1XBASE_OFFSET 0x4010 /* PBAR2XLAT */
74#define GEN3_EMBAR1XLMT_OFFSET 0x4018 /* PBAR2LMT */
75#define GEN3_EMBAR2XBASE_OFFSET 0x4020 /* PBAR4XLAT */
76#define GEN3_EMBAR2XLMT_OFFSET 0x4028 /* PBAR4LMT */
77#define GEN3_EM_INT_STATUS_OFFSET 0x4040
78#define GEN3_EM_INT_DISABLE_OFFSET 0x4048
79#define GEN3_EM_SPAD_OFFSET 0x4080 /* remote SPAD */
80#define GEN3_EM_DOORBELL_OFFSET 0x4100 /* PDOORBELL0 */
81#define GEN3_SPCICMD_OFFSET 0x4504 /* SPCICMD */
82#define GEN3_EMBAR0_OFFSET 0x4510 /* SBAR0BASE */
83#define GEN3_EMBAR1_OFFSET 0x4518 /* SBAR23BASE */
84#define GEN3_EMBAR2_OFFSET 0x4520 /* SBAR45BASE */
85
86#define GEN3_DB_COUNT 32
87#define GEN3_DB_LINK 32
88#define GEN3_DB_LINK_BIT BIT_ULL(GEN3_DB_LINK)
89#define GEN3_DB_MSIX_VECTOR_COUNT 33
90#define GEN3_DB_MSIX_VECTOR_SHIFT 1
91#define GEN3_DB_TOTAL_SHIFT 33
92#define GEN3_SPAD_COUNT 16
93
94static inline u64 gen3_db_ioread(const void __iomem *mmio)
95{
96 return ioread64(mmio);
97}
98
99static inline void gen3_db_iowrite(u64 bits, void __iomem *mmio)
100{
101 iowrite64(bits, mmio);
102}
103
104ssize_t ndev_ntb3_debugfs_read(struct file *filp, char __user *ubuf,
105 size_t count, loff_t *offp);
106int gen3_init_dev(struct intel_ntb_dev *ndev);
107int intel_ntb3_link_enable(struct ntb_dev *ntb, enum ntb_speed max_speed,
108 enum ntb_width max_width);
109u64 intel_ntb3_db_read(struct ntb_dev *ntb);
110int intel_ntb3_db_clear(struct ntb_dev *ntb, u64 db_bits);
111int intel_ntb3_peer_db_set(struct ntb_dev *ntb, u64 db_bits);
112int intel_ntb3_peer_db_addr(struct ntb_dev *ntb, phys_addr_t *db_addr,
113 resource_size_t *db_size,
114 u64 *db_data, int db_bit);
115
116extern const struct ntb_dev_ops intel_ntb3_ops;
117
118#endif