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1// SPDX-License-Identifier: GPL-2.0-only
2/**
3 * SDHCI Controller driver for TI's OMAP SoCs
4 *
5 * Copyright (C) 2017 Texas Instruments
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
7 */
8
9#include <linux/delay.h>
10#include <linux/mmc/mmc.h>
11#include <linux/mmc/slot-gpio.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/of_device.h>
15#include <linux/of_irq.h>
16#include <linux/platform_device.h>
17#include <linux/pm_runtime.h>
18#include <linux/pm_wakeirq.h>
19#include <linux/regulator/consumer.h>
20#include <linux/pinctrl/consumer.h>
21#include <linux/sys_soc.h>
22#include <linux/thermal.h>
23
24#include "sdhci-pltfm.h"
25
26/*
27 * Note that the register offsets used here are from omap_regs
28 * base which is 0x100 for omap4 and later, and 0 for omap3 and
29 * earlier.
30 */
31#define SDHCI_OMAP_SYSCONFIG 0x10
32
33#define SDHCI_OMAP_CON 0x2c
34#define CON_DW8 BIT(5)
35#define CON_DMA_MASTER BIT(20)
36#define CON_DDR BIT(19)
37#define CON_CLKEXTFREE BIT(16)
38#define CON_PADEN BIT(15)
39#define CON_CTPL BIT(11)
40#define CON_INIT BIT(1)
41#define CON_OD BIT(0)
42
43#define SDHCI_OMAP_DLL 0x34
44#define DLL_SWT BIT(20)
45#define DLL_FORCE_SR_C_SHIFT 13
46#define DLL_FORCE_SR_C_MASK (0x7f << DLL_FORCE_SR_C_SHIFT)
47#define DLL_FORCE_VALUE BIT(12)
48#define DLL_CALIB BIT(1)
49
50#define SDHCI_OMAP_CMD 0x10c
51
52#define SDHCI_OMAP_PSTATE 0x124
53#define PSTATE_DLEV_DAT0 BIT(20)
54#define PSTATE_DATI BIT(1)
55
56#define SDHCI_OMAP_HCTL 0x128
57#define HCTL_SDBP BIT(8)
58#define HCTL_SDVS_SHIFT 9
59#define HCTL_SDVS_MASK (0x7 << HCTL_SDVS_SHIFT)
60#define HCTL_SDVS_33 (0x7 << HCTL_SDVS_SHIFT)
61#define HCTL_SDVS_30 (0x6 << HCTL_SDVS_SHIFT)
62#define HCTL_SDVS_18 (0x5 << HCTL_SDVS_SHIFT)
63
64#define SDHCI_OMAP_SYSCTL 0x12c
65#define SYSCTL_CEN BIT(2)
66#define SYSCTL_CLKD_SHIFT 6
67#define SYSCTL_CLKD_MASK 0x3ff
68
69#define SDHCI_OMAP_STAT 0x130
70
71#define SDHCI_OMAP_IE 0x134
72#define INT_CC_EN BIT(0)
73
74#define SDHCI_OMAP_ISE 0x138
75
76#define SDHCI_OMAP_AC12 0x13c
77#define AC12_V1V8_SIGEN BIT(19)
78#define AC12_SCLK_SEL BIT(23)
79
80#define SDHCI_OMAP_CAPA 0x140
81#define CAPA_VS33 BIT(24)
82#define CAPA_VS30 BIT(25)
83#define CAPA_VS18 BIT(26)
84
85#define SDHCI_OMAP_CAPA2 0x144
86#define CAPA2_TSDR50 BIT(13)
87
88#define SDHCI_OMAP_TIMEOUT 1 /* 1 msec */
89
90#define SYSCTL_CLKD_MAX 0x3FF
91
92#define IOV_1V8 1800000 /* 180000 uV */
93#define IOV_3V0 3000000 /* 300000 uV */
94#define IOV_3V3 3300000 /* 330000 uV */
95
96#define MAX_PHASE_DELAY 0x7C
97
98/* sdhci-omap controller flags */
99#define SDHCI_OMAP_REQUIRE_IODELAY BIT(0)
100#define SDHCI_OMAP_SPECIAL_RESET BIT(1)
101
102struct sdhci_omap_data {
103 int omap_offset; /* Offset for omap regs from base */
104 u32 offset; /* Offset for SDHCI regs from base */
105 u8 flags;
106};
107
108struct sdhci_omap_host {
109 char *version;
110 void __iomem *base;
111 struct device *dev;
112 struct regulator *pbias;
113 bool pbias_enabled;
114 struct sdhci_host *host;
115 u8 bus_mode;
116 u8 power_mode;
117 u8 timing;
118 u8 flags;
119
120 struct pinctrl *pinctrl;
121 struct pinctrl_state **pinctrl_state;
122 int wakeirq;
123 bool is_tuning;
124
125 /* Offset for omap specific registers from base */
126 int omap_offset;
127
128 /* Omap specific context save */
129 u32 con;
130 u32 hctl;
131 u32 sysctl;
132 u32 capa;
133 u32 ie;
134 u32 ise;
135};
136
137static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host);
138static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host);
139
140static inline u32 sdhci_omap_readl(struct sdhci_omap_host *host,
141 unsigned int offset)
142{
143 return readl(host->base + host->omap_offset + offset);
144}
145
146static inline void sdhci_omap_writel(struct sdhci_omap_host *host,
147 unsigned int offset, u32 data)
148{
149 writel(data, host->base + host->omap_offset + offset);
150}
151
152static int sdhci_omap_set_pbias(struct sdhci_omap_host *omap_host,
153 bool power_on, unsigned int iov)
154{
155 int ret;
156 struct device *dev = omap_host->dev;
157
158 if (IS_ERR(omap_host->pbias))
159 return 0;
160
161 if (power_on) {
162 ret = regulator_set_voltage(omap_host->pbias, iov, iov);
163 if (ret) {
164 dev_err(dev, "pbias set voltage failed\n");
165 return ret;
166 }
167
168 if (omap_host->pbias_enabled)
169 return 0;
170
171 ret = regulator_enable(omap_host->pbias);
172 if (ret) {
173 dev_err(dev, "pbias reg enable fail\n");
174 return ret;
175 }
176
177 omap_host->pbias_enabled = true;
178 } else {
179 if (!omap_host->pbias_enabled)
180 return 0;
181
182 ret = regulator_disable(omap_host->pbias);
183 if (ret) {
184 dev_err(dev, "pbias reg disable fail\n");
185 return ret;
186 }
187 omap_host->pbias_enabled = false;
188 }
189
190 return 0;
191}
192
193static int sdhci_omap_enable_iov(struct sdhci_omap_host *omap_host,
194 unsigned int iov_pbias)
195{
196 int ret;
197 struct sdhci_host *host = omap_host->host;
198 struct mmc_host *mmc = host->mmc;
199
200 ret = sdhci_omap_set_pbias(omap_host, false, 0);
201 if (ret)
202 return ret;
203
204 if (!IS_ERR(mmc->supply.vqmmc)) {
205 /* Pick the right voltage to allow 3.0V for 3.3V nominal PBIAS */
206 ret = mmc_regulator_set_vqmmc(mmc, &mmc->ios);
207 if (ret < 0) {
208 dev_err(mmc_dev(mmc), "vqmmc set voltage failed\n");
209 return ret;
210 }
211 }
212
213 ret = sdhci_omap_set_pbias(omap_host, true, iov_pbias);
214 if (ret)
215 return ret;
216
217 return 0;
218}
219
220static void sdhci_omap_conf_bus_power(struct sdhci_omap_host *omap_host,
221 unsigned char signal_voltage)
222{
223 u32 reg, capa;
224 ktime_t timeout;
225
226 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL);
227 reg &= ~HCTL_SDVS_MASK;
228
229 switch (signal_voltage) {
230 case MMC_SIGNAL_VOLTAGE_330:
231 capa = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
232 if (capa & CAPA_VS33)
233 reg |= HCTL_SDVS_33;
234 else if (capa & CAPA_VS30)
235 reg |= HCTL_SDVS_30;
236 else
237 dev_warn(omap_host->dev, "misconfigured CAPA: %08x\n",
238 capa);
239 break;
240 case MMC_SIGNAL_VOLTAGE_180:
241 default:
242 reg |= HCTL_SDVS_18;
243 break;
244 }
245
246 sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg);
247
248 reg |= HCTL_SDBP;
249 sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg);
250
251 /* wait 1ms */
252 timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT);
253 while (1) {
254 bool timedout = ktime_after(ktime_get(), timeout);
255
256 if (sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL) & HCTL_SDBP)
257 break;
258 if (WARN_ON(timedout))
259 return;
260 usleep_range(5, 10);
261 }
262}
263
264static void sdhci_omap_enable_sdio_irq(struct mmc_host *mmc, int enable)
265{
266 struct sdhci_host *host = mmc_priv(mmc);
267 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
268 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
269 u32 reg;
270
271 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
272 if (enable)
273 reg |= (CON_CTPL | CON_CLKEXTFREE);
274 else
275 reg &= ~(CON_CTPL | CON_CLKEXTFREE);
276 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
277
278 sdhci_enable_sdio_irq(mmc, enable);
279}
280
281static inline void sdhci_omap_set_dll(struct sdhci_omap_host *omap_host,
282 int count)
283{
284 int i;
285 u32 reg;
286
287 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
288 reg |= DLL_FORCE_VALUE;
289 reg &= ~DLL_FORCE_SR_C_MASK;
290 reg |= (count << DLL_FORCE_SR_C_SHIFT);
291 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
292
293 reg |= DLL_CALIB;
294 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
295 for (i = 0; i < 1000; i++) {
296 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
297 if (reg & DLL_CALIB)
298 break;
299 }
300 reg &= ~DLL_CALIB;
301 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
302}
303
304static void sdhci_omap_disable_tuning(struct sdhci_omap_host *omap_host)
305{
306 u32 reg;
307
308 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
309 reg &= ~AC12_SCLK_SEL;
310 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
311
312 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
313 reg &= ~(DLL_FORCE_VALUE | DLL_SWT);
314 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
315}
316
317static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode)
318{
319 struct sdhci_host *host = mmc_priv(mmc);
320 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
321 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
322 struct thermal_zone_device *thermal_dev;
323 struct device *dev = omap_host->dev;
324 struct mmc_ios *ios = &mmc->ios;
325 u32 start_window = 0, max_window = 0;
326 bool single_point_failure = false;
327 bool dcrc_was_enabled = false;
328 u8 cur_match, prev_match = 0;
329 u32 length = 0, max_len = 0;
330 u32 phase_delay = 0;
331 int temperature;
332 int ret = 0;
333 u32 reg;
334 int i;
335
336 /* clock tuning is not needed for upto 52MHz */
337 if (ios->clock <= 52000000)
338 return 0;
339
340 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA2);
341 if (ios->timing == MMC_TIMING_UHS_SDR50 && !(reg & CAPA2_TSDR50))
342 return 0;
343
344 thermal_dev = thermal_zone_get_zone_by_name("cpu_thermal");
345 if (IS_ERR(thermal_dev)) {
346 dev_err(dev, "Unable to get thermal zone for tuning\n");
347 return PTR_ERR(thermal_dev);
348 }
349
350 ret = thermal_zone_get_temp(thermal_dev, &temperature);
351 if (ret)
352 return ret;
353
354 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
355 reg |= DLL_SWT;
356 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
357
358 /*
359 * OMAP5/DRA74X/DRA72x Errata i802:
360 * DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur
361 * during the tuning procedure. So disable it during the
362 * tuning procedure.
363 */
364 if (host->ier & SDHCI_INT_DATA_CRC) {
365 host->ier &= ~SDHCI_INT_DATA_CRC;
366 dcrc_was_enabled = true;
367 }
368
369 omap_host->is_tuning = true;
370
371 /*
372 * Stage 1: Search for a maximum pass window ignoring any
373 * single point failures. If the tuning value ends up
374 * near it, move away from it in stage 2 below
375 */
376 while (phase_delay <= MAX_PHASE_DELAY) {
377 sdhci_omap_set_dll(omap_host, phase_delay);
378
379 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
380 if (cur_match) {
381 if (prev_match) {
382 length++;
383 } else if (single_point_failure) {
384 /* ignore single point failure */
385 length++;
386 } else {
387 start_window = phase_delay;
388 length = 1;
389 }
390 } else {
391 single_point_failure = prev_match;
392 }
393
394 if (length > max_len) {
395 max_window = start_window;
396 max_len = length;
397 }
398
399 prev_match = cur_match;
400 phase_delay += 4;
401 }
402
403 if (!max_len) {
404 dev_err(dev, "Unable to find match\n");
405 ret = -EIO;
406 goto tuning_error;
407 }
408
409 /*
410 * Assign tuning value as a ratio of maximum pass window based
411 * on temperature
412 */
413 if (temperature < -20000)
414 phase_delay = min(max_window + 4 * (max_len - 1) - 24,
415 max_window +
416 DIV_ROUND_UP(13 * max_len, 16) * 4);
417 else if (temperature < 20000)
418 phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4;
419 else if (temperature < 40000)
420 phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4;
421 else if (temperature < 70000)
422 phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4;
423 else if (temperature < 90000)
424 phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4;
425 else if (temperature < 120000)
426 phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4;
427 else
428 phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4;
429
430 /*
431 * Stage 2: Search for a single point failure near the chosen tuning
432 * value in two steps. First in the +3 to +10 range and then in the
433 * +2 to -10 range. If found, move away from it in the appropriate
434 * direction by the appropriate amount depending on the temperature.
435 */
436 for (i = 3; i <= 10; i++) {
437 sdhci_omap_set_dll(omap_host, phase_delay + i);
438
439 if (mmc_send_tuning(mmc, opcode, NULL)) {
440 if (temperature < 10000)
441 phase_delay += i + 6;
442 else if (temperature < 20000)
443 phase_delay += i - 12;
444 else if (temperature < 70000)
445 phase_delay += i - 8;
446 else
447 phase_delay += i - 6;
448
449 goto single_failure_found;
450 }
451 }
452
453 for (i = 2; i >= -10; i--) {
454 sdhci_omap_set_dll(omap_host, phase_delay + i);
455
456 if (mmc_send_tuning(mmc, opcode, NULL)) {
457 if (temperature < 10000)
458 phase_delay += i + 12;
459 else if (temperature < 20000)
460 phase_delay += i + 8;
461 else if (temperature < 70000)
462 phase_delay += i + 8;
463 else if (temperature < 90000)
464 phase_delay += i + 10;
465 else
466 phase_delay += i + 12;
467
468 goto single_failure_found;
469 }
470 }
471
472single_failure_found:
473 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
474 if (!(reg & AC12_SCLK_SEL)) {
475 ret = -EIO;
476 goto tuning_error;
477 }
478
479 sdhci_omap_set_dll(omap_host, phase_delay);
480
481 omap_host->is_tuning = false;
482
483 goto ret;
484
485tuning_error:
486 omap_host->is_tuning = false;
487 dev_err(dev, "Tuning failed\n");
488 sdhci_omap_disable_tuning(omap_host);
489
490ret:
491 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
492 /* Reenable forbidden interrupt */
493 if (dcrc_was_enabled)
494 host->ier |= SDHCI_INT_DATA_CRC;
495 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
496 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
497 return ret;
498}
499
500static int sdhci_omap_card_busy(struct mmc_host *mmc)
501{
502 u32 reg, ac12;
503 int ret = false;
504 struct sdhci_host *host = mmc_priv(mmc);
505 struct sdhci_pltfm_host *pltfm_host;
506 struct sdhci_omap_host *omap_host;
507 u32 ier = host->ier;
508
509 pltfm_host = sdhci_priv(host);
510 omap_host = sdhci_pltfm_priv(pltfm_host);
511
512 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
513 ac12 = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
514 reg &= ~CON_CLKEXTFREE;
515 if (ac12 & AC12_V1V8_SIGEN)
516 reg |= CON_CLKEXTFREE;
517 reg |= CON_PADEN;
518 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
519
520 disable_irq(host->irq);
521 ier |= SDHCI_INT_CARD_INT;
522 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
523 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
524
525 /*
526 * Delay is required for PSTATE to correctly reflect
527 * DLEV/CLEV values after PADEN is set.
528 */
529 usleep_range(50, 100);
530 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_PSTATE);
531 if ((reg & PSTATE_DATI) || !(reg & PSTATE_DLEV_DAT0))
532 ret = true;
533
534 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
535 reg &= ~(CON_CLKEXTFREE | CON_PADEN);
536 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
537
538 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
539 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
540 enable_irq(host->irq);
541
542 return ret;
543}
544
545static int sdhci_omap_start_signal_voltage_switch(struct mmc_host *mmc,
546 struct mmc_ios *ios)
547{
548 u32 reg;
549 int ret;
550 unsigned int iov;
551 struct sdhci_host *host = mmc_priv(mmc);
552 struct sdhci_pltfm_host *pltfm_host;
553 struct sdhci_omap_host *omap_host;
554 struct device *dev;
555
556 pltfm_host = sdhci_priv(host);
557 omap_host = sdhci_pltfm_priv(pltfm_host);
558 dev = omap_host->dev;
559
560 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
561 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
562 if (!(reg & (CAPA_VS30 | CAPA_VS33)))
563 return -EOPNOTSUPP;
564
565 if (reg & CAPA_VS30)
566 iov = IOV_3V0;
567 else
568 iov = IOV_3V3;
569
570 sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage);
571
572 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
573 reg &= ~AC12_V1V8_SIGEN;
574 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
575
576 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
577 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
578 if (!(reg & CAPA_VS18))
579 return -EOPNOTSUPP;
580
581 iov = IOV_1V8;
582
583 sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage);
584
585 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
586 reg |= AC12_V1V8_SIGEN;
587 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
588 } else {
589 return -EOPNOTSUPP;
590 }
591
592 ret = sdhci_omap_enable_iov(omap_host, iov);
593 if (ret) {
594 dev_err(dev, "failed to switch IO voltage to %dmV\n", iov);
595 return ret;
596 }
597
598 dev_dbg(dev, "IO voltage switched to %dmV\n", iov);
599 return 0;
600}
601
602static void sdhci_omap_set_timing(struct sdhci_omap_host *omap_host, u8 timing)
603{
604 int ret;
605 struct pinctrl_state *pinctrl_state;
606 struct device *dev = omap_host->dev;
607
608 if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY))
609 return;
610
611 if (omap_host->timing == timing)
612 return;
613
614 sdhci_omap_stop_clock(omap_host);
615
616 pinctrl_state = omap_host->pinctrl_state[timing];
617 ret = pinctrl_select_state(omap_host->pinctrl, pinctrl_state);
618 if (ret) {
619 dev_err(dev, "failed to select pinctrl state\n");
620 return;
621 }
622
623 sdhci_omap_start_clock(omap_host);
624 omap_host->timing = timing;
625}
626
627static void sdhci_omap_set_power_mode(struct sdhci_omap_host *omap_host,
628 u8 power_mode)
629{
630 if (omap_host->bus_mode == MMC_POWER_OFF)
631 sdhci_omap_disable_tuning(omap_host);
632 omap_host->power_mode = power_mode;
633}
634
635static void sdhci_omap_set_bus_mode(struct sdhci_omap_host *omap_host,
636 unsigned int mode)
637{
638 u32 reg;
639
640 if (omap_host->bus_mode == mode)
641 return;
642
643 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
644 if (mode == MMC_BUSMODE_OPENDRAIN)
645 reg |= CON_OD;
646 else
647 reg &= ~CON_OD;
648 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
649
650 omap_host->bus_mode = mode;
651}
652
653static void sdhci_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
654{
655 struct sdhci_host *host = mmc_priv(mmc);
656 struct sdhci_pltfm_host *pltfm_host;
657 struct sdhci_omap_host *omap_host;
658
659 pltfm_host = sdhci_priv(host);
660 omap_host = sdhci_pltfm_priv(pltfm_host);
661
662 sdhci_omap_set_bus_mode(omap_host, ios->bus_mode);
663 sdhci_omap_set_timing(omap_host, ios->timing);
664 sdhci_set_ios(mmc, ios);
665 sdhci_omap_set_power_mode(omap_host, ios->power_mode);
666}
667
668static u16 sdhci_omap_calc_divisor(struct sdhci_pltfm_host *host,
669 unsigned int clock)
670{
671 u16 dsor;
672
673 dsor = DIV_ROUND_UP(clk_get_rate(host->clk), clock);
674 if (dsor > SYSCTL_CLKD_MAX)
675 dsor = SYSCTL_CLKD_MAX;
676
677 return dsor;
678}
679
680static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host)
681{
682 u32 reg;
683
684 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
685 reg |= SYSCTL_CEN;
686 sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg);
687}
688
689static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host)
690{
691 u32 reg;
692
693 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
694 reg &= ~SYSCTL_CEN;
695 sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg);
696}
697
698static void sdhci_omap_set_clock(struct sdhci_host *host, unsigned int clock)
699{
700 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
701 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
702 unsigned long clkdiv;
703
704 sdhci_omap_stop_clock(omap_host);
705
706 if (!clock)
707 return;
708
709 clkdiv = sdhci_omap_calc_divisor(pltfm_host, clock);
710 clkdiv = (clkdiv & SYSCTL_CLKD_MASK) << SYSCTL_CLKD_SHIFT;
711 sdhci_enable_clk(host, clkdiv);
712
713 sdhci_omap_start_clock(omap_host);
714}
715
716static void sdhci_omap_set_power(struct sdhci_host *host, unsigned char mode,
717 unsigned short vdd)
718{
719 struct mmc_host *mmc = host->mmc;
720
721 if (!IS_ERR(mmc->supply.vmmc))
722 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
723}
724
725/*
726 * MMCHS_HL_HWINFO has the MADMA_EN bit set if the controller instance
727 * is connected to L3 interconnect and is bus master capable. Note that
728 * the MMCHS_HL_HWINFO register is in the module registers before the
729 * omap registers and sdhci registers. The offset can vary for omap
730 * registers depending on the SoC. Do not use sdhci_omap_readl() here.
731 */
732static bool sdhci_omap_has_adma(struct sdhci_omap_host *omap_host, int offset)
733{
734 /* MMCHS_HL_HWINFO register is only available on omap4 and later */
735 if (offset < 0x200)
736 return false;
737
738 return readl(omap_host->base + 4) & 1;
739}
740
741static int sdhci_omap_enable_dma(struct sdhci_host *host)
742{
743 u32 reg;
744 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
745 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
746
747 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
748 reg &= ~CON_DMA_MASTER;
749 /* Switch to DMA slave mode when using external DMA */
750 if (!host->use_external_dma)
751 reg |= CON_DMA_MASTER;
752
753 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
754
755 return 0;
756}
757
758static unsigned int sdhci_omap_get_min_clock(struct sdhci_host *host)
759{
760 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
761
762 return clk_get_rate(pltfm_host->clk) / SYSCTL_CLKD_MAX;
763}
764
765static void sdhci_omap_set_bus_width(struct sdhci_host *host, int width)
766{
767 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
768 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
769 u32 reg;
770
771 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
772 if (width == MMC_BUS_WIDTH_8)
773 reg |= CON_DW8;
774 else
775 reg &= ~CON_DW8;
776 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
777
778 sdhci_set_bus_width(host, width);
779}
780
781static void sdhci_omap_init_74_clocks(struct sdhci_host *host, u8 power_mode)
782{
783 u32 reg;
784 ktime_t timeout;
785 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
786 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
787
788 if (omap_host->power_mode == power_mode)
789 return;
790
791 if (power_mode != MMC_POWER_ON)
792 return;
793
794 disable_irq(host->irq);
795
796 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
797 reg |= CON_INIT;
798 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
799 sdhci_omap_writel(omap_host, SDHCI_OMAP_CMD, 0x0);
800
801 /* wait 1ms */
802 timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT);
803 while (1) {
804 bool timedout = ktime_after(ktime_get(), timeout);
805
806 if (sdhci_omap_readl(omap_host, SDHCI_OMAP_STAT) & INT_CC_EN)
807 break;
808 if (WARN_ON(timedout))
809 return;
810 usleep_range(5, 10);
811 }
812
813 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
814 reg &= ~CON_INIT;
815 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
816 sdhci_omap_writel(omap_host, SDHCI_OMAP_STAT, INT_CC_EN);
817
818 enable_irq(host->irq);
819}
820
821static void sdhci_omap_set_uhs_signaling(struct sdhci_host *host,
822 unsigned int timing)
823{
824 u32 reg;
825 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
826 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
827
828 sdhci_omap_stop_clock(omap_host);
829
830 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
831 if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52)
832 reg |= CON_DDR;
833 else
834 reg &= ~CON_DDR;
835 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
836
837 sdhci_set_uhs_signaling(host, timing);
838 sdhci_omap_start_clock(omap_host);
839}
840
841#define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */
842static void sdhci_omap_reset(struct sdhci_host *host, u8 mask)
843{
844 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
845 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
846 unsigned long limit = MMC_TIMEOUT_US;
847 unsigned long i = 0;
848 u32 sysc;
849
850 /* Save target module sysconfig configured by SoC PM layer */
851 if (mask & SDHCI_RESET_ALL)
852 sysc = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCONFIG);
853
854 /* Don't reset data lines during tuning operation */
855 if (omap_host->is_tuning)
856 mask &= ~SDHCI_RESET_DATA;
857
858 if (omap_host->flags & SDHCI_OMAP_SPECIAL_RESET) {
859 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
860 while ((!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask)) &&
861 (i++ < limit))
862 udelay(1);
863 i = 0;
864 while ((sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) &&
865 (i++ < limit))
866 udelay(1);
867
868 if (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask)
869 dev_err(mmc_dev(host->mmc),
870 "Timeout waiting on controller reset in %s\n",
871 __func__);
872
873 goto restore_sysc;
874 }
875
876 sdhci_reset(host, mask);
877
878restore_sysc:
879 if (mask & SDHCI_RESET_ALL)
880 sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCONFIG, sysc);
881}
882
883#define CMD_ERR_MASK (SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX |\
884 SDHCI_INT_TIMEOUT)
885#define CMD_MASK (CMD_ERR_MASK | SDHCI_INT_RESPONSE)
886
887static u32 sdhci_omap_irq(struct sdhci_host *host, u32 intmask)
888{
889 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
890 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
891
892 if (omap_host->is_tuning && host->cmd && !host->data_early &&
893 (intmask & CMD_ERR_MASK)) {
894
895 /*
896 * Since we are not resetting data lines during tuning
897 * operation, data error or data complete interrupts
898 * might still arrive. Mark this request as a failure
899 * but still wait for the data interrupt
900 */
901 if (intmask & SDHCI_INT_TIMEOUT)
902 host->cmd->error = -ETIMEDOUT;
903 else
904 host->cmd->error = -EILSEQ;
905
906 host->cmd = NULL;
907
908 /*
909 * Sometimes command error interrupts and command complete
910 * interrupt will arrive together. Clear all command related
911 * interrupts here.
912 */
913 sdhci_writel(host, intmask & CMD_MASK, SDHCI_INT_STATUS);
914 intmask &= ~CMD_MASK;
915 }
916
917 return intmask;
918}
919
920static void sdhci_omap_set_timeout(struct sdhci_host *host,
921 struct mmc_command *cmd)
922{
923 if (cmd->opcode == MMC_ERASE)
924 sdhci_set_data_timeout_irq(host, false);
925
926 __sdhci_set_timeout(host, cmd);
927}
928
929static struct sdhci_ops sdhci_omap_ops = {
930 .set_clock = sdhci_omap_set_clock,
931 .set_power = sdhci_omap_set_power,
932 .enable_dma = sdhci_omap_enable_dma,
933 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
934 .get_min_clock = sdhci_omap_get_min_clock,
935 .set_bus_width = sdhci_omap_set_bus_width,
936 .platform_send_init_74_clocks = sdhci_omap_init_74_clocks,
937 .reset = sdhci_omap_reset,
938 .set_uhs_signaling = sdhci_omap_set_uhs_signaling,
939 .irq = sdhci_omap_irq,
940 .set_timeout = sdhci_omap_set_timeout,
941};
942
943static unsigned int sdhci_omap_regulator_get_caps(struct device *dev,
944 const char *name)
945{
946 struct regulator *reg;
947 unsigned int caps = 0;
948
949 reg = regulator_get(dev, name);
950 if (IS_ERR(reg))
951 return ~0U;
952
953 if (regulator_is_supported_voltage(reg, 1700000, 1950000))
954 caps |= SDHCI_CAN_VDD_180;
955 if (regulator_is_supported_voltage(reg, 2700000, 3150000))
956 caps |= SDHCI_CAN_VDD_300;
957 if (regulator_is_supported_voltage(reg, 3150000, 3600000))
958 caps |= SDHCI_CAN_VDD_330;
959
960 regulator_put(reg);
961
962 return caps;
963}
964
965static int sdhci_omap_set_capabilities(struct sdhci_host *host)
966{
967 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
968 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
969 struct device *dev = omap_host->dev;
970 const u32 mask = SDHCI_CAN_VDD_180 | SDHCI_CAN_VDD_300 | SDHCI_CAN_VDD_330;
971 unsigned int pbias, vqmmc, caps = 0;
972 u32 reg;
973
974 pbias = sdhci_omap_regulator_get_caps(dev, "pbias");
975 vqmmc = sdhci_omap_regulator_get_caps(dev, "vqmmc");
976 caps = pbias & vqmmc;
977
978 if (pbias != ~0U && vqmmc == ~0U)
979 dev_warn(dev, "vqmmc regulator missing for pbias\n");
980 else if (caps == ~0U)
981 return 0;
982
983 /*
984 * Quirk handling to allow 3.0V vqmmc with a valid 3.3V PBIAS. This is
985 * needed for 3.0V ldo9_reg on omap5 at least.
986 */
987 if (pbias != ~0U && (pbias & SDHCI_CAN_VDD_330) &&
988 (vqmmc & SDHCI_CAN_VDD_300))
989 caps |= SDHCI_CAN_VDD_330;
990
991 /* voltage capabilities might be set by boot loader, clear it */
992 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
993 reg &= ~(CAPA_VS18 | CAPA_VS30 | CAPA_VS33);
994
995 if (caps & SDHCI_CAN_VDD_180)
996 reg |= CAPA_VS18;
997
998 if (caps & SDHCI_CAN_VDD_300)
999 reg |= CAPA_VS30;
1000
1001 if (caps & SDHCI_CAN_VDD_330)
1002 reg |= CAPA_VS33;
1003
1004 sdhci_omap_writel(omap_host, SDHCI_OMAP_CAPA, reg);
1005
1006 host->caps &= ~mask;
1007 host->caps |= caps;
1008
1009 return 0;
1010}
1011
1012static const struct sdhci_pltfm_data sdhci_omap_pdata = {
1013 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
1014 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
1015 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1016 SDHCI_QUIRK_NO_HISPD_BIT |
1017 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
1018 .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN |
1019 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1020 SDHCI_QUIRK2_RSP_136_HAS_CRC |
1021 SDHCI_QUIRK2_DISABLE_HW_TIMEOUT,
1022 .ops = &sdhci_omap_ops,
1023};
1024
1025static const struct sdhci_omap_data omap2430_data = {
1026 .omap_offset = 0,
1027 .offset = 0x100,
1028};
1029
1030static const struct sdhci_omap_data omap3_data = {
1031 .omap_offset = 0,
1032 .offset = 0x100,
1033};
1034
1035static const struct sdhci_omap_data omap4_data = {
1036 .omap_offset = 0x100,
1037 .offset = 0x200,
1038 .flags = SDHCI_OMAP_SPECIAL_RESET,
1039};
1040
1041static const struct sdhci_omap_data omap5_data = {
1042 .omap_offset = 0x100,
1043 .offset = 0x200,
1044 .flags = SDHCI_OMAP_SPECIAL_RESET,
1045};
1046
1047static const struct sdhci_omap_data k2g_data = {
1048 .omap_offset = 0x100,
1049 .offset = 0x200,
1050};
1051
1052static const struct sdhci_omap_data am335_data = {
1053 .omap_offset = 0x100,
1054 .offset = 0x200,
1055 .flags = SDHCI_OMAP_SPECIAL_RESET,
1056};
1057
1058static const struct sdhci_omap_data am437_data = {
1059 .omap_offset = 0x100,
1060 .offset = 0x200,
1061 .flags = SDHCI_OMAP_SPECIAL_RESET,
1062};
1063
1064static const struct sdhci_omap_data dra7_data = {
1065 .omap_offset = 0x100,
1066 .offset = 0x200,
1067 .flags = SDHCI_OMAP_REQUIRE_IODELAY,
1068};
1069
1070static const struct of_device_id omap_sdhci_match[] = {
1071 { .compatible = "ti,omap2430-sdhci", .data = &omap2430_data },
1072 { .compatible = "ti,omap3-sdhci", .data = &omap3_data },
1073 { .compatible = "ti,omap4-sdhci", .data = &omap4_data },
1074 { .compatible = "ti,omap5-sdhci", .data = &omap5_data },
1075 { .compatible = "ti,dra7-sdhci", .data = &dra7_data },
1076 { .compatible = "ti,k2g-sdhci", .data = &k2g_data },
1077 { .compatible = "ti,am335-sdhci", .data = &am335_data },
1078 { .compatible = "ti,am437-sdhci", .data = &am437_data },
1079 {},
1080};
1081MODULE_DEVICE_TABLE(of, omap_sdhci_match);
1082
1083static struct pinctrl_state
1084*sdhci_omap_iodelay_pinctrl_state(struct sdhci_omap_host *omap_host, char *mode,
1085 u32 *caps, u32 capmask)
1086{
1087 struct device *dev = omap_host->dev;
1088 char *version = omap_host->version;
1089 struct pinctrl_state *pinctrl_state = ERR_PTR(-ENODEV);
1090 char str[20];
1091
1092 if (!(*caps & capmask))
1093 goto ret;
1094
1095 if (version) {
1096 snprintf(str, 20, "%s-%s", mode, version);
1097 pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, str);
1098 }
1099
1100 if (IS_ERR(pinctrl_state))
1101 pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, mode);
1102
1103 if (IS_ERR(pinctrl_state)) {
1104 dev_err(dev, "no pinctrl state for %s mode", mode);
1105 *caps &= ~capmask;
1106 }
1107
1108ret:
1109 return pinctrl_state;
1110}
1111
1112static int sdhci_omap_config_iodelay_pinctrl_state(struct sdhci_omap_host
1113 *omap_host)
1114{
1115 struct device *dev = omap_host->dev;
1116 struct sdhci_host *host = omap_host->host;
1117 struct mmc_host *mmc = host->mmc;
1118 u32 *caps = &mmc->caps;
1119 u32 *caps2 = &mmc->caps2;
1120 struct pinctrl_state *state;
1121 struct pinctrl_state **pinctrl_state;
1122
1123 if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY))
1124 return 0;
1125
1126 pinctrl_state = devm_kcalloc(dev,
1127 MMC_TIMING_MMC_HS200 + 1,
1128 sizeof(*pinctrl_state),
1129 GFP_KERNEL);
1130 if (!pinctrl_state)
1131 return -ENOMEM;
1132
1133 omap_host->pinctrl = devm_pinctrl_get(omap_host->dev);
1134 if (IS_ERR(omap_host->pinctrl)) {
1135 dev_err(dev, "Cannot get pinctrl\n");
1136 return PTR_ERR(omap_host->pinctrl);
1137 }
1138
1139 state = pinctrl_lookup_state(omap_host->pinctrl, "default");
1140 if (IS_ERR(state)) {
1141 dev_err(dev, "no pinctrl state for default mode\n");
1142 return PTR_ERR(state);
1143 }
1144 pinctrl_state[MMC_TIMING_LEGACY] = state;
1145
1146 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr104", caps,
1147 MMC_CAP_UHS_SDR104);
1148 if (!IS_ERR(state))
1149 pinctrl_state[MMC_TIMING_UHS_SDR104] = state;
1150
1151 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr50", caps,
1152 MMC_CAP_UHS_DDR50);
1153 if (!IS_ERR(state))
1154 pinctrl_state[MMC_TIMING_UHS_DDR50] = state;
1155
1156 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr50", caps,
1157 MMC_CAP_UHS_SDR50);
1158 if (!IS_ERR(state))
1159 pinctrl_state[MMC_TIMING_UHS_SDR50] = state;
1160
1161 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr25", caps,
1162 MMC_CAP_UHS_SDR25);
1163 if (!IS_ERR(state))
1164 pinctrl_state[MMC_TIMING_UHS_SDR25] = state;
1165
1166 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr12", caps,
1167 MMC_CAP_UHS_SDR12);
1168 if (!IS_ERR(state))
1169 pinctrl_state[MMC_TIMING_UHS_SDR12] = state;
1170
1171 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_1_8v", caps,
1172 MMC_CAP_1_8V_DDR);
1173 if (!IS_ERR(state)) {
1174 pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
1175 } else {
1176 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_3_3v",
1177 caps,
1178 MMC_CAP_3_3V_DDR);
1179 if (!IS_ERR(state))
1180 pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
1181 }
1182
1183 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
1184 MMC_CAP_SD_HIGHSPEED);
1185 if (!IS_ERR(state))
1186 pinctrl_state[MMC_TIMING_SD_HS] = state;
1187
1188 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
1189 MMC_CAP_MMC_HIGHSPEED);
1190 if (!IS_ERR(state))
1191 pinctrl_state[MMC_TIMING_MMC_HS] = state;
1192
1193 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs200_1_8v", caps2,
1194 MMC_CAP2_HS200_1_8V_SDR);
1195 if (!IS_ERR(state))
1196 pinctrl_state[MMC_TIMING_MMC_HS200] = state;
1197
1198 omap_host->pinctrl_state = pinctrl_state;
1199
1200 return 0;
1201}
1202
1203static const struct soc_device_attribute sdhci_omap_soc_devices[] = {
1204 {
1205 .machine = "DRA7[45]*",
1206 .revision = "ES1.[01]",
1207 },
1208 {
1209 /* sentinel */
1210 }
1211};
1212
1213static int sdhci_omap_probe(struct platform_device *pdev)
1214{
1215 int ret;
1216 u32 offset;
1217 struct device *dev = &pdev->dev;
1218 struct sdhci_host *host;
1219 struct sdhci_pltfm_host *pltfm_host;
1220 struct sdhci_omap_host *omap_host;
1221 struct mmc_host *mmc;
1222 const struct sdhci_omap_data *data;
1223 const struct soc_device_attribute *soc;
1224 struct resource *regs;
1225
1226 data = of_device_get_match_data(&pdev->dev);
1227 if (!data) {
1228 dev_err(dev, "no sdhci omap data\n");
1229 return -EINVAL;
1230 }
1231 offset = data->offset;
1232
1233 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1234 if (!regs)
1235 return -ENXIO;
1236
1237 host = sdhci_pltfm_init(pdev, &sdhci_omap_pdata,
1238 sizeof(*omap_host));
1239 if (IS_ERR(host)) {
1240 dev_err(dev, "Failed sdhci_pltfm_init\n");
1241 return PTR_ERR(host);
1242 }
1243
1244 pltfm_host = sdhci_priv(host);
1245 omap_host = sdhci_pltfm_priv(pltfm_host);
1246 omap_host->host = host;
1247 omap_host->base = host->ioaddr;
1248 omap_host->dev = dev;
1249 omap_host->power_mode = MMC_POWER_UNDEFINED;
1250 omap_host->timing = MMC_TIMING_LEGACY;
1251 omap_host->flags = data->flags;
1252 omap_host->omap_offset = data->omap_offset;
1253 omap_host->con = -EINVAL; /* Prevent invalid restore on first resume */
1254 host->ioaddr += offset;
1255 host->mapbase = regs->start + offset;
1256
1257 mmc = host->mmc;
1258 sdhci_get_of_property(pdev);
1259 ret = mmc_of_parse(mmc);
1260 if (ret)
1261 goto err_pltfm_free;
1262
1263 soc = soc_device_match(sdhci_omap_soc_devices);
1264 if (soc) {
1265 omap_host->version = "rev11";
1266 if (!strcmp(dev_name(dev), "4809c000.mmc"))
1267 mmc->f_max = 96000000;
1268 if (!strcmp(dev_name(dev), "480b4000.mmc"))
1269 mmc->f_max = 48000000;
1270 if (!strcmp(dev_name(dev), "480ad000.mmc"))
1271 mmc->f_max = 48000000;
1272 }
1273
1274 if (!mmc_can_gpio_ro(mmc))
1275 mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
1276
1277 pltfm_host->clk = devm_clk_get(dev, "fck");
1278 if (IS_ERR(pltfm_host->clk)) {
1279 ret = PTR_ERR(pltfm_host->clk);
1280 goto err_pltfm_free;
1281 }
1282
1283 ret = clk_set_rate(pltfm_host->clk, mmc->f_max);
1284 if (ret) {
1285 dev_err(dev, "failed to set clock to %d\n", mmc->f_max);
1286 goto err_pltfm_free;
1287 }
1288
1289 omap_host->pbias = devm_regulator_get_optional(dev, "pbias");
1290 if (IS_ERR(omap_host->pbias)) {
1291 ret = PTR_ERR(omap_host->pbias);
1292 if (ret != -ENODEV)
1293 goto err_pltfm_free;
1294 dev_dbg(dev, "unable to get pbias regulator %d\n", ret);
1295 }
1296 omap_host->pbias_enabled = false;
1297
1298 /*
1299 * omap_device_pm_domain has callbacks to enable the main
1300 * functional clock, interface clock and also configure the
1301 * SYSCONFIG register to clear any boot loader set voltage
1302 * capabilities before calling sdhci_setup_host(). The
1303 * callback will be invoked as part of pm_runtime_get_sync.
1304 */
1305 pm_runtime_use_autosuspend(dev);
1306 pm_runtime_set_autosuspend_delay(dev, 50);
1307 pm_runtime_enable(dev);
1308 ret = pm_runtime_resume_and_get(dev);
1309 if (ret) {
1310 dev_err(dev, "pm_runtime_get_sync failed\n");
1311 goto err_rpm_disable;
1312 }
1313
1314 ret = sdhci_omap_set_capabilities(host);
1315 if (ret) {
1316 dev_err(dev, "failed to set system capabilities\n");
1317 goto err_rpm_put;
1318 }
1319
1320 host->mmc_host_ops.start_signal_voltage_switch =
1321 sdhci_omap_start_signal_voltage_switch;
1322 host->mmc_host_ops.set_ios = sdhci_omap_set_ios;
1323 host->mmc_host_ops.card_busy = sdhci_omap_card_busy;
1324 host->mmc_host_ops.execute_tuning = sdhci_omap_execute_tuning;
1325 host->mmc_host_ops.enable_sdio_irq = sdhci_omap_enable_sdio_irq;
1326
1327 /*
1328 * Switch to external DMA only if there is the "dmas" property and
1329 * ADMA is not available on the controller instance.
1330 */
1331 if (device_property_present(dev, "dmas") &&
1332 !sdhci_omap_has_adma(omap_host, offset))
1333 sdhci_switch_external_dma(host, true);
1334
1335 if (device_property_read_bool(dev, "ti,non-removable")) {
1336 dev_warn_once(dev, "using old ti,non-removable property\n");
1337 mmc->caps |= MMC_CAP_NONREMOVABLE;
1338 }
1339
1340 /* R1B responses is required to properly manage HW busy detection. */
1341 mmc->caps |= MMC_CAP_NEED_RSP_BUSY;
1342
1343 /* Allow card power off and runtime PM for eMMC/SD card devices */
1344 mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_AGGRESSIVE_PM;
1345
1346 ret = sdhci_setup_host(host);
1347 if (ret)
1348 goto err_rpm_put;
1349
1350 ret = sdhci_omap_config_iodelay_pinctrl_state(omap_host);
1351 if (ret)
1352 goto err_cleanup_host;
1353
1354 ret = __sdhci_add_host(host);
1355 if (ret)
1356 goto err_cleanup_host;
1357
1358 /*
1359 * SDIO devices can use the dat1 pin as a wake-up interrupt. Some
1360 * devices like wl1xxx, use an out-of-band GPIO interrupt instead.
1361 */
1362 omap_host->wakeirq = of_irq_get_byname(dev->of_node, "wakeup");
1363 if (omap_host->wakeirq == -EPROBE_DEFER) {
1364 ret = -EPROBE_DEFER;
1365 goto err_cleanup_host;
1366 }
1367 if (omap_host->wakeirq > 0) {
1368 device_init_wakeup(dev, true);
1369 ret = dev_pm_set_dedicated_wake_irq(dev, omap_host->wakeirq);
1370 if (ret) {
1371 device_init_wakeup(dev, false);
1372 goto err_cleanup_host;
1373 }
1374 host->mmc->pm_caps |= MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
1375 }
1376
1377 pm_runtime_mark_last_busy(dev);
1378 pm_runtime_put_autosuspend(dev);
1379
1380 return 0;
1381
1382err_cleanup_host:
1383 sdhci_cleanup_host(host);
1384
1385err_rpm_put:
1386 pm_runtime_mark_last_busy(dev);
1387 pm_runtime_put_autosuspend(dev);
1388err_rpm_disable:
1389 pm_runtime_dont_use_autosuspend(dev);
1390 pm_runtime_disable(dev);
1391
1392err_pltfm_free:
1393 sdhci_pltfm_free(pdev);
1394 return ret;
1395}
1396
1397static int sdhci_omap_remove(struct platform_device *pdev)
1398{
1399 struct device *dev = &pdev->dev;
1400 struct sdhci_host *host = platform_get_drvdata(pdev);
1401
1402 pm_runtime_get_sync(dev);
1403 sdhci_remove_host(host, true);
1404 device_init_wakeup(dev, false);
1405 dev_pm_clear_wake_irq(dev);
1406 pm_runtime_dont_use_autosuspend(dev);
1407 pm_runtime_put_sync(dev);
1408 /* Ensure device gets disabled despite userspace sysfs config */
1409 pm_runtime_force_suspend(dev);
1410 sdhci_pltfm_free(pdev);
1411
1412 return 0;
1413}
1414
1415#ifdef CONFIG_PM
1416static void __maybe_unused sdhci_omap_context_save(struct sdhci_omap_host *omap_host)
1417{
1418 omap_host->con = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
1419 omap_host->hctl = sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL);
1420 omap_host->sysctl = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
1421 omap_host->capa = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
1422 omap_host->ie = sdhci_omap_readl(omap_host, SDHCI_OMAP_IE);
1423 omap_host->ise = sdhci_omap_readl(omap_host, SDHCI_OMAP_ISE);
1424}
1425
1426/* Order matters here, HCTL must be restored in two phases */
1427static void __maybe_unused sdhci_omap_context_restore(struct sdhci_omap_host *omap_host)
1428{
1429 sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, omap_host->hctl);
1430 sdhci_omap_writel(omap_host, SDHCI_OMAP_CAPA, omap_host->capa);
1431 sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, omap_host->hctl);
1432
1433 sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, omap_host->sysctl);
1434 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, omap_host->con);
1435 sdhci_omap_writel(omap_host, SDHCI_OMAP_IE, omap_host->ie);
1436 sdhci_omap_writel(omap_host, SDHCI_OMAP_ISE, omap_host->ise);
1437}
1438
1439static int __maybe_unused sdhci_omap_runtime_suspend(struct device *dev)
1440{
1441 struct sdhci_host *host = dev_get_drvdata(dev);
1442 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1443 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
1444
1445 if (omap_host->con != -EINVAL)
1446 sdhci_runtime_suspend_host(host);
1447
1448 sdhci_omap_context_save(omap_host);
1449
1450 pinctrl_pm_select_idle_state(dev);
1451
1452 return 0;
1453}
1454
1455static int __maybe_unused sdhci_omap_runtime_resume(struct device *dev)
1456{
1457 struct sdhci_host *host = dev_get_drvdata(dev);
1458 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1459 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
1460
1461 pinctrl_pm_select_default_state(dev);
1462
1463 if (omap_host->con != -EINVAL) {
1464 sdhci_omap_context_restore(omap_host);
1465 sdhci_runtime_resume_host(host, 0);
1466 }
1467
1468 return 0;
1469}
1470#endif
1471
1472static const struct dev_pm_ops sdhci_omap_dev_pm_ops = {
1473 SET_RUNTIME_PM_OPS(sdhci_omap_runtime_suspend,
1474 sdhci_omap_runtime_resume, NULL)
1475 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1476 pm_runtime_force_resume)
1477};
1478
1479static struct platform_driver sdhci_omap_driver = {
1480 .probe = sdhci_omap_probe,
1481 .remove = sdhci_omap_remove,
1482 .driver = {
1483 .name = "sdhci-omap",
1484 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1485 .pm = &sdhci_omap_dev_pm_ops,
1486 .of_match_table = omap_sdhci_match,
1487 },
1488};
1489
1490module_platform_driver(sdhci_omap_driver);
1491
1492MODULE_DESCRIPTION("SDHCI driver for OMAP SoCs");
1493MODULE_AUTHOR("Texas Instruments Inc.");
1494MODULE_LICENSE("GPL v2");
1495MODULE_ALIAS("platform:sdhci_omap");
1// SPDX-License-Identifier: GPL-2.0-only
2/**
3 * SDHCI Controller driver for TI's OMAP SoCs
4 *
5 * Copyright (C) 2017 Texas Instruments
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
7 */
8
9#include <linux/delay.h>
10#include <linux/mmc/mmc.h>
11#include <linux/mmc/slot-gpio.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/of_device.h>
15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17#include <linux/regulator/consumer.h>
18#include <linux/pinctrl/consumer.h>
19#include <linux/sys_soc.h>
20#include <linux/thermal.h>
21
22#include "sdhci-pltfm.h"
23
24#define SDHCI_OMAP_CON 0x12c
25#define CON_DW8 BIT(5)
26#define CON_DMA_MASTER BIT(20)
27#define CON_DDR BIT(19)
28#define CON_CLKEXTFREE BIT(16)
29#define CON_PADEN BIT(15)
30#define CON_CTPL BIT(11)
31#define CON_INIT BIT(1)
32#define CON_OD BIT(0)
33
34#define SDHCI_OMAP_DLL 0x0134
35#define DLL_SWT BIT(20)
36#define DLL_FORCE_SR_C_SHIFT 13
37#define DLL_FORCE_SR_C_MASK (0x7f << DLL_FORCE_SR_C_SHIFT)
38#define DLL_FORCE_VALUE BIT(12)
39#define DLL_CALIB BIT(1)
40
41#define SDHCI_OMAP_CMD 0x20c
42
43#define SDHCI_OMAP_PSTATE 0x0224
44#define PSTATE_DLEV_DAT0 BIT(20)
45#define PSTATE_DATI BIT(1)
46
47#define SDHCI_OMAP_HCTL 0x228
48#define HCTL_SDBP BIT(8)
49#define HCTL_SDVS_SHIFT 9
50#define HCTL_SDVS_MASK (0x7 << HCTL_SDVS_SHIFT)
51#define HCTL_SDVS_33 (0x7 << HCTL_SDVS_SHIFT)
52#define HCTL_SDVS_30 (0x6 << HCTL_SDVS_SHIFT)
53#define HCTL_SDVS_18 (0x5 << HCTL_SDVS_SHIFT)
54
55#define SDHCI_OMAP_SYSCTL 0x22c
56#define SYSCTL_CEN BIT(2)
57#define SYSCTL_CLKD_SHIFT 6
58#define SYSCTL_CLKD_MASK 0x3ff
59
60#define SDHCI_OMAP_STAT 0x230
61
62#define SDHCI_OMAP_IE 0x234
63#define INT_CC_EN BIT(0)
64
65#define SDHCI_OMAP_AC12 0x23c
66#define AC12_V1V8_SIGEN BIT(19)
67#define AC12_SCLK_SEL BIT(23)
68
69#define SDHCI_OMAP_CAPA 0x240
70#define CAPA_VS33 BIT(24)
71#define CAPA_VS30 BIT(25)
72#define CAPA_VS18 BIT(26)
73
74#define SDHCI_OMAP_CAPA2 0x0244
75#define CAPA2_TSDR50 BIT(13)
76
77#define SDHCI_OMAP_TIMEOUT 1 /* 1 msec */
78
79#define SYSCTL_CLKD_MAX 0x3FF
80
81#define IOV_1V8 1800000 /* 180000 uV */
82#define IOV_3V0 3000000 /* 300000 uV */
83#define IOV_3V3 3300000 /* 330000 uV */
84
85#define MAX_PHASE_DELAY 0x7C
86
87/* sdhci-omap controller flags */
88#define SDHCI_OMAP_REQUIRE_IODELAY BIT(0)
89#define SDHCI_OMAP_SPECIAL_RESET BIT(1)
90
91struct sdhci_omap_data {
92 u32 offset;
93 u8 flags;
94};
95
96struct sdhci_omap_host {
97 char *version;
98 void __iomem *base;
99 struct device *dev;
100 struct regulator *pbias;
101 bool pbias_enabled;
102 struct sdhci_host *host;
103 u8 bus_mode;
104 u8 power_mode;
105 u8 timing;
106 u8 flags;
107
108 struct pinctrl *pinctrl;
109 struct pinctrl_state **pinctrl_state;
110 bool is_tuning;
111 /* Omap specific context save */
112 u32 con;
113 u32 hctl;
114 u32 sysctl;
115 u32 capa;
116};
117
118static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host);
119static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host);
120
121static inline u32 sdhci_omap_readl(struct sdhci_omap_host *host,
122 unsigned int offset)
123{
124 return readl(host->base + offset);
125}
126
127static inline void sdhci_omap_writel(struct sdhci_omap_host *host,
128 unsigned int offset, u32 data)
129{
130 writel(data, host->base + offset);
131}
132
133static int sdhci_omap_set_pbias(struct sdhci_omap_host *omap_host,
134 bool power_on, unsigned int iov)
135{
136 int ret;
137 struct device *dev = omap_host->dev;
138
139 if (IS_ERR(omap_host->pbias))
140 return 0;
141
142 if (power_on) {
143 ret = regulator_set_voltage(omap_host->pbias, iov, iov);
144 if (ret) {
145 dev_err(dev, "pbias set voltage failed\n");
146 return ret;
147 }
148
149 if (omap_host->pbias_enabled)
150 return 0;
151
152 ret = regulator_enable(omap_host->pbias);
153 if (ret) {
154 dev_err(dev, "pbias reg enable fail\n");
155 return ret;
156 }
157
158 omap_host->pbias_enabled = true;
159 } else {
160 if (!omap_host->pbias_enabled)
161 return 0;
162
163 ret = regulator_disable(omap_host->pbias);
164 if (ret) {
165 dev_err(dev, "pbias reg disable fail\n");
166 return ret;
167 }
168 omap_host->pbias_enabled = false;
169 }
170
171 return 0;
172}
173
174static int sdhci_omap_enable_iov(struct sdhci_omap_host *omap_host,
175 unsigned int iov)
176{
177 int ret;
178 struct sdhci_host *host = omap_host->host;
179 struct mmc_host *mmc = host->mmc;
180
181 ret = sdhci_omap_set_pbias(omap_host, false, 0);
182 if (ret)
183 return ret;
184
185 if (!IS_ERR(mmc->supply.vqmmc)) {
186 ret = regulator_set_voltage(mmc->supply.vqmmc, iov, iov);
187 if (ret) {
188 dev_err(mmc_dev(mmc), "vqmmc set voltage failed\n");
189 return ret;
190 }
191 }
192
193 ret = sdhci_omap_set_pbias(omap_host, true, iov);
194 if (ret)
195 return ret;
196
197 return 0;
198}
199
200static void sdhci_omap_conf_bus_power(struct sdhci_omap_host *omap_host,
201 unsigned char signal_voltage)
202{
203 u32 reg;
204 ktime_t timeout;
205
206 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL);
207 reg &= ~HCTL_SDVS_MASK;
208
209 if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
210 reg |= HCTL_SDVS_33;
211 else
212 reg |= HCTL_SDVS_18;
213
214 sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg);
215
216 reg |= HCTL_SDBP;
217 sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg);
218
219 /* wait 1ms */
220 timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT);
221 while (1) {
222 bool timedout = ktime_after(ktime_get(), timeout);
223
224 if (sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL) & HCTL_SDBP)
225 break;
226 if (WARN_ON(timedout))
227 return;
228 usleep_range(5, 10);
229 }
230}
231
232static void sdhci_omap_enable_sdio_irq(struct mmc_host *mmc, int enable)
233{
234 struct sdhci_host *host = mmc_priv(mmc);
235 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
236 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
237 u32 reg;
238
239 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
240 if (enable)
241 reg |= (CON_CTPL | CON_CLKEXTFREE);
242 else
243 reg &= ~(CON_CTPL | CON_CLKEXTFREE);
244 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
245
246 sdhci_enable_sdio_irq(mmc, enable);
247}
248
249static inline void sdhci_omap_set_dll(struct sdhci_omap_host *omap_host,
250 int count)
251{
252 int i;
253 u32 reg;
254
255 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
256 reg |= DLL_FORCE_VALUE;
257 reg &= ~DLL_FORCE_SR_C_MASK;
258 reg |= (count << DLL_FORCE_SR_C_SHIFT);
259 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
260
261 reg |= DLL_CALIB;
262 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
263 for (i = 0; i < 1000; i++) {
264 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
265 if (reg & DLL_CALIB)
266 break;
267 }
268 reg &= ~DLL_CALIB;
269 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
270}
271
272static void sdhci_omap_disable_tuning(struct sdhci_omap_host *omap_host)
273{
274 u32 reg;
275
276 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
277 reg &= ~AC12_SCLK_SEL;
278 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
279
280 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
281 reg &= ~(DLL_FORCE_VALUE | DLL_SWT);
282 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
283}
284
285static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode)
286{
287 struct sdhci_host *host = mmc_priv(mmc);
288 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
289 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
290 struct thermal_zone_device *thermal_dev;
291 struct device *dev = omap_host->dev;
292 struct mmc_ios *ios = &mmc->ios;
293 u32 start_window = 0, max_window = 0;
294 bool single_point_failure = false;
295 bool dcrc_was_enabled = false;
296 u8 cur_match, prev_match = 0;
297 u32 length = 0, max_len = 0;
298 u32 phase_delay = 0;
299 int temperature;
300 int ret = 0;
301 u32 reg;
302 int i;
303
304 /* clock tuning is not needed for upto 52MHz */
305 if (ios->clock <= 52000000)
306 return 0;
307
308 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA2);
309 if (ios->timing == MMC_TIMING_UHS_SDR50 && !(reg & CAPA2_TSDR50))
310 return 0;
311
312 thermal_dev = thermal_zone_get_zone_by_name("cpu_thermal");
313 if (IS_ERR(thermal_dev)) {
314 dev_err(dev, "Unable to get thermal zone for tuning\n");
315 return PTR_ERR(thermal_dev);
316 }
317
318 ret = thermal_zone_get_temp(thermal_dev, &temperature);
319 if (ret)
320 return ret;
321
322 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
323 reg |= DLL_SWT;
324 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
325
326 /*
327 * OMAP5/DRA74X/DRA72x Errata i802:
328 * DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur
329 * during the tuning procedure. So disable it during the
330 * tuning procedure.
331 */
332 if (host->ier & SDHCI_INT_DATA_CRC) {
333 host->ier &= ~SDHCI_INT_DATA_CRC;
334 dcrc_was_enabled = true;
335 }
336
337 omap_host->is_tuning = true;
338
339 /*
340 * Stage 1: Search for a maximum pass window ignoring any
341 * any single point failures. If the tuning value ends up
342 * near it, move away from it in stage 2 below
343 */
344 while (phase_delay <= MAX_PHASE_DELAY) {
345 sdhci_omap_set_dll(omap_host, phase_delay);
346
347 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
348 if (cur_match) {
349 if (prev_match) {
350 length++;
351 } else if (single_point_failure) {
352 /* ignore single point failure */
353 length++;
354 } else {
355 start_window = phase_delay;
356 length = 1;
357 }
358 } else {
359 single_point_failure = prev_match;
360 }
361
362 if (length > max_len) {
363 max_window = start_window;
364 max_len = length;
365 }
366
367 prev_match = cur_match;
368 phase_delay += 4;
369 }
370
371 if (!max_len) {
372 dev_err(dev, "Unable to find match\n");
373 ret = -EIO;
374 goto tuning_error;
375 }
376
377 /*
378 * Assign tuning value as a ratio of maximum pass window based
379 * on temperature
380 */
381 if (temperature < -20000)
382 phase_delay = min(max_window + 4 * (max_len - 1) - 24,
383 max_window +
384 DIV_ROUND_UP(13 * max_len, 16) * 4);
385 else if (temperature < 20000)
386 phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4;
387 else if (temperature < 40000)
388 phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4;
389 else if (temperature < 70000)
390 phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4;
391 else if (temperature < 90000)
392 phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4;
393 else if (temperature < 120000)
394 phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4;
395 else
396 phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4;
397
398 /*
399 * Stage 2: Search for a single point failure near the chosen tuning
400 * value in two steps. First in the +3 to +10 range and then in the
401 * +2 to -10 range. If found, move away from it in the appropriate
402 * direction by the appropriate amount depending on the temperature.
403 */
404 for (i = 3; i <= 10; i++) {
405 sdhci_omap_set_dll(omap_host, phase_delay + i);
406
407 if (mmc_send_tuning(mmc, opcode, NULL)) {
408 if (temperature < 10000)
409 phase_delay += i + 6;
410 else if (temperature < 20000)
411 phase_delay += i - 12;
412 else if (temperature < 70000)
413 phase_delay += i - 8;
414 else
415 phase_delay += i - 6;
416
417 goto single_failure_found;
418 }
419 }
420
421 for (i = 2; i >= -10; i--) {
422 sdhci_omap_set_dll(omap_host, phase_delay + i);
423
424 if (mmc_send_tuning(mmc, opcode, NULL)) {
425 if (temperature < 10000)
426 phase_delay += i + 12;
427 else if (temperature < 20000)
428 phase_delay += i + 8;
429 else if (temperature < 70000)
430 phase_delay += i + 8;
431 else if (temperature < 90000)
432 phase_delay += i + 10;
433 else
434 phase_delay += i + 12;
435
436 goto single_failure_found;
437 }
438 }
439
440single_failure_found:
441 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
442 if (!(reg & AC12_SCLK_SEL)) {
443 ret = -EIO;
444 goto tuning_error;
445 }
446
447 sdhci_omap_set_dll(omap_host, phase_delay);
448
449 omap_host->is_tuning = false;
450
451 goto ret;
452
453tuning_error:
454 omap_host->is_tuning = false;
455 dev_err(dev, "Tuning failed\n");
456 sdhci_omap_disable_tuning(omap_host);
457
458ret:
459 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
460 /* Reenable forbidden interrupt */
461 if (dcrc_was_enabled)
462 host->ier |= SDHCI_INT_DATA_CRC;
463 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
464 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
465 return ret;
466}
467
468static int sdhci_omap_card_busy(struct mmc_host *mmc)
469{
470 u32 reg, ac12;
471 int ret = false;
472 struct sdhci_host *host = mmc_priv(mmc);
473 struct sdhci_pltfm_host *pltfm_host;
474 struct sdhci_omap_host *omap_host;
475 u32 ier = host->ier;
476
477 pltfm_host = sdhci_priv(host);
478 omap_host = sdhci_pltfm_priv(pltfm_host);
479
480 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
481 ac12 = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
482 reg &= ~CON_CLKEXTFREE;
483 if (ac12 & AC12_V1V8_SIGEN)
484 reg |= CON_CLKEXTFREE;
485 reg |= CON_PADEN;
486 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
487
488 disable_irq(host->irq);
489 ier |= SDHCI_INT_CARD_INT;
490 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
491 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
492
493 /*
494 * Delay is required for PSTATE to correctly reflect
495 * DLEV/CLEV values after PADEN is set.
496 */
497 usleep_range(50, 100);
498 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_PSTATE);
499 if ((reg & PSTATE_DATI) || !(reg & PSTATE_DLEV_DAT0))
500 ret = true;
501
502 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
503 reg &= ~(CON_CLKEXTFREE | CON_PADEN);
504 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
505
506 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
507 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
508 enable_irq(host->irq);
509
510 return ret;
511}
512
513static int sdhci_omap_start_signal_voltage_switch(struct mmc_host *mmc,
514 struct mmc_ios *ios)
515{
516 u32 reg;
517 int ret;
518 unsigned int iov;
519 struct sdhci_host *host = mmc_priv(mmc);
520 struct sdhci_pltfm_host *pltfm_host;
521 struct sdhci_omap_host *omap_host;
522 struct device *dev;
523
524 pltfm_host = sdhci_priv(host);
525 omap_host = sdhci_pltfm_priv(pltfm_host);
526 dev = omap_host->dev;
527
528 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
529 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
530 if (!(reg & CAPA_VS33))
531 return -EOPNOTSUPP;
532
533 sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage);
534
535 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
536 reg &= ~AC12_V1V8_SIGEN;
537 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
538
539 iov = IOV_3V3;
540 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
541 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
542 if (!(reg & CAPA_VS18))
543 return -EOPNOTSUPP;
544
545 sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage);
546
547 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
548 reg |= AC12_V1V8_SIGEN;
549 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
550
551 iov = IOV_1V8;
552 } else {
553 return -EOPNOTSUPP;
554 }
555
556 ret = sdhci_omap_enable_iov(omap_host, iov);
557 if (ret) {
558 dev_err(dev, "failed to switch IO voltage to %dmV\n", iov);
559 return ret;
560 }
561
562 dev_dbg(dev, "IO voltage switched to %dmV\n", iov);
563 return 0;
564}
565
566static void sdhci_omap_set_timing(struct sdhci_omap_host *omap_host, u8 timing)
567{
568 int ret;
569 struct pinctrl_state *pinctrl_state;
570 struct device *dev = omap_host->dev;
571
572 if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY))
573 return;
574
575 if (omap_host->timing == timing)
576 return;
577
578 sdhci_omap_stop_clock(omap_host);
579
580 pinctrl_state = omap_host->pinctrl_state[timing];
581 ret = pinctrl_select_state(omap_host->pinctrl, pinctrl_state);
582 if (ret) {
583 dev_err(dev, "failed to select pinctrl state\n");
584 return;
585 }
586
587 sdhci_omap_start_clock(omap_host);
588 omap_host->timing = timing;
589}
590
591static void sdhci_omap_set_power_mode(struct sdhci_omap_host *omap_host,
592 u8 power_mode)
593{
594 if (omap_host->bus_mode == MMC_POWER_OFF)
595 sdhci_omap_disable_tuning(omap_host);
596 omap_host->power_mode = power_mode;
597}
598
599static void sdhci_omap_set_bus_mode(struct sdhci_omap_host *omap_host,
600 unsigned int mode)
601{
602 u32 reg;
603
604 if (omap_host->bus_mode == mode)
605 return;
606
607 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
608 if (mode == MMC_BUSMODE_OPENDRAIN)
609 reg |= CON_OD;
610 else
611 reg &= ~CON_OD;
612 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
613
614 omap_host->bus_mode = mode;
615}
616
617static void sdhci_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
618{
619 struct sdhci_host *host = mmc_priv(mmc);
620 struct sdhci_pltfm_host *pltfm_host;
621 struct sdhci_omap_host *omap_host;
622
623 pltfm_host = sdhci_priv(host);
624 omap_host = sdhci_pltfm_priv(pltfm_host);
625
626 sdhci_omap_set_bus_mode(omap_host, ios->bus_mode);
627 sdhci_omap_set_timing(omap_host, ios->timing);
628 sdhci_set_ios(mmc, ios);
629 sdhci_omap_set_power_mode(omap_host, ios->power_mode);
630}
631
632static u16 sdhci_omap_calc_divisor(struct sdhci_pltfm_host *host,
633 unsigned int clock)
634{
635 u16 dsor;
636
637 dsor = DIV_ROUND_UP(clk_get_rate(host->clk), clock);
638 if (dsor > SYSCTL_CLKD_MAX)
639 dsor = SYSCTL_CLKD_MAX;
640
641 return dsor;
642}
643
644static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host)
645{
646 u32 reg;
647
648 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
649 reg |= SYSCTL_CEN;
650 sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg);
651}
652
653static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host)
654{
655 u32 reg;
656
657 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
658 reg &= ~SYSCTL_CEN;
659 sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg);
660}
661
662static void sdhci_omap_set_clock(struct sdhci_host *host, unsigned int clock)
663{
664 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
665 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
666 unsigned long clkdiv;
667
668 sdhci_omap_stop_clock(omap_host);
669
670 if (!clock)
671 return;
672
673 clkdiv = sdhci_omap_calc_divisor(pltfm_host, clock);
674 clkdiv = (clkdiv & SYSCTL_CLKD_MASK) << SYSCTL_CLKD_SHIFT;
675 sdhci_enable_clk(host, clkdiv);
676
677 sdhci_omap_start_clock(omap_host);
678}
679
680static void sdhci_omap_set_power(struct sdhci_host *host, unsigned char mode,
681 unsigned short vdd)
682{
683 struct mmc_host *mmc = host->mmc;
684
685 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
686}
687
688static int sdhci_omap_enable_dma(struct sdhci_host *host)
689{
690 u32 reg;
691 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
692 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
693
694 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
695 reg &= ~CON_DMA_MASTER;
696 /* Switch to DMA slave mode when using external DMA */
697 if (!host->use_external_dma)
698 reg |= CON_DMA_MASTER;
699
700 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
701
702 return 0;
703}
704
705static unsigned int sdhci_omap_get_min_clock(struct sdhci_host *host)
706{
707 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
708
709 return clk_get_rate(pltfm_host->clk) / SYSCTL_CLKD_MAX;
710}
711
712static void sdhci_omap_set_bus_width(struct sdhci_host *host, int width)
713{
714 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
715 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
716 u32 reg;
717
718 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
719 if (width == MMC_BUS_WIDTH_8)
720 reg |= CON_DW8;
721 else
722 reg &= ~CON_DW8;
723 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
724
725 sdhci_set_bus_width(host, width);
726}
727
728static void sdhci_omap_init_74_clocks(struct sdhci_host *host, u8 power_mode)
729{
730 u32 reg;
731 ktime_t timeout;
732 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
733 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
734
735 if (omap_host->power_mode == power_mode)
736 return;
737
738 if (power_mode != MMC_POWER_ON)
739 return;
740
741 disable_irq(host->irq);
742
743 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
744 reg |= CON_INIT;
745 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
746 sdhci_omap_writel(omap_host, SDHCI_OMAP_CMD, 0x0);
747
748 /* wait 1ms */
749 timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT);
750 while (1) {
751 bool timedout = ktime_after(ktime_get(), timeout);
752
753 if (sdhci_omap_readl(omap_host, SDHCI_OMAP_STAT) & INT_CC_EN)
754 break;
755 if (WARN_ON(timedout))
756 return;
757 usleep_range(5, 10);
758 }
759
760 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
761 reg &= ~CON_INIT;
762 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
763 sdhci_omap_writel(omap_host, SDHCI_OMAP_STAT, INT_CC_EN);
764
765 enable_irq(host->irq);
766}
767
768static void sdhci_omap_set_uhs_signaling(struct sdhci_host *host,
769 unsigned int timing)
770{
771 u32 reg;
772 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
773 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
774
775 sdhci_omap_stop_clock(omap_host);
776
777 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
778 if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52)
779 reg |= CON_DDR;
780 else
781 reg &= ~CON_DDR;
782 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
783
784 sdhci_set_uhs_signaling(host, timing);
785 sdhci_omap_start_clock(omap_host);
786}
787
788#define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */
789static void sdhci_omap_reset(struct sdhci_host *host, u8 mask)
790{
791 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
792 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
793 unsigned long limit = MMC_TIMEOUT_US;
794 unsigned long i = 0;
795
796 /* Don't reset data lines during tuning operation */
797 if (omap_host->is_tuning)
798 mask &= ~SDHCI_RESET_DATA;
799
800 if (omap_host->flags & SDHCI_OMAP_SPECIAL_RESET) {
801 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
802 while ((!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask)) &&
803 (i++ < limit))
804 udelay(1);
805 i = 0;
806 while ((sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) &&
807 (i++ < limit))
808 udelay(1);
809
810 if (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask)
811 dev_err(mmc_dev(host->mmc),
812 "Timeout waiting on controller reset in %s\n",
813 __func__);
814 return;
815 }
816
817 sdhci_reset(host, mask);
818}
819
820#define CMD_ERR_MASK (SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX |\
821 SDHCI_INT_TIMEOUT)
822#define CMD_MASK (CMD_ERR_MASK | SDHCI_INT_RESPONSE)
823
824static u32 sdhci_omap_irq(struct sdhci_host *host, u32 intmask)
825{
826 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
827 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
828
829 if (omap_host->is_tuning && host->cmd && !host->data_early &&
830 (intmask & CMD_ERR_MASK)) {
831
832 /*
833 * Since we are not resetting data lines during tuning
834 * operation, data error or data complete interrupts
835 * might still arrive. Mark this request as a failure
836 * but still wait for the data interrupt
837 */
838 if (intmask & SDHCI_INT_TIMEOUT)
839 host->cmd->error = -ETIMEDOUT;
840 else
841 host->cmd->error = -EILSEQ;
842
843 host->cmd = NULL;
844
845 /*
846 * Sometimes command error interrupts and command complete
847 * interrupt will arrive together. Clear all command related
848 * interrupts here.
849 */
850 sdhci_writel(host, intmask & CMD_MASK, SDHCI_INT_STATUS);
851 intmask &= ~CMD_MASK;
852 }
853
854 return intmask;
855}
856
857static void sdhci_omap_set_timeout(struct sdhci_host *host,
858 struct mmc_command *cmd)
859{
860 if (cmd->opcode == MMC_ERASE)
861 sdhci_set_data_timeout_irq(host, false);
862
863 __sdhci_set_timeout(host, cmd);
864}
865
866static struct sdhci_ops sdhci_omap_ops = {
867 .set_clock = sdhci_omap_set_clock,
868 .set_power = sdhci_omap_set_power,
869 .enable_dma = sdhci_omap_enable_dma,
870 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
871 .get_min_clock = sdhci_omap_get_min_clock,
872 .set_bus_width = sdhci_omap_set_bus_width,
873 .platform_send_init_74_clocks = sdhci_omap_init_74_clocks,
874 .reset = sdhci_omap_reset,
875 .set_uhs_signaling = sdhci_omap_set_uhs_signaling,
876 .irq = sdhci_omap_irq,
877 .set_timeout = sdhci_omap_set_timeout,
878};
879
880static int sdhci_omap_set_capabilities(struct sdhci_omap_host *omap_host)
881{
882 u32 reg;
883 int ret = 0;
884 struct device *dev = omap_host->dev;
885 struct regulator *vqmmc;
886
887 vqmmc = regulator_get(dev, "vqmmc");
888 if (IS_ERR(vqmmc)) {
889 ret = PTR_ERR(vqmmc);
890 goto reg_put;
891 }
892
893 /* voltage capabilities might be set by boot loader, clear it */
894 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
895 reg &= ~(CAPA_VS18 | CAPA_VS30 | CAPA_VS33);
896
897 if (regulator_is_supported_voltage(vqmmc, IOV_3V3, IOV_3V3))
898 reg |= CAPA_VS33;
899 if (regulator_is_supported_voltage(vqmmc, IOV_1V8, IOV_1V8))
900 reg |= CAPA_VS18;
901
902 sdhci_omap_writel(omap_host, SDHCI_OMAP_CAPA, reg);
903
904reg_put:
905 regulator_put(vqmmc);
906
907 return ret;
908}
909
910static const struct sdhci_pltfm_data sdhci_omap_pdata = {
911 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
912 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
913 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
914 SDHCI_QUIRK_NO_HISPD_BIT |
915 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
916 .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN |
917 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
918 SDHCI_QUIRK2_RSP_136_HAS_CRC |
919 SDHCI_QUIRK2_DISABLE_HW_TIMEOUT,
920 .ops = &sdhci_omap_ops,
921};
922
923static const struct sdhci_omap_data k2g_data = {
924 .offset = 0x200,
925};
926
927static const struct sdhci_omap_data am335_data = {
928 .offset = 0x200,
929 .flags = SDHCI_OMAP_SPECIAL_RESET,
930};
931
932static const struct sdhci_omap_data am437_data = {
933 .offset = 0x200,
934 .flags = SDHCI_OMAP_SPECIAL_RESET,
935};
936
937static const struct sdhci_omap_data dra7_data = {
938 .offset = 0x200,
939 .flags = SDHCI_OMAP_REQUIRE_IODELAY,
940};
941
942static const struct of_device_id omap_sdhci_match[] = {
943 { .compatible = "ti,dra7-sdhci", .data = &dra7_data },
944 { .compatible = "ti,k2g-sdhci", .data = &k2g_data },
945 { .compatible = "ti,am335-sdhci", .data = &am335_data },
946 { .compatible = "ti,am437-sdhci", .data = &am437_data },
947 {},
948};
949MODULE_DEVICE_TABLE(of, omap_sdhci_match);
950
951static struct pinctrl_state
952*sdhci_omap_iodelay_pinctrl_state(struct sdhci_omap_host *omap_host, char *mode,
953 u32 *caps, u32 capmask)
954{
955 struct device *dev = omap_host->dev;
956 char *version = omap_host->version;
957 struct pinctrl_state *pinctrl_state = ERR_PTR(-ENODEV);
958 char str[20];
959
960 if (!(*caps & capmask))
961 goto ret;
962
963 if (version) {
964 snprintf(str, 20, "%s-%s", mode, version);
965 pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, str);
966 }
967
968 if (IS_ERR(pinctrl_state))
969 pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, mode);
970
971 if (IS_ERR(pinctrl_state)) {
972 dev_err(dev, "no pinctrl state for %s mode", mode);
973 *caps &= ~capmask;
974 }
975
976ret:
977 return pinctrl_state;
978}
979
980static int sdhci_omap_config_iodelay_pinctrl_state(struct sdhci_omap_host
981 *omap_host)
982{
983 struct device *dev = omap_host->dev;
984 struct sdhci_host *host = omap_host->host;
985 struct mmc_host *mmc = host->mmc;
986 u32 *caps = &mmc->caps;
987 u32 *caps2 = &mmc->caps2;
988 struct pinctrl_state *state;
989 struct pinctrl_state **pinctrl_state;
990
991 if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY))
992 return 0;
993
994 pinctrl_state = devm_kcalloc(dev,
995 MMC_TIMING_MMC_HS200 + 1,
996 sizeof(*pinctrl_state),
997 GFP_KERNEL);
998 if (!pinctrl_state)
999 return -ENOMEM;
1000
1001 omap_host->pinctrl = devm_pinctrl_get(omap_host->dev);
1002 if (IS_ERR(omap_host->pinctrl)) {
1003 dev_err(dev, "Cannot get pinctrl\n");
1004 return PTR_ERR(omap_host->pinctrl);
1005 }
1006
1007 state = pinctrl_lookup_state(omap_host->pinctrl, "default");
1008 if (IS_ERR(state)) {
1009 dev_err(dev, "no pinctrl state for default mode\n");
1010 return PTR_ERR(state);
1011 }
1012 pinctrl_state[MMC_TIMING_LEGACY] = state;
1013
1014 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr104", caps,
1015 MMC_CAP_UHS_SDR104);
1016 if (!IS_ERR(state))
1017 pinctrl_state[MMC_TIMING_UHS_SDR104] = state;
1018
1019 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr50", caps,
1020 MMC_CAP_UHS_DDR50);
1021 if (!IS_ERR(state))
1022 pinctrl_state[MMC_TIMING_UHS_DDR50] = state;
1023
1024 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr50", caps,
1025 MMC_CAP_UHS_SDR50);
1026 if (!IS_ERR(state))
1027 pinctrl_state[MMC_TIMING_UHS_SDR50] = state;
1028
1029 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr25", caps,
1030 MMC_CAP_UHS_SDR25);
1031 if (!IS_ERR(state))
1032 pinctrl_state[MMC_TIMING_UHS_SDR25] = state;
1033
1034 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr12", caps,
1035 MMC_CAP_UHS_SDR12);
1036 if (!IS_ERR(state))
1037 pinctrl_state[MMC_TIMING_UHS_SDR12] = state;
1038
1039 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_1_8v", caps,
1040 MMC_CAP_1_8V_DDR);
1041 if (!IS_ERR(state)) {
1042 pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
1043 } else {
1044 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_3_3v",
1045 caps,
1046 MMC_CAP_3_3V_DDR);
1047 if (!IS_ERR(state))
1048 pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
1049 }
1050
1051 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
1052 MMC_CAP_SD_HIGHSPEED);
1053 if (!IS_ERR(state))
1054 pinctrl_state[MMC_TIMING_SD_HS] = state;
1055
1056 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
1057 MMC_CAP_MMC_HIGHSPEED);
1058 if (!IS_ERR(state))
1059 pinctrl_state[MMC_TIMING_MMC_HS] = state;
1060
1061 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs200_1_8v", caps2,
1062 MMC_CAP2_HS200_1_8V_SDR);
1063 if (!IS_ERR(state))
1064 pinctrl_state[MMC_TIMING_MMC_HS200] = state;
1065
1066 omap_host->pinctrl_state = pinctrl_state;
1067
1068 return 0;
1069}
1070
1071static const struct soc_device_attribute sdhci_omap_soc_devices[] = {
1072 {
1073 .machine = "DRA7[45]*",
1074 .revision = "ES1.[01]",
1075 },
1076 {
1077 /* sentinel */
1078 }
1079};
1080
1081static int sdhci_omap_probe(struct platform_device *pdev)
1082{
1083 int ret;
1084 u32 offset;
1085 struct device *dev = &pdev->dev;
1086 struct sdhci_host *host;
1087 struct sdhci_pltfm_host *pltfm_host;
1088 struct sdhci_omap_host *omap_host;
1089 struct mmc_host *mmc;
1090 const struct of_device_id *match;
1091 struct sdhci_omap_data *data;
1092 const struct soc_device_attribute *soc;
1093 struct resource *regs;
1094
1095 match = of_match_device(omap_sdhci_match, dev);
1096 if (!match)
1097 return -EINVAL;
1098
1099 data = (struct sdhci_omap_data *)match->data;
1100 if (!data) {
1101 dev_err(dev, "no sdhci omap data\n");
1102 return -EINVAL;
1103 }
1104 offset = data->offset;
1105
1106 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1107 if (!regs)
1108 return -ENXIO;
1109
1110 host = sdhci_pltfm_init(pdev, &sdhci_omap_pdata,
1111 sizeof(*omap_host));
1112 if (IS_ERR(host)) {
1113 dev_err(dev, "Failed sdhci_pltfm_init\n");
1114 return PTR_ERR(host);
1115 }
1116
1117 pltfm_host = sdhci_priv(host);
1118 omap_host = sdhci_pltfm_priv(pltfm_host);
1119 omap_host->host = host;
1120 omap_host->base = host->ioaddr;
1121 omap_host->dev = dev;
1122 omap_host->power_mode = MMC_POWER_UNDEFINED;
1123 omap_host->timing = MMC_TIMING_LEGACY;
1124 omap_host->flags = data->flags;
1125 host->ioaddr += offset;
1126 host->mapbase = regs->start + offset;
1127
1128 mmc = host->mmc;
1129 sdhci_get_of_property(pdev);
1130 ret = mmc_of_parse(mmc);
1131 if (ret)
1132 goto err_pltfm_free;
1133
1134 soc = soc_device_match(sdhci_omap_soc_devices);
1135 if (soc) {
1136 omap_host->version = "rev11";
1137 if (!strcmp(dev_name(dev), "4809c000.mmc"))
1138 mmc->f_max = 96000000;
1139 if (!strcmp(dev_name(dev), "480b4000.mmc"))
1140 mmc->f_max = 48000000;
1141 if (!strcmp(dev_name(dev), "480ad000.mmc"))
1142 mmc->f_max = 48000000;
1143 }
1144
1145 if (!mmc_can_gpio_ro(mmc))
1146 mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
1147
1148 pltfm_host->clk = devm_clk_get(dev, "fck");
1149 if (IS_ERR(pltfm_host->clk)) {
1150 ret = PTR_ERR(pltfm_host->clk);
1151 goto err_pltfm_free;
1152 }
1153
1154 ret = clk_set_rate(pltfm_host->clk, mmc->f_max);
1155 if (ret) {
1156 dev_err(dev, "failed to set clock to %d\n", mmc->f_max);
1157 goto err_pltfm_free;
1158 }
1159
1160 omap_host->pbias = devm_regulator_get_optional(dev, "pbias");
1161 if (IS_ERR(omap_host->pbias)) {
1162 ret = PTR_ERR(omap_host->pbias);
1163 if (ret != -ENODEV)
1164 goto err_pltfm_free;
1165 dev_dbg(dev, "unable to get pbias regulator %d\n", ret);
1166 }
1167 omap_host->pbias_enabled = false;
1168
1169 /*
1170 * omap_device_pm_domain has callbacks to enable the main
1171 * functional clock, interface clock and also configure the
1172 * SYSCONFIG register of omap devices. The callback will be invoked
1173 * as part of pm_runtime_get_sync.
1174 */
1175 pm_runtime_enable(dev);
1176 ret = pm_runtime_get_sync(dev);
1177 if (ret < 0) {
1178 dev_err(dev, "pm_runtime_get_sync failed\n");
1179 pm_runtime_put_noidle(dev);
1180 goto err_rpm_disable;
1181 }
1182
1183 ret = sdhci_omap_set_capabilities(omap_host);
1184 if (ret) {
1185 dev_err(dev, "failed to set system capabilities\n");
1186 goto err_put_sync;
1187 }
1188
1189 host->mmc_host_ops.start_signal_voltage_switch =
1190 sdhci_omap_start_signal_voltage_switch;
1191 host->mmc_host_ops.set_ios = sdhci_omap_set_ios;
1192 host->mmc_host_ops.card_busy = sdhci_omap_card_busy;
1193 host->mmc_host_ops.execute_tuning = sdhci_omap_execute_tuning;
1194 host->mmc_host_ops.enable_sdio_irq = sdhci_omap_enable_sdio_irq;
1195
1196 /* Switch to external DMA only if there is the "dmas" property */
1197 if (of_find_property(dev->of_node, "dmas", NULL))
1198 sdhci_switch_external_dma(host, true);
1199
1200 /* R1B responses is required to properly manage HW busy detection. */
1201 mmc->caps |= MMC_CAP_NEED_RSP_BUSY;
1202
1203 ret = sdhci_setup_host(host);
1204 if (ret)
1205 goto err_put_sync;
1206
1207 ret = sdhci_omap_config_iodelay_pinctrl_state(omap_host);
1208 if (ret)
1209 goto err_cleanup_host;
1210
1211 ret = __sdhci_add_host(host);
1212 if (ret)
1213 goto err_cleanup_host;
1214
1215 return 0;
1216
1217err_cleanup_host:
1218 sdhci_cleanup_host(host);
1219
1220err_put_sync:
1221 pm_runtime_put_sync(dev);
1222
1223err_rpm_disable:
1224 pm_runtime_disable(dev);
1225
1226err_pltfm_free:
1227 sdhci_pltfm_free(pdev);
1228 return ret;
1229}
1230
1231static int sdhci_omap_remove(struct platform_device *pdev)
1232{
1233 struct device *dev = &pdev->dev;
1234 struct sdhci_host *host = platform_get_drvdata(pdev);
1235
1236 sdhci_remove_host(host, true);
1237 pm_runtime_put_sync(dev);
1238 pm_runtime_disable(dev);
1239 sdhci_pltfm_free(pdev);
1240
1241 return 0;
1242}
1243#ifdef CONFIG_PM_SLEEP
1244static void sdhci_omap_context_save(struct sdhci_omap_host *omap_host)
1245{
1246 omap_host->con = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
1247 omap_host->hctl = sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL);
1248 omap_host->capa = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
1249}
1250
1251static void sdhci_omap_context_restore(struct sdhci_omap_host *omap_host)
1252{
1253 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, omap_host->con);
1254 sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, omap_host->hctl);
1255 sdhci_omap_writel(omap_host, SDHCI_OMAP_CAPA, omap_host->capa);
1256}
1257
1258static int __maybe_unused sdhci_omap_suspend(struct device *dev)
1259{
1260 struct sdhci_host *host = dev_get_drvdata(dev);
1261 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1262 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
1263
1264 sdhci_suspend_host(host);
1265
1266 sdhci_omap_context_save(omap_host);
1267
1268 pinctrl_pm_select_idle_state(dev);
1269
1270 pm_runtime_force_suspend(dev);
1271
1272 return 0;
1273}
1274
1275static int __maybe_unused sdhci_omap_resume(struct device *dev)
1276{
1277 struct sdhci_host *host = dev_get_drvdata(dev);
1278 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1279 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
1280
1281 pm_runtime_force_resume(dev);
1282
1283 pinctrl_pm_select_default_state(dev);
1284
1285 sdhci_omap_context_restore(omap_host);
1286
1287 sdhci_resume_host(host);
1288
1289 return 0;
1290}
1291#endif
1292static SIMPLE_DEV_PM_OPS(sdhci_omap_dev_pm_ops, sdhci_omap_suspend,
1293 sdhci_omap_resume);
1294
1295static struct platform_driver sdhci_omap_driver = {
1296 .probe = sdhci_omap_probe,
1297 .remove = sdhci_omap_remove,
1298 .driver = {
1299 .name = "sdhci-omap",
1300 .pm = &sdhci_omap_dev_pm_ops,
1301 .of_match_table = omap_sdhci_match,
1302 },
1303};
1304
1305module_platform_driver(sdhci_omap_driver);
1306
1307MODULE_DESCRIPTION("SDHCI driver for OMAP SoCs");
1308MODULE_AUTHOR("Texas Instruments Inc.");
1309MODULE_LICENSE("GPL v2");
1310MODULE_ALIAS("platform:sdhci_omap");