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1/*
2 * Copyright 2012-16 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __DAL_CLK_MGR_H__
27#define __DAL_CLK_MGR_H__
28
29#include "dc.h"
30#include "dm_pp_smu.h"
31
32#define DCN_MINIMUM_DISPCLK_Khz 100000
33#define DCN_MINIMUM_DPPCLK_Khz 100000
34
35/* Constants */
36#define DDR4_DRAM_WIDTH 64
37#define WM_A 0
38#define WM_B 1
39#define WM_C 2
40#define WM_D 3
41#define WM_SET_COUNT 4
42
43#define DCN_MINIMUM_DISPCLK_Khz 100000
44#define DCN_MINIMUM_DPPCLK_Khz 100000
45
46struct dcn3_clk_internal {
47 int dummy;
48 /*TODO:
49 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk
50 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk
51 uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk
52 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk
53 uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider
54 uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow
55
56 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
57 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
58 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass
59 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
60 */
61};
62
63struct dcn301_clk_internal {
64 int dummy;
65 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk
66 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk
67 uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk
68 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk
69 uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider
70 uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow
71
72 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
73 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
74 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass
75 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
76};
77
78/* Will these bw structures be ASIC specific? */
79
80#define MAX_NUM_DPM_LVL 8
81#define WM_SET_COUNT 4
82
83
84struct clk_limit_table_entry {
85 unsigned int voltage; /* milivolts withh 2 fractional bits */
86 unsigned int dcfclk_mhz;
87 unsigned int fclk_mhz;
88 unsigned int memclk_mhz;
89 unsigned int socclk_mhz;
90 unsigned int dtbclk_mhz;
91 unsigned int dispclk_mhz;
92 unsigned int dppclk_mhz;
93 unsigned int phyclk_mhz;
94 unsigned int phyclk_d18_mhz;
95 unsigned int wck_ratio;
96};
97
98struct clk_limit_num_entries {
99 unsigned int num_dcfclk_levels;
100 unsigned int num_fclk_levels;
101 unsigned int num_memclk_levels;
102 unsigned int num_socclk_levels;
103 unsigned int num_dtbclk_levels;
104 unsigned int num_dispclk_levels;
105 unsigned int num_dppclk_levels;
106 unsigned int num_phyclk_levels;
107 unsigned int num_phyclk_d18_levels;
108};
109
110/* This table is contiguous */
111struct clk_limit_table {
112 struct clk_limit_table_entry entries[MAX_NUM_DPM_LVL];
113 struct clk_limit_num_entries num_entries_per_clk;
114 unsigned int num_entries; /* highest populated dpm level for back compatibility */
115};
116
117struct wm_range_table_entry {
118 unsigned int wm_inst;
119 unsigned int wm_type;
120 double pstate_latency_us;
121 double sr_exit_time_us;
122 double sr_enter_plus_exit_time_us;
123 bool valid;
124};
125
126struct nv_wm_range_entry {
127 bool valid;
128
129 struct {
130 uint8_t wm_type;
131 uint16_t min_dcfclk;
132 uint16_t max_dcfclk;
133 uint16_t min_uclk;
134 uint16_t max_uclk;
135 } pmfw_breakdown;
136
137 struct {
138 double pstate_latency_us;
139 double sr_exit_time_us;
140 double sr_enter_plus_exit_time_us;
141 double fclk_change_latency_us;
142 } dml_input;
143};
144
145struct clk_log_info {
146 bool enabled;
147 char *pBuf;
148 unsigned int bufSize;
149 unsigned int *sum_chars_printed;
150};
151
152struct clk_state_registers_and_bypass {
153 uint32_t dcfclk;
154 uint32_t dcf_deep_sleep_divider;
155 uint32_t dcf_deep_sleep_allow;
156 uint32_t dprefclk;
157 uint32_t dispclk;
158 uint32_t dppclk;
159 uint32_t dtbclk;
160
161 uint32_t dppclk_bypass;
162 uint32_t dcfclk_bypass;
163 uint32_t dprefclk_bypass;
164 uint32_t dispclk_bypass;
165};
166
167struct rv1_clk_internal {
168 uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk
169 uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider
170 uint32_t CLK0_CLK8_ALLOW_DS; //dcf_deep_sleep_allow
171 uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk
172 uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk
173
174 uint32_t CLK0_CLK8_BYPASS_CNTL; //dcfclk bypass
175 uint32_t CLK0_CLK10_BYPASS_CNTL; //dprefclk bypass
176 uint32_t CLK0_CLK11_BYPASS_CNTL; //dispclk bypass
177};
178
179struct rn_clk_internal {
180 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk
181 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk
182 uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk
183 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk
184 uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider
185 uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow
186
187 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
188 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
189 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass
190 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
191
192};
193
194/* For dtn logging and debugging */
195struct clk_state_registers {
196 uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk
197 uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider
198 uint32_t CLK0_CLK8_ALLOW_DS; //dcf_deep_sleep_allow
199 uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk
200 uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk
201};
202
203/* TODO: combine this with the above */
204struct clk_bypass {
205 uint32_t dcfclk_bypass;
206 uint32_t dispclk_pypass;
207 uint32_t dprefclk_bypass;
208};
209/*
210 * This table is not contiguous, can have holes, each
211 * entry correspond to one set of WM. For example if
212 * we have 2 DPM and LPDDR, we will WM set A, B and
213 * D occupied, C will be emptry.
214 */
215struct wm_table {
216 union {
217 struct nv_wm_range_entry nv_entries[WM_SET_COUNT];
218 struct wm_range_table_entry entries[WM_SET_COUNT];
219 };
220};
221
222struct dummy_pstate_entry {
223 unsigned int dram_speed_mts;
224 double dummy_pstate_latency_us;
225};
226
227struct clk_bw_params {
228 unsigned int vram_type;
229 unsigned int num_channels;
230 unsigned int dram_channel_width_bytes;
231 unsigned int dispclk_vco_khz;
232 unsigned int dc_mode_softmax_memclk;
233 struct clk_limit_table clk_table;
234 struct wm_table wm_table;
235 struct dummy_pstate_entry dummy_pstate_table[4];
236};
237/* Public interfaces */
238
239struct clk_states {
240 uint32_t dprefclk_khz;
241};
242
243struct clk_mgr_funcs {
244 /*
245 * This function should set new clocks based on the input "safe_to_lower".
246 * If safe_to_lower == false, then only clocks which are to be increased
247 * should changed.
248 * If safe_to_lower == true, then only clocks which are to be decreased
249 * should be changed.
250 */
251 void (*update_clocks)(struct clk_mgr *clk_mgr,
252 struct dc_state *context,
253 bool safe_to_lower);
254
255 int (*get_dp_ref_clk_frequency)(struct clk_mgr *clk_mgr);
256 int (*get_dtb_ref_clk_frequency)(struct clk_mgr *clk_mgr);
257
258 void (*set_low_power_state)(struct clk_mgr *clk_mgr);
259
260 void (*init_clocks)(struct clk_mgr *clk_mgr);
261
262 void (*dump_clk_registers)(struct clk_state_registers_and_bypass *regs_and_bypass,
263 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info);
264
265 void (*enable_pme_wa) (struct clk_mgr *clk_mgr);
266 void (*get_clock)(struct clk_mgr *clk_mgr,
267 struct dc_state *context,
268 enum dc_clock_type clock_type,
269 struct dc_clock_config *clock_cfg);
270
271 bool (*are_clock_states_equal) (struct dc_clocks *a,
272 struct dc_clocks *b);
273 void (*notify_wm_ranges)(struct clk_mgr *clk_mgr);
274
275 /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */
276 void (*notify_link_rate_change)(struct clk_mgr *clk_mgr, struct dc_link *link);
277 /*
278 * Send message to PMFW to set hard min memclk frequency
279 * When current_mode = false, set DPM0
280 * When current_mode = true, set required clock for current mode
281 */
282 void (*set_hard_min_memclk)(struct clk_mgr *clk_mgr, bool current_mode);
283
284 /* Send message to PMFW to set hard max memclk frequency to highest DPM */
285 void (*set_hard_max_memclk)(struct clk_mgr *clk_mgr);
286
287 /* Custom set a memclk freq range*/
288 void (*set_max_memclk)(struct clk_mgr *clk_mgr, unsigned int memclk_mhz);
289 void (*set_min_memclk)(struct clk_mgr *clk_mgr, unsigned int memclk_mhz);
290
291 /* Get current memclk states from PMFW, update relevant structures */
292 void (*get_memclk_states_from_smu)(struct clk_mgr *clk_mgr);
293
294 /* Get SMU present */
295 bool (*is_smu_present)(struct clk_mgr *clk_mgr);
296};
297
298struct clk_mgr {
299 struct dc_context *ctx;
300 struct clk_mgr_funcs *funcs;
301 struct dc_clocks clks;
302 bool psr_allow_active_cache;
303 bool force_smu_not_present;
304 bool dc_mode_softmax_enabled;
305 int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes
306 int dentist_vco_freq_khz;
307 struct clk_state_registers_and_bypass boot_snapshot;
308 struct clk_bw_params *bw_params;
309 struct pp_smu_wm_range_sets ranges;
310};
311
312/* forward declarations */
313struct dccg;
314
315struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg);
316
317void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr);
318
319void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr);
320
321void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr);
322
323#endif /* __DAL_CLK_MGR_H__ */
1/*
2 * Copyright 2012-16 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __DAL_CLK_MGR_H__
27#define __DAL_CLK_MGR_H__
28
29#include "dc.h"
30#include "dm_pp_smu.h"
31
32#define DCN_MINIMUM_DISPCLK_Khz 100000
33#define DCN_MINIMUM_DPPCLK_Khz 100000
34
35/* Constants */
36#define DDR4_DRAM_WIDTH 64
37#define WM_A 0
38#define WM_B 1
39#define WM_C 2
40#define WM_D 3
41#define WM_SET_COUNT 4
42
43#define DCN_MINIMUM_DISPCLK_Khz 100000
44#define DCN_MINIMUM_DPPCLK_Khz 100000
45
46#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
47struct dcn3_clk_internal {
48 int dummy;
49 /*TODO:
50 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk
51 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk
52 uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk
53 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk
54 uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider
55 uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow
56
57 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
58 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
59 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass
60 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
61 */
62};
63
64#endif
65/* Will these bw structures be ASIC specific? */
66
67#define MAX_NUM_DPM_LVL 8
68#define WM_SET_COUNT 4
69
70
71struct clk_limit_table_entry {
72 unsigned int voltage; /* milivolts withh 2 fractional bits */
73 unsigned int dcfclk_mhz;
74 unsigned int fclk_mhz;
75 unsigned int memclk_mhz;
76 unsigned int socclk_mhz;
77#ifdef CONFIG_DRM_AMD_DC_DCN3_0
78 unsigned int dtbclk_mhz;
79 unsigned int dispclk_mhz;
80 unsigned int dppclk_mhz;
81 unsigned int phyclk_mhz;
82#endif
83};
84
85/* This table is contiguous */
86struct clk_limit_table {
87 struct clk_limit_table_entry entries[MAX_NUM_DPM_LVL];
88 unsigned int num_entries;
89};
90
91struct wm_range_table_entry {
92 unsigned int wm_inst;
93 unsigned int wm_type;
94 double pstate_latency_us;
95 double sr_exit_time_us;
96 double sr_enter_plus_exit_time_us;
97 bool valid;
98};
99
100#ifdef CONFIG_DRM_AMD_DC_DCN3_0
101
102struct nv_wm_range_entry {
103 bool valid;
104
105 struct {
106 uint8_t wm_type;
107 uint16_t min_dcfclk;
108 uint16_t max_dcfclk;
109 uint16_t min_uclk;
110 uint16_t max_uclk;
111 } pmfw_breakdown;
112
113 struct {
114 double pstate_latency_us;
115 double sr_exit_time_us;
116 double sr_enter_plus_exit_time_us;
117 } dml_input;
118};
119#endif
120
121struct clk_log_info {
122 bool enabled;
123 char *pBuf;
124 unsigned int bufSize;
125 unsigned int *sum_chars_printed;
126};
127
128struct clk_state_registers_and_bypass {
129 uint32_t dcfclk;
130 uint32_t dcf_deep_sleep_divider;
131 uint32_t dcf_deep_sleep_allow;
132 uint32_t dprefclk;
133 uint32_t dispclk;
134 uint32_t dppclk;
135
136 uint32_t dppclk_bypass;
137 uint32_t dcfclk_bypass;
138 uint32_t dprefclk_bypass;
139 uint32_t dispclk_bypass;
140};
141
142struct rv1_clk_internal {
143 uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk
144 uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider
145 uint32_t CLK0_CLK8_ALLOW_DS; //dcf_deep_sleep_allow
146 uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk
147 uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk
148
149 uint32_t CLK0_CLK8_BYPASS_CNTL; //dcfclk bypass
150 uint32_t CLK0_CLK10_BYPASS_CNTL; //dprefclk bypass
151 uint32_t CLK0_CLK11_BYPASS_CNTL; //dispclk bypass
152};
153
154struct rn_clk_internal {
155 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk
156 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk
157 uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk
158 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk
159 uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider
160 uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow
161
162 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
163 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
164 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass
165 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
166
167};
168
169/* For dtn logging and debugging */
170struct clk_state_registers {
171 uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk
172 uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider
173 uint32_t CLK0_CLK8_ALLOW_DS; //dcf_deep_sleep_allow
174 uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk
175 uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk
176};
177
178/* TODO: combine this with the above */
179struct clk_bypass {
180 uint32_t dcfclk_bypass;
181 uint32_t dispclk_pypass;
182 uint32_t dprefclk_bypass;
183};
184/*
185 * This table is not contiguous, can have holes, each
186 * entry correspond to one set of WM. For example if
187 * we have 2 DPM and LPDDR, we will WM set A, B and
188 * D occupied, C will be emptry.
189 */
190struct wm_table {
191#ifdef CONFIG_DRM_AMD_DC_DCN3_0
192 union {
193 struct nv_wm_range_entry nv_entries[WM_SET_COUNT];
194#endif
195 struct wm_range_table_entry entries[WM_SET_COUNT];
196#ifdef CONFIG_DRM_AMD_DC_DCN3_0
197 };
198#endif
199};
200
201struct dummy_pstate_entry {
202 unsigned int dram_speed_mts;
203 unsigned int dummy_pstate_latency_us;
204};
205
206struct clk_bw_params {
207 unsigned int vram_type;
208 unsigned int num_channels;
209 struct clk_limit_table clk_table;
210 struct wm_table wm_table;
211 struct dummy_pstate_entry dummy_pstate_table[4];
212};
213/* Public interfaces */
214
215struct clk_states {
216 uint32_t dprefclk_khz;
217};
218
219struct clk_mgr_funcs {
220 /*
221 * This function should set new clocks based on the input "safe_to_lower".
222 * If safe_to_lower == false, then only clocks which are to be increased
223 * should changed.
224 * If safe_to_lower == true, then only clocks which are to be decreased
225 * should be changed.
226 */
227 void (*update_clocks)(struct clk_mgr *clk_mgr,
228 struct dc_state *context,
229 bool safe_to_lower);
230
231 int (*get_dp_ref_clk_frequency)(struct clk_mgr *clk_mgr);
232
233 void (*set_low_power_state)(struct clk_mgr *clk_mgr);
234
235 void (*init_clocks)(struct clk_mgr *clk_mgr);
236
237 void (*enable_pme_wa) (struct clk_mgr *clk_mgr);
238 void (*get_clock)(struct clk_mgr *clk_mgr,
239 struct dc_state *context,
240 enum dc_clock_type clock_type,
241 struct dc_clock_config *clock_cfg);
242
243 bool (*are_clock_states_equal) (struct dc_clocks *a,
244 struct dc_clocks *b);
245 void (*notify_wm_ranges)(struct clk_mgr *clk_mgr);
246
247 /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */
248 void (*notify_link_rate_change)(struct clk_mgr *clk_mgr, struct dc_link *link);
249#ifdef CONFIG_DRM_AMD_DC_DCN3_0
250 /*
251 * Send message to PMFW to set hard min memclk frequency
252 * When current_mode = false, set DPM0
253 * When current_mode = true, set required clock for current mode
254 */
255 void (*set_hard_min_memclk)(struct clk_mgr *clk_mgr, bool current_mode);
256
257 /* Send message to PMFW to set hard max memclk frequency to highest DPM */
258 void (*set_hard_max_memclk)(struct clk_mgr *clk_mgr);
259
260 /* Get current memclk states from PMFW, update relevant structures */
261 void (*get_memclk_states_from_smu)(struct clk_mgr *clk_mgr);
262#endif
263};
264
265struct clk_mgr {
266 struct dc_context *ctx;
267 struct clk_mgr_funcs *funcs;
268 struct dc_clocks clks;
269 bool psr_allow_active_cache;
270#ifdef CONFIG_DRM_AMD_DC_DCN3_0
271 bool force_smu_not_present;
272#endif
273 int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes
274 int dentist_vco_freq_khz;
275 struct clk_state_registers_and_bypass boot_snapshot;
276 struct clk_bw_params *bw_params;
277 struct pp_smu_wm_range_sets ranges;
278};
279
280/* forward declarations */
281struct dccg;
282
283struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg);
284
285void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr);
286
287void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr);
288
289void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr);
290
291#endif /* __DAL_CLK_MGR_H__ */