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1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include <linux/firmware.h>
24#include <linux/module.h>
25#include "amdgpu.h"
26#include "amdgpu_psp.h"
27#include "amdgpu_ucode.h"
28#include "soc15_common.h"
29#include "psp_v12_0.h"
30
31#include "mp/mp_12_0_0_offset.h"
32#include "mp/mp_12_0_0_sh_mask.h"
33#include "gc/gc_9_0_offset.h"
34#include "sdma0/sdma0_4_0_offset.h"
35#include "nbio/nbio_7_4_offset.h"
36
37#include "oss/osssys_4_0_offset.h"
38#include "oss/osssys_4_0_sh_mask.h"
39
40MODULE_FIRMWARE("amdgpu/renoir_asd.bin");
41MODULE_FIRMWARE("amdgpu/renoir_ta.bin");
42MODULE_FIRMWARE("amdgpu/green_sardine_asd.bin");
43MODULE_FIRMWARE("amdgpu/green_sardine_ta.bin");
44
45/* address block */
46#define smnMP1_FIRMWARE_FLAGS 0x3010024
47
48static int psp_v12_0_init_microcode(struct psp_context *psp)
49{
50 struct amdgpu_device *adev = psp->adev;
51 const char *chip_name;
52 char fw_name[30];
53 int err = 0;
54 const struct ta_firmware_header_v1_0 *ta_hdr;
55 DRM_DEBUG("\n");
56
57 switch (adev->asic_type) {
58 case CHIP_RENOIR:
59 if (adev->apu_flags & AMD_APU_IS_RENOIR)
60 chip_name = "renoir";
61 else
62 chip_name = "green_sardine";
63 break;
64 default:
65 BUG();
66 }
67
68 err = psp_init_asd_microcode(psp, chip_name);
69 if (err)
70 return err;
71
72 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
73 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
74 if (err) {
75 release_firmware(adev->psp.ta_fw);
76 adev->psp.ta_fw = NULL;
77 dev_info(adev->dev,
78 "psp v12.0: Failed to load firmware \"%s\"\n",
79 fw_name);
80 } else {
81 err = amdgpu_ucode_validate(adev->psp.ta_fw);
82 if (err)
83 goto out;
84
85 ta_hdr = (const struct ta_firmware_header_v1_0 *)
86 adev->psp.ta_fw->data;
87 adev->psp.hdcp_context.context.bin_desc.fw_version =
88 le32_to_cpu(ta_hdr->hdcp.fw_version);
89 adev->psp.hdcp_context.context.bin_desc.size_bytes =
90 le32_to_cpu(ta_hdr->hdcp.size_bytes);
91 adev->psp.hdcp_context.context.bin_desc.start_addr =
92 (uint8_t *)ta_hdr +
93 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
94
95 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
96
97 adev->psp.dtm_context.context.bin_desc.fw_version =
98 le32_to_cpu(ta_hdr->dtm.fw_version);
99 adev->psp.dtm_context.context.bin_desc.size_bytes =
100 le32_to_cpu(ta_hdr->dtm.size_bytes);
101 adev->psp.dtm_context.context.bin_desc.start_addr =
102 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
103 le32_to_cpu(ta_hdr->dtm.offset_bytes);
104
105 if (adev->apu_flags & AMD_APU_IS_RENOIR) {
106 adev->psp.securedisplay_context.context.bin_desc.fw_version =
107 le32_to_cpu(ta_hdr->securedisplay.fw_version);
108 adev->psp.securedisplay_context.context.bin_desc.size_bytes =
109 le32_to_cpu(ta_hdr->securedisplay.size_bytes);
110 adev->psp.securedisplay_context.context.bin_desc.start_addr =
111 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
112 le32_to_cpu(ta_hdr->securedisplay.offset_bytes);
113 }
114 }
115
116 return 0;
117
118out:
119 release_firmware(adev->psp.ta_fw);
120 adev->psp.ta_fw = NULL;
121 if (err) {
122 dev_err(adev->dev,
123 "psp v12.0: Failed to load firmware \"%s\"\n",
124 fw_name);
125 }
126
127 return err;
128}
129
130static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp)
131{
132 int ret;
133 uint32_t psp_gfxdrv_command_reg = 0;
134 struct amdgpu_device *adev = psp->adev;
135 uint32_t sol_reg;
136
137 /* Check sOS sign of life register to confirm sys driver and sOS
138 * are already been loaded.
139 */
140 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
141 if (sol_reg)
142 return 0;
143
144 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
145 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
146 0x80000000, 0x80000000, false);
147 if (ret)
148 return ret;
149
150 /* Copy PSP System Driver binary to memory */
151 psp_copy_fw(psp, psp->sys.start_addr, psp->sys.size_bytes);
152
153 /* Provide the sys driver to bootloader */
154 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
155 (uint32_t)(psp->fw_pri_mc_addr >> 20));
156 psp_gfxdrv_command_reg = 1 << 16;
157 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
158 psp_gfxdrv_command_reg);
159
160 /* there might be handshake issue with hardware which needs delay */
161 mdelay(20);
162
163 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
164 0x80000000, 0x80000000, false);
165
166 return ret;
167}
168
169static int psp_v12_0_bootloader_load_sos(struct psp_context *psp)
170{
171 int ret;
172 unsigned int psp_gfxdrv_command_reg = 0;
173 struct amdgpu_device *adev = psp->adev;
174 uint32_t sol_reg;
175
176 /* Check sOS sign of life register to confirm sys driver and sOS
177 * are already been loaded.
178 */
179 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
180 if (sol_reg)
181 return 0;
182
183 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
184 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
185 0x80000000, 0x80000000, false);
186 if (ret)
187 return ret;
188
189 /* Copy Secure OS binary to PSP memory */
190 psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes);
191
192 /* Provide the PSP secure OS to bootloader */
193 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
194 (uint32_t)(psp->fw_pri_mc_addr >> 20));
195 psp_gfxdrv_command_reg = 2 << 16;
196 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
197 psp_gfxdrv_command_reg);
198
199 /* there might be handshake issue with hardware which needs delay */
200 mdelay(20);
201 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
202 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
203 0, true);
204
205 return ret;
206}
207
208static void psp_v12_0_reroute_ih(struct psp_context *psp)
209{
210 struct amdgpu_device *adev = psp->adev;
211 uint32_t tmp;
212
213 /* Change IH ring for VMC */
214 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
215 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
216 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
217
218 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
219 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
220 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
221
222 mdelay(20);
223 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
224 0x80000000, 0x8000FFFF, false);
225
226 /* Change IH ring for UMC */
227 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
228 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
229
230 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
231 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
232 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
233
234 mdelay(20);
235 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
236 0x80000000, 0x8000FFFF, false);
237}
238
239static int psp_v12_0_ring_create(struct psp_context *psp,
240 enum psp_ring_type ring_type)
241{
242 int ret = 0;
243 unsigned int psp_ring_reg = 0;
244 struct psp_ring *ring = &psp->km_ring;
245 struct amdgpu_device *adev = psp->adev;
246
247 psp_v12_0_reroute_ih(psp);
248
249 if (amdgpu_sriov_vf(psp->adev)) {
250 /* Write low address of the ring to C2PMSG_102 */
251 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
252 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
253 /* Write high address of the ring to C2PMSG_103 */
254 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
255 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
256
257 /* Write the ring initialization command to C2PMSG_101 */
258 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
259 GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
260
261 /* there might be handshake issue with hardware which needs delay */
262 mdelay(20);
263
264 /* Wait for response flag (bit 31) in C2PMSG_101 */
265 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
266 0x80000000, 0x8000FFFF, false);
267
268 } else {
269 /* Write low address of the ring to C2PMSG_69 */
270 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
271 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
272 /* Write high address of the ring to C2PMSG_70 */
273 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
274 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
275 /* Write size of ring to C2PMSG_71 */
276 psp_ring_reg = ring->ring_size;
277 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
278 /* Write the ring initialization command to C2PMSG_64 */
279 psp_ring_reg = ring_type;
280 psp_ring_reg = psp_ring_reg << 16;
281 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
282
283 /* there might be handshake issue with hardware which needs delay */
284 mdelay(20);
285
286 /* Wait for response flag (bit 31) in C2PMSG_64 */
287 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
288 0x80000000, 0x8000FFFF, false);
289 }
290
291 return ret;
292}
293
294static int psp_v12_0_ring_stop(struct psp_context *psp,
295 enum psp_ring_type ring_type)
296{
297 int ret = 0;
298 struct amdgpu_device *adev = psp->adev;
299
300 /* Write the ring destroy command*/
301 if (amdgpu_sriov_vf(adev))
302 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
303 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
304 else
305 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
306 GFX_CTRL_CMD_ID_DESTROY_RINGS);
307
308 /* there might be handshake issue with hardware which needs delay */
309 mdelay(20);
310
311 /* Wait for response flag (bit 31) */
312 if (amdgpu_sriov_vf(adev))
313 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
314 0x80000000, 0x80000000, false);
315 else
316 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
317 0x80000000, 0x80000000, false);
318
319 return ret;
320}
321
322static int psp_v12_0_ring_destroy(struct psp_context *psp,
323 enum psp_ring_type ring_type)
324{
325 int ret = 0;
326 struct psp_ring *ring = &psp->km_ring;
327 struct amdgpu_device *adev = psp->adev;
328
329 ret = psp_v12_0_ring_stop(psp, ring_type);
330 if (ret)
331 DRM_ERROR("Fail to stop psp ring\n");
332
333 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
334 &ring->ring_mem_mc_addr,
335 (void **)&ring->ring_mem);
336
337 return ret;
338}
339
340static int psp_v12_0_mode1_reset(struct psp_context *psp)
341{
342 int ret;
343 uint32_t offset;
344 struct amdgpu_device *adev = psp->adev;
345
346 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
347
348 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
349
350 if (ret) {
351 DRM_INFO("psp is not working correctly before mode1 reset!\n");
352 return -EINVAL;
353 }
354
355 /*send the mode 1 reset command*/
356 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
357
358 msleep(500);
359
360 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
361
362 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
363
364 if (ret) {
365 DRM_INFO("psp mode 1 reset failed!\n");
366 return -EINVAL;
367 }
368
369 DRM_INFO("psp mode1 reset succeed \n");
370
371 return 0;
372}
373
374static uint32_t psp_v12_0_ring_get_wptr(struct psp_context *psp)
375{
376 uint32_t data;
377 struct amdgpu_device *adev = psp->adev;
378
379 if (amdgpu_sriov_vf(adev))
380 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
381 else
382 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
383
384 return data;
385}
386
387static void psp_v12_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
388{
389 struct amdgpu_device *adev = psp->adev;
390
391 if (amdgpu_sriov_vf(adev)) {
392 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
393 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
394 } else
395 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
396}
397
398static const struct psp_funcs psp_v12_0_funcs = {
399 .init_microcode = psp_v12_0_init_microcode,
400 .bootloader_load_sysdrv = psp_v12_0_bootloader_load_sysdrv,
401 .bootloader_load_sos = psp_v12_0_bootloader_load_sos,
402 .ring_create = psp_v12_0_ring_create,
403 .ring_stop = psp_v12_0_ring_stop,
404 .ring_destroy = psp_v12_0_ring_destroy,
405 .mode1_reset = psp_v12_0_mode1_reset,
406 .ring_get_wptr = psp_v12_0_ring_get_wptr,
407 .ring_set_wptr = psp_v12_0_ring_set_wptr,
408};
409
410void psp_v12_0_set_psp_funcs(struct psp_context *psp)
411{
412 psp->funcs = &psp_v12_0_funcs;
413}
1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include <linux/firmware.h>
24#include <linux/module.h>
25#include "amdgpu.h"
26#include "amdgpu_psp.h"
27#include "amdgpu_ucode.h"
28#include "soc15_common.h"
29#include "psp_v12_0.h"
30
31#include "mp/mp_12_0_0_offset.h"
32#include "mp/mp_12_0_0_sh_mask.h"
33#include "gc/gc_9_0_offset.h"
34#include "sdma0/sdma0_4_0_offset.h"
35#include "nbio/nbio_7_4_offset.h"
36
37#include "oss/osssys_4_0_offset.h"
38#include "oss/osssys_4_0_sh_mask.h"
39
40MODULE_FIRMWARE("amdgpu/renoir_asd.bin");
41/* address block */
42#define smnMP1_FIRMWARE_FLAGS 0x3010024
43
44static int psp_v12_0_init_microcode(struct psp_context *psp)
45{
46 struct amdgpu_device *adev = psp->adev;
47 const char *chip_name;
48 int err = 0;
49
50 switch (adev->asic_type) {
51 case CHIP_RENOIR:
52 chip_name = "renoir";
53 break;
54 default:
55 BUG();
56 }
57
58 err = psp_init_asd_microcode(psp, chip_name);
59 return err;
60}
61
62static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp)
63{
64 int ret;
65 uint32_t psp_gfxdrv_command_reg = 0;
66 struct amdgpu_device *adev = psp->adev;
67 uint32_t sol_reg;
68
69 /* Check sOS sign of life register to confirm sys driver and sOS
70 * are already been loaded.
71 */
72 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
73 if (sol_reg)
74 return 0;
75
76 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
77 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
78 0x80000000, 0x80000000, false);
79 if (ret)
80 return ret;
81
82 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
83
84 /* Copy PSP System Driver binary to memory */
85 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
86
87 /* Provide the sys driver to bootloader */
88 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
89 (uint32_t)(psp->fw_pri_mc_addr >> 20));
90 psp_gfxdrv_command_reg = 1 << 16;
91 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
92 psp_gfxdrv_command_reg);
93
94 /* there might be handshake issue with hardware which needs delay */
95 mdelay(20);
96
97 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
98 0x80000000, 0x80000000, false);
99
100 return ret;
101}
102
103static int psp_v12_0_bootloader_load_sos(struct psp_context *psp)
104{
105 int ret;
106 unsigned int psp_gfxdrv_command_reg = 0;
107 struct amdgpu_device *adev = psp->adev;
108 uint32_t sol_reg;
109
110 /* Check sOS sign of life register to confirm sys driver and sOS
111 * are already been loaded.
112 */
113 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
114 if (sol_reg)
115 return 0;
116
117 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
118 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
119 0x80000000, 0x80000000, false);
120 if (ret)
121 return ret;
122
123 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
124
125 /* Copy Secure OS binary to PSP memory */
126 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
127
128 /* Provide the PSP secure OS to bootloader */
129 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
130 (uint32_t)(psp->fw_pri_mc_addr >> 20));
131 psp_gfxdrv_command_reg = 2 << 16;
132 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
133 psp_gfxdrv_command_reg);
134
135 /* there might be handshake issue with hardware which needs delay */
136 mdelay(20);
137 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
138 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
139 0, true);
140
141 return ret;
142}
143
144static void psp_v12_0_reroute_ih(struct psp_context *psp)
145{
146 struct amdgpu_device *adev = psp->adev;
147 uint32_t tmp;
148
149 /* Change IH ring for VMC */
150 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
151 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
152 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
153
154 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
155 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
156 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
157
158 mdelay(20);
159 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
160 0x80000000, 0x8000FFFF, false);
161
162 /* Change IH ring for UMC */
163 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
164 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
165
166 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
167 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
168 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
169
170 mdelay(20);
171 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
172 0x80000000, 0x8000FFFF, false);
173}
174
175static int psp_v12_0_ring_init(struct psp_context *psp,
176 enum psp_ring_type ring_type)
177{
178 int ret = 0;
179 struct psp_ring *ring;
180 struct amdgpu_device *adev = psp->adev;
181
182 psp_v12_0_reroute_ih(psp);
183
184 ring = &psp->km_ring;
185
186 ring->ring_type = ring_type;
187
188 /* allocate 4k Page of Local Frame Buffer memory for ring */
189 ring->ring_size = 0x1000;
190 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
191 AMDGPU_GEM_DOMAIN_VRAM,
192 &adev->firmware.rbuf,
193 &ring->ring_mem_mc_addr,
194 (void **)&ring->ring_mem);
195 if (ret) {
196 ring->ring_size = 0;
197 return ret;
198 }
199
200 return 0;
201}
202
203static int psp_v12_0_ring_create(struct psp_context *psp,
204 enum psp_ring_type ring_type)
205{
206 int ret = 0;
207 unsigned int psp_ring_reg = 0;
208 struct psp_ring *ring = &psp->km_ring;
209 struct amdgpu_device *adev = psp->adev;
210
211 if (amdgpu_sriov_vf(psp->adev)) {
212 /* Write low address of the ring to C2PMSG_102 */
213 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
214 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
215 /* Write high address of the ring to C2PMSG_103 */
216 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
217 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
218
219 /* Write the ring initialization command to C2PMSG_101 */
220 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
221 GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
222
223 /* there might be handshake issue with hardware which needs delay */
224 mdelay(20);
225
226 /* Wait for response flag (bit 31) in C2PMSG_101 */
227 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
228 0x80000000, 0x8000FFFF, false);
229
230 } else {
231 /* Write low address of the ring to C2PMSG_69 */
232 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
233 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
234 /* Write high address of the ring to C2PMSG_70 */
235 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
236 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
237 /* Write size of ring to C2PMSG_71 */
238 psp_ring_reg = ring->ring_size;
239 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
240 /* Write the ring initialization command to C2PMSG_64 */
241 psp_ring_reg = ring_type;
242 psp_ring_reg = psp_ring_reg << 16;
243 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
244
245 /* there might be handshake issue with hardware which needs delay */
246 mdelay(20);
247
248 /* Wait for response flag (bit 31) in C2PMSG_64 */
249 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
250 0x80000000, 0x8000FFFF, false);
251 }
252
253 return ret;
254}
255
256static int psp_v12_0_ring_stop(struct psp_context *psp,
257 enum psp_ring_type ring_type)
258{
259 int ret = 0;
260 struct amdgpu_device *adev = psp->adev;
261
262 /* Write the ring destroy command*/
263 if (amdgpu_sriov_vf(adev))
264 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
265 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
266 else
267 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
268 GFX_CTRL_CMD_ID_DESTROY_RINGS);
269
270 /* there might be handshake issue with hardware which needs delay */
271 mdelay(20);
272
273 /* Wait for response flag (bit 31) */
274 if (amdgpu_sriov_vf(adev))
275 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
276 0x80000000, 0x80000000, false);
277 else
278 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
279 0x80000000, 0x80000000, false);
280
281 return ret;
282}
283
284static int psp_v12_0_ring_destroy(struct psp_context *psp,
285 enum psp_ring_type ring_type)
286{
287 int ret = 0;
288 struct psp_ring *ring = &psp->km_ring;
289 struct amdgpu_device *adev = psp->adev;
290
291 ret = psp_v12_0_ring_stop(psp, ring_type);
292 if (ret)
293 DRM_ERROR("Fail to stop psp ring\n");
294
295 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
296 &ring->ring_mem_mc_addr,
297 (void **)&ring->ring_mem);
298
299 return ret;
300}
301
302static int psp_v12_0_mode1_reset(struct psp_context *psp)
303{
304 int ret;
305 uint32_t offset;
306 struct amdgpu_device *adev = psp->adev;
307
308 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
309
310 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
311
312 if (ret) {
313 DRM_INFO("psp is not working correctly before mode1 reset!\n");
314 return -EINVAL;
315 }
316
317 /*send the mode 1 reset command*/
318 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
319
320 msleep(500);
321
322 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
323
324 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
325
326 if (ret) {
327 DRM_INFO("psp mode 1 reset failed!\n");
328 return -EINVAL;
329 }
330
331 DRM_INFO("psp mode1 reset succeed \n");
332
333 return 0;
334}
335
336static uint32_t psp_v12_0_ring_get_wptr(struct psp_context *psp)
337{
338 uint32_t data;
339 struct amdgpu_device *adev = psp->adev;
340
341 if (amdgpu_sriov_vf(adev))
342 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
343 else
344 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
345
346 return data;
347}
348
349static void psp_v12_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
350{
351 struct amdgpu_device *adev = psp->adev;
352
353 if (amdgpu_sriov_vf(adev)) {
354 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
355 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
356 } else
357 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
358}
359
360static const struct psp_funcs psp_v12_0_funcs = {
361 .init_microcode = psp_v12_0_init_microcode,
362 .bootloader_load_sysdrv = psp_v12_0_bootloader_load_sysdrv,
363 .bootloader_load_sos = psp_v12_0_bootloader_load_sos,
364 .ring_init = psp_v12_0_ring_init,
365 .ring_create = psp_v12_0_ring_create,
366 .ring_stop = psp_v12_0_ring_stop,
367 .ring_destroy = psp_v12_0_ring_destroy,
368 .mode1_reset = psp_v12_0_mode1_reset,
369 .ring_get_wptr = psp_v12_0_ring_get_wptr,
370 .ring_set_wptr = psp_v12_0_ring_set_wptr,
371};
372
373void psp_v12_0_set_psp_funcs(struct psp_context *psp)
374{
375 psp->funcs = &psp_v12_0_funcs;
376}