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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/ktime.h>
29#include <linux/module.h>
30#include <linux/pagemap.h>
31#include <linux/pci.h>
32#include <linux/dma-buf.h>
33
34#include <drm/amdgpu_drm.h>
35#include <drm/drm_drv.h>
36#include <drm/drm_gem_ttm_helper.h>
37
38#include "amdgpu.h"
39#include "amdgpu_display.h"
40#include "amdgpu_dma_buf.h"
41#include "amdgpu_hmm.h"
42#include "amdgpu_xgmi.h"
43
44static const struct drm_gem_object_funcs amdgpu_gem_object_funcs;
45
46static vm_fault_t amdgpu_gem_fault(struct vm_fault *vmf)
47{
48 struct ttm_buffer_object *bo = vmf->vma->vm_private_data;
49 struct drm_device *ddev = bo->base.dev;
50 vm_fault_t ret;
51 int idx;
52
53 ret = ttm_bo_vm_reserve(bo, vmf);
54 if (ret)
55 return ret;
56
57 if (drm_dev_enter(ddev, &idx)) {
58 ret = amdgpu_bo_fault_reserve_notify(bo);
59 if (ret) {
60 drm_dev_exit(idx);
61 goto unlock;
62 }
63
64 ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot,
65 TTM_BO_VM_NUM_PREFAULT);
66
67 drm_dev_exit(idx);
68 } else {
69 ret = ttm_bo_vm_dummy_page(vmf, vmf->vma->vm_page_prot);
70 }
71 if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT))
72 return ret;
73
74unlock:
75 dma_resv_unlock(bo->base.resv);
76 return ret;
77}
78
79static const struct vm_operations_struct amdgpu_gem_vm_ops = {
80 .fault = amdgpu_gem_fault,
81 .open = ttm_bo_vm_open,
82 .close = ttm_bo_vm_close,
83 .access = ttm_bo_vm_access
84};
85
86static void amdgpu_gem_object_free(struct drm_gem_object *gobj)
87{
88 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
89
90 if (robj) {
91 amdgpu_hmm_unregister(robj);
92 amdgpu_bo_unref(&robj);
93 }
94}
95
96int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
97 int alignment, u32 initial_domain,
98 u64 flags, enum ttm_bo_type type,
99 struct dma_resv *resv,
100 struct drm_gem_object **obj)
101{
102 struct amdgpu_bo *bo;
103 struct amdgpu_bo_user *ubo;
104 struct amdgpu_bo_param bp;
105 int r;
106
107 memset(&bp, 0, sizeof(bp));
108 *obj = NULL;
109
110 bp.size = size;
111 bp.byte_align = alignment;
112 bp.type = type;
113 bp.resv = resv;
114 bp.preferred_domain = initial_domain;
115 bp.flags = flags;
116 bp.domain = initial_domain;
117 bp.bo_ptr_size = sizeof(struct amdgpu_bo);
118
119 r = amdgpu_bo_create_user(adev, &bp, &ubo);
120 if (r)
121 return r;
122
123 bo = &ubo->bo;
124 *obj = &bo->tbo.base;
125 (*obj)->funcs = &amdgpu_gem_object_funcs;
126
127 return 0;
128}
129
130void amdgpu_gem_force_release(struct amdgpu_device *adev)
131{
132 struct drm_device *ddev = adev_to_drm(adev);
133 struct drm_file *file;
134
135 mutex_lock(&ddev->filelist_mutex);
136
137 list_for_each_entry(file, &ddev->filelist, lhead) {
138 struct drm_gem_object *gobj;
139 int handle;
140
141 WARN_ONCE(1, "Still active user space clients!\n");
142 spin_lock(&file->table_lock);
143 idr_for_each_entry(&file->object_idr, gobj, handle) {
144 WARN_ONCE(1, "And also active allocations!\n");
145 drm_gem_object_put(gobj);
146 }
147 idr_destroy(&file->object_idr);
148 spin_unlock(&file->table_lock);
149 }
150
151 mutex_unlock(&ddev->filelist_mutex);
152}
153
154/*
155 * Call from drm_gem_handle_create which appear in both new and open ioctl
156 * case.
157 */
158static int amdgpu_gem_object_open(struct drm_gem_object *obj,
159 struct drm_file *file_priv)
160{
161 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj);
162 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
163 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
164 struct amdgpu_vm *vm = &fpriv->vm;
165 struct amdgpu_bo_va *bo_va;
166 struct mm_struct *mm;
167 int r;
168
169 mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm);
170 if (mm && mm != current->mm)
171 return -EPERM;
172
173 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID &&
174 abo->tbo.base.resv != vm->root.bo->tbo.base.resv)
175 return -EPERM;
176
177 r = amdgpu_bo_reserve(abo, false);
178 if (r)
179 return r;
180
181 bo_va = amdgpu_vm_bo_find(vm, abo);
182 if (!bo_va) {
183 bo_va = amdgpu_vm_bo_add(adev, vm, abo);
184 } else {
185 ++bo_va->ref_count;
186 }
187 amdgpu_bo_unreserve(abo);
188 return 0;
189}
190
191static void amdgpu_gem_object_close(struct drm_gem_object *obj,
192 struct drm_file *file_priv)
193{
194 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
195 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
196 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
197 struct amdgpu_vm *vm = &fpriv->vm;
198
199 struct amdgpu_bo_list_entry vm_pd;
200 struct list_head list, duplicates;
201 struct dma_fence *fence = NULL;
202 struct ttm_validate_buffer tv;
203 struct ww_acquire_ctx ticket;
204 struct amdgpu_bo_va *bo_va;
205 long r;
206
207 INIT_LIST_HEAD(&list);
208 INIT_LIST_HEAD(&duplicates);
209
210 tv.bo = &bo->tbo;
211 tv.num_shared = 2;
212 list_add(&tv.head, &list);
213
214 amdgpu_vm_get_pd_bo(vm, &list, &vm_pd);
215
216 r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates);
217 if (r) {
218 dev_err(adev->dev, "leaking bo va because "
219 "we fail to reserve bo (%ld)\n", r);
220 return;
221 }
222 bo_va = amdgpu_vm_bo_find(vm, bo);
223 if (!bo_va || --bo_va->ref_count)
224 goto out_unlock;
225
226 amdgpu_vm_bo_del(adev, bo_va);
227 if (!amdgpu_vm_ready(vm))
228 goto out_unlock;
229
230 r = amdgpu_vm_clear_freed(adev, vm, &fence);
231 if (r || !fence)
232 goto out_unlock;
233
234 amdgpu_bo_fence(bo, fence, true);
235 dma_fence_put(fence);
236
237out_unlock:
238 if (unlikely(r < 0))
239 dev_err(adev->dev, "failed to clear page "
240 "tables on GEM object close (%ld)\n", r);
241 ttm_eu_backoff_reservation(&ticket, &list);
242}
243
244static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma)
245{
246 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
247
248 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
249 return -EPERM;
250 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
251 return -EPERM;
252
253 /* Workaround for Thunk bug creating PROT_NONE,MAP_PRIVATE mappings
254 * for debugger access to invisible VRAM. Should have used MAP_SHARED
255 * instead. Clearing VM_MAYWRITE prevents the mapping from ever
256 * becoming writable and makes is_cow_mapping(vm_flags) false.
257 */
258 if (is_cow_mapping(vma->vm_flags) &&
259 !(vma->vm_flags & VM_ACCESS_FLAGS))
260 vma->vm_flags &= ~VM_MAYWRITE;
261
262 return drm_gem_ttm_mmap(obj, vma);
263}
264
265static const struct drm_gem_object_funcs amdgpu_gem_object_funcs = {
266 .free = amdgpu_gem_object_free,
267 .open = amdgpu_gem_object_open,
268 .close = amdgpu_gem_object_close,
269 .export = amdgpu_gem_prime_export,
270 .vmap = drm_gem_ttm_vmap,
271 .vunmap = drm_gem_ttm_vunmap,
272 .mmap = amdgpu_gem_object_mmap,
273 .vm_ops = &amdgpu_gem_vm_ops,
274};
275
276/*
277 * GEM ioctls.
278 */
279int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
280 struct drm_file *filp)
281{
282 struct amdgpu_device *adev = drm_to_adev(dev);
283 struct amdgpu_fpriv *fpriv = filp->driver_priv;
284 struct amdgpu_vm *vm = &fpriv->vm;
285 union drm_amdgpu_gem_create *args = data;
286 uint64_t flags = args->in.domain_flags;
287 uint64_t size = args->in.bo_size;
288 struct dma_resv *resv = NULL;
289 struct drm_gem_object *gobj;
290 uint32_t handle, initial_domain;
291 int r;
292
293 /* reject invalid gem flags */
294 if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
295 AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
296 AMDGPU_GEM_CREATE_CPU_GTT_USWC |
297 AMDGPU_GEM_CREATE_VRAM_CLEARED |
298 AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
299 AMDGPU_GEM_CREATE_EXPLICIT_SYNC |
300 AMDGPU_GEM_CREATE_ENCRYPTED |
301 AMDGPU_GEM_CREATE_DISCARDABLE))
302 return -EINVAL;
303
304 /* reject invalid gem domains */
305 if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK)
306 return -EINVAL;
307
308 if (!amdgpu_is_tmz(adev) && (flags & AMDGPU_GEM_CREATE_ENCRYPTED)) {
309 DRM_NOTE_ONCE("Cannot allocate secure buffer since TMZ is disabled\n");
310 return -EINVAL;
311 }
312
313 /* create a gem object to contain this object in */
314 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
315 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
316 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
317 /* if gds bo is created from user space, it must be
318 * passed to bo list
319 */
320 DRM_ERROR("GDS bo cannot be per-vm-bo\n");
321 return -EINVAL;
322 }
323 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
324 }
325
326 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
327 r = amdgpu_bo_reserve(vm->root.bo, false);
328 if (r)
329 return r;
330
331 resv = vm->root.bo->tbo.base.resv;
332 }
333
334 initial_domain = (u32)(0xffffffff & args->in.domains);
335retry:
336 r = amdgpu_gem_object_create(adev, size, args->in.alignment,
337 initial_domain,
338 flags, ttm_bo_type_device, resv, &gobj);
339 if (r && r != -ERESTARTSYS) {
340 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
341 flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
342 goto retry;
343 }
344
345 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
346 initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
347 goto retry;
348 }
349 DRM_DEBUG("Failed to allocate GEM object (%llu, %d, %llu, %d)\n",
350 size, initial_domain, args->in.alignment, r);
351 }
352
353 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
354 if (!r) {
355 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
356
357 abo->parent = amdgpu_bo_ref(vm->root.bo);
358 }
359 amdgpu_bo_unreserve(vm->root.bo);
360 }
361 if (r)
362 return r;
363
364 r = drm_gem_handle_create(filp, gobj, &handle);
365 /* drop reference from allocate - handle holds it now */
366 drm_gem_object_put(gobj);
367 if (r)
368 return r;
369
370 memset(args, 0, sizeof(*args));
371 args->out.handle = handle;
372 return 0;
373}
374
375int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
376 struct drm_file *filp)
377{
378 struct ttm_operation_ctx ctx = { true, false };
379 struct amdgpu_device *adev = drm_to_adev(dev);
380 struct drm_amdgpu_gem_userptr *args = data;
381 struct drm_gem_object *gobj;
382 struct hmm_range *range;
383 struct amdgpu_bo *bo;
384 uint32_t handle;
385 int r;
386
387 args->addr = untagged_addr(args->addr);
388
389 if (offset_in_page(args->addr | args->size))
390 return -EINVAL;
391
392 /* reject unknown flag values */
393 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
394 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
395 AMDGPU_GEM_USERPTR_REGISTER))
396 return -EINVAL;
397
398 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) &&
399 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
400
401 /* if we want to write to it we must install a MMU notifier */
402 return -EACCES;
403 }
404
405 /* create a gem object to contain this object in */
406 r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU,
407 0, ttm_bo_type_device, NULL, &gobj);
408 if (r)
409 return r;
410
411 bo = gem_to_amdgpu_bo(gobj);
412 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
413 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
414 r = amdgpu_ttm_tt_set_userptr(&bo->tbo, args->addr, args->flags);
415 if (r)
416 goto release_object;
417
418 r = amdgpu_hmm_register(bo, args->addr);
419 if (r)
420 goto release_object;
421
422 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
423 r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages,
424 &range);
425 if (r)
426 goto release_object;
427
428 r = amdgpu_bo_reserve(bo, true);
429 if (r)
430 goto user_pages_done;
431
432 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
433 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
434 amdgpu_bo_unreserve(bo);
435 if (r)
436 goto user_pages_done;
437 }
438
439 r = drm_gem_handle_create(filp, gobj, &handle);
440 if (r)
441 goto user_pages_done;
442
443 args->handle = handle;
444
445user_pages_done:
446 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE)
447 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range);
448
449release_object:
450 drm_gem_object_put(gobj);
451
452 return r;
453}
454
455int amdgpu_mode_dumb_mmap(struct drm_file *filp,
456 struct drm_device *dev,
457 uint32_t handle, uint64_t *offset_p)
458{
459 struct drm_gem_object *gobj;
460 struct amdgpu_bo *robj;
461
462 gobj = drm_gem_object_lookup(filp, handle);
463 if (gobj == NULL) {
464 return -ENOENT;
465 }
466 robj = gem_to_amdgpu_bo(gobj);
467 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) ||
468 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
469 drm_gem_object_put(gobj);
470 return -EPERM;
471 }
472 *offset_p = amdgpu_bo_mmap_offset(robj);
473 drm_gem_object_put(gobj);
474 return 0;
475}
476
477int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
478 struct drm_file *filp)
479{
480 union drm_amdgpu_gem_mmap *args = data;
481 uint32_t handle = args->in.handle;
482 memset(args, 0, sizeof(*args));
483 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
484}
485
486/**
487 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
488 *
489 * @timeout_ns: timeout in ns
490 *
491 * Calculate the timeout in jiffies from an absolute timeout in ns.
492 */
493unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
494{
495 unsigned long timeout_jiffies;
496 ktime_t timeout;
497
498 /* clamp timeout if it's to large */
499 if (((int64_t)timeout_ns) < 0)
500 return MAX_SCHEDULE_TIMEOUT;
501
502 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
503 if (ktime_to_ns(timeout) < 0)
504 return 0;
505
506 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
507 /* clamp timeout to avoid unsigned-> signed overflow */
508 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT )
509 return MAX_SCHEDULE_TIMEOUT - 1;
510
511 return timeout_jiffies;
512}
513
514int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
515 struct drm_file *filp)
516{
517 union drm_amdgpu_gem_wait_idle *args = data;
518 struct drm_gem_object *gobj;
519 struct amdgpu_bo *robj;
520 uint32_t handle = args->in.handle;
521 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
522 int r = 0;
523 long ret;
524
525 gobj = drm_gem_object_lookup(filp, handle);
526 if (gobj == NULL) {
527 return -ENOENT;
528 }
529 robj = gem_to_amdgpu_bo(gobj);
530 ret = dma_resv_wait_timeout(robj->tbo.base.resv, DMA_RESV_USAGE_READ,
531 true, timeout);
532
533 /* ret == 0 means not signaled,
534 * ret > 0 means signaled
535 * ret < 0 means interrupted before timeout
536 */
537 if (ret >= 0) {
538 memset(args, 0, sizeof(*args));
539 args->out.status = (ret == 0);
540 } else
541 r = ret;
542
543 drm_gem_object_put(gobj);
544 return r;
545}
546
547int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
548 struct drm_file *filp)
549{
550 struct drm_amdgpu_gem_metadata *args = data;
551 struct drm_gem_object *gobj;
552 struct amdgpu_bo *robj;
553 int r = -1;
554
555 DRM_DEBUG("%d \n", args->handle);
556 gobj = drm_gem_object_lookup(filp, args->handle);
557 if (gobj == NULL)
558 return -ENOENT;
559 robj = gem_to_amdgpu_bo(gobj);
560
561 r = amdgpu_bo_reserve(robj, false);
562 if (unlikely(r != 0))
563 goto out;
564
565 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
566 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
567 r = amdgpu_bo_get_metadata(robj, args->data.data,
568 sizeof(args->data.data),
569 &args->data.data_size_bytes,
570 &args->data.flags);
571 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
572 if (args->data.data_size_bytes > sizeof(args->data.data)) {
573 r = -EINVAL;
574 goto unreserve;
575 }
576 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
577 if (!r)
578 r = amdgpu_bo_set_metadata(robj, args->data.data,
579 args->data.data_size_bytes,
580 args->data.flags);
581 }
582
583unreserve:
584 amdgpu_bo_unreserve(robj);
585out:
586 drm_gem_object_put(gobj);
587 return r;
588}
589
590/**
591 * amdgpu_gem_va_update_vm -update the bo_va in its VM
592 *
593 * @adev: amdgpu_device pointer
594 * @vm: vm to update
595 * @bo_va: bo_va to update
596 * @operation: map, unmap or clear
597 *
598 * Update the bo_va directly after setting its address. Errors are not
599 * vital here, so they are not reported back to userspace.
600 */
601static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
602 struct amdgpu_vm *vm,
603 struct amdgpu_bo_va *bo_va,
604 uint32_t operation)
605{
606 int r;
607
608 if (!amdgpu_vm_ready(vm))
609 return;
610
611 r = amdgpu_vm_clear_freed(adev, vm, NULL);
612 if (r)
613 goto error;
614
615 if (operation == AMDGPU_VA_OP_MAP ||
616 operation == AMDGPU_VA_OP_REPLACE) {
617 r = amdgpu_vm_bo_update(adev, bo_va, false);
618 if (r)
619 goto error;
620 }
621
622 r = amdgpu_vm_update_pdes(adev, vm, false);
623
624error:
625 if (r && r != -ERESTARTSYS)
626 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
627}
628
629/**
630 * amdgpu_gem_va_map_flags - map GEM UAPI flags into hardware flags
631 *
632 * @adev: amdgpu_device pointer
633 * @flags: GEM UAPI flags
634 *
635 * Returns the GEM UAPI flags mapped into hardware for the ASIC.
636 */
637uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags)
638{
639 uint64_t pte_flag = 0;
640
641 if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
642 pte_flag |= AMDGPU_PTE_EXECUTABLE;
643 if (flags & AMDGPU_VM_PAGE_READABLE)
644 pte_flag |= AMDGPU_PTE_READABLE;
645 if (flags & AMDGPU_VM_PAGE_WRITEABLE)
646 pte_flag |= AMDGPU_PTE_WRITEABLE;
647 if (flags & AMDGPU_VM_PAGE_PRT)
648 pte_flag |= AMDGPU_PTE_PRT;
649 if (flags & AMDGPU_VM_PAGE_NOALLOC)
650 pte_flag |= AMDGPU_PTE_NOALLOC;
651
652 if (adev->gmc.gmc_funcs->map_mtype)
653 pte_flag |= amdgpu_gmc_map_mtype(adev,
654 flags & AMDGPU_VM_MTYPE_MASK);
655
656 return pte_flag;
657}
658
659int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
660 struct drm_file *filp)
661{
662 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
663 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
664 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK |
665 AMDGPU_VM_PAGE_NOALLOC;
666 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
667 AMDGPU_VM_PAGE_PRT;
668
669 struct drm_amdgpu_gem_va *args = data;
670 struct drm_gem_object *gobj;
671 struct amdgpu_device *adev = drm_to_adev(dev);
672 struct amdgpu_fpriv *fpriv = filp->driver_priv;
673 struct amdgpu_bo *abo;
674 struct amdgpu_bo_va *bo_va;
675 struct amdgpu_bo_list_entry vm_pd;
676 struct ttm_validate_buffer tv;
677 struct ww_acquire_ctx ticket;
678 struct list_head list, duplicates;
679 uint64_t va_flags;
680 uint64_t vm_size;
681 int r = 0;
682
683 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
684 dev_dbg(dev->dev,
685 "va_address 0x%LX is in reserved area 0x%LX\n",
686 args->va_address, AMDGPU_VA_RESERVED_SIZE);
687 return -EINVAL;
688 }
689
690 if (args->va_address >= AMDGPU_GMC_HOLE_START &&
691 args->va_address < AMDGPU_GMC_HOLE_END) {
692 dev_dbg(dev->dev,
693 "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n",
694 args->va_address, AMDGPU_GMC_HOLE_START,
695 AMDGPU_GMC_HOLE_END);
696 return -EINVAL;
697 }
698
699 args->va_address &= AMDGPU_GMC_HOLE_MASK;
700
701 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
702 vm_size -= AMDGPU_VA_RESERVED_SIZE;
703 if (args->va_address + args->map_size > vm_size) {
704 dev_dbg(dev->dev,
705 "va_address 0x%llx is in top reserved area 0x%llx\n",
706 args->va_address + args->map_size, vm_size);
707 return -EINVAL;
708 }
709
710 if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
711 dev_dbg(dev->dev, "invalid flags combination 0x%08X\n",
712 args->flags);
713 return -EINVAL;
714 }
715
716 switch (args->operation) {
717 case AMDGPU_VA_OP_MAP:
718 case AMDGPU_VA_OP_UNMAP:
719 case AMDGPU_VA_OP_CLEAR:
720 case AMDGPU_VA_OP_REPLACE:
721 break;
722 default:
723 dev_dbg(dev->dev, "unsupported operation %d\n",
724 args->operation);
725 return -EINVAL;
726 }
727
728 INIT_LIST_HEAD(&list);
729 INIT_LIST_HEAD(&duplicates);
730 if ((args->operation != AMDGPU_VA_OP_CLEAR) &&
731 !(args->flags & AMDGPU_VM_PAGE_PRT)) {
732 gobj = drm_gem_object_lookup(filp, args->handle);
733 if (gobj == NULL)
734 return -ENOENT;
735 abo = gem_to_amdgpu_bo(gobj);
736 tv.bo = &abo->tbo;
737 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
738 tv.num_shared = 1;
739 else
740 tv.num_shared = 0;
741 list_add(&tv.head, &list);
742 } else {
743 gobj = NULL;
744 abo = NULL;
745 }
746
747 amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd);
748
749 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
750 if (r)
751 goto error_unref;
752
753 if (abo) {
754 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
755 if (!bo_va) {
756 r = -ENOENT;
757 goto error_backoff;
758 }
759 } else if (args->operation != AMDGPU_VA_OP_CLEAR) {
760 bo_va = fpriv->prt_va;
761 } else {
762 bo_va = NULL;
763 }
764
765 switch (args->operation) {
766 case AMDGPU_VA_OP_MAP:
767 va_flags = amdgpu_gem_va_map_flags(adev, args->flags);
768 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
769 args->offset_in_bo, args->map_size,
770 va_flags);
771 break;
772 case AMDGPU_VA_OP_UNMAP:
773 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
774 break;
775
776 case AMDGPU_VA_OP_CLEAR:
777 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm,
778 args->va_address,
779 args->map_size);
780 break;
781 case AMDGPU_VA_OP_REPLACE:
782 va_flags = amdgpu_gem_va_map_flags(adev, args->flags);
783 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address,
784 args->offset_in_bo, args->map_size,
785 va_flags);
786 break;
787 default:
788 break;
789 }
790 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug)
791 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va,
792 args->operation);
793
794error_backoff:
795 ttm_eu_backoff_reservation(&ticket, &list);
796
797error_unref:
798 drm_gem_object_put(gobj);
799 return r;
800}
801
802int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
803 struct drm_file *filp)
804{
805 struct amdgpu_device *adev = drm_to_adev(dev);
806 struct drm_amdgpu_gem_op *args = data;
807 struct drm_gem_object *gobj;
808 struct amdgpu_vm_bo_base *base;
809 struct amdgpu_bo *robj;
810 int r;
811
812 gobj = drm_gem_object_lookup(filp, args->handle);
813 if (gobj == NULL) {
814 return -ENOENT;
815 }
816 robj = gem_to_amdgpu_bo(gobj);
817
818 r = amdgpu_bo_reserve(robj, false);
819 if (unlikely(r))
820 goto out;
821
822 switch (args->op) {
823 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
824 struct drm_amdgpu_gem_create_in info;
825 void __user *out = u64_to_user_ptr(args->value);
826
827 info.bo_size = robj->tbo.base.size;
828 info.alignment = robj->tbo.page_alignment << PAGE_SHIFT;
829 info.domains = robj->preferred_domains;
830 info.domain_flags = robj->flags;
831 amdgpu_bo_unreserve(robj);
832 if (copy_to_user(out, &info, sizeof(info)))
833 r = -EFAULT;
834 break;
835 }
836 case AMDGPU_GEM_OP_SET_PLACEMENT:
837 if (robj->tbo.base.import_attach &&
838 args->value & AMDGPU_GEM_DOMAIN_VRAM) {
839 r = -EINVAL;
840 amdgpu_bo_unreserve(robj);
841 break;
842 }
843 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
844 r = -EPERM;
845 amdgpu_bo_unreserve(robj);
846 break;
847 }
848 for (base = robj->vm_bo; base; base = base->next)
849 if (amdgpu_xgmi_same_hive(amdgpu_ttm_adev(robj->tbo.bdev),
850 amdgpu_ttm_adev(base->vm->root.bo->tbo.bdev))) {
851 r = -EINVAL;
852 amdgpu_bo_unreserve(robj);
853 goto out;
854 }
855
856
857 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
858 AMDGPU_GEM_DOMAIN_GTT |
859 AMDGPU_GEM_DOMAIN_CPU);
860 robj->allowed_domains = robj->preferred_domains;
861 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
862 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
863
864 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
865 amdgpu_vm_bo_invalidate(adev, robj, true);
866
867 amdgpu_bo_unreserve(robj);
868 break;
869 default:
870 amdgpu_bo_unreserve(robj);
871 r = -EINVAL;
872 }
873
874out:
875 drm_gem_object_put(gobj);
876 return r;
877}
878
879static int amdgpu_gem_align_pitch(struct amdgpu_device *adev,
880 int width,
881 int cpp,
882 bool tiled)
883{
884 int aligned = width;
885 int pitch_mask = 0;
886
887 switch (cpp) {
888 case 1:
889 pitch_mask = 255;
890 break;
891 case 2:
892 pitch_mask = 127;
893 break;
894 case 3:
895 case 4:
896 pitch_mask = 63;
897 break;
898 }
899
900 aligned += pitch_mask;
901 aligned &= ~pitch_mask;
902 return aligned * cpp;
903}
904
905int amdgpu_mode_dumb_create(struct drm_file *file_priv,
906 struct drm_device *dev,
907 struct drm_mode_create_dumb *args)
908{
909 struct amdgpu_device *adev = drm_to_adev(dev);
910 struct drm_gem_object *gobj;
911 uint32_t handle;
912 u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
913 AMDGPU_GEM_CREATE_CPU_GTT_USWC |
914 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
915 u32 domain;
916 int r;
917
918 /*
919 * The buffer returned from this function should be cleared, but
920 * it can only be done if the ring is enabled or we'll fail to
921 * create the buffer.
922 */
923 if (adev->mman.buffer_funcs_enabled)
924 flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED;
925
926 args->pitch = amdgpu_gem_align_pitch(adev, args->width,
927 DIV_ROUND_UP(args->bpp, 8), 0);
928 args->size = (u64)args->pitch * args->height;
929 args->size = ALIGN(args->size, PAGE_SIZE);
930 domain = amdgpu_bo_get_preferred_domain(adev,
931 amdgpu_display_supported_domains(adev, flags));
932 r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags,
933 ttm_bo_type_device, NULL, &gobj);
934 if (r)
935 return -ENOMEM;
936
937 r = drm_gem_handle_create(file_priv, gobj, &handle);
938 /* drop reference from allocate - handle holds it now */
939 drm_gem_object_put(gobj);
940 if (r) {
941 return r;
942 }
943 args->handle = handle;
944 return 0;
945}
946
947#if defined(CONFIG_DEBUG_FS)
948static int amdgpu_debugfs_gem_info_show(struct seq_file *m, void *unused)
949{
950 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
951 struct drm_device *dev = adev_to_drm(adev);
952 struct drm_file *file;
953 int r;
954
955 r = mutex_lock_interruptible(&dev->filelist_mutex);
956 if (r)
957 return r;
958
959 list_for_each_entry(file, &dev->filelist, lhead) {
960 struct task_struct *task;
961 struct drm_gem_object *gobj;
962 int id;
963
964 /*
965 * Although we have a valid reference on file->pid, that does
966 * not guarantee that the task_struct who called get_pid() is
967 * still alive (e.g. get_pid(current) => fork() => exit()).
968 * Therefore, we need to protect this ->comm access using RCU.
969 */
970 rcu_read_lock();
971 task = pid_task(file->pid, PIDTYPE_PID);
972 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid),
973 task ? task->comm : "<unknown>");
974 rcu_read_unlock();
975
976 spin_lock(&file->table_lock);
977 idr_for_each_entry(&file->object_idr, gobj, id) {
978 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
979
980 amdgpu_bo_print_info(id, bo, m);
981 }
982 spin_unlock(&file->table_lock);
983 }
984
985 mutex_unlock(&dev->filelist_mutex);
986 return 0;
987}
988
989DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_gem_info);
990
991#endif
992
993void amdgpu_debugfs_gem_init(struct amdgpu_device *adev)
994{
995#if defined(CONFIG_DEBUG_FS)
996 struct drm_minor *minor = adev_to_drm(adev)->primary;
997 struct dentry *root = minor->debugfs_root;
998
999 debugfs_create_file("amdgpu_gem_info", 0444, root, adev,
1000 &amdgpu_debugfs_gem_info_fops);
1001#endif
1002}
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/ktime.h>
29#include <linux/module.h>
30#include <linux/pagemap.h>
31#include <linux/pci.h>
32#include <linux/dma-buf.h>
33
34#include <drm/amdgpu_drm.h>
35#include <drm/drm_debugfs.h>
36
37#include "amdgpu.h"
38#include "amdgpu_display.h"
39#include "amdgpu_xgmi.h"
40
41void amdgpu_gem_object_free(struct drm_gem_object *gobj)
42{
43 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
44
45 if (robj) {
46 amdgpu_mn_unregister(robj);
47 amdgpu_bo_unref(&robj);
48 }
49}
50
51int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
52 int alignment, u32 initial_domain,
53 u64 flags, enum ttm_bo_type type,
54 struct dma_resv *resv,
55 struct drm_gem_object **obj)
56{
57 struct amdgpu_bo *bo;
58 struct amdgpu_bo_param bp;
59 int r;
60
61 memset(&bp, 0, sizeof(bp));
62 *obj = NULL;
63
64 bp.size = size;
65 bp.byte_align = alignment;
66 bp.type = type;
67 bp.resv = resv;
68 bp.preferred_domain = initial_domain;
69retry:
70 bp.flags = flags;
71 bp.domain = initial_domain;
72 r = amdgpu_bo_create(adev, &bp, &bo);
73 if (r) {
74 if (r != -ERESTARTSYS) {
75 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
76 flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
77 goto retry;
78 }
79
80 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
81 initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
82 goto retry;
83 }
84 DRM_DEBUG("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
85 size, initial_domain, alignment, r);
86 }
87 return r;
88 }
89 *obj = &bo->tbo.base;
90
91 return 0;
92}
93
94void amdgpu_gem_force_release(struct amdgpu_device *adev)
95{
96 struct drm_device *ddev = adev->ddev;
97 struct drm_file *file;
98
99 mutex_lock(&ddev->filelist_mutex);
100
101 list_for_each_entry(file, &ddev->filelist, lhead) {
102 struct drm_gem_object *gobj;
103 int handle;
104
105 WARN_ONCE(1, "Still active user space clients!\n");
106 spin_lock(&file->table_lock);
107 idr_for_each_entry(&file->object_idr, gobj, handle) {
108 WARN_ONCE(1, "And also active allocations!\n");
109 drm_gem_object_put(gobj);
110 }
111 idr_destroy(&file->object_idr);
112 spin_unlock(&file->table_lock);
113 }
114
115 mutex_unlock(&ddev->filelist_mutex);
116}
117
118/*
119 * Call from drm_gem_handle_create which appear in both new and open ioctl
120 * case.
121 */
122int amdgpu_gem_object_open(struct drm_gem_object *obj,
123 struct drm_file *file_priv)
124{
125 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj);
126 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
127 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
128 struct amdgpu_vm *vm = &fpriv->vm;
129 struct amdgpu_bo_va *bo_va;
130 struct mm_struct *mm;
131 int r;
132
133 mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm);
134 if (mm && mm != current->mm)
135 return -EPERM;
136
137 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID &&
138 abo->tbo.base.resv != vm->root.base.bo->tbo.base.resv)
139 return -EPERM;
140
141 r = amdgpu_bo_reserve(abo, false);
142 if (r)
143 return r;
144
145 bo_va = amdgpu_vm_bo_find(vm, abo);
146 if (!bo_va) {
147 bo_va = amdgpu_vm_bo_add(adev, vm, abo);
148 } else {
149 ++bo_va->ref_count;
150 }
151 amdgpu_bo_unreserve(abo);
152 return 0;
153}
154
155void amdgpu_gem_object_close(struct drm_gem_object *obj,
156 struct drm_file *file_priv)
157{
158 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
159 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
160 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
161 struct amdgpu_vm *vm = &fpriv->vm;
162
163 struct amdgpu_bo_list_entry vm_pd;
164 struct list_head list, duplicates;
165 struct dma_fence *fence = NULL;
166 struct ttm_validate_buffer tv;
167 struct ww_acquire_ctx ticket;
168 struct amdgpu_bo_va *bo_va;
169 long r;
170
171 INIT_LIST_HEAD(&list);
172 INIT_LIST_HEAD(&duplicates);
173
174 tv.bo = &bo->tbo;
175 tv.num_shared = 2;
176 list_add(&tv.head, &list);
177
178 amdgpu_vm_get_pd_bo(vm, &list, &vm_pd);
179
180 r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates);
181 if (r) {
182 dev_err(adev->dev, "leaking bo va because "
183 "we fail to reserve bo (%ld)\n", r);
184 return;
185 }
186 bo_va = amdgpu_vm_bo_find(vm, bo);
187 if (!bo_va || --bo_va->ref_count)
188 goto out_unlock;
189
190 amdgpu_vm_bo_rmv(adev, bo_va);
191 if (!amdgpu_vm_ready(vm))
192 goto out_unlock;
193
194 fence = dma_resv_get_excl(bo->tbo.base.resv);
195 if (fence) {
196 amdgpu_bo_fence(bo, fence, true);
197 fence = NULL;
198 }
199
200 r = amdgpu_vm_clear_freed(adev, vm, &fence);
201 if (r || !fence)
202 goto out_unlock;
203
204 amdgpu_bo_fence(bo, fence, true);
205 dma_fence_put(fence);
206
207out_unlock:
208 if (unlikely(r < 0))
209 dev_err(adev->dev, "failed to clear page "
210 "tables on GEM object close (%ld)\n", r);
211 ttm_eu_backoff_reservation(&ticket, &list);
212}
213
214/*
215 * GEM ioctls.
216 */
217int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
218 struct drm_file *filp)
219{
220 struct amdgpu_device *adev = dev->dev_private;
221 struct amdgpu_fpriv *fpriv = filp->driver_priv;
222 struct amdgpu_vm *vm = &fpriv->vm;
223 union drm_amdgpu_gem_create *args = data;
224 uint64_t flags = args->in.domain_flags;
225 uint64_t size = args->in.bo_size;
226 struct dma_resv *resv = NULL;
227 struct drm_gem_object *gobj;
228 uint32_t handle;
229 int r;
230
231 /* reject invalid gem flags */
232 if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
233 AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
234 AMDGPU_GEM_CREATE_CPU_GTT_USWC |
235 AMDGPU_GEM_CREATE_VRAM_CLEARED |
236 AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
237 AMDGPU_GEM_CREATE_EXPLICIT_SYNC |
238 AMDGPU_GEM_CREATE_ENCRYPTED))
239
240 return -EINVAL;
241
242 /* reject invalid gem domains */
243 if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK)
244 return -EINVAL;
245
246 if (!amdgpu_is_tmz(adev) && (flags & AMDGPU_GEM_CREATE_ENCRYPTED)) {
247 DRM_NOTE_ONCE("Cannot allocate secure buffer since TMZ is disabled\n");
248 return -EINVAL;
249 }
250
251 /* create a gem object to contain this object in */
252 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
253 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
254 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
255 /* if gds bo is created from user space, it must be
256 * passed to bo list
257 */
258 DRM_ERROR("GDS bo cannot be per-vm-bo\n");
259 return -EINVAL;
260 }
261 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
262 }
263
264 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
265 r = amdgpu_bo_reserve(vm->root.base.bo, false);
266 if (r)
267 return r;
268
269 resv = vm->root.base.bo->tbo.base.resv;
270 }
271
272 r = amdgpu_gem_object_create(adev, size, args->in.alignment,
273 (u32)(0xffffffff & args->in.domains),
274 flags, ttm_bo_type_device, resv, &gobj);
275 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
276 if (!r) {
277 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
278
279 abo->parent = amdgpu_bo_ref(vm->root.base.bo);
280 }
281 amdgpu_bo_unreserve(vm->root.base.bo);
282 }
283 if (r)
284 return r;
285
286 r = drm_gem_handle_create(filp, gobj, &handle);
287 /* drop reference from allocate - handle holds it now */
288 drm_gem_object_put(gobj);
289 if (r)
290 return r;
291
292 memset(args, 0, sizeof(*args));
293 args->out.handle = handle;
294 return 0;
295}
296
297int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
298 struct drm_file *filp)
299{
300 struct ttm_operation_ctx ctx = { true, false };
301 struct amdgpu_device *adev = dev->dev_private;
302 struct drm_amdgpu_gem_userptr *args = data;
303 struct drm_gem_object *gobj;
304 struct amdgpu_bo *bo;
305 uint32_t handle;
306 int r;
307
308 args->addr = untagged_addr(args->addr);
309
310 if (offset_in_page(args->addr | args->size))
311 return -EINVAL;
312
313 /* reject unknown flag values */
314 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
315 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
316 AMDGPU_GEM_USERPTR_REGISTER))
317 return -EINVAL;
318
319 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) &&
320 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
321
322 /* if we want to write to it we must install a MMU notifier */
323 return -EACCES;
324 }
325
326 /* create a gem object to contain this object in */
327 r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU,
328 0, ttm_bo_type_device, NULL, &gobj);
329 if (r)
330 return r;
331
332 bo = gem_to_amdgpu_bo(gobj);
333 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
334 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
335 r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags);
336 if (r)
337 goto release_object;
338
339 if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) {
340 r = amdgpu_mn_register(bo, args->addr);
341 if (r)
342 goto release_object;
343 }
344
345 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
346 r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages);
347 if (r)
348 goto release_object;
349
350 r = amdgpu_bo_reserve(bo, true);
351 if (r)
352 goto user_pages_done;
353
354 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
355 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
356 amdgpu_bo_unreserve(bo);
357 if (r)
358 goto user_pages_done;
359 }
360
361 r = drm_gem_handle_create(filp, gobj, &handle);
362 if (r)
363 goto user_pages_done;
364
365 args->handle = handle;
366
367user_pages_done:
368 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE)
369 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
370
371release_object:
372 drm_gem_object_put(gobj);
373
374 return r;
375}
376
377int amdgpu_mode_dumb_mmap(struct drm_file *filp,
378 struct drm_device *dev,
379 uint32_t handle, uint64_t *offset_p)
380{
381 struct drm_gem_object *gobj;
382 struct amdgpu_bo *robj;
383
384 gobj = drm_gem_object_lookup(filp, handle);
385 if (gobj == NULL) {
386 return -ENOENT;
387 }
388 robj = gem_to_amdgpu_bo(gobj);
389 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) ||
390 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
391 drm_gem_object_put(gobj);
392 return -EPERM;
393 }
394 *offset_p = amdgpu_bo_mmap_offset(robj);
395 drm_gem_object_put(gobj);
396 return 0;
397}
398
399int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
400 struct drm_file *filp)
401{
402 union drm_amdgpu_gem_mmap *args = data;
403 uint32_t handle = args->in.handle;
404 memset(args, 0, sizeof(*args));
405 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
406}
407
408/**
409 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
410 *
411 * @timeout_ns: timeout in ns
412 *
413 * Calculate the timeout in jiffies from an absolute timeout in ns.
414 */
415unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
416{
417 unsigned long timeout_jiffies;
418 ktime_t timeout;
419
420 /* clamp timeout if it's to large */
421 if (((int64_t)timeout_ns) < 0)
422 return MAX_SCHEDULE_TIMEOUT;
423
424 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
425 if (ktime_to_ns(timeout) < 0)
426 return 0;
427
428 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
429 /* clamp timeout to avoid unsigned-> signed overflow */
430 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT )
431 return MAX_SCHEDULE_TIMEOUT - 1;
432
433 return timeout_jiffies;
434}
435
436int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
437 struct drm_file *filp)
438{
439 union drm_amdgpu_gem_wait_idle *args = data;
440 struct drm_gem_object *gobj;
441 struct amdgpu_bo *robj;
442 uint32_t handle = args->in.handle;
443 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
444 int r = 0;
445 long ret;
446
447 gobj = drm_gem_object_lookup(filp, handle);
448 if (gobj == NULL) {
449 return -ENOENT;
450 }
451 robj = gem_to_amdgpu_bo(gobj);
452 ret = dma_resv_wait_timeout_rcu(robj->tbo.base.resv, true, true,
453 timeout);
454
455 /* ret == 0 means not signaled,
456 * ret > 0 means signaled
457 * ret < 0 means interrupted before timeout
458 */
459 if (ret >= 0) {
460 memset(args, 0, sizeof(*args));
461 args->out.status = (ret == 0);
462 } else
463 r = ret;
464
465 drm_gem_object_put(gobj);
466 return r;
467}
468
469int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
470 struct drm_file *filp)
471{
472 struct drm_amdgpu_gem_metadata *args = data;
473 struct drm_gem_object *gobj;
474 struct amdgpu_bo *robj;
475 int r = -1;
476
477 DRM_DEBUG("%d \n", args->handle);
478 gobj = drm_gem_object_lookup(filp, args->handle);
479 if (gobj == NULL)
480 return -ENOENT;
481 robj = gem_to_amdgpu_bo(gobj);
482
483 r = amdgpu_bo_reserve(robj, false);
484 if (unlikely(r != 0))
485 goto out;
486
487 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
488 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
489 r = amdgpu_bo_get_metadata(robj, args->data.data,
490 sizeof(args->data.data),
491 &args->data.data_size_bytes,
492 &args->data.flags);
493 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
494 if (args->data.data_size_bytes > sizeof(args->data.data)) {
495 r = -EINVAL;
496 goto unreserve;
497 }
498 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
499 if (!r)
500 r = amdgpu_bo_set_metadata(robj, args->data.data,
501 args->data.data_size_bytes,
502 args->data.flags);
503 }
504
505unreserve:
506 amdgpu_bo_unreserve(robj);
507out:
508 drm_gem_object_put(gobj);
509 return r;
510}
511
512/**
513 * amdgpu_gem_va_update_vm -update the bo_va in its VM
514 *
515 * @adev: amdgpu_device pointer
516 * @vm: vm to update
517 * @bo_va: bo_va to update
518 * @operation: map, unmap or clear
519 *
520 * Update the bo_va directly after setting its address. Errors are not
521 * vital here, so they are not reported back to userspace.
522 */
523static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
524 struct amdgpu_vm *vm,
525 struct amdgpu_bo_va *bo_va,
526 uint32_t operation)
527{
528 int r;
529
530 if (!amdgpu_vm_ready(vm))
531 return;
532
533 r = amdgpu_vm_clear_freed(adev, vm, NULL);
534 if (r)
535 goto error;
536
537 if (operation == AMDGPU_VA_OP_MAP ||
538 operation == AMDGPU_VA_OP_REPLACE) {
539 r = amdgpu_vm_bo_update(adev, bo_va, false);
540 if (r)
541 goto error;
542 }
543
544 r = amdgpu_vm_update_pdes(adev, vm, false);
545
546error:
547 if (r && r != -ERESTARTSYS)
548 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
549}
550
551/**
552 * amdgpu_gem_va_map_flags - map GEM UAPI flags into hardware flags
553 *
554 * @adev: amdgpu_device pointer
555 * @flags: GEM UAPI flags
556 *
557 * Returns the GEM UAPI flags mapped into hardware for the ASIC.
558 */
559uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags)
560{
561 uint64_t pte_flag = 0;
562
563 if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
564 pte_flag |= AMDGPU_PTE_EXECUTABLE;
565 if (flags & AMDGPU_VM_PAGE_READABLE)
566 pte_flag |= AMDGPU_PTE_READABLE;
567 if (flags & AMDGPU_VM_PAGE_WRITEABLE)
568 pte_flag |= AMDGPU_PTE_WRITEABLE;
569 if (flags & AMDGPU_VM_PAGE_PRT)
570 pte_flag |= AMDGPU_PTE_PRT;
571
572 if (adev->gmc.gmc_funcs->map_mtype)
573 pte_flag |= amdgpu_gmc_map_mtype(adev,
574 flags & AMDGPU_VM_MTYPE_MASK);
575
576 return pte_flag;
577}
578
579int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
580 struct drm_file *filp)
581{
582 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
583 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
584 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK;
585 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
586 AMDGPU_VM_PAGE_PRT;
587
588 struct drm_amdgpu_gem_va *args = data;
589 struct drm_gem_object *gobj;
590 struct amdgpu_device *adev = dev->dev_private;
591 struct amdgpu_fpriv *fpriv = filp->driver_priv;
592 struct amdgpu_bo *abo;
593 struct amdgpu_bo_va *bo_va;
594 struct amdgpu_bo_list_entry vm_pd;
595 struct ttm_validate_buffer tv;
596 struct ww_acquire_ctx ticket;
597 struct list_head list, duplicates;
598 uint64_t va_flags;
599 int r = 0;
600
601 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
602 dev_dbg(&dev->pdev->dev,
603 "va_address 0x%LX is in reserved area 0x%LX\n",
604 args->va_address, AMDGPU_VA_RESERVED_SIZE);
605 return -EINVAL;
606 }
607
608 if (args->va_address >= AMDGPU_GMC_HOLE_START &&
609 args->va_address < AMDGPU_GMC_HOLE_END) {
610 dev_dbg(&dev->pdev->dev,
611 "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n",
612 args->va_address, AMDGPU_GMC_HOLE_START,
613 AMDGPU_GMC_HOLE_END);
614 return -EINVAL;
615 }
616
617 args->va_address &= AMDGPU_GMC_HOLE_MASK;
618
619 if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
620 dev_dbg(&dev->pdev->dev, "invalid flags combination 0x%08X\n",
621 args->flags);
622 return -EINVAL;
623 }
624
625 switch (args->operation) {
626 case AMDGPU_VA_OP_MAP:
627 case AMDGPU_VA_OP_UNMAP:
628 case AMDGPU_VA_OP_CLEAR:
629 case AMDGPU_VA_OP_REPLACE:
630 break;
631 default:
632 dev_dbg(&dev->pdev->dev, "unsupported operation %d\n",
633 args->operation);
634 return -EINVAL;
635 }
636
637 INIT_LIST_HEAD(&list);
638 INIT_LIST_HEAD(&duplicates);
639 if ((args->operation != AMDGPU_VA_OP_CLEAR) &&
640 !(args->flags & AMDGPU_VM_PAGE_PRT)) {
641 gobj = drm_gem_object_lookup(filp, args->handle);
642 if (gobj == NULL)
643 return -ENOENT;
644 abo = gem_to_amdgpu_bo(gobj);
645 tv.bo = &abo->tbo;
646 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
647 tv.num_shared = 1;
648 else
649 tv.num_shared = 0;
650 list_add(&tv.head, &list);
651 } else {
652 gobj = NULL;
653 abo = NULL;
654 }
655
656 amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd);
657
658 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
659 if (r)
660 goto error_unref;
661
662 if (abo) {
663 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
664 if (!bo_va) {
665 r = -ENOENT;
666 goto error_backoff;
667 }
668 } else if (args->operation != AMDGPU_VA_OP_CLEAR) {
669 bo_va = fpriv->prt_va;
670 } else {
671 bo_va = NULL;
672 }
673
674 switch (args->operation) {
675 case AMDGPU_VA_OP_MAP:
676 va_flags = amdgpu_gem_va_map_flags(adev, args->flags);
677 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
678 args->offset_in_bo, args->map_size,
679 va_flags);
680 break;
681 case AMDGPU_VA_OP_UNMAP:
682 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
683 break;
684
685 case AMDGPU_VA_OP_CLEAR:
686 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm,
687 args->va_address,
688 args->map_size);
689 break;
690 case AMDGPU_VA_OP_REPLACE:
691 va_flags = amdgpu_gem_va_map_flags(adev, args->flags);
692 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address,
693 args->offset_in_bo, args->map_size,
694 va_flags);
695 break;
696 default:
697 break;
698 }
699 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug)
700 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va,
701 args->operation);
702
703error_backoff:
704 ttm_eu_backoff_reservation(&ticket, &list);
705
706error_unref:
707 drm_gem_object_put(gobj);
708 return r;
709}
710
711int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
712 struct drm_file *filp)
713{
714 struct amdgpu_device *adev = dev->dev_private;
715 struct drm_amdgpu_gem_op *args = data;
716 struct drm_gem_object *gobj;
717 struct amdgpu_vm_bo_base *base;
718 struct amdgpu_bo *robj;
719 int r;
720
721 gobj = drm_gem_object_lookup(filp, args->handle);
722 if (gobj == NULL) {
723 return -ENOENT;
724 }
725 robj = gem_to_amdgpu_bo(gobj);
726
727 r = amdgpu_bo_reserve(robj, false);
728 if (unlikely(r))
729 goto out;
730
731 switch (args->op) {
732 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
733 struct drm_amdgpu_gem_create_in info;
734 void __user *out = u64_to_user_ptr(args->value);
735
736 info.bo_size = robj->tbo.base.size;
737 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT;
738 info.domains = robj->preferred_domains;
739 info.domain_flags = robj->flags;
740 amdgpu_bo_unreserve(robj);
741 if (copy_to_user(out, &info, sizeof(info)))
742 r = -EFAULT;
743 break;
744 }
745 case AMDGPU_GEM_OP_SET_PLACEMENT:
746 if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) {
747 r = -EINVAL;
748 amdgpu_bo_unreserve(robj);
749 break;
750 }
751 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
752 r = -EPERM;
753 amdgpu_bo_unreserve(robj);
754 break;
755 }
756 for (base = robj->vm_bo; base; base = base->next)
757 if (amdgpu_xgmi_same_hive(amdgpu_ttm_adev(robj->tbo.bdev),
758 amdgpu_ttm_adev(base->vm->root.base.bo->tbo.bdev))) {
759 r = -EINVAL;
760 amdgpu_bo_unreserve(robj);
761 goto out;
762 }
763
764
765 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
766 AMDGPU_GEM_DOMAIN_GTT |
767 AMDGPU_GEM_DOMAIN_CPU);
768 robj->allowed_domains = robj->preferred_domains;
769 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
770 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
771
772 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
773 amdgpu_vm_bo_invalidate(adev, robj, true);
774
775 amdgpu_bo_unreserve(robj);
776 break;
777 default:
778 amdgpu_bo_unreserve(robj);
779 r = -EINVAL;
780 }
781
782out:
783 drm_gem_object_put(gobj);
784 return r;
785}
786
787int amdgpu_mode_dumb_create(struct drm_file *file_priv,
788 struct drm_device *dev,
789 struct drm_mode_create_dumb *args)
790{
791 struct amdgpu_device *adev = dev->dev_private;
792 struct drm_gem_object *gobj;
793 uint32_t handle;
794 u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
795 AMDGPU_GEM_CREATE_CPU_GTT_USWC;
796 u32 domain;
797 int r;
798
799 /*
800 * The buffer returned from this function should be cleared, but
801 * it can only be done if the ring is enabled or we'll fail to
802 * create the buffer.
803 */
804 if (adev->mman.buffer_funcs_enabled)
805 flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED;
806
807 args->pitch = amdgpu_align_pitch(adev, args->width,
808 DIV_ROUND_UP(args->bpp, 8), 0);
809 args->size = (u64)args->pitch * args->height;
810 args->size = ALIGN(args->size, PAGE_SIZE);
811 domain = amdgpu_bo_get_preferred_pin_domain(adev,
812 amdgpu_display_supported_domains(adev, flags));
813 r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags,
814 ttm_bo_type_device, NULL, &gobj);
815 if (r)
816 return -ENOMEM;
817
818 r = drm_gem_handle_create(file_priv, gobj, &handle);
819 /* drop reference from allocate - handle holds it now */
820 drm_gem_object_put(gobj);
821 if (r) {
822 return r;
823 }
824 args->handle = handle;
825 return 0;
826}
827
828#if defined(CONFIG_DEBUG_FS)
829
830#define amdgpu_debugfs_gem_bo_print_flag(m, bo, flag) \
831 if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \
832 seq_printf((m), " " #flag); \
833 }
834
835static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data)
836{
837 struct drm_gem_object *gobj = ptr;
838 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
839 struct seq_file *m = data;
840
841 struct dma_buf_attachment *attachment;
842 struct dma_buf *dma_buf;
843 unsigned domain;
844 const char *placement;
845 unsigned pin_count;
846
847 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
848 switch (domain) {
849 case AMDGPU_GEM_DOMAIN_VRAM:
850 placement = "VRAM";
851 break;
852 case AMDGPU_GEM_DOMAIN_GTT:
853 placement = " GTT";
854 break;
855 case AMDGPU_GEM_DOMAIN_CPU:
856 default:
857 placement = " CPU";
858 break;
859 }
860 seq_printf(m, "\t0x%08x: %12ld byte %s",
861 id, amdgpu_bo_size(bo), placement);
862
863 pin_count = READ_ONCE(bo->pin_count);
864 if (pin_count)
865 seq_printf(m, " pin count %d", pin_count);
866
867 dma_buf = READ_ONCE(bo->tbo.base.dma_buf);
868 attachment = READ_ONCE(bo->tbo.base.import_attach);
869
870 if (attachment)
871 seq_printf(m, " imported from %p%s", dma_buf,
872 attachment->peer2peer ? " P2P" : "");
873 else if (dma_buf)
874 seq_printf(m, " exported as %p", dma_buf);
875
876 amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED);
877 amdgpu_debugfs_gem_bo_print_flag(m, bo, NO_CPU_ACCESS);
878 amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_GTT_USWC);
879 amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CLEARED);
880 amdgpu_debugfs_gem_bo_print_flag(m, bo, SHADOW);
881 amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CONTIGUOUS);
882 amdgpu_debugfs_gem_bo_print_flag(m, bo, VM_ALWAYS_VALID);
883 amdgpu_debugfs_gem_bo_print_flag(m, bo, EXPLICIT_SYNC);
884
885 seq_printf(m, "\n");
886
887 return 0;
888}
889
890static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
891{
892 struct drm_info_node *node = (struct drm_info_node *)m->private;
893 struct drm_device *dev = node->minor->dev;
894 struct drm_file *file;
895 int r;
896
897 r = mutex_lock_interruptible(&dev->filelist_mutex);
898 if (r)
899 return r;
900
901 list_for_each_entry(file, &dev->filelist, lhead) {
902 struct task_struct *task;
903
904 /*
905 * Although we have a valid reference on file->pid, that does
906 * not guarantee that the task_struct who called get_pid() is
907 * still alive (e.g. get_pid(current) => fork() => exit()).
908 * Therefore, we need to protect this ->comm access using RCU.
909 */
910 rcu_read_lock();
911 task = pid_task(file->pid, PIDTYPE_PID);
912 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid),
913 task ? task->comm : "<unknown>");
914 rcu_read_unlock();
915
916 spin_lock(&file->table_lock);
917 idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m);
918 spin_unlock(&file->table_lock);
919 }
920
921 mutex_unlock(&dev->filelist_mutex);
922 return 0;
923}
924
925static const struct drm_info_list amdgpu_debugfs_gem_list[] = {
926 {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL},
927};
928#endif
929
930int amdgpu_debugfs_gem_init(struct amdgpu_device *adev)
931{
932#if defined(CONFIG_DEBUG_FS)
933 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list,
934 ARRAY_SIZE(amdgpu_debugfs_gem_list));
935#endif
936 return 0;
937}