1/*
  2 * Copyright 2011, Netlogic Microsystems.
  3 * Copyright 2004, Matt Porter <mporter@kernel.crashing.org>
  4 *
  5 * This file is licensed under the terms of the GNU General Public
  6 * License version 2.  This program is licensed "as is" without any
  7 * warranty of any kind, whether express or implied.
  8 */
  9
 10#include <linux/device.h>
 11#include <linux/platform_device.h>
 12#include <linux/kernel.h>
 13#include <linux/init.h>
 14#include <linux/io.h>
 15#include <linux/delay.h>
 16#include <linux/ioport.h>
 17#include <linux/resource.h>
 18#include <linux/spi/flash.h>
 19
 20#include <linux/mtd/mtd.h>
 21#include <linux/mtd/physmap.h>
 22#include <linux/mtd/platnand.h>
 23
 24#include <asm/netlogic/haldefs.h>
 25#include <asm/netlogic/xlr/iomap.h>
 26#include <asm/netlogic/xlr/flash.h>
 27#include <asm/netlogic/xlr/bridge.h>
 28#include <asm/netlogic/xlr/gpio.h>
 29#include <asm/netlogic/xlr/xlr.h>
 30
 31/*
 32 * Default NOR partition layout
 33 */
 34static struct mtd_partition xlr_nor_parts[] = {
 35	{
 36		.name = "User FS",
 37		.offset = 0x800000,
 38		.size	= MTDPART_SIZ_FULL,
 39	}
 40};
 41
 42/*
 43 * Default NAND partition layout
 44 */
 45static struct mtd_partition xlr_nand_parts[] = {
 46	{
 47		.name	= "Root Filesystem",
 48		.offset = 64 * 64 * 2048,
 49		.size	= 432 * 64 * 2048,
 50	},
 51	{
 52		.name	= "Home Filesystem",
 53		.offset = MTDPART_OFS_APPEND,
 54		.size	= MTDPART_SIZ_FULL,
 55	},
 56};
 57
 58/* Use PHYSMAP flash for NOR */
 59struct physmap_flash_data xlr_nor_data = {
 60	.width		= 2,
 61	.parts		= xlr_nor_parts,
 62	.nr_parts	= ARRAY_SIZE(xlr_nor_parts),
 63};
 64
 65static struct resource xlr_nor_res[] = {
 66	{
 67		.flags	= IORESOURCE_MEM,
 68	},
 69};
 70
 71static struct platform_device xlr_nor_dev = {
 72	.name	= "physmap-flash",
 73	.dev	= {
 74		.platform_data	= &xlr_nor_data,
 75	},
 76	.num_resources	= ARRAY_SIZE(xlr_nor_res),
 77	.resource	= xlr_nor_res,
 78};
 79
 80/*
 81 * Use "gen_nand" driver for NAND flash
 82 *
 83 * There seems to be no way to store a private pointer containing
 84 * platform specific info in gen_nand drivier. We will use a global
 85 * struct for now, since we currently have only one NAND chip per board.
 86 */
 87struct xlr_nand_flash_priv {
 88	int cs;
 89	uint64_t flash_mmio;
 90};
 91
 92static struct xlr_nand_flash_priv nand_priv;
 93
 94static void xlr_nand_ctrl(struct nand_chip *chip, int cmd,
 95			  unsigned int ctrl)
 96{
 97	if (ctrl & NAND_CLE)
 98		nlm_write_reg(nand_priv.flash_mmio,
 99			FLASH_NAND_CLE(nand_priv.cs), cmd);
100	else if (ctrl & NAND_ALE)
101		nlm_write_reg(nand_priv.flash_mmio,
102			FLASH_NAND_ALE(nand_priv.cs), cmd);
103}
104
105struct platform_nand_data xlr_nand_data = {
106	.chip = {
107		.nr_chips	= 1,
108		.nr_partitions	= ARRAY_SIZE(xlr_nand_parts),
109		.chip_delay	= 50,
110		.partitions	= xlr_nand_parts,
111	},
112	.ctrl = {
113		.cmd_ctrl	= xlr_nand_ctrl,
114	},
115};
116
117static struct resource xlr_nand_res[] = {
118	{
119		.flags		= IORESOURCE_MEM,
120	},
121};
122
123static struct platform_device xlr_nand_dev = {
124	.name		= "gen_nand",
125	.id		= -1,
126	.num_resources	= ARRAY_SIZE(xlr_nand_res),
127	.resource	= xlr_nand_res,
128	.dev		= {
129		.platform_data	= &xlr_nand_data,
130	}
131};
132
133/*
134 * XLR/XLS supports upto 8 devices on its FLASH interface. The value in
135 * FLASH_BAR (on the MEM/IO bridge) gives the base for mapping all the
136 * flash devices.
137 * Under this, each flash device has an offset and size given by the
138 * CSBASE_ADDR and CSBASE_MASK registers for the device.
139 *
140 * The CSBASE_ registers are expected to be setup by the bootloader.
141 */
142static void setup_flash_resource(uint64_t flash_mmio,
143	uint64_t flash_map_base, int cs, struct resource *res)
144{
145	u32 base, mask;
146
147	base = nlm_read_reg(flash_mmio, FLASH_CSBASE_ADDR(cs));
148	mask = nlm_read_reg(flash_mmio, FLASH_CSADDR_MASK(cs));
149
150	res->start = flash_map_base + ((unsigned long)base << 16);
151	res->end = res->start + (mask + 1) * 64 * 1024;
152}
153
154static int __init xlr_flash_init(void)
155{
156	uint64_t gpio_mmio, flash_mmio, flash_map_base;
157	u32 gpio_resetcfg, flash_bar;
158	int cs, boot_nand, boot_nor;
159
160	/* Flash address bits 39:24 is in bridge flash BAR */
161	flash_bar = nlm_read_reg(nlm_io_base, BRIDGE_FLASH_BAR);
162	flash_map_base = (flash_bar & 0xffff0000) << 8;
163
164	gpio_mmio = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET);
165	flash_mmio = nlm_mmio_base(NETLOGIC_IO_FLASH_OFFSET);
166
167	/* Get the chip reset config */
168	gpio_resetcfg = nlm_read_reg(gpio_mmio, GPIO_PWRON_RESET_CFG_REG);
169
170	/* Check for boot flash type */
171	boot_nor = boot_nand = 0;
172	if (nlm_chip_is_xls()) {
173		/* On XLS, check boot from NAND bit (GPIO reset reg bit 16) */
174		if (gpio_resetcfg & (1 << 16))
175			boot_nand = 1;
176
177		/* check boot from PCMCIA, (GPIO reset reg bit 15 */
178		if ((gpio_resetcfg & (1 << 15)) == 0)
179			boot_nor = 1;	/* not set, booted from NOR */
180	} else { /* XLR */
181		/* check boot from PCMCIA (bit 16 in GPIO reset on XLR) */
182		if ((gpio_resetcfg & (1 << 16)) == 0)
183			boot_nor = 1;	/* not set, booted from NOR */
184	}
185
186	/* boot flash at chip select 0 */
187	cs = 0;
188
189	if (boot_nand) {
190		nand_priv.cs = cs;
191		nand_priv.flash_mmio = flash_mmio;
192		setup_flash_resource(flash_mmio, flash_map_base, cs,
193			 xlr_nand_res);
194
195		/* Initialize NAND flash at CS 0 */
196		nlm_write_reg(flash_mmio, FLASH_CSDEV_PARM(cs),
197				FLASH_NAND_CSDEV_PARAM);
198		nlm_write_reg(flash_mmio, FLASH_CSTIME_PARMA(cs),
199				FLASH_NAND_CSTIME_PARAMA);
200		nlm_write_reg(flash_mmio, FLASH_CSTIME_PARMB(cs),
201				FLASH_NAND_CSTIME_PARAMB);
202
203		pr_info("ChipSelect %d: NAND Flash %pR\n", cs, xlr_nand_res);
204		return platform_device_register(&xlr_nand_dev);
205	}
206
207	if (boot_nor) {
208		setup_flash_resource(flash_mmio, flash_map_base, cs,
209			xlr_nor_res);
210		pr_info("ChipSelect %d: NOR Flash %pR\n", cs, xlr_nor_res);
211		return platform_device_register(&xlr_nor_dev);
212	}
213	return 0;
214}
215
216arch_initcall(xlr_flash_init);