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1// SPDX-License-Identifier: (GPL-2.0+ OR X11)
2/*
3 * Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
4 * Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com>
5 */
6
7#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
8#include <dt-bindings/reset/suniv-ccu-f1c100s.h>
9
10/ {
11 #address-cells = <1>;
12 #size-cells = <1>;
13 interrupt-parent = <&intc>;
14
15 clocks {
16 osc24M: clk-24M {
17 #clock-cells = <0>;
18 compatible = "fixed-clock";
19 clock-frequency = <24000000>;
20 clock-output-names = "osc24M";
21 };
22
23 osc32k: clk-32k {
24 #clock-cells = <0>;
25 compatible = "fixed-clock";
26 clock-frequency = <32768>;
27 clock-output-names = "osc32k";
28 };
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu@0 {
36 compatible = "arm,arm926ej-s";
37 device_type = "cpu";
38 reg = <0x0>;
39 };
40 };
41
42 soc {
43 compatible = "simple-bus";
44 #address-cells = <1>;
45 #size-cells = <1>;
46 ranges;
47
48 sram-controller@1c00000 {
49 compatible = "allwinner,suniv-f1c100s-system-control",
50 "allwinner,sun4i-a10-system-control";
51 reg = <0x01c00000 0x30>;
52 #address-cells = <1>;
53 #size-cells = <1>;
54 ranges;
55
56 sram_d: sram@10000 {
57 compatible = "mmio-sram";
58 reg = <0x00010000 0x1000>;
59 #address-cells = <1>;
60 #size-cells = <1>;
61 ranges = <0 0x00010000 0x1000>;
62
63 otg_sram: sram-section@0 {
64 compatible = "allwinner,suniv-f1c100s-sram-d",
65 "allwinner,sun4i-a10-sram-d";
66 reg = <0x0000 0x1000>;
67 status = "disabled";
68 };
69 };
70 };
71
72 spi0: spi@1c05000 {
73 compatible = "allwinner,suniv-f1c100s-spi",
74 "allwinner,sun8i-h3-spi";
75 reg = <0x01c05000 0x1000>;
76 interrupts = <10>;
77 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_BUS_SPI0>;
78 clock-names = "ahb", "mod";
79 resets = <&ccu RST_BUS_SPI0>;
80 status = "disabled";
81 num-cs = <1>;
82 #address-cells = <1>;
83 #size-cells = <0>;
84 };
85
86 spi1: spi@1c06000 {
87 compatible = "allwinner,suniv-f1c100s-spi",
88 "allwinner,sun8i-h3-spi";
89 reg = <0x01c06000 0x1000>;
90 interrupts = <11>;
91 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_BUS_SPI1>;
92 clock-names = "ahb", "mod";
93 resets = <&ccu RST_BUS_SPI1>;
94 status = "disabled";
95 num-cs = <1>;
96 #address-cells = <1>;
97 #size-cells = <0>;
98 };
99
100 mmc0: mmc@1c0f000 {
101 compatible = "allwinner,suniv-f1c100s-mmc",
102 "allwinner,sun7i-a20-mmc";
103 reg = <0x01c0f000 0x1000>;
104 clocks = <&ccu CLK_BUS_MMC0>,
105 <&ccu CLK_MMC0>,
106 <&ccu CLK_MMC0_OUTPUT>,
107 <&ccu CLK_MMC0_SAMPLE>;
108 clock-names = "ahb", "mmc", "output", "sample";
109 resets = <&ccu RST_BUS_MMC0>;
110 reset-names = "ahb";
111 interrupts = <23>;
112 pinctrl-names = "default";
113 pinctrl-0 = <&mmc0_pins>;
114 status = "disabled";
115 #address-cells = <1>;
116 #size-cells = <0>;
117 };
118
119 mmc1: mmc@1c10000 {
120 compatible = "allwinner,suniv-f1c100s-mmc",
121 "allwinner,sun7i-a20-mmc";
122 reg = <0x01c10000 0x1000>;
123 clocks = <&ccu CLK_BUS_MMC1>,
124 <&ccu CLK_MMC1>,
125 <&ccu CLK_MMC1_OUTPUT>,
126 <&ccu CLK_MMC1_SAMPLE>;
127 clock-names = "ahb", "mmc", "output", "sample";
128 resets = <&ccu RST_BUS_MMC1>;
129 reset-names = "ahb";
130 interrupts = <24>;
131 status = "disabled";
132 #address-cells = <1>;
133 #size-cells = <0>;
134 };
135
136 ccu: clock@1c20000 {
137 compatible = "allwinner,suniv-f1c100s-ccu";
138 reg = <0x01c20000 0x400>;
139 clocks = <&osc24M>, <&osc32k>;
140 clock-names = "hosc", "losc";
141 #clock-cells = <1>;
142 #reset-cells = <1>;
143 };
144
145 intc: interrupt-controller@1c20400 {
146 compatible = "allwinner,suniv-f1c100s-ic";
147 reg = <0x01c20400 0x400>;
148 interrupt-controller;
149 #interrupt-cells = <1>;
150 };
151
152 pio: pinctrl@1c20800 {
153 compatible = "allwinner,suniv-f1c100s-pinctrl";
154 reg = <0x01c20800 0x400>;
155 interrupts = <38>, <39>, <40>;
156 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
157 clock-names = "apb", "hosc", "losc";
158 gpio-controller;
159 interrupt-controller;
160 #interrupt-cells = <3>;
161 #gpio-cells = <3>;
162
163 mmc0_pins: mmc0-pins {
164 pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
165 function = "mmc0";
166 drive-strength = <30>;
167 };
168
169 /omit-if-no-ref/
170 i2c0_pd_pins: i2c0-pd-pins {
171 pins = "PD0", "PD12";
172 function = "i2c0";
173 };
174
175 spi0_pc_pins: spi0-pc-pins {
176 pins = "PC0", "PC1", "PC2", "PC3";
177 function = "spi0";
178 };
179
180 uart0_pe_pins: uart0-pe-pins {
181 pins = "PE0", "PE1";
182 function = "uart0";
183 };
184 };
185
186 i2c0: i2c@1c27000 {
187 compatible = "allwinner,suniv-f1c100s-i2c",
188 "allwinner,sun6i-a31-i2c";
189 reg = <0x01c27000 0x400>;
190 interrupts = <7>;
191 clocks = <&ccu CLK_BUS_I2C0>;
192 resets = <&ccu RST_BUS_I2C0>;
193 #address-cells = <1>;
194 #size-cells = <0>;
195 status = "disabled";
196 };
197
198 i2c1: i2c@1c27400 {
199 compatible = "allwinner,suniv-f1c100s-i2c",
200 "allwinner,sun6i-a31-i2c";
201 reg = <0x01c27400 0x400>;
202 interrupts = <8>;
203 clocks = <&ccu CLK_BUS_I2C1>;
204 resets = <&ccu RST_BUS_I2C1>;
205 #address-cells = <1>;
206 #size-cells = <0>;
207 status = "disabled";
208 };
209
210 i2c2: i2c@1c27800 {
211 compatible = "allwinner,suniv-f1c100s-i2c",
212 "allwinner,sun6i-a31-i2c";
213 reg = <0x01c27800 0x400>;
214 interrupts = <9>;
215 clocks = <&ccu CLK_BUS_I2C2>;
216 resets = <&ccu RST_BUS_I2C2>;
217 #address-cells = <1>;
218 #size-cells = <0>;
219 status = "disabled";
220 };
221
222 timer@1c20c00 {
223 compatible = "allwinner,suniv-f1c100s-timer";
224 reg = <0x01c20c00 0x90>;
225 interrupts = <13>, <14>, <15>;
226 clocks = <&osc24M>;
227 };
228
229 wdt: watchdog@1c20ca0 {
230 compatible = "allwinner,suniv-f1c100s-wdt",
231 "allwinner,sun6i-a31-wdt";
232 reg = <0x01c20ca0 0x20>;
233 interrupts = <16>;
234 clocks = <&osc32k>;
235 };
236
237 pwm: pwm@1c21000 {
238 compatible = "allwinner,suniv-f1c100s-pwm",
239 "allwinner,sun7i-a20-pwm";
240 reg = <0x01c21000 0x400>;
241 clocks = <&osc24M>;
242 #pwm-cells = <3>;
243 status = "disabled";
244 };
245
246 ir: ir@1c22c00 {
247 compatible = "allwinner,suniv-f1c100s-ir",
248 "allwinner,sun6i-a31-ir";
249 reg = <0x01c22c00 0x400>;
250 clocks = <&ccu CLK_BUS_IR>, <&ccu CLK_IR>;
251 clock-names = "apb", "ir";
252 resets = <&ccu RST_BUS_IR>;
253 interrupts = <6>;
254 status = "disabled";
255 };
256
257 lradc: lradc@1c23400 {
258 compatible = "allwinner,suniv-f1c100s-lradc",
259 "allwinner,sun8i-a83t-r-lradc";
260 reg = <0x01c23400 0x400>;
261 interrupts = <22>;
262 status = "disabled";
263 };
264
265 uart0: serial@1c25000 {
266 compatible = "snps,dw-apb-uart";
267 reg = <0x01c25000 0x400>;
268 interrupts = <1>;
269 reg-shift = <2>;
270 reg-io-width = <4>;
271 clocks = <&ccu CLK_BUS_UART0>;
272 resets = <&ccu RST_BUS_UART0>;
273 status = "disabled";
274 };
275
276 uart1: serial@1c25400 {
277 compatible = "snps,dw-apb-uart";
278 reg = <0x01c25400 0x400>;
279 interrupts = <2>;
280 reg-shift = <2>;
281 reg-io-width = <4>;
282 clocks = <&ccu CLK_BUS_UART1>;
283 resets = <&ccu RST_BUS_UART1>;
284 status = "disabled";
285 };
286
287 uart2: serial@1c25800 {
288 compatible = "snps,dw-apb-uart";
289 reg = <0x01c25800 0x400>;
290 interrupts = <3>;
291 reg-shift = <2>;
292 reg-io-width = <4>;
293 clocks = <&ccu CLK_BUS_UART2>;
294 resets = <&ccu RST_BUS_UART2>;
295 status = "disabled";
296 };
297 };
298};
1// SPDX-License-Identifier: (GPL-2.0+ OR X11)
2/*
3 * Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
4 * Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com>
5 */
6
7/ {
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&intc>;
11
12 clocks {
13 osc24M: clk-24M {
14 #clock-cells = <0>;
15 compatible = "fixed-clock";
16 clock-frequency = <24000000>;
17 clock-output-names = "osc24M";
18 };
19
20 osc32k: clk-32k {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <32768>;
24 clock-output-names = "osc32k";
25 };
26 };
27
28 cpus {
29 cpu {
30 compatible = "arm,arm926ej-s";
31 device_type = "cpu";
32 };
33 };
34
35 soc {
36 compatible = "simple-bus";
37 #address-cells = <1>;
38 #size-cells = <1>;
39 ranges;
40
41 sram-controller@1c00000 {
42 compatible = "allwinner,suniv-f1c100s-system-control",
43 "allwinner,sun4i-a10-system-control";
44 reg = <0x01c00000 0x30>;
45 #address-cells = <1>;
46 #size-cells = <1>;
47 ranges;
48
49 sram_d: sram@10000 {
50 compatible = "mmio-sram";
51 reg = <0x00010000 0x1000>;
52 #address-cells = <1>;
53 #size-cells = <1>;
54 ranges = <0 0x00010000 0x1000>;
55
56 otg_sram: sram-section@0 {
57 compatible = "allwinner,suniv-f1c100s-sram-d",
58 "allwinner,sun4i-a10-sram-d";
59 reg = <0x0000 0x1000>;
60 status = "disabled";
61 };
62 };
63 };
64
65 ccu: clock@1c20000 {
66 compatible = "allwinner,suniv-f1c100s-ccu";
67 reg = <0x01c20000 0x400>;
68 clocks = <&osc24M>, <&osc32k>;
69 clock-names = "hosc", "losc";
70 #clock-cells = <1>;
71 #reset-cells = <1>;
72 };
73
74 intc: interrupt-controller@1c20400 {
75 compatible = "allwinner,suniv-f1c100s-ic";
76 reg = <0x01c20400 0x400>;
77 interrupt-controller;
78 #interrupt-cells = <1>;
79 };
80
81 pio: pinctrl@1c20800 {
82 compatible = "allwinner,suniv-f1c100s-pinctrl";
83 reg = <0x01c20800 0x400>;
84 interrupts = <38>, <39>, <40>;
85 clocks = <&ccu 37>, <&osc24M>, <&osc32k>;
86 clock-names = "apb", "hosc", "losc";
87 gpio-controller;
88 interrupt-controller;
89 #interrupt-cells = <3>;
90 #gpio-cells = <3>;
91
92 uart0_pe_pins: uart0-pe-pins {
93 pins = "PE0", "PE1";
94 function = "uart0";
95 };
96 };
97
98 timer@1c20c00 {
99 compatible = "allwinner,suniv-f1c100s-timer";
100 reg = <0x01c20c00 0x90>;
101 interrupts = <13>;
102 clocks = <&osc24M>;
103 };
104
105 wdt: watchdog@1c20ca0 {
106 compatible = "allwinner,suniv-f1c100s-wdt",
107 "allwinner,sun4i-a10-wdt";
108 reg = <0x01c20ca0 0x20>;
109 };
110
111 uart0: serial@1c25000 {
112 compatible = "snps,dw-apb-uart";
113 reg = <0x01c25000 0x400>;
114 interrupts = <1>;
115 reg-shift = <2>;
116 reg-io-width = <4>;
117 clocks = <&ccu 38>;
118 resets = <&ccu 24>;
119 status = "disabled";
120 };
121
122 uart1: serial@1c25400 {
123 compatible = "snps,dw-apb-uart";
124 reg = <0x01c25400 0x400>;
125 interrupts = <2>;
126 reg-shift = <2>;
127 reg-io-width = <4>;
128 clocks = <&ccu 39>;
129 resets = <&ccu 25>;
130 status = "disabled";
131 };
132
133 uart2: serial@1c25800 {
134 compatible = "snps,dw-apb-uart";
135 reg = <0x01c25800 0x400>;
136 interrupts = <3>;
137 reg-shift = <2>;
138 reg-io-width = <4>;
139 clocks = <&ccu 40>;
140 resets = <&ccu 26>;
141 status = "disabled";
142 };
143 };
144};