Loading...
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree for the ARM Integrator/AP platform
4 * with the IM-PD1 example logical module mounted.
5 */
6
7#include "integratorap.dts"
8
9/ {
10 model = "ARM Integrator/AP with IM-PD1";
11 compatible = "arm,integrator-ap";
12
13 reserved-memory {
14 #address-cells = <1>;
15 #size-cells = <1>;
16 ranges;
17
18 impd1_ram: vram@c2000000 {
19 /* 1 MB of designated video RAM on the IM-PD1 */
20 compatible = "shared-dma-pool";
21 reg = <0xc2000000 0x00100000>;
22 no-map;
23 };
24 };
25};
26
27&lm0 {
28 syscon@0 {
29 compatible = "arm,im-pd1-syscon", "syscon";
30 reg = <0x00000000 0x1000>;
31 ranges;
32 #address-cells = <1>;
33 #size-cells = <1>;
34
35 vco1: clock-controller@0 {
36 compatible = "arm,impd1-vco1";
37 reg = <0x00 0x04>;
38 #clock-cells = <0>;
39 lock-offset = <0x08>;
40 vco-offset = <0x00>;
41 clocks = <&sysclk>;
42 clock-output-names = "IM-PD1-VCO1";
43 };
44
45 vco2: clock-controller@4 {
46 compatible = "arm,impd1-vco2";
47 reg = <0x04 0x04>;
48 #clock-cells = <0>;
49 lock-offset = <0x08>;
50 vco-offset = <0x04>;
51 clocks = <&sysclk>;
52 clock-output-names = "IM-PD1-VCO2";
53 };
54 };
55
56 /* Also used for the Smart Card Interface SCI */
57 impd1_uartclk: clock@1_4 {
58 compatible = "fixed-factor-clock";
59 #clock-cells = <0>;
60 clock-div = <4>;
61 clock-mult = <1>;
62 clocks = <&vco2>;
63 clock-output-names = "VCO2_DIV4";
64 };
65
66 /* For the SSP the clock is divided by 64 */
67 impd1_sspclk: clock@1_64 {
68 compatible = "fixed-factor-clock";
69 #clock-cells = <0>;
70 clock-div = <64>;
71 clock-mult = <1>;
72 clocks = <&vco2>;
73 clock-output-names = "VCO2_DIV64";
74 };
75
76 /* Fixed regulator for the MMC */
77 impd1_3v3: regulator {
78 compatible = "regulator-fixed";
79 regulator-name = "3V3";
80 regulator-min-microvolt = <3300000>;
81 regulator-max-microvolt = <3300000>;
82 regulator-always-on;
83 };
84
85 /* Push buttons on the IM-PD1 */
86 gpio_keys {
87 compatible = "gpio-keys";
88 #address-cells = <1>;
89 #size-cells = <0>;
90
91 button@0 {
92 debounce-interval = <50>;
93 linux,code = <KEY_UP>;
94 label = "UP";
95 gpios = <&impd1_gpio1 0 GPIO_ACTIVE_HIGH>;
96 };
97 button@1 {
98 debounce-interval = <50>;
99 linux,code = <KEY_DOWN>;
100 label = "DOWN";
101 gpios = <&impd1_gpio1 1 GPIO_ACTIVE_HIGH>;
102 };
103 button@2 {
104 debounce-interval = <50>;
105 linux,code = <KEY_LEFT>;
106 label = "LEFT";
107 gpios = <&impd1_gpio1 2 GPIO_ACTIVE_HIGH>;
108 };
109 button@3 {
110 debounce-interval = <50>;
111 linux,code = <KEY_RIGHT>;
112 label = "UP";
113 gpios = <&impd1_gpio1 3 GPIO_ACTIVE_HIGH>;
114 };
115 button@4 {
116 debounce-interval = <50>;
117 linux,code = <KEY_ESC>;
118 label = "ESC";
119 gpios = <&impd1_gpio1 4 GPIO_ACTIVE_HIGH>;
120 };
121 button@5 {
122 debounce-interval = <50>;
123 linux,code = <KEY_ENTER>;
124 label = "ENTER";
125 gpios = <&impd1_gpio1 5 GPIO_ACTIVE_HIGH>;
126 };
127 };
128
129
130 bridge {
131 compatible = "ti,ths8134b", "ti,ths8134";
132 #address-cells = <1>;
133 #size-cells = <0>;
134
135 ports {
136 #address-cells = <1>;
137 #size-cells = <0>;
138 port@0 {
139 reg = <0>;
140 vga_bridge_in: endpoint {
141 remote-endpoint = <&clcd_pads_vga_dac>;
142 };
143 };
144
145 port@1 {
146 reg = <1>;
147
148 vga_bridge_out: endpoint {
149 remote-endpoint = <&vga_con_in>;
150 };
151 };
152 };
153 };
154
155 vga {
156 compatible = "vga-connector";
157
158 port {
159 vga_con_in: endpoint {
160 remote-endpoint = <&vga_bridge_out>;
161 };
162 };
163 };
164
165 uart@100000 {
166 compatible = "arm,pl011", "arm,primecell";
167 reg = <0x00100000 0x1000>;
168 interrupts-extended = <&impd1_vic 1>;
169 clocks = <&impd1_uartclk>, <&sysclk>;
170 clock-names = "uartclk", "apb_pclk";
171 };
172
173 uart@200000 {
174 compatible = "arm,pl011", "arm,primecell";
175 reg = <0x00200000 0x1000>;
176 interrupts-extended = <&impd1_vic 2>;
177 clocks = <&impd1_uartclk>, <&sysclk>;
178 clock-names = "uartclk", "apb_pclk";
179 };
180
181 spi@300000 {
182 compatible = "arm,pl022", "arm,primecell";
183 reg = <0x00300000 0x1000>;
184 interrupts-extended = <&impd1_vic 3>;
185 clocks = <&impd1_sspclk>, <&sysclk>;
186 clock-names = "sspclk", "apb_pclk";
187 };
188
189 impd1_gpio0: gpio@400000 {
190 compatible = "arm,pl061", "arm,primecell";
191 reg = <0x00400000 0x1000>;
192 gpio-controller;
193 #gpio-cells = <2>;
194 interrupt-controller;
195 #interrupt-cells = <2>;
196 interrupts-extended = <&impd1_vic 4>;
197 clocks = <&sysclk>;
198 clock-names = "apb_pclk";
199 };
200
201 impd1_gpio1: gpio@500000 {
202 compatible = "arm,pl061", "arm,primecell";
203 reg = <0x00500000 0x1000>;
204 gpio-controller;
205 #gpio-cells = <2>;
206 interrupt-controller;
207 #interrupt-cells = <2>;
208 interrupts-extended = <&impd1_vic 5>;
209 clocks = <&sysclk>;
210 clock-names = "apb_pclk";
211 };
212
213 rtc@600000 {
214 compatible = "arm,pl030", "arm,primecell";
215 reg = <0x00600000 0x1000>;
216 interrupts-extended = <&impd1_vic 6>;
217 clocks = <&sysclk>;
218 clock-names = "apb_pclk";
219 };
220
221 mmc@700000 {
222 compatible = "arm,pl181", "arm,primecell";
223 reg = <0x00700000 0x1000>;
224 interrupts-extended = <&impd1_vic 7>,
225 <&impd1_vic 8>;
226 clocks = <&sysclk>, <&sysclk>;
227 clock-names = "mclk", "apb_pclk";
228 bus-width = <1>;
229 max-frequency = <515633>;
230 vmmc-supply = <&impd1_3v3>;
231 wp-gpios = <&impd1_gpio0 3 GPIO_ACTIVE_HIGH>;
232 cd-gpios = <&impd1_gpio0 4 GPIO_ACTIVE_LOW>;
233 };
234
235 aaci@800000 {
236 compatible = "arm,pl041", "arm,primecell";
237 reg = <0x00800000 0x1000>;
238 interrupts-extended = <&impd1_vic 9>;
239 clocks = <&sysclk>;
240 clock-names = "apb_pclk";
241 };
242
243 display@1000000 {
244 compatible = "arm,pl110", "arm,primecell";
245 reg = <0x01000000 0x1000>;
246 interrupts-extended = <&impd1_vic 11>;
247 clocks = <&vco1>, <&sysclk>;
248 clock-names = "clcdclk", "apb_pclk";
249 /* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */
250 max-memory-bandwidth = <40000000>;
251 memory-region = <&impd1_ram>;
252 dma-ranges;
253
254 port@0 {
255 #address-cells = <1>;
256 #size-cells = <0>;
257
258 clcd_pads_vga_dac: endpoint@0 {
259 reg = <0>;
260 remote-endpoint = <&vga_bridge_in>;
261 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
262 };
263 };
264 };
265
266 impd1_vic: interrupt-controller@3000000 {
267 compatible = "arm,pl192-vic";
268 interrupt-controller;
269 #interrupt-cells = <1>;
270 reg = <0x03000000 0x1000>;
271 /* Valid interrupts, 0-9 and 11 */
272 valid-mask = <0x00000bff>;
273 /* LM site 0 has IRQ 9 on the PIC */
274 interrupts-extended = <&pic 9>;
275 };
276};
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree for the ARM Integrator/AP platform
4 * with the IM-PD1 example logical module mounted.
5 */
6
7#include "integratorap.dts"
8
9/ {
10 model = "ARM Integrator/AP with IM-PD1";
11 compatible = "arm,integrator-ap";
12
13 reserved-memory {
14 #address-cells = <1>;
15 #size-cells = <1>;
16 ranges;
17
18 impd1_ram: vram@c2000000 {
19 /* 1 MB of designated video RAM on the IM-PD1 */
20 compatible = "shared-dma-pool";
21 reg = <0xc2000000 0x00100000>;
22 no-map;
23 };
24 };
25};
26
27&lm0 {
28 syscon@0 {
29 compatible = "arm,im-pd1-syscon", "syscon";
30 reg = <0x00000000 0x1000>;
31
32 vco1: clock@00 {
33 compatible = "arm,impd1-vco1";
34 #clock-cells = <0>;
35 lock-offset = <0x08>;
36 vco-offset = <0x00>;
37 clocks = <&sysclk>;
38 clock-output-names = "IM-PD1-VCO1";
39 };
40
41 vco2: clock@04 {
42 compatible = "arm,impd1-vco2";
43 #clock-cells = <0>;
44 lock-offset = <0x08>;
45 vco-offset = <0x04>;
46 clocks = <&sysclk>;
47 clock-output-names = "IM-PD1-VCO2";
48 };
49 };
50
51 /* Also used for the Smart Card Interface SCI */
52 impd1_uartclk: clock@1_4 {
53 compatible = "fixed-factor-clock";
54 #clock-cells = <0>;
55 clock-div = <4>;
56 clock-mult = <1>;
57 clocks = <&vco2>;
58 clock-output-names = "VCO2_DIV4";
59 };
60
61 /* For the SSP the clock is divided by 64 */
62 impd1_sspclk: clock@1_64 {
63 compatible = "fixed-factor-clock";
64 #clock-cells = <0>;
65 clock-div = <64>;
66 clock-mult = <1>;
67 clocks = <&vco2>;
68 clock-output-names = "VCO2_DIV64";
69 };
70
71 /* Fixed regulator for the MMC */
72 impd1_3v3: regulator {
73 compatible = "regulator-fixed";
74 regulator-name = "3V3";
75 regulator-min-microvolt = <3300000>;
76 regulator-max-microvolt = <3300000>;
77 regulator-always-on;
78 };
79
80 /* Push buttons on the IM-PD1 */
81 gpio_keys {
82 compatible = "gpio-keys";
83 #address-cells = <1>;
84 #size-cells = <0>;
85
86 button@0 {
87 debounce-interval = <50>;
88 linux,code = <KEY_UP>;
89 label = "UP";
90 gpios = <&impd1_gpio1 0 GPIO_ACTIVE_HIGH>;
91 };
92 button@1 {
93 debounce-interval = <50>;
94 linux,code = <KEY_DOWN>;
95 label = "DOWN";
96 gpios = <&impd1_gpio1 1 GPIO_ACTIVE_HIGH>;
97 };
98 button@2 {
99 debounce-interval = <50>;
100 linux,code = <KEY_LEFT>;
101 label = "LEFT";
102 gpios = <&impd1_gpio1 2 GPIO_ACTIVE_HIGH>;
103 };
104 button@3 {
105 debounce-interval = <50>;
106 linux,code = <KEY_RIGHT>;
107 label = "UP";
108 gpios = <&impd1_gpio1 3 GPIO_ACTIVE_HIGH>;
109 };
110 button@4 {
111 debounce-interval = <50>;
112 linux,code = <KEY_ESC>;
113 label = "ESC";
114 gpios = <&impd1_gpio1 4 GPIO_ACTIVE_HIGH>;
115 };
116 button@5 {
117 debounce-interval = <50>;
118 linux,code = <KEY_ENTER>;
119 label = "ENTER";
120 gpios = <&impd1_gpio1 5 GPIO_ACTIVE_HIGH>;
121 };
122 };
123
124
125 bridge {
126 compatible = "ti,ths8134b", "ti,ths8134";
127 #address-cells = <1>;
128 #size-cells = <0>;
129
130 ports {
131 #address-cells = <1>;
132 #size-cells = <0>;
133 port@0 {
134 reg = <0>;
135 vga_bridge_in: endpoint {
136 remote-endpoint = <&clcd_pads_vga_dac>;
137 };
138 };
139
140 port@1 {
141 reg = <1>;
142
143 vga_bridge_out: endpoint {
144 remote-endpoint = <&vga_con_in>;
145 };
146 };
147 };
148 };
149
150 vga {
151 compatible = "vga-connector";
152
153 port {
154 vga_con_in: endpoint {
155 remote-endpoint = <&vga_bridge_out>;
156 };
157 };
158 };
159
160 uart@100000 {
161 compatible = "arm,pl011", "arm,primecell";
162 reg = <0x00100000 0x1000>;
163 interrupts-extended = <&impd1_vic 1>;
164 clocks = <&impd1_uartclk>, <&sysclk>;
165 clock-names = "uartclk", "apb_pclk";
166 };
167
168 uart@200000 {
169 compatible = "arm,pl011", "arm,primecell";
170 reg = <0x00200000 0x1000>;
171 interrupts-extended = <&impd1_vic 2>;
172 clocks = <&impd1_uartclk>, <&sysclk>;
173 clock-names = "uartclk", "apb_pclk";
174 };
175
176 ssp@300000 {
177 compatible = "arm,pl022", "arm,primecell";
178 reg = <0x00300000 0x1000>;
179 interrupts-extended = <&impd1_vic 3>;
180 clocks = <&impd1_sspclk>, <&sysclk>;
181 clock-names = "spiclk", "apb_pclk";
182 };
183
184 impd1_gpio0: gpio@400000 {
185 compatible = "arm,pl061", "arm,primecell";
186 reg = <0x00400000 0x1000>;
187 gpio-controller;
188 #gpio-cells = <2>;
189 interrupt-controller;
190 #interrupt-cells = <2>;
191 interrupts-extended = <&impd1_vic 4>;
192 clocks = <&sysclk>;
193 clock-names = "apb_pclk";
194 };
195
196 impd1_gpio1: gpio@500000 {
197 compatible = "arm,pl061", "arm,primecell";
198 reg = <0x00500000 0x1000>;
199 gpio-controller;
200 #gpio-cells = <2>;
201 interrupt-controller;
202 #interrupt-cells = <2>;
203 interrupts-extended = <&impd1_vic 5>;
204 clocks = <&sysclk>;
205 clock-names = "apb_pclk";
206 };
207
208 rtc@600000 {
209 compatible = "arm,pl030", "arm,primecell";
210 reg = <0x00600000 0x1000>;
211 interrupts-extended = <&impd1_vic 6>;
212 clocks = <&sysclk>;
213 clock-names = "apb_pclk";
214 };
215
216 mmc@700000 {
217 compatible = "arm,pl181", "arm,primecell";
218 reg = <0x00700000 0x1000>;
219 interrupts-extended = <&impd1_vic 7>,
220 <&impd1_vic 8>;
221 clocks = <&sysclk>, <&sysclk>;
222 clock-names = "mclk", "apb_pclk";
223 bus-width = <1>;
224 max-frequency = <515633>;
225 vmmc-supply = <&impd1_3v3>;
226 wp-gpios = <&impd1_gpio0 3 GPIO_ACTIVE_HIGH>;
227 cd-gpios = <&impd1_gpio0 4 GPIO_ACTIVE_LOW>;
228 };
229
230 aaci@800000 {
231 compatible = "arm,pl041", "arm,primecell";
232 reg = <0x00800000 0x1000>;
233 interrupts-extended = <&impd1_vic 9>;
234 clocks = <&sysclk>;
235 clock-names = "apb_pclk";
236 };
237
238 display@1000000 {
239 compatible = "arm,pl110", "arm,primecell";
240 reg = <0x01000000 0x1000>;
241 interrupts-extended = <&impd1_vic 11>;
242 clocks = <&vco1>, <&sysclk>;
243 clock-names = "clcdclk", "apb_pclk";
244 /* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */
245 max-memory-bandwidth = <40000000>;
246 memory-region = <&impd1_ram>;
247
248 port@0 {
249 #address-cells = <1>;
250 #size-cells = <0>;
251
252 clcd_pads_vga_dac: endpoint@0 {
253 reg = <0>;
254 remote-endpoint = <&vga_bridge_in>;
255 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
256 };
257 };
258 };
259
260 impd1_vic: interrupt-controller@3000000 {
261 compatible = "arm,pl192-vic";
262 interrupt-controller;
263 #interrupt-cells = <1>;
264 reg = <0x03000000 0x1000>;
265 /* Valid interrupts, 0-9 and 11 */
266 valid-mask = <0x00000bff>;
267 /* LM site 0 has IRQ 9 on the PIC */
268 interrupts-extended = <&pic 9>;
269 };
270};