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1/*
2 * Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42#include <dt-bindings/gpio/gpio.h>
43#include <dt-bindings/interrupt-controller/irq.h>
44#include <dt-bindings/pwm/pwm.h>
45
46/ {
47 aliases {
48 can0 = &can2;
49 can1 = &can1;
50 display = &display;
51 i2c0 = &i2c2;
52 i2c1 = &i2c_gpio;
53 i2c2 = &i2c1;
54 i2c3 = &i2c3;
55 i2c4 = &i2c4;
56 lcdif-23bit-pins-a = &pinctrl_disp0_1;
57 lcdif-24bit-pins-a = &pinctrl_disp0_2;
58 pwm0 = &pwm5;
59 reg-can-xcvr = ®_can_xcvr;
60 serial2 = &uart5;
61 serial4 = &uart3;
62 spi0 = &ecspi2;
63 spi1 = &spi_gpio;
64 stk5led = &user_led;
65 usbh1 = &usbotg2;
66 usbotg = &usbotg1;
67 };
68
69 chosen {
70 stdout-path = &uart1;
71 };
72
73 memory@80000000 {
74 device_type = "memory";
75 reg = <0x80000000 0>; /* will be filled by U-Boot */
76 };
77
78 clocks {
79 mclk: mclk {
80 compatible = "fixed-clock";
81 #clock-cells = <0>;
82 clock-frequency = <26000000>;
83 };
84 };
85
86 backlight: backlight {
87 compatible = "pwm-backlight";
88 pinctrl-names = "default";
89 pinctrl-0 = <&pinctrl_lcd_rst>;
90 enable-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
91 pwms = <&pwm5 0 500000 PWM_POLARITY_INVERTED>;
92 power-supply = <®_lcd_pwr>;
93 /*
94 * a poor man's way to create a 1:1 relationship between
95 * the PWM value and the actual duty cycle
96 */
97 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
98 10 11 12 13 14 15 16 17 18 19
99 20 21 22 23 24 25 26 27 28 29
100 30 31 32 33 34 35 36 37 38 39
101 40 41 42 43 44 45 46 47 48 49
102 50 51 52 53 54 55 56 57 58 59
103 60 61 62 63 64 65 66 67 68 69
104 70 71 72 73 74 75 76 77 78 79
105 80 81 82 83 84 85 86 87 88 89
106 90 91 92 93 94 95 96 97 98 99
107 100>;
108 default-brightness-level = <50>;
109 };
110
111 i2c_gpio: i2c-gpio {
112 compatible = "i2c-gpio";
113 #address-cells = <1>;
114 #size-cells = <0>;
115 pinctrl-names = "default";
116 pinctrl-0 = <&pinctrl_i2c_gpio>;
117 gpios = <
118 &gpio5 1 GPIO_ACTIVE_HIGH /* SDA */
119 &gpio5 0 GPIO_ACTIVE_HIGH /* SCL */
120 >;
121 clock-frequency = <400000>;
122 status = "okay";
123
124 ds1339: rtc@68 {
125 compatible = "dallas,ds1339";
126 reg = <0x68>;
127 status = "disabled";
128 };
129 };
130
131 leds {
132 compatible = "gpio-leds";
133
134 user_led: user {
135 label = "Heartbeat";
136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_led>;
138 gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
139 linux,default-trigger = "heartbeat";
140 };
141 };
142
143 reg_3v3_etn: regulator-3v3etn {
144 compatible = "regulator-fixed";
145 regulator-name = "3V3_ETN";
146 regulator-min-microvolt = <3300000>;
147 regulator-max-microvolt = <3300000>;
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_etnphy_power>;
150 gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
151 enable-active-high;
152 };
153
154 reg_2v5: regulator-2v5 {
155 compatible = "regulator-fixed";
156 regulator-name = "2V5";
157 regulator-min-microvolt = <2500000>;
158 regulator-max-microvolt = <2500000>;
159 regulator-always-on;
160 };
161
162 reg_3v3: regulator-3v3 {
163 compatible = "regulator-fixed";
164 regulator-name = "3V3";
165 regulator-min-microvolt = <3300000>;
166 regulator-max-microvolt = <3300000>;
167 regulator-always-on;
168 };
169
170 reg_can_xcvr: regulator-canxcvr {
171 compatible = "regulator-fixed";
172 regulator-name = "CAN XCVR";
173 regulator-min-microvolt = <3300000>;
174 regulator-max-microvolt = <3300000>;
175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_flexcan_xcvr>;
177 gpio = <&gpio3 5 GPIO_ACTIVE_LOW>;
178 };
179
180 reg_lcd_pwr: regulator-lcdpwr {
181 compatible = "regulator-fixed";
182 regulator-name = "LCD POWER";
183 regulator-min-microvolt = <3300000>;
184 regulator-max-microvolt = <3300000>;
185 pinctrl-names = "default";
186 pinctrl-0 = <&pinctrl_lcd_pwr>;
187 gpio = <&gpio5 4 GPIO_ACTIVE_HIGH>;
188 enable-active-high;
189 regulator-boot-on;
190 regulator-always-on;
191 };
192
193 reg_usbh1_vbus: regulator-usbh1vbus {
194 compatible = "regulator-fixed";
195 regulator-name = "usbh1_vbus";
196 regulator-min-microvolt = <5000000>;
197 regulator-max-microvolt = <5000000>;
198 pinctrl-names = "default";
199 pinctrl-0 = <&pinctrl_usbh1_vbus &pinctrl_usbh1_oc>;
200 gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
201 enable-active-high;
202 };
203
204 reg_usbotg_vbus: regulator-usbotgvbus {
205 compatible = "regulator-fixed";
206 regulator-name = "usbotg_vbus";
207 regulator-min-microvolt = <5000000>;
208 regulator-max-microvolt = <5000000>;
209 pinctrl-names = "default";
210 pinctrl-0 = <&pinctrl_usbotg_vbus &pinctrl_usbotg_oc>;
211 gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
212 enable-active-high;
213 };
214
215 spi_gpio: spi {
216 #address-cells = <1>;
217 #size-cells = <0>;
218 compatible = "spi-gpio";
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_spi_gpio>;
221 gpio-mosi = <&gpio1 30 GPIO_ACTIVE_HIGH>;
222 gpio-miso = <&gpio1 31 GPIO_ACTIVE_HIGH>;
223 gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>;
224 num-chipselects = <2>;
225 cs-gpios = <
226 &gpio1 29 GPIO_ACTIVE_HIGH
227 &gpio1 10 GPIO_ACTIVE_HIGH
228 >;
229 status = "disabled";
230 };
231
232 sound {
233 compatible = "karo,imx6ul-tx6ul-sgtl5000",
234 "simple-audio-card";
235 simple-audio-card,name = "imx6ul-tx6ul-sgtl5000-audio";
236 simple-audio-card,format = "i2s";
237 simple-audio-card,bitclock-master = <&codec_dai>;
238 simple-audio-card,frame-master = <&codec_dai>;
239 simple-audio-card,widgets =
240 "Microphone", "Mic Jack",
241 "Line", "Line In",
242 "Line", "Line Out",
243 "Headphone", "Headphone Jack";
244 simple-audio-card,routing =
245 "MIC_IN", "Mic Jack",
246 "Mic Jack", "Mic Bias",
247 "Headphone Jack", "HP_OUT";
248
249 cpu_dai: simple-audio-card,cpu {
250 sound-dai = <&sai2>;
251 };
252
253 codec_dai: simple-audio-card,codec {
254 sound-dai = <&sgtl5000>;
255 };
256 };
257};
258
259&can1 {
260 pinctrl-names = "default";
261 pinctrl-0 = <&pinctrl_flexcan1>;
262 xceiver-supply = <®_can_xcvr>;
263 status = "okay";
264};
265
266&can2 {
267 pinctrl-names = "default";
268 pinctrl-0 = <&pinctrl_flexcan2>;
269 xceiver-supply = <®_can_xcvr>;
270 status = "okay";
271};
272
273&ecspi2 {
274 pinctrl-names = "default";
275 pinctrl-0 = <&pinctrl_ecspi2>;
276 cs-gpios = <
277 &gpio1 29 GPIO_ACTIVE_HIGH
278 &gpio1 10 GPIO_ACTIVE_HIGH
279 >;
280 status = "disabled";
281};
282
283&fec1 {
284 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio &pinctrl_etnphy0_rst>;
286 phy-mode = "rmii";
287 phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
288 phy-supply = <®_3v3_etn>;
289 phy-handle = <&etnphy0>;
290 status = "okay";
291
292 mdio {
293 #address-cells = <1>;
294 #size-cells = <0>;
295
296 etnphy0: ethernet-phy@0 {
297 compatible = "ethernet-phy-ieee802.3-c22";
298 reg = <0>;
299 pinctrl-names = "default";
300 pinctrl-0 = <&pinctrl_etnphy0_int>;
301 interrupt-parent = <&gpio5>;
302 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
303 status = "okay";
304 };
305
306 etnphy1: ethernet-phy@2 {
307 compatible = "ethernet-phy-ieee802.3-c22";
308 reg = <2>;
309 pinctrl-names = "default";
310 pinctrl-0 = <&pinctrl_etnphy1_int>;
311 interrupt-parent = <&gpio4>;
312 interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
313 status = "okay";
314 };
315 };
316};
317
318&fec2 {
319 pinctrl-names = "default";
320 pinctrl-0 = <&pinctrl_enet2 &pinctrl_etnphy1_rst>;
321 phy-mode = "rmii";
322 phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
323 phy-supply = <®_3v3_etn>;
324 phy-handle = <&etnphy1>;
325 status = "disabled";
326};
327
328&gpmi {
329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_gpmi_nand>;
331 nand-on-flash-bbt;
332 fsl,no-blockmark-swap;
333 status = "okay";
334};
335
336&i2c2 {
337 pinctrl-names = "default";
338 pinctrl-0 = <&pinctrl_i2c2>;
339 clock-frequency = <400000>;
340 status = "okay";
341
342 sgtl5000: codec@a {
343 compatible = "fsl,sgtl5000";
344 reg = <0x0a>;
345 #sound-dai-cells = <0>;
346 VDDA-supply = <®_2v5>;
347 VDDIO-supply = <®_3v3>;
348 clocks = <&mclk>;
349 };
350
351 polytouch: polytouch@38 {
352 compatible = "edt,edt-ft5x06";
353 reg = <0x38>;
354 pinctrl-names = "default";
355 pinctrl-0 = <&pinctrl_edt_ft5x06>;
356 interrupt-parent = <&gpio5>;
357 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
358 reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
359 wake-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
360 wakeup-source;
361 };
362
363 touchscreen: touchscreen@48 {
364 compatible = "ti,tsc2007";
365 reg = <0x48>;
366 pinctrl-names = "default";
367 pinctrl-0 = <&pinctrl_tsc2007>;
368 interrupt-parent = <&gpio3>;
369 interrupts = <26 IRQ_TYPE_NONE>;
370 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
371 ti,x-plate-ohms = <660>;
372 wakeup-source;
373 };
374};
375
376&kpp {
377 pinctrl-names = "default";
378 pinctrl-0 = <&pinctrl_kpp>;
379 /* sample keymap */
380 /* row/col 0..3 are mapped to KPP row/col 4..7 */
381 linux,keymap = <
382 MATRIX_KEY(4, 4, KEY_POWER)
383 MATRIX_KEY(4, 5, KEY_KP0)
384 MATRIX_KEY(4, 6, KEY_KP1)
385 MATRIX_KEY(4, 7, KEY_KP2)
386 MATRIX_KEY(5, 4, KEY_KP3)
387 MATRIX_KEY(5, 5, KEY_KP4)
388 MATRIX_KEY(5, 6, KEY_KP5)
389 MATRIX_KEY(5, 7, KEY_KP6)
390 MATRIX_KEY(6, 4, KEY_KP7)
391 MATRIX_KEY(6, 5, KEY_KP8)
392 MATRIX_KEY(6, 6, KEY_KP9)
393 >;
394 status = "okay";
395};
396
397&lcdif {
398 pinctrl-names = "default";
399 pinctrl-0 = <&pinctrl_disp0_1>;
400 lcd-supply = <®_lcd_pwr>;
401 display = <&display>;
402 status = "okay";
403
404 display: disp0 {
405 bits-per-pixel = <32>;
406 bus-width = <24>;
407 status = "okay";
408
409 display-timings {
410 VGA {
411 clock-frequency = <25200000>;
412 hactive = <640>;
413 vactive = <480>;
414 hback-porch = <48>;
415 hsync-len = <96>;
416 hfront-porch = <16>;
417 vback-porch = <31>;
418 vsync-len = <2>;
419 vfront-porch = <12>;
420 hsync-active = <0>;
421 vsync-active = <0>;
422 de-active = <1>;
423 pixelclk-active = <1>;
424 };
425
426 ETV570 {
427 clock-frequency = <25200000>;
428 hactive = <640>;
429 vactive = <480>;
430 hback-porch = <114>;
431 hsync-len = <30>;
432 hfront-porch = <16>;
433 vback-porch = <32>;
434 vsync-len = <3>;
435 vfront-porch = <10>;
436 hsync-active = <0>;
437 vsync-active = <0>;
438 de-active = <1>;
439 pixelclk-active = <1>;
440 };
441
442 ET0350 {
443 clock-frequency = <6413760>;
444 hactive = <320>;
445 vactive = <240>;
446 hback-porch = <34>;
447 hsync-len = <34>;
448 hfront-porch = <20>;
449 vback-porch = <15>;
450 vsync-len = <3>;
451 vfront-porch = <4>;
452 hsync-active = <0>;
453 vsync-active = <0>;
454 de-active = <1>;
455 pixelclk-active = <1>;
456 };
457
458 ET0430 {
459 clock-frequency = <9009000>;
460 hactive = <480>;
461 vactive = <272>;
462 hback-porch = <2>;
463 hsync-len = <41>;
464 hfront-porch = <2>;
465 vback-porch = <2>;
466 vsync-len = <10>;
467 vfront-porch = <2>;
468 hsync-active = <0>;
469 vsync-active = <0>;
470 de-active = <1>;
471 pixelclk-active = <0>;
472 };
473
474 ET0500 {
475 clock-frequency = <33264000>;
476 hactive = <800>;
477 vactive = <480>;
478 hback-porch = <88>;
479 hsync-len = <128>;
480 hfront-porch = <40>;
481 vback-porch = <33>;
482 vsync-len = <2>;
483 vfront-porch = <10>;
484 hsync-active = <0>;
485 vsync-active = <0>;
486 de-active = <1>;
487 pixelclk-active = <1>;
488 };
489
490 ET0700 { /* same as ET0500 */
491 clock-frequency = <33264000>;
492 hactive = <800>;
493 vactive = <480>;
494 hback-porch = <88>;
495 hsync-len = <128>;
496 hfront-porch = <40>;
497 vback-porch = <33>;
498 vsync-len = <2>;
499 vfront-porch = <10>;
500 hsync-active = <0>;
501 vsync-active = <0>;
502 de-active = <1>;
503 pixelclk-active = <1>;
504 };
505
506 ETQ570 {
507 clock-frequency = <6596040>;
508 hactive = <320>;
509 vactive = <240>;
510 hback-porch = <38>;
511 hsync-len = <30>;
512 hfront-porch = <30>;
513 vback-porch = <16>;
514 vsync-len = <3>;
515 vfront-porch = <4>;
516 hsync-active = <0>;
517 vsync-active = <0>;
518 de-active = <1>;
519 pixelclk-active = <1>;
520 };
521 };
522 };
523};
524
525&pwm5 {
526 pinctrl-names = "default";
527 pinctrl-0 = <&pinctrl_pwm5>;
528 status = "okay";
529};
530
531&sai2 {
532 pinctrl-names = "default";
533 pinctrl-0 = <&pinctrl_sai2>;
534 status = "okay";
535};
536
537&uart1 {
538 pinctrl-names = "default";
539 pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
540 uart-has-rtscts;
541 status = "okay";
542};
543
544&uart2 {
545 pinctrl-names = "default";
546 pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
547 uart-has-rtscts;
548 status = "okay";
549};
550
551&uart5 {
552 pinctrl-names = "default";
553 pinctrl-0 = <&pinctrl_uart5 &pinctrl_uart5_rtscts>;
554 uart-has-rtscts;
555 status = "okay";
556};
557
558&usbotg1 {
559 vbus-supply = <®_usbotg_vbus>;
560 dr_mode = "peripheral";
561 disable-over-current;
562 status = "okay";
563};
564
565&usbotg2 {
566 vbus-supply = <®_usbh1_vbus>;
567 dr_mode = "host";
568 disable-over-current;
569 status = "okay";
570};
571
572&usdhc1 {
573 pinctrl-names = "default";
574 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_cd>;
575 bus-width = <4>;
576 no-1-8-v;
577 cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
578 fsl,wp-controller;
579 status = "okay";
580};
581
582&iomuxc {
583 pinctrl-names = "default";
584 pinctrl-0 = <&pinctrl_hog>;
585
586 pinctrl_hog: hoggrp {
587 };
588
589 pinctrl_led: ledgrp {
590 fsl,pins = <
591 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x0b0b0 /* LED */
592 >;
593 };
594
595 pinctrl_disp0_1: disp0grp-1 {
596 fsl,pins = <
597 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */
598 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */
599 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */
600 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */
601 /* PAD DISP0_DAT0 is used for the Flexcan transceiver control on STK5-v5 */
602 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x10
603 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10
604 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10
605 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10
606 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10
607 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10
608 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10
609 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x10
610 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x10
611 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10
612 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10
613 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10
614 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10
615 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10
616 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10
617 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x10
618 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x10
619 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10
620 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10
621 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10
622 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10
623 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10
624 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10
625 >;
626 };
627
628 pinctrl_disp0_2: disp0grp-2 {
629 fsl,pins = <
630 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */
631 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */
632 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */
633 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */
634 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x10
635 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x10
636 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10
637 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10
638 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10
639 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10
640 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10
641 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10
642 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x10
643 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x10
644 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10
645 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10
646 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10
647 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10
648 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10
649 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10
650 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x10
651 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x10
652 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10
653 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10
654 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10
655 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10
656 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10
657 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10
658 >;
659 };
660
661 pinctrl_ecspi2: ecspi2grp {
662 fsl,pins = <
663 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x0b0b0 /* CSPI_SS */
664 MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0b0b0 /* CSPI_SS */
665 MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x0b0b0 /* CSPI_MOSI */
666 MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x0b0b0 /* CSPI_MISO */
667 MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x0b0b0 /* CSPI_SCLK */
668 >;
669 };
670
671 pinctrl_edt_ft5x06: edt-ft5x06grp {
672 fsl,pins = <
673 MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* Interrupt */
674 MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* Reset */
675 MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 /* Wake */
676 >;
677 };
678
679 pinctrl_enet1: enet1grp {
680 fsl,pins = <
681 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x000b0
682 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x000b0
683 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x000b0
684 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x000b0
685 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x000b0
686 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x000b0
687 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x000b0
688 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x400000b1
689 >;
690 };
691
692 pinctrl_enet2: enet2grp {
693 fsl,pins = <
694 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x000b0
695 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x000b0
696 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x000b0
697 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x000b0
698 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x000b0
699 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x000b0
700 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x000b0
701 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x400000b1
702 >;
703 };
704
705 pinctrl_enet1_mdio: enet1-mdiogrp {
706 fsl,pins = <
707 MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x0b0b0
708 MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
709 >;
710 };
711
712 pinctrl_etnphy_power: etnphy-pwrgrp {
713 fsl,pins = <
714 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0 /* ETN PHY POWER */
715 >;
716 };
717
718 pinctrl_etnphy0_int: etnphy-intgrp-0 {
719 fsl,pins = <
720 MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 /* ETN PHY INT */
721 >;
722 };
723
724 pinctrl_etnphy0_rst: etnphy-rstgrp-0 {
725 fsl,pins = <
726 MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0 /* ETN PHY RESET */
727 >;
728 };
729
730 pinctrl_etnphy1_int: etnphy-intgrp-1 {
731 fsl,pins = <
732 MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x0b0b0 /* ETN PHY INT */
733 >;
734 };
735
736 pinctrl_etnphy1_rst: etnphy-rstgrp-1 {
737 fsl,pins = <
738 MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x0b0b0 /* ETN PHY RESET */
739 >;
740 };
741
742 pinctrl_flexcan1: flexcan1grp {
743 fsl,pins = <
744 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0
745 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0
746 >;
747 };
748
749 pinctrl_flexcan2: flexcan2grp {
750 fsl,pins = <
751 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0
752 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0
753 >;
754 };
755
756 pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
757 fsl,pins = <
758 MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0b0b0 /* Flexcan XCVR enable */
759 >;
760 };
761
762 pinctrl_gpmi_nand: gpminandgrp {
763 fsl,pins = <
764 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
765 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
766 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1
767 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
768 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
769 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1
770 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1
771 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1
772 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1
773 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1
774 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1
775 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1
776 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1
777 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1
778 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1
779 >;
780 };
781
782 pinctrl_i2c_gpio: i2c-gpiogrp {
783 fsl,pins = <
784 MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x4001b8b1 /* I2C SCL */
785 MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x4001b8b1 /* I2C SDA */
786 >;
787 };
788
789 pinctrl_i2c2: i2c2grp {
790 fsl,pins = <
791 MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b1
792 MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b1
793 >;
794 };
795
796 pinctrl_kpp: kppgrp {
797 fsl,pins = <
798 MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04 0x1b0b0
799 MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x1b0b0
800 MX6UL_PAD_ENET2_TX_EN__KPP_COL06 0x1b0b0
801 MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x1b0b0
802 MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04 0x1b0b0
803 MX6UL_PAD_ENET2_RX_EN__KPP_ROW05 0x1b0b0
804 MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06 0x1b0b0
805 MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07 0x1b0b0
806 >;
807 };
808
809 pinctrl_lcd_pwr: lcd-pwrgrp {
810 fsl,pins = <
811 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 /* LCD Power Enable */
812 >;
813 };
814
815 pinctrl_lcd_rst: lcd-rstgrp {
816 fsl,pins = <
817 MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0 /* LCD Reset */
818 >;
819 };
820
821 pinctrl_pwm5: pwm5grp {
822 fsl,pins = <
823 MX6UL_PAD_NAND_DQS__PWM5_OUT 0x0b0b0
824 >;
825 };
826
827 pinctrl_sai2: sai2grp {
828 fsl,pins = <
829 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0b0b0 /* SSI1_RXD */
830 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0b0b0 /* SSI1_TXD */
831 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x0b0b0 /* SSI1_CLK */
832 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x0b0b0 /* SSI1_FS */
833 >;
834 };
835
836 pinctrl_spi_gpio: spi-gpiogrp {
837 fsl,pins = <
838 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x0b0b0 /* CSPI_SS */
839 MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0b0b0 /* CSPI_SS */
840 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x0b0b0 /* CSPI_MOSI */
841 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x0b0b0 /* CSPI_MISO */
842 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x0b0b0 /* CSPI_SCLK */
843 >;
844 };
845
846 pinctrl_tsc2007: tsc2007grp {
847 fsl,pins = <
848 MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x1b0b0 /* Interrupt */
849 >;
850 };
851
852 pinctrl_uart1: uart1grp {
853 fsl,pins = <
854 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x0b0b0
855 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0b0b0
856 >;
857 };
858
859 pinctrl_uart1_rtscts: uart1-rtsctsgrp {
860 fsl,pins = <
861 MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x0b0b0
862 MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x0b0b0
863 >;
864 };
865
866 pinctrl_uart2: uart2grp {
867 fsl,pins = <
868 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0b0b0
869 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0b0b0
870 >;
871 };
872
873 pinctrl_uart2_rtscts: uart2-rtsctsgrp {
874 fsl,pins = <
875 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x0b0b0
876 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x0b0b0
877 >;
878 };
879
880 pinctrl_uart5: uart5grp {
881 fsl,pins = <
882 MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x0b0b0
883 MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x0b0b0
884 >;
885 };
886
887 pinctrl_uart5_rtscts: uart5-rtsctsgrp {
888 fsl,pins = <
889 MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x0b0b0
890 MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x0b0b0
891 >;
892 };
893
894 pinctrl_usbh1_oc: usbh1-ocgrp {
895 fsl,pins = <
896 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x17059 /* USBH1_OC */
897 >;
898 };
899
900 pinctrl_usbh1_vbus: usbh1-vbusgrp {
901 fsl,pins = <
902 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0b0b0 /* USBH1_VBUSEN */
903 >;
904 };
905
906 pinctrl_usbotg_oc: usbotg-ocgrp {
907 fsl,pins = <
908 MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x17059 /* USBOTG_OC */
909 >;
910 };
911
912 pinctrl_usbotg_vbus: usbotg-vbusgrp {
913 fsl,pins = <
914 MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x1b0b0 /* USBOTG_VBUSEN */
915 >;
916 };
917
918 pinctrl_usdhc1: usdhc1grp {
919 fsl,pins = <
920 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x070b1
921 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x07099
922 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x070b1
923 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x070b1
924 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x070b1
925 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x070b1
926 >;
927 };
928
929 pinctrl_usdhc1_cd: usdhc1cdgrp {
930 fsl,pins = <
931 MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x170b0 /* SD1 CD */
932 >;
933 };
934
935 pinctrl_usdhc2: usdhc2grp {
936 fsl,pins = <
937 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x070b1
938 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x070b1
939 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x070b1
940 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x070b1
941 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x070b1
942 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x070b1
943 /* eMMC RESET */
944 MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x170b0
945 >;
946 };
947};
1/*
2 * Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42#include <dt-bindings/gpio/gpio.h>
43#include <dt-bindings/interrupt-controller/irq.h>
44#include <dt-bindings/pwm/pwm.h>
45
46/ {
47 aliases {
48 can0 = &can2;
49 can1 = &can1;
50 display = &display;
51 i2c0 = &i2c2;
52 i2c1 = &i2c_gpio;
53 i2c2 = &i2c1;
54 i2c3 = &i2c3;
55 i2c4 = &i2c4;
56 lcdif-23bit-pins-a = &pinctrl_disp0_1;
57 lcdif-24bit-pins-a = &pinctrl_disp0_2;
58 pwm0 = &pwm5;
59 reg-can-xcvr = ®_can_xcvr;
60 serial2 = &uart5;
61 serial4 = &uart3;
62 spi0 = &ecspi2;
63 spi1 = &spi_gpio;
64 stk5led = &user_led;
65 usbh1 = &usbotg2;
66 usbotg = &usbotg1;
67 };
68
69 chosen {
70 stdout-path = &uart1;
71 };
72
73 memory@80000000 {
74 device_type = "memory";
75 reg = <0x80000000 0>; /* will be filled by U-Boot */
76 };
77
78 clocks {
79 mclk: mclk {
80 compatible = "fixed-clock";
81 #clock-cells = <0>;
82 clock-frequency = <26000000>;
83 };
84 };
85
86 backlight: backlight {
87 compatible = "pwm-backlight";
88 pinctrl-names = "default";
89 pinctrl-0 = <&pinctrl_lcd_rst>;
90 enable-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
91 pwms = <&pwm5 0 500000 PWM_POLARITY_INVERTED>;
92 power-supply = <®_lcd_pwr>;
93 /*
94 * a poor man's way to create a 1:1 relationship between
95 * the PWM value and the actual duty cycle
96 */
97 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
98 10 11 12 13 14 15 16 17 18 19
99 20 21 22 23 24 25 26 27 28 29
100 30 31 32 33 34 35 36 37 38 39
101 40 41 42 43 44 45 46 47 48 49
102 50 51 52 53 54 55 56 57 58 59
103 60 61 62 63 64 65 66 67 68 69
104 70 71 72 73 74 75 76 77 78 79
105 80 81 82 83 84 85 86 87 88 89
106 90 91 92 93 94 95 96 97 98 99
107 100>;
108 default-brightness-level = <50>;
109 };
110
111 i2c_gpio: i2c-gpio {
112 compatible = "i2c-gpio";
113 #address-cells = <1>;
114 #size-cells = <0>;
115 pinctrl-names = "default";
116 pinctrl-0 = <&pinctrl_i2c_gpio>;
117 gpios = <
118 &gpio5 1 GPIO_ACTIVE_HIGH /* SDA */
119 &gpio5 0 GPIO_ACTIVE_HIGH /* SCL */
120 >;
121 clock-frequency = <400000>;
122 status = "okay";
123
124 ds1339: rtc@68 {
125 compatible = "dallas,ds1339";
126 reg = <0x68>;
127 status = "disabled";
128 };
129 };
130
131 leds {
132 compatible = "gpio-leds";
133
134 user_led: user {
135 label = "Heartbeat";
136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_led>;
138 gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
139 linux,default-trigger = "heartbeat";
140 };
141 };
142
143 reg_3v3_etn: regulator-3v3etn {
144 compatible = "regulator-fixed";
145 regulator-name = "3V3_ETN";
146 regulator-min-microvolt = <3300000>;
147 regulator-max-microvolt = <3300000>;
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_etnphy_power>;
150 gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
151 enable-active-high;
152 };
153
154 reg_2v5: regulator-2v5 {
155 compatible = "regulator-fixed";
156 regulator-name = "2V5";
157 regulator-min-microvolt = <2500000>;
158 regulator-max-microvolt = <2500000>;
159 regulator-always-on;
160 };
161
162 reg_3v3: regulator-3v3 {
163 compatible = "regulator-fixed";
164 regulator-name = "3V3";
165 regulator-min-microvolt = <3300000>;
166 regulator-max-microvolt = <3300000>;
167 regulator-always-on;
168 };
169
170 reg_can_xcvr: regulator-canxcvr {
171 compatible = "regulator-fixed";
172 regulator-name = "CAN XCVR";
173 regulator-min-microvolt = <3300000>;
174 regulator-max-microvolt = <3300000>;
175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_flexcan_xcvr>;
177 gpio = <&gpio3 5 GPIO_ACTIVE_LOW>;
178 };
179
180 reg_lcd_pwr: regulator-lcdpwr {
181 compatible = "regulator-fixed";
182 regulator-name = "LCD POWER";
183 regulator-min-microvolt = <3300000>;
184 regulator-max-microvolt = <3300000>;
185 pinctrl-names = "default";
186 pinctrl-0 = <&pinctrl_lcd_pwr>;
187 gpio = <&gpio5 4 GPIO_ACTIVE_HIGH>;
188 enable-active-high;
189 regulator-boot-on;
190 regulator-always-on;
191 };
192
193 reg_usbh1_vbus: regulator-usbh1vbus {
194 compatible = "regulator-fixed";
195 regulator-name = "usbh1_vbus";
196 regulator-min-microvolt = <5000000>;
197 regulator-max-microvolt = <5000000>;
198 pinctrl-names = "default";
199 pinctrl-0 = <&pinctrl_usbh1_vbus &pinctrl_usbh1_oc>;
200 gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
201 enable-active-high;
202 };
203
204 reg_usbotg_vbus: regulator-usbotgvbus {
205 compatible = "regulator-fixed";
206 regulator-name = "usbotg_vbus";
207 regulator-min-microvolt = <5000000>;
208 regulator-max-microvolt = <5000000>;
209 pinctrl-names = "default";
210 pinctrl-0 = <&pinctrl_usbotg_vbus &pinctrl_usbotg_oc>;
211 gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
212 enable-active-high;
213 };
214
215 spi_gpio: spi-gpio {
216 #address-cells = <1>;
217 #size-cells = <0>;
218 compatible = "spi-gpio";
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_spi_gpio>;
221 gpio-mosi = <&gpio1 30 GPIO_ACTIVE_HIGH>;
222 gpio-miso = <&gpio1 31 GPIO_ACTIVE_HIGH>;
223 gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>;
224 num-chipselects = <2>;
225 cs-gpios = <
226 &gpio1 29 GPIO_ACTIVE_HIGH
227 &gpio1 10 GPIO_ACTIVE_HIGH
228 >;
229 status = "disabled";
230
231 spi@0 {
232 compatible = "spidev";
233 reg = <0>;
234 spi-max-frequency = <660000>;
235 };
236
237 spi@1 {
238 compatible = "spidev";
239 reg = <1>;
240 spi-max-frequency = <660000>;
241 };
242 };
243
244 sound {
245 compatible = "karo,imx6ul-tx6ul-sgtl5000",
246 "simple-audio-card";
247 simple-audio-card,name = "imx6ul-tx6ul-sgtl5000-audio";
248 simple-audio-card,format = "i2s";
249 simple-audio-card,bitclock-master = <&codec_dai>;
250 simple-audio-card,frame-master = <&codec_dai>;
251 simple-audio-card,widgets =
252 "Microphone", "Mic Jack",
253 "Line", "Line In",
254 "Line", "Line Out",
255 "Headphone", "Headphone Jack";
256 simple-audio-card,routing =
257 "MIC_IN", "Mic Jack",
258 "Mic Jack", "Mic Bias",
259 "Headphone Jack", "HP_OUT";
260
261 cpu_dai: simple-audio-card,cpu {
262 sound-dai = <&sai2>;
263 };
264
265 codec_dai: simple-audio-card,codec {
266 sound-dai = <&sgtl5000>;
267 };
268 };
269};
270
271&can1 {
272 pinctrl-names = "default";
273 pinctrl-0 = <&pinctrl_flexcan1>;
274 xceiver-supply = <®_can_xcvr>;
275 status = "okay";
276};
277
278&can2 {
279 pinctrl-names = "default";
280 pinctrl-0 = <&pinctrl_flexcan2>;
281 xceiver-supply = <®_can_xcvr>;
282 status = "okay";
283};
284
285&ecspi2 {
286 pinctrl-names = "default";
287 pinctrl-0 = <&pinctrl_ecspi2>;
288 cs-gpios = <
289 &gpio1 29 GPIO_ACTIVE_HIGH
290 &gpio1 10 GPIO_ACTIVE_HIGH
291 >;
292 status = "disabled";
293
294 spidev0: spi@0 {
295 compatible = "spidev";
296 reg = <0>;
297 spi-max-frequency = <60000000>;
298 };
299
300 spidev1: spi@1 {
301 compatible = "spidev";
302 reg = <1>;
303 spi-max-frequency = <60000000>;
304 };
305};
306
307&fec1 {
308 pinctrl-names = "default";
309 pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio &pinctrl_etnphy0_rst>;
310 phy-mode = "rmii";
311 phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
312 phy-supply = <®_3v3_etn>;
313 phy-handle = <&etnphy0>;
314 status = "okay";
315
316 mdio {
317 #address-cells = <1>;
318 #size-cells = <0>;
319
320 etnphy0: ethernet-phy@0 {
321 compatible = "ethernet-phy-ieee802.3-c22";
322 reg = <0>;
323 pinctrl-names = "default";
324 pinctrl-0 = <&pinctrl_etnphy0_int>;
325 interrupt-parent = <&gpio5>;
326 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
327 status = "okay";
328 };
329
330 etnphy1: ethernet-phy@2 {
331 compatible = "ethernet-phy-ieee802.3-c22";
332 reg = <2>;
333 pinctrl-names = "default";
334 pinctrl-0 = <&pinctrl_etnphy1_int>;
335 interrupt-parent = <&gpio4>;
336 interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
337 status = "okay";
338 };
339 };
340};
341
342&fec2 {
343 pinctrl-names = "default";
344 pinctrl-0 = <&pinctrl_enet2 &pinctrl_etnphy1_rst>;
345 phy-mode = "rmii";
346 phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
347 phy-supply = <®_3v3_etn>;
348 phy-handle = <&etnphy1>;
349 status = "disabled";
350};
351
352&gpmi {
353 pinctrl-names = "default";
354 pinctrl-0 = <&pinctrl_gpmi_nand>;
355 nand-on-flash-bbt;
356 fsl,no-blockmark-swap;
357 status = "okay";
358};
359
360&i2c2 {
361 pinctrl-names = "default";
362 pinctrl-0 = <&pinctrl_i2c2>;
363 clock-frequency = <400000>;
364 status = "okay";
365
366 sgtl5000: codec@a {
367 compatible = "fsl,sgtl5000";
368 reg = <0x0a>;
369 #sound-dai-cells = <0>;
370 VDDA-supply = <®_2v5>;
371 VDDIO-supply = <®_3v3>;
372 clocks = <&mclk>;
373 };
374
375 polytouch: polytouch@38 {
376 compatible = "edt,edt-ft5x06";
377 reg = <0x38>;
378 pinctrl-names = "default";
379 pinctrl-0 = <&pinctrl_edt_ft5x06>;
380 interrupt-parent = <&gpio5>;
381 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
382 reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
383 wake-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
384 wakeup-source;
385 };
386
387 touchscreen: touchscreen@48 {
388 compatible = "ti,tsc2007";
389 reg = <0x48>;
390 pinctrl-names = "default";
391 pinctrl-0 = <&pinctrl_tsc2007>;
392 interrupt-parent = <&gpio3>;
393 interrupts = <26 IRQ_TYPE_NONE>;
394 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
395 ti,x-plate-ohms = <660>;
396 wakeup-source;
397 };
398};
399
400&kpp {
401 pinctrl-names = "default";
402 pinctrl-0 = <&pinctrl_kpp>;
403 /* sample keymap */
404 /* row/col 0..3 are mapped to KPP row/col 4..7 */
405 linux,keymap = <
406 MATRIX_KEY(4, 4, KEY_POWER)
407 MATRIX_KEY(4, 5, KEY_KP0)
408 MATRIX_KEY(4, 6, KEY_KP1)
409 MATRIX_KEY(4, 7, KEY_KP2)
410 MATRIX_KEY(5, 4, KEY_KP3)
411 MATRIX_KEY(5, 5, KEY_KP4)
412 MATRIX_KEY(5, 6, KEY_KP5)
413 MATRIX_KEY(5, 7, KEY_KP6)
414 MATRIX_KEY(6, 4, KEY_KP7)
415 MATRIX_KEY(6, 5, KEY_KP8)
416 MATRIX_KEY(6, 6, KEY_KP9)
417 >;
418 status = "okay";
419};
420
421&lcdif {
422 pinctrl-names = "default";
423 pinctrl-0 = <&pinctrl_disp0_1>;
424 lcd-supply = <®_lcd_pwr>;
425 display = <&display>;
426 status = "okay";
427
428 display: disp0 {
429 bits-per-pixel = <32>;
430 bus-width = <24>;
431 status = "okay";
432
433 display-timings {
434 VGA {
435 clock-frequency = <25200000>;
436 hactive = <640>;
437 vactive = <480>;
438 hback-porch = <48>;
439 hsync-len = <96>;
440 hfront-porch = <16>;
441 vback-porch = <31>;
442 vsync-len = <2>;
443 vfront-porch = <12>;
444 hsync-active = <0>;
445 vsync-active = <0>;
446 de-active = <1>;
447 pixelclk-active = <1>;
448 };
449
450 ETV570 {
451 clock-frequency = <25200000>;
452 hactive = <640>;
453 vactive = <480>;
454 hback-porch = <114>;
455 hsync-len = <30>;
456 hfront-porch = <16>;
457 vback-porch = <32>;
458 vsync-len = <3>;
459 vfront-porch = <10>;
460 hsync-active = <0>;
461 vsync-active = <0>;
462 de-active = <1>;
463 pixelclk-active = <1>;
464 };
465
466 ET0350 {
467 clock-frequency = <6413760>;
468 hactive = <320>;
469 vactive = <240>;
470 hback-porch = <34>;
471 hsync-len = <34>;
472 hfront-porch = <20>;
473 vback-porch = <15>;
474 vsync-len = <3>;
475 vfront-porch = <4>;
476 hsync-active = <0>;
477 vsync-active = <0>;
478 de-active = <1>;
479 pixelclk-active = <1>;
480 };
481
482 ET0430 {
483 clock-frequency = <9009000>;
484 hactive = <480>;
485 vactive = <272>;
486 hback-porch = <2>;
487 hsync-len = <41>;
488 hfront-porch = <2>;
489 vback-porch = <2>;
490 vsync-len = <10>;
491 vfront-porch = <2>;
492 hsync-active = <0>;
493 vsync-active = <0>;
494 de-active = <1>;
495 pixelclk-active = <0>;
496 };
497
498 ET0500 {
499 clock-frequency = <33264000>;
500 hactive = <800>;
501 vactive = <480>;
502 hback-porch = <88>;
503 hsync-len = <128>;
504 hfront-porch = <40>;
505 vback-porch = <33>;
506 vsync-len = <2>;
507 vfront-porch = <10>;
508 hsync-active = <0>;
509 vsync-active = <0>;
510 de-active = <1>;
511 pixelclk-active = <1>;
512 };
513
514 ET0700 { /* same as ET0500 */
515 clock-frequency = <33264000>;
516 hactive = <800>;
517 vactive = <480>;
518 hback-porch = <88>;
519 hsync-len = <128>;
520 hfront-porch = <40>;
521 vback-porch = <33>;
522 vsync-len = <2>;
523 vfront-porch = <10>;
524 hsync-active = <0>;
525 vsync-active = <0>;
526 de-active = <1>;
527 pixelclk-active = <1>;
528 };
529
530 ETQ570 {
531 clock-frequency = <6596040>;
532 hactive = <320>;
533 vactive = <240>;
534 hback-porch = <38>;
535 hsync-len = <30>;
536 hfront-porch = <30>;
537 vback-porch = <16>;
538 vsync-len = <3>;
539 vfront-porch = <4>;
540 hsync-active = <0>;
541 vsync-active = <0>;
542 de-active = <1>;
543 pixelclk-active = <1>;
544 };
545 };
546 };
547};
548
549&pwm5 {
550 pinctrl-names = "default";
551 pinctrl-0 = <&pinctrl_pwm5>;
552 status = "okay";
553};
554
555&sai2 {
556 pinctrl-names = "default";
557 pinctrl-0 = <&pinctrl_sai2>;
558 status = "okay";
559};
560
561&uart1 {
562 pinctrl-names = "default";
563 pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
564 uart-has-rtscts;
565 status = "okay";
566};
567
568&uart2 {
569 pinctrl-names = "default";
570 pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
571 uart-has-rtscts;
572 status = "okay";
573};
574
575&uart5 {
576 pinctrl-names = "default";
577 pinctrl-0 = <&pinctrl_uart5 &pinctrl_uart5_rtscts>;
578 uart-has-rtscts;
579 status = "okay";
580};
581
582&usbotg1 {
583 vbus-supply = <®_usbotg_vbus>;
584 dr_mode = "peripheral";
585 disable-over-current;
586 status = "okay";
587};
588
589&usbotg2 {
590 vbus-supply = <®_usbh1_vbus>;
591 dr_mode = "host";
592 disable-over-current;
593 status = "okay";
594};
595
596&usdhc1 {
597 pinctrl-names = "default";
598 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_cd>;
599 bus-width = <4>;
600 no-1-8-v;
601 cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
602 fsl,wp-controller;
603 status = "okay";
604};
605
606&iomuxc {
607 pinctrl-names = "default";
608 pinctrl-0 = <&pinctrl_hog>;
609
610 pinctrl_hog: hoggrp {
611 };
612
613 pinctrl_led: ledgrp {
614 fsl,pins = <
615 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x0b0b0 /* LED */
616 >;
617 };
618
619 pinctrl_disp0_1: disp0grp-1 {
620 fsl,pins = <
621 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */
622 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */
623 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */
624 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */
625 /* PAD DISP0_DAT0 is used for the Flexcan transceiver control on STK5-v5 */
626 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x10
627 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10
628 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10
629 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10
630 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10
631 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10
632 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10
633 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x10
634 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x10
635 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10
636 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10
637 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10
638 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10
639 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10
640 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10
641 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x10
642 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x10
643 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10
644 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10
645 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10
646 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10
647 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10
648 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10
649 >;
650 };
651
652 pinctrl_disp0_2: disp0grp-2 {
653 fsl,pins = <
654 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */
655 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */
656 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */
657 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */
658 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x10
659 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x10
660 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10
661 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10
662 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10
663 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10
664 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10
665 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10
666 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x10
667 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x10
668 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10
669 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10
670 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10
671 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10
672 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10
673 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10
674 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x10
675 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x10
676 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10
677 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10
678 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10
679 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10
680 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10
681 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10
682 >;
683 };
684
685 pinctrl_ecspi2: ecspi2grp {
686 fsl,pins = <
687 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x0b0b0 /* CSPI_SS */
688 MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0b0b0 /* CSPI_SS */
689 MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x0b0b0 /* CSPI_MOSI */
690 MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x0b0b0 /* CSPI_MISO */
691 MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x0b0b0 /* CSPI_SCLK */
692 >;
693 };
694
695 pinctrl_edt_ft5x06: edt-ft5x06grp {
696 fsl,pins = <
697 MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* Interrupt */
698 MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* Reset */
699 MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 /* Wake */
700 >;
701 };
702
703 pinctrl_enet1: enet1grp {
704 fsl,pins = <
705 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x000b0
706 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x000b0
707 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x000b0
708 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x000b0
709 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x000b0
710 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x000b0
711 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x000b0
712 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x400000b1
713 >;
714 };
715
716 pinctrl_enet2: enet2grp {
717 fsl,pins = <
718 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x000b0
719 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x000b0
720 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x000b0
721 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x000b0
722 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x000b0
723 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x000b0
724 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x000b0
725 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x400000b1
726 >;
727 };
728
729 pinctrl_enet1_mdio: enet1-mdiogrp {
730 fsl,pins = <
731 MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x0b0b0
732 MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
733 >;
734 };
735
736 pinctrl_etnphy_power: etnphy-pwrgrp {
737 fsl,pins = <
738 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0 /* ETN PHY POWER */
739 >;
740 };
741
742 pinctrl_etnphy0_int: etnphy-intgrp-0 {
743 fsl,pins = <
744 MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 /* ETN PHY INT */
745 >;
746 };
747
748 pinctrl_etnphy0_rst: etnphy-rstgrp-0 {
749 fsl,pins = <
750 MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0 /* ETN PHY RESET */
751 >;
752 };
753
754 pinctrl_etnphy1_int: etnphy-intgrp-1 {
755 fsl,pins = <
756 MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x0b0b0 /* ETN PHY INT */
757 >;
758 };
759
760 pinctrl_etnphy1_rst: etnphy-rstgrp-1 {
761 fsl,pins = <
762 MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x0b0b0 /* ETN PHY RESET */
763 >;
764 };
765
766 pinctrl_flexcan1: flexcan1grp {
767 fsl,pins = <
768 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0
769 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0
770 >;
771 };
772
773 pinctrl_flexcan2: flexcan2grp {
774 fsl,pins = <
775 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0
776 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0
777 >;
778 };
779
780 pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
781 fsl,pins = <
782 MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0b0b0 /* Flexcan XCVR enable */
783 >;
784 };
785
786 pinctrl_gpmi_nand: gpminandgrp {
787 fsl,pins = <
788 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
789 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
790 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1
791 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
792 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
793 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1
794 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1
795 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1
796 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1
797 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1
798 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1
799 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1
800 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1
801 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1
802 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1
803 >;
804 };
805
806 pinctrl_i2c_gpio: i2c-gpiogrp {
807 fsl,pins = <
808 MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x4001b8b1 /* I2C SCL */
809 MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x4001b8b1 /* I2C SDA */
810 >;
811 };
812
813 pinctrl_i2c2: i2c2grp {
814 fsl,pins = <
815 MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b1
816 MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b1
817 >;
818 };
819
820 pinctrl_kpp: kppgrp {
821 fsl,pins = <
822 MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04 0x1b0b0
823 MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x1b0b0
824 MX6UL_PAD_ENET2_TX_EN__KPP_COL06 0x1b0b0
825 MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x1b0b0
826 MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04 0x1b0b0
827 MX6UL_PAD_ENET2_RX_EN__KPP_ROW05 0x1b0b0
828 MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06 0x1b0b0
829 MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07 0x1b0b0
830 >;
831 };
832
833 pinctrl_lcd_pwr: lcd-pwrgrp {
834 fsl,pins = <
835 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 /* LCD Power Enable */
836 >;
837 };
838
839 pinctrl_lcd_rst: lcd-rstgrp {
840 fsl,pins = <
841 MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0 /* LCD Reset */
842 >;
843 };
844
845 pinctrl_pwm5: pwm5grp {
846 fsl,pins = <
847 MX6UL_PAD_NAND_DQS__PWM5_OUT 0x0b0b0
848 >;
849 };
850
851 pinctrl_sai2: sai2grp {
852 fsl,pins = <
853 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0b0b0 /* SSI1_RXD */
854 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0b0b0 /* SSI1_TXD */
855 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x0b0b0 /* SSI1_CLK */
856 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x0b0b0 /* SSI1_FS */
857 >;
858 };
859
860 pinctrl_spi_gpio: spi-gpiogrp {
861 fsl,pins = <
862 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x0b0b0 /* CSPI_SS */
863 MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0b0b0 /* CSPI_SS */
864 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x0b0b0 /* CSPI_MOSI */
865 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x0b0b0 /* CSPI_MISO */
866 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x0b0b0 /* CSPI_SCLK */
867 >;
868 };
869
870 pinctrl_tsc2007: tsc2007grp {
871 fsl,pins = <
872 MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x1b0b0 /* Interrupt */
873 >;
874 };
875
876 pinctrl_uart1: uart1grp {
877 fsl,pins = <
878 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x0b0b0
879 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0b0b0
880 >;
881 };
882
883 pinctrl_uart1_rtscts: uart1-rtsctsgrp {
884 fsl,pins = <
885 MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x0b0b0
886 MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x0b0b0
887 >;
888 };
889
890 pinctrl_uart2: uart2grp {
891 fsl,pins = <
892 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0b0b0
893 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0b0b0
894 >;
895 };
896
897 pinctrl_uart2_rtscts: uart2-rtsctsgrp {
898 fsl,pins = <
899 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x0b0b0
900 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x0b0b0
901 >;
902 };
903
904 pinctrl_uart5: uart5grp {
905 fsl,pins = <
906 MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x0b0b0
907 MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x0b0b0
908 >;
909 };
910
911 pinctrl_uart5_rtscts: uart5-rtsctsgrp {
912 fsl,pins = <
913 MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x0b0b0
914 MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x0b0b0
915 >;
916 };
917
918 pinctrl_usbh1_oc: usbh1-ocgrp {
919 fsl,pins = <
920 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x17059 /* USBH1_OC */
921 >;
922 };
923
924 pinctrl_usbh1_vbus: usbh1-vbusgrp {
925 fsl,pins = <
926 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0b0b0 /* USBH1_VBUSEN */
927 >;
928 };
929
930 pinctrl_usbotg_oc: usbotg-ocgrp {
931 fsl,pins = <
932 MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x17059 /* USBOTG_OC */
933 >;
934 };
935
936 pinctrl_usbotg_vbus: usbotg-vbusgrp {
937 fsl,pins = <
938 MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x1b0b0 /* USBOTG_VBUSEN */
939 >;
940 };
941
942 pinctrl_usdhc1: usdhc1grp {
943 fsl,pins = <
944 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x070b1
945 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x07099
946 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x070b1
947 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x070b1
948 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x070b1
949 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x070b1
950 >;
951 };
952
953 pinctrl_usdhc1_cd: usdhc1cdgrp {
954 fsl,pins = <
955 MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x170b0 /* SD1 CD */
956 >;
957 };
958
959 pinctrl_usdhc2: usdhc2grp {
960 fsl,pins = <
961 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x070b1
962 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x070b1
963 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x070b1
964 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x070b1
965 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x070b1
966 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x070b1
967 /* eMMC RESET */
968 MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x170b0
969 >;
970 };
971};