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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dwc3-pci.c - PCI Specific glue layer
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/slab.h>
14#include <linux/pci.h>
15#include <linux/workqueue.h>
16#include <linux/pm_runtime.h>
17#include <linux/platform_device.h>
18#include <linux/gpio/consumer.h>
19#include <linux/gpio/machine.h>
20#include <linux/acpi.h>
21#include <linux/delay.h>
22
23#define PCI_DEVICE_ID_INTEL_BYT 0x0f37
24#define PCI_DEVICE_ID_INTEL_MRFLD 0x119e
25#define PCI_DEVICE_ID_INTEL_BSW 0x22b7
26#define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30
27#define PCI_DEVICE_ID_INTEL_SPTH 0xa130
28#define PCI_DEVICE_ID_INTEL_BXT 0x0aaa
29#define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa
30#define PCI_DEVICE_ID_INTEL_APL 0x5aaa
31#define PCI_DEVICE_ID_INTEL_KBP 0xa2b0
32#define PCI_DEVICE_ID_INTEL_CMLLP 0x02ee
33#define PCI_DEVICE_ID_INTEL_CMLH 0x06ee
34#define PCI_DEVICE_ID_INTEL_GLK 0x31aa
35#define PCI_DEVICE_ID_INTEL_CNPLP 0x9dee
36#define PCI_DEVICE_ID_INTEL_CNPH 0xa36e
37#define PCI_DEVICE_ID_INTEL_CNPV 0xa3b0
38#define PCI_DEVICE_ID_INTEL_ICLLP 0x34ee
39#define PCI_DEVICE_ID_INTEL_EHL 0x4b7e
40#define PCI_DEVICE_ID_INTEL_TGPLP 0xa0ee
41#define PCI_DEVICE_ID_INTEL_TGPH 0x43ee
42#define PCI_DEVICE_ID_INTEL_JSP 0x4dee
43#define PCI_DEVICE_ID_INTEL_ADL 0x460e
44#define PCI_DEVICE_ID_INTEL_ADL_PCH 0x51ee
45#define PCI_DEVICE_ID_INTEL_ADLN 0x465e
46#define PCI_DEVICE_ID_INTEL_ADLN_PCH 0x54ee
47#define PCI_DEVICE_ID_INTEL_ADLS 0x7ae1
48#define PCI_DEVICE_ID_INTEL_RPL 0xa70e
49#define PCI_DEVICE_ID_INTEL_RPLS 0x7a61
50#define PCI_DEVICE_ID_INTEL_MTLP 0x7ec1
51#define PCI_DEVICE_ID_INTEL_MTL 0x7e7e
52#define PCI_DEVICE_ID_INTEL_TGL 0x9a15
53#define PCI_DEVICE_ID_AMD_MR 0x163a
54
55#define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511"
56#define PCI_INTEL_BXT_FUNC_PMU_PWR 4
57#define PCI_INTEL_BXT_STATE_D0 0
58#define PCI_INTEL_BXT_STATE_D3 3
59
60#define GP_RWBAR 1
61#define GP_RWREG1 0xa0
62#define GP_RWREG1_ULPI_REFCLK_DISABLE (1 << 17)
63
64/**
65 * struct dwc3_pci - Driver private structure
66 * @dwc3: child dwc3 platform_device
67 * @pci: our link to PCI bus
68 * @guid: _DSM GUID
69 * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM
70 * @wakeup_work: work for asynchronous resume
71 */
72struct dwc3_pci {
73 struct platform_device *dwc3;
74 struct pci_dev *pci;
75
76 guid_t guid;
77
78 unsigned int has_dsm_for_pm:1;
79 struct work_struct wakeup_work;
80};
81
82static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
83static const struct acpi_gpio_params cs_gpios = { 1, 0, false };
84
85static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
86 { "reset-gpios", &reset_gpios, 1 },
87 { "cs-gpios", &cs_gpios, 1 },
88 { },
89};
90
91static struct gpiod_lookup_table platform_bytcr_gpios = {
92 .dev_id = "0000:00:16.0",
93 .table = {
94 GPIO_LOOKUP("INT33FC:00", 54, "cs", GPIO_ACTIVE_HIGH),
95 GPIO_LOOKUP("INT33FC:02", 14, "reset", GPIO_ACTIVE_HIGH),
96 {}
97 },
98};
99
100static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci)
101{
102 void __iomem *reg;
103 u32 value;
104
105 reg = pcim_iomap(pci, GP_RWBAR, 0);
106 if (!reg)
107 return -ENOMEM;
108
109 value = readl(reg + GP_RWREG1);
110 if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE))
111 goto unmap; /* ULPI refclk already enabled */
112
113 value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE;
114 writel(value, reg + GP_RWREG1);
115 /* This comes from the Intel Android x86 tree w/o any explanation */
116 msleep(100);
117unmap:
118 pcim_iounmap(pci, reg);
119 return 0;
120}
121
122static const struct property_entry dwc3_pci_intel_properties[] = {
123 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
124 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
125 {}
126};
127
128static const struct property_entry dwc3_pci_intel_phy_charger_detect_properties[] = {
129 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
130 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
131 PROPERTY_ENTRY_BOOL("linux,phy_charger_detect"),
132 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
133 {}
134};
135
136static const struct property_entry dwc3_pci_intel_byt_properties[] = {
137 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
138 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
139 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
140 {}
141};
142
143static const struct property_entry dwc3_pci_mrfld_properties[] = {
144 PROPERTY_ENTRY_STRING("dr_mode", "otg"),
145 PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"),
146 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
147 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
148 PROPERTY_ENTRY_BOOL("snps,usb2-gadget-lpm-disable"),
149 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
150 {}
151};
152
153static const struct property_entry dwc3_pci_amd_properties[] = {
154 PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
155 PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf),
156 PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"),
157 PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"),
158 PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"),
159 PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"),
160 PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"),
161 PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"),
162 PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"),
163 PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"),
164 PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1),
165 /* FIXME these quirks should be removed when AMD NL tapes out */
166 PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"),
167 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
168 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
169 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
170 {}
171};
172
173static const struct property_entry dwc3_pci_mr_properties[] = {
174 PROPERTY_ENTRY_STRING("dr_mode", "otg"),
175 PROPERTY_ENTRY_BOOL("usb-role-switch"),
176 PROPERTY_ENTRY_STRING("role-switch-default-mode", "host"),
177 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
178 {}
179};
180
181static const struct software_node dwc3_pci_intel_swnode = {
182 .properties = dwc3_pci_intel_properties,
183};
184
185static const struct software_node dwc3_pci_intel_phy_charger_detect_swnode = {
186 .properties = dwc3_pci_intel_phy_charger_detect_properties,
187};
188
189static const struct software_node dwc3_pci_intel_byt_swnode = {
190 .properties = dwc3_pci_intel_byt_properties,
191};
192
193static const struct software_node dwc3_pci_intel_mrfld_swnode = {
194 .properties = dwc3_pci_mrfld_properties,
195};
196
197static const struct software_node dwc3_pci_amd_swnode = {
198 .properties = dwc3_pci_amd_properties,
199};
200
201static const struct software_node dwc3_pci_amd_mr_swnode = {
202 .properties = dwc3_pci_mr_properties,
203};
204
205static int dwc3_pci_quirks(struct dwc3_pci *dwc,
206 const struct software_node *swnode)
207{
208 struct pci_dev *pdev = dwc->pci;
209
210 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
211 if (pdev->device == PCI_DEVICE_ID_INTEL_BXT ||
212 pdev->device == PCI_DEVICE_ID_INTEL_BXT_M ||
213 pdev->device == PCI_DEVICE_ID_INTEL_EHL) {
214 guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid);
215 dwc->has_dsm_for_pm = true;
216 }
217
218 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
219 struct gpio_desc *gpio;
220 int ret;
221
222 /* On BYT the FW does not always enable the refclock */
223 ret = dwc3_byt_enable_ulpi_refclock(pdev);
224 if (ret)
225 return ret;
226
227 ret = devm_acpi_dev_add_driver_gpios(&pdev->dev,
228 acpi_dwc3_byt_gpios);
229 if (ret)
230 dev_dbg(&pdev->dev, "failed to add mapping table\n");
231
232 /*
233 * A lot of BYT devices lack ACPI resource entries for
234 * the GPIOs, add a fallback mapping to the reference
235 * design GPIOs which all boards seem to use.
236 */
237 gpiod_add_lookup_table(&platform_bytcr_gpios);
238
239 /*
240 * These GPIOs will turn on the USB2 PHY. Note that we have to
241 * put the gpio descriptors again here because the phy driver
242 * might want to grab them, too.
243 */
244 gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW);
245 if (IS_ERR(gpio))
246 return PTR_ERR(gpio);
247
248 gpiod_set_value_cansleep(gpio, 1);
249 gpiod_put(gpio);
250
251 gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
252 if (IS_ERR(gpio))
253 return PTR_ERR(gpio);
254
255 if (gpio) {
256 gpiod_set_value_cansleep(gpio, 1);
257 gpiod_put(gpio);
258 usleep_range(10000, 11000);
259 }
260
261 /*
262 * Make the pdev name predictable (only 1 DWC3 on BYT)
263 * and patch the phy dev-name into the lookup table so
264 * that the phy-driver can get the GPIOs.
265 */
266 dwc->dwc3->id = PLATFORM_DEVID_NONE;
267 platform_bytcr_gpios.dev_id = "dwc3.ulpi";
268
269 /*
270 * Some Android tablets with a Crystal Cove PMIC
271 * (INT33FD), rely on the TUSB1211 phy for charger
272 * detection. These can be identified by them _not_
273 * using the standard ACPI battery and ac drivers.
274 */
275 if (acpi_dev_present("INT33FD", "1", 2) &&
276 acpi_quirk_skip_acpi_ac_and_battery()) {
277 dev_info(&pdev->dev, "Using TUSB1211 phy for charger detection\n");
278 swnode = &dwc3_pci_intel_phy_charger_detect_swnode;
279 }
280 }
281 }
282
283 return device_add_software_node(&dwc->dwc3->dev, swnode);
284}
285
286#ifdef CONFIG_PM
287static void dwc3_pci_resume_work(struct work_struct *work)
288{
289 struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work);
290 struct platform_device *dwc3 = dwc->dwc3;
291 int ret;
292
293 ret = pm_runtime_get_sync(&dwc3->dev);
294 if (ret < 0) {
295 pm_runtime_put_sync_autosuspend(&dwc3->dev);
296 return;
297 }
298
299 pm_runtime_mark_last_busy(&dwc3->dev);
300 pm_runtime_put_sync_autosuspend(&dwc3->dev);
301}
302#endif
303
304static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
305{
306 struct dwc3_pci *dwc;
307 struct resource res[2];
308 int ret;
309 struct device *dev = &pci->dev;
310
311 ret = pcim_enable_device(pci);
312 if (ret) {
313 dev_err(dev, "failed to enable pci device\n");
314 return -ENODEV;
315 }
316
317 pci_set_master(pci);
318
319 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
320 if (!dwc)
321 return -ENOMEM;
322
323 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
324 if (!dwc->dwc3)
325 return -ENOMEM;
326
327 memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
328
329 res[0].start = pci_resource_start(pci, 0);
330 res[0].end = pci_resource_end(pci, 0);
331 res[0].name = "dwc_usb3";
332 res[0].flags = IORESOURCE_MEM;
333
334 res[1].start = pci->irq;
335 res[1].name = "dwc_usb3";
336 res[1].flags = IORESOURCE_IRQ;
337
338 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res));
339 if (ret) {
340 dev_err(dev, "couldn't add resources to dwc3 device\n");
341 goto err;
342 }
343
344 dwc->pci = pci;
345 dwc->dwc3->dev.parent = dev;
346 ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev));
347
348 ret = dwc3_pci_quirks(dwc, (void *)id->driver_data);
349 if (ret)
350 goto err;
351
352 ret = platform_device_add(dwc->dwc3);
353 if (ret) {
354 dev_err(dev, "failed to register dwc3 device\n");
355 goto err;
356 }
357
358 device_init_wakeup(dev, true);
359 pci_set_drvdata(pci, dwc);
360 pm_runtime_put(dev);
361#ifdef CONFIG_PM
362 INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work);
363#endif
364
365 return 0;
366err:
367 device_remove_software_node(&dwc->dwc3->dev);
368 platform_device_put(dwc->dwc3);
369 return ret;
370}
371
372static void dwc3_pci_remove(struct pci_dev *pci)
373{
374 struct dwc3_pci *dwc = pci_get_drvdata(pci);
375 struct pci_dev *pdev = dwc->pci;
376
377 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT)
378 gpiod_remove_lookup_table(&platform_bytcr_gpios);
379#ifdef CONFIG_PM
380 cancel_work_sync(&dwc->wakeup_work);
381#endif
382 device_init_wakeup(&pci->dev, false);
383 pm_runtime_get(&pci->dev);
384 device_remove_software_node(&dwc->dwc3->dev);
385 platform_device_unregister(dwc->dwc3);
386}
387
388static const struct pci_device_id dwc3_pci_id_table[] = {
389 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BSW),
390 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
391
392 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BYT),
393 (kernel_ulong_t) &dwc3_pci_intel_byt_swnode, },
394
395 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD),
396 (kernel_ulong_t) &dwc3_pci_intel_mrfld_swnode, },
397
398 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLLP),
399 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
400
401 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLH),
402 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
403
404 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTLP),
405 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
406
407 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTH),
408 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
409
410 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT),
411 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
412
413 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT_M),
414 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
415
416 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_APL),
417 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
418
419 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_KBP),
420 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
421
422 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_GLK),
423 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
424
425 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPLP),
426 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
427
428 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPH),
429 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
430
431 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPV),
432 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
433
434 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICLLP),
435 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
436
437 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_EHL),
438 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
439
440 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPLP),
441 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
442
443 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPH),
444 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
445
446 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_JSP),
447 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
448
449 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL),
450 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
451
452 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL_PCH),
453 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
454
455 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLN),
456 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
457
458 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLN_PCH),
459 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
460
461 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLS),
462 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
463
464 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_RPL),
465 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
466
467 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_RPLS),
468 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
469
470 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTLP),
471 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
472
473 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL),
474 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
475
476 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL),
477 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
478
479 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB),
480 (kernel_ulong_t) &dwc3_pci_amd_swnode, },
481
482 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_MR),
483 (kernel_ulong_t)&dwc3_pci_amd_mr_swnode, },
484
485 { } /* Terminating Entry */
486};
487MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
488
489#if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP)
490static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param)
491{
492 union acpi_object *obj;
493 union acpi_object tmp;
494 union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp);
495
496 if (!dwc->has_dsm_for_pm)
497 return 0;
498
499 tmp.type = ACPI_TYPE_INTEGER;
500 tmp.integer.value = param;
501
502 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid,
503 1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4);
504 if (!obj) {
505 dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n");
506 return -EIO;
507 }
508
509 ACPI_FREE(obj);
510
511 return 0;
512}
513#endif /* CONFIG_PM || CONFIG_PM_SLEEP */
514
515#ifdef CONFIG_PM
516static int dwc3_pci_runtime_suspend(struct device *dev)
517{
518 struct dwc3_pci *dwc = dev_get_drvdata(dev);
519
520 if (device_can_wakeup(dev))
521 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
522
523 return -EBUSY;
524}
525
526static int dwc3_pci_runtime_resume(struct device *dev)
527{
528 struct dwc3_pci *dwc = dev_get_drvdata(dev);
529 int ret;
530
531 ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
532 if (ret)
533 return ret;
534
535 queue_work(pm_wq, &dwc->wakeup_work);
536
537 return 0;
538}
539#endif /* CONFIG_PM */
540
541#ifdef CONFIG_PM_SLEEP
542static int dwc3_pci_suspend(struct device *dev)
543{
544 struct dwc3_pci *dwc = dev_get_drvdata(dev);
545
546 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
547}
548
549static int dwc3_pci_resume(struct device *dev)
550{
551 struct dwc3_pci *dwc = dev_get_drvdata(dev);
552
553 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
554}
555#endif /* CONFIG_PM_SLEEP */
556
557static const struct dev_pm_ops dwc3_pci_dev_pm_ops = {
558 SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume)
559 SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume,
560 NULL)
561};
562
563static struct pci_driver dwc3_pci_driver = {
564 .name = "dwc3-pci",
565 .id_table = dwc3_pci_id_table,
566 .probe = dwc3_pci_probe,
567 .remove = dwc3_pci_remove,
568 .driver = {
569 .pm = &dwc3_pci_dev_pm_ops,
570 }
571};
572
573MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
574MODULE_LICENSE("GPL v2");
575MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
576
577module_pci_driver(dwc3_pci_driver);
1// SPDX-License-Identifier: GPL-2.0
2/**
3 * dwc3-pci.c - PCI Specific glue layer
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/slab.h>
14#include <linux/pci.h>
15#include <linux/workqueue.h>
16#include <linux/pm_runtime.h>
17#include <linux/platform_device.h>
18#include <linux/gpio/consumer.h>
19#include <linux/gpio/machine.h>
20#include <linux/acpi.h>
21#include <linux/delay.h>
22
23#define PCI_DEVICE_ID_INTEL_BYT 0x0f37
24#define PCI_DEVICE_ID_INTEL_MRFLD 0x119e
25#define PCI_DEVICE_ID_INTEL_BSW 0x22b7
26#define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30
27#define PCI_DEVICE_ID_INTEL_SPTH 0xa130
28#define PCI_DEVICE_ID_INTEL_BXT 0x0aaa
29#define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa
30#define PCI_DEVICE_ID_INTEL_APL 0x5aaa
31#define PCI_DEVICE_ID_INTEL_KBP 0xa2b0
32#define PCI_DEVICE_ID_INTEL_CMLLP 0x02ee
33#define PCI_DEVICE_ID_INTEL_CMLH 0x06ee
34#define PCI_DEVICE_ID_INTEL_GLK 0x31aa
35#define PCI_DEVICE_ID_INTEL_CNPLP 0x9dee
36#define PCI_DEVICE_ID_INTEL_CNPH 0xa36e
37#define PCI_DEVICE_ID_INTEL_CNPV 0xa3b0
38#define PCI_DEVICE_ID_INTEL_ICLLP 0x34ee
39#define PCI_DEVICE_ID_INTEL_EHLLP 0x4b7e
40#define PCI_DEVICE_ID_INTEL_TGPLP 0xa0ee
41#define PCI_DEVICE_ID_INTEL_TGPH 0x43ee
42#define PCI_DEVICE_ID_INTEL_JSP 0x4dee
43
44#define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511"
45#define PCI_INTEL_BXT_FUNC_PMU_PWR 4
46#define PCI_INTEL_BXT_STATE_D0 0
47#define PCI_INTEL_BXT_STATE_D3 3
48
49#define GP_RWBAR 1
50#define GP_RWREG1 0xa0
51#define GP_RWREG1_ULPI_REFCLK_DISABLE (1 << 17)
52
53/**
54 * struct dwc3_pci - Driver private structure
55 * @dwc3: child dwc3 platform_device
56 * @pci: our link to PCI bus
57 * @guid: _DSM GUID
58 * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM
59 * @wakeup_work: work for asynchronous resume
60 */
61struct dwc3_pci {
62 struct platform_device *dwc3;
63 struct pci_dev *pci;
64
65 guid_t guid;
66
67 unsigned int has_dsm_for_pm:1;
68 struct work_struct wakeup_work;
69};
70
71static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
72static const struct acpi_gpio_params cs_gpios = { 1, 0, false };
73
74static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
75 { "reset-gpios", &reset_gpios, 1 },
76 { "cs-gpios", &cs_gpios, 1 },
77 { },
78};
79
80static struct gpiod_lookup_table platform_bytcr_gpios = {
81 .dev_id = "0000:00:16.0",
82 .table = {
83 GPIO_LOOKUP("INT33FC:00", 54, "reset", GPIO_ACTIVE_HIGH),
84 GPIO_LOOKUP("INT33FC:02", 14, "cs", GPIO_ACTIVE_HIGH),
85 {}
86 },
87};
88
89static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci)
90{
91 void __iomem *reg;
92 u32 value;
93
94 reg = pcim_iomap(pci, GP_RWBAR, 0);
95 if (!reg)
96 return -ENOMEM;
97
98 value = readl(reg + GP_RWREG1);
99 if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE))
100 goto unmap; /* ULPI refclk already enabled */
101
102 value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE;
103 writel(value, reg + GP_RWREG1);
104 /* This comes from the Intel Android x86 tree w/o any explanation */
105 msleep(100);
106unmap:
107 pcim_iounmap(pci, reg);
108 return 0;
109}
110
111static const struct property_entry dwc3_pci_intel_properties[] = {
112 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
113 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
114 {}
115};
116
117static const struct property_entry dwc3_pci_mrfld_properties[] = {
118 PROPERTY_ENTRY_STRING("dr_mode", "otg"),
119 PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"),
120 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
121 {}
122};
123
124static const struct property_entry dwc3_pci_amd_properties[] = {
125 PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
126 PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf),
127 PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"),
128 PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"),
129 PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"),
130 PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"),
131 PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"),
132 PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"),
133 PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"),
134 PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"),
135 PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1),
136 /* FIXME these quirks should be removed when AMD NL tapes out */
137 PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"),
138 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
139 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
140 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
141 {}
142};
143
144static int dwc3_pci_quirks(struct dwc3_pci *dwc)
145{
146 struct pci_dev *pdev = dwc->pci;
147
148 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
149 if (pdev->device == PCI_DEVICE_ID_INTEL_BXT ||
150 pdev->device == PCI_DEVICE_ID_INTEL_BXT_M) {
151 guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid);
152 dwc->has_dsm_for_pm = true;
153 }
154
155 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
156 struct gpio_desc *gpio;
157 int ret;
158
159 /* On BYT the FW does not always enable the refclock */
160 ret = dwc3_byt_enable_ulpi_refclock(pdev);
161 if (ret)
162 return ret;
163
164 ret = devm_acpi_dev_add_driver_gpios(&pdev->dev,
165 acpi_dwc3_byt_gpios);
166 if (ret)
167 dev_dbg(&pdev->dev, "failed to add mapping table\n");
168
169 /*
170 * A lot of BYT devices lack ACPI resource entries for
171 * the GPIOs, add a fallback mapping to the reference
172 * design GPIOs which all boards seem to use.
173 */
174 gpiod_add_lookup_table(&platform_bytcr_gpios);
175
176 /*
177 * These GPIOs will turn on the USB2 PHY. Note that we have to
178 * put the gpio descriptors again here because the phy driver
179 * might want to grab them, too.
180 */
181 gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW);
182 if (IS_ERR(gpio))
183 return PTR_ERR(gpio);
184
185 gpiod_set_value_cansleep(gpio, 1);
186 gpiod_put(gpio);
187
188 gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
189 if (IS_ERR(gpio))
190 return PTR_ERR(gpio);
191
192 if (gpio) {
193 gpiod_set_value_cansleep(gpio, 1);
194 gpiod_put(gpio);
195 usleep_range(10000, 11000);
196 }
197 }
198 }
199
200 return 0;
201}
202
203#ifdef CONFIG_PM
204static void dwc3_pci_resume_work(struct work_struct *work)
205{
206 struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work);
207 struct platform_device *dwc3 = dwc->dwc3;
208 int ret;
209
210 ret = pm_runtime_get_sync(&dwc3->dev);
211 if (ret) {
212 pm_runtime_put_sync_autosuspend(&dwc3->dev);
213 return;
214 }
215
216 pm_runtime_mark_last_busy(&dwc3->dev);
217 pm_runtime_put_sync_autosuspend(&dwc3->dev);
218}
219#endif
220
221static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
222{
223 struct property_entry *p = (struct property_entry *)id->driver_data;
224 struct dwc3_pci *dwc;
225 struct resource res[2];
226 int ret;
227 struct device *dev = &pci->dev;
228
229 ret = pcim_enable_device(pci);
230 if (ret) {
231 dev_err(dev, "failed to enable pci device\n");
232 return -ENODEV;
233 }
234
235 pci_set_master(pci);
236
237 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
238 if (!dwc)
239 return -ENOMEM;
240
241 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
242 if (!dwc->dwc3)
243 return -ENOMEM;
244
245 memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
246
247 res[0].start = pci_resource_start(pci, 0);
248 res[0].end = pci_resource_end(pci, 0);
249 res[0].name = "dwc_usb3";
250 res[0].flags = IORESOURCE_MEM;
251
252 res[1].start = pci->irq;
253 res[1].name = "dwc_usb3";
254 res[1].flags = IORESOURCE_IRQ;
255
256 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res));
257 if (ret) {
258 dev_err(dev, "couldn't add resources to dwc3 device\n");
259 goto err;
260 }
261
262 dwc->pci = pci;
263 dwc->dwc3->dev.parent = dev;
264 ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev));
265
266 ret = platform_device_add_properties(dwc->dwc3, p);
267 if (ret < 0)
268 goto err;
269
270 ret = dwc3_pci_quirks(dwc);
271 if (ret)
272 goto err;
273
274 ret = platform_device_add(dwc->dwc3);
275 if (ret) {
276 dev_err(dev, "failed to register dwc3 device\n");
277 goto err;
278 }
279
280 device_init_wakeup(dev, true);
281 pci_set_drvdata(pci, dwc);
282 pm_runtime_put(dev);
283#ifdef CONFIG_PM
284 INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work);
285#endif
286
287 return 0;
288err:
289 platform_device_put(dwc->dwc3);
290 return ret;
291}
292
293static void dwc3_pci_remove(struct pci_dev *pci)
294{
295 struct dwc3_pci *dwc = pci_get_drvdata(pci);
296 struct pci_dev *pdev = dwc->pci;
297
298 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT)
299 gpiod_remove_lookup_table(&platform_bytcr_gpios);
300#ifdef CONFIG_PM
301 cancel_work_sync(&dwc->wakeup_work);
302#endif
303 device_init_wakeup(&pci->dev, false);
304 pm_runtime_get(&pci->dev);
305 platform_device_unregister(dwc->dwc3);
306}
307
308static const struct pci_device_id dwc3_pci_id_table[] = {
309 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BSW),
310 (kernel_ulong_t) &dwc3_pci_intel_properties },
311
312 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BYT),
313 (kernel_ulong_t) &dwc3_pci_intel_properties, },
314
315 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD),
316 (kernel_ulong_t) &dwc3_pci_mrfld_properties, },
317
318 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLLP),
319 (kernel_ulong_t) &dwc3_pci_intel_properties, },
320
321 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLH),
322 (kernel_ulong_t) &dwc3_pci_intel_properties, },
323
324 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTLP),
325 (kernel_ulong_t) &dwc3_pci_intel_properties, },
326
327 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTH),
328 (kernel_ulong_t) &dwc3_pci_intel_properties, },
329
330 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT),
331 (kernel_ulong_t) &dwc3_pci_intel_properties, },
332
333 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT_M),
334 (kernel_ulong_t) &dwc3_pci_intel_properties, },
335
336 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_APL),
337 (kernel_ulong_t) &dwc3_pci_intel_properties, },
338
339 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_KBP),
340 (kernel_ulong_t) &dwc3_pci_intel_properties, },
341
342 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_GLK),
343 (kernel_ulong_t) &dwc3_pci_intel_properties, },
344
345 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPLP),
346 (kernel_ulong_t) &dwc3_pci_intel_properties, },
347
348 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPH),
349 (kernel_ulong_t) &dwc3_pci_intel_properties, },
350
351 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPV),
352 (kernel_ulong_t) &dwc3_pci_intel_properties, },
353
354 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICLLP),
355 (kernel_ulong_t) &dwc3_pci_intel_properties, },
356
357 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_EHLLP),
358 (kernel_ulong_t) &dwc3_pci_intel_properties, },
359
360 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPLP),
361 (kernel_ulong_t) &dwc3_pci_intel_properties, },
362
363 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPH),
364 (kernel_ulong_t) &dwc3_pci_intel_properties, },
365
366 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_JSP),
367 (kernel_ulong_t) &dwc3_pci_intel_properties, },
368
369 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB),
370 (kernel_ulong_t) &dwc3_pci_amd_properties, },
371 { } /* Terminating Entry */
372};
373MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
374
375#if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP)
376static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param)
377{
378 union acpi_object *obj;
379 union acpi_object tmp;
380 union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp);
381
382 if (!dwc->has_dsm_for_pm)
383 return 0;
384
385 tmp.type = ACPI_TYPE_INTEGER;
386 tmp.integer.value = param;
387
388 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid,
389 1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4);
390 if (!obj) {
391 dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n");
392 return -EIO;
393 }
394
395 ACPI_FREE(obj);
396
397 return 0;
398}
399#endif /* CONFIG_PM || CONFIG_PM_SLEEP */
400
401#ifdef CONFIG_PM
402static int dwc3_pci_runtime_suspend(struct device *dev)
403{
404 struct dwc3_pci *dwc = dev_get_drvdata(dev);
405
406 if (device_can_wakeup(dev))
407 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
408
409 return -EBUSY;
410}
411
412static int dwc3_pci_runtime_resume(struct device *dev)
413{
414 struct dwc3_pci *dwc = dev_get_drvdata(dev);
415 int ret;
416
417 ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
418 if (ret)
419 return ret;
420
421 queue_work(pm_wq, &dwc->wakeup_work);
422
423 return 0;
424}
425#endif /* CONFIG_PM */
426
427#ifdef CONFIG_PM_SLEEP
428static int dwc3_pci_suspend(struct device *dev)
429{
430 struct dwc3_pci *dwc = dev_get_drvdata(dev);
431
432 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
433}
434
435static int dwc3_pci_resume(struct device *dev)
436{
437 struct dwc3_pci *dwc = dev_get_drvdata(dev);
438
439 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
440}
441#endif /* CONFIG_PM_SLEEP */
442
443static const struct dev_pm_ops dwc3_pci_dev_pm_ops = {
444 SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume)
445 SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume,
446 NULL)
447};
448
449static struct pci_driver dwc3_pci_driver = {
450 .name = "dwc3-pci",
451 .id_table = dwc3_pci_id_table,
452 .probe = dwc3_pci_probe,
453 .remove = dwc3_pci_remove,
454 .driver = {
455 .pm = &dwc3_pci_dev_pm_ops,
456 }
457};
458
459MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
460MODULE_LICENSE("GPL v2");
461MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
462
463module_pci_driver(dwc3_pci_driver);