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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * An I2C driver for the PCF85063 RTC
4 * Copyright 2014 Rose Technology
5 *
6 * Author: Søren Andersen <san@rosetechnology.dk>
7 * Maintainers: http://www.nslu2-linux.org/
8 *
9 * Copyright (C) 2019 Micro Crystal AG
10 * Author: Alexandre Belloni <alexandre.belloni@bootlin.com>
11 */
12#include <linux/clk-provider.h>
13#include <linux/i2c.h>
14#include <linux/bcd.h>
15#include <linux/rtc.h>
16#include <linux/module.h>
17#include <linux/of_device.h>
18#include <linux/pm_wakeirq.h>
19#include <linux/regmap.h>
20
21/*
22 * Information for this driver was pulled from the following datasheets.
23 *
24 * https://www.nxp.com/docs/en/data-sheet/PCF85063A.pdf
25 * https://www.nxp.com/docs/en/data-sheet/PCF85063TP.pdf
26 *
27 * PCF85063A -- Rev. 7 — 30 March 2018
28 * PCF85063TP -- Rev. 4 — 6 May 2015
29 *
30 * https://www.microcrystal.com/fileadmin/Media/Products/RTC/App.Manual/RV-8263-C7_App-Manual.pdf
31 * RV8263 -- Rev. 1.0 — January 2019
32 */
33
34#define PCF85063_REG_CTRL1 0x00 /* status */
35#define PCF85063_REG_CTRL1_CAP_SEL BIT(0)
36#define PCF85063_REG_CTRL1_STOP BIT(5)
37#define PCF85063_REG_CTRL1_EXT_TEST BIT(7)
38
39#define PCF85063_REG_CTRL2 0x01
40#define PCF85063_CTRL2_AF BIT(6)
41#define PCF85063_CTRL2_AIE BIT(7)
42
43#define PCF85063_REG_OFFSET 0x02
44#define PCF85063_OFFSET_SIGN_BIT 6 /* 2's complement sign bit */
45#define PCF85063_OFFSET_MODE BIT(7)
46#define PCF85063_OFFSET_STEP0 4340
47#define PCF85063_OFFSET_STEP1 4069
48
49#define PCF85063_REG_CLKO_F_MASK 0x07 /* frequency mask */
50#define PCF85063_REG_CLKO_F_32768HZ 0x00
51#define PCF85063_REG_CLKO_F_OFF 0x07
52
53#define PCF85063_REG_RAM 0x03
54
55#define PCF85063_REG_SC 0x04 /* datetime */
56#define PCF85063_REG_SC_OS 0x80
57
58#define PCF85063_REG_ALM_S 0x0b
59#define PCF85063_AEN BIT(7)
60
61struct pcf85063_config {
62 struct regmap_config regmap;
63 unsigned has_alarms:1;
64 unsigned force_cap_7000:1;
65};
66
67struct pcf85063 {
68 struct rtc_device *rtc;
69 struct regmap *regmap;
70#ifdef CONFIG_COMMON_CLK
71 struct clk_hw clkout_hw;
72#endif
73};
74
75static int pcf85063_rtc_read_time(struct device *dev, struct rtc_time *tm)
76{
77 struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
78 int rc;
79 u8 regs[7];
80
81 /*
82 * while reading, the time/date registers are blocked and not updated
83 * anymore until the access is finished. To not lose a second
84 * event, the access must be finished within one second. So, read all
85 * time/date registers in one turn.
86 */
87 rc = regmap_bulk_read(pcf85063->regmap, PCF85063_REG_SC, regs,
88 sizeof(regs));
89 if (rc)
90 return rc;
91
92 /* if the clock has lost its power it makes no sense to use its time */
93 if (regs[0] & PCF85063_REG_SC_OS) {
94 dev_warn(&pcf85063->rtc->dev, "Power loss detected, invalid time\n");
95 return -EINVAL;
96 }
97
98 tm->tm_sec = bcd2bin(regs[0] & 0x7F);
99 tm->tm_min = bcd2bin(regs[1] & 0x7F);
100 tm->tm_hour = bcd2bin(regs[2] & 0x3F); /* rtc hr 0-23 */
101 tm->tm_mday = bcd2bin(regs[3] & 0x3F);
102 tm->tm_wday = regs[4] & 0x07;
103 tm->tm_mon = bcd2bin(regs[5] & 0x1F) - 1; /* rtc mn 1-12 */
104 tm->tm_year = bcd2bin(regs[6]);
105 tm->tm_year += 100;
106
107 return 0;
108}
109
110static int pcf85063_rtc_set_time(struct device *dev, struct rtc_time *tm)
111{
112 struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
113 int rc;
114 u8 regs[7];
115
116 /*
117 * to accurately set the time, reset the divider chain and keep it in
118 * reset state until all time/date registers are written
119 */
120 rc = regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
121 PCF85063_REG_CTRL1_EXT_TEST |
122 PCF85063_REG_CTRL1_STOP,
123 PCF85063_REG_CTRL1_STOP);
124 if (rc)
125 return rc;
126
127 /* hours, minutes and seconds */
128 regs[0] = bin2bcd(tm->tm_sec) & 0x7F; /* clear OS flag */
129
130 regs[1] = bin2bcd(tm->tm_min);
131 regs[2] = bin2bcd(tm->tm_hour);
132
133 /* Day of month, 1 - 31 */
134 regs[3] = bin2bcd(tm->tm_mday);
135
136 /* Day, 0 - 6 */
137 regs[4] = tm->tm_wday & 0x07;
138
139 /* month, 1 - 12 */
140 regs[5] = bin2bcd(tm->tm_mon + 1);
141
142 /* year and century */
143 regs[6] = bin2bcd(tm->tm_year - 100);
144
145 /* write all registers at once */
146 rc = regmap_bulk_write(pcf85063->regmap, PCF85063_REG_SC,
147 regs, sizeof(regs));
148 if (rc)
149 return rc;
150
151 /*
152 * Write the control register as a separate action since the size of
153 * the register space is different between the PCF85063TP and
154 * PCF85063A devices. The rollover point can not be used.
155 */
156 return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
157 PCF85063_REG_CTRL1_STOP, 0);
158}
159
160static int pcf85063_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
161{
162 struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
163 u8 buf[4];
164 unsigned int val;
165 int ret;
166
167 ret = regmap_bulk_read(pcf85063->regmap, PCF85063_REG_ALM_S,
168 buf, sizeof(buf));
169 if (ret)
170 return ret;
171
172 alrm->time.tm_sec = bcd2bin(buf[0] & 0x7f);
173 alrm->time.tm_min = bcd2bin(buf[1] & 0x7f);
174 alrm->time.tm_hour = bcd2bin(buf[2] & 0x3f);
175 alrm->time.tm_mday = bcd2bin(buf[3] & 0x3f);
176
177 ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &val);
178 if (ret)
179 return ret;
180
181 alrm->enabled = !!(val & PCF85063_CTRL2_AIE);
182
183 return 0;
184}
185
186static int pcf85063_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
187{
188 struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
189 u8 buf[5];
190 int ret;
191
192 buf[0] = bin2bcd(alrm->time.tm_sec);
193 buf[1] = bin2bcd(alrm->time.tm_min);
194 buf[2] = bin2bcd(alrm->time.tm_hour);
195 buf[3] = bin2bcd(alrm->time.tm_mday);
196 buf[4] = PCF85063_AEN; /* Do not match on week day */
197
198 ret = regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
199 PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF, 0);
200 if (ret)
201 return ret;
202
203 ret = regmap_bulk_write(pcf85063->regmap, PCF85063_REG_ALM_S,
204 buf, sizeof(buf));
205 if (ret)
206 return ret;
207
208 return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
209 PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF,
210 alrm->enabled ? PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF : PCF85063_CTRL2_AF);
211}
212
213static int pcf85063_rtc_alarm_irq_enable(struct device *dev,
214 unsigned int enabled)
215{
216 struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
217
218 return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
219 PCF85063_CTRL2_AIE,
220 enabled ? PCF85063_CTRL2_AIE : 0);
221}
222
223static irqreturn_t pcf85063_rtc_handle_irq(int irq, void *dev_id)
224{
225 struct pcf85063 *pcf85063 = dev_id;
226 unsigned int val;
227 int err;
228
229 err = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &val);
230 if (err)
231 return IRQ_NONE;
232
233 if (val & PCF85063_CTRL2_AF) {
234 rtc_update_irq(pcf85063->rtc, 1, RTC_IRQF | RTC_AF);
235 regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
236 PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF,
237 0);
238 return IRQ_HANDLED;
239 }
240
241 return IRQ_NONE;
242}
243
244static int pcf85063_read_offset(struct device *dev, long *offset)
245{
246 struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
247 long val;
248 u32 reg;
249 int ret;
250
251 ret = regmap_read(pcf85063->regmap, PCF85063_REG_OFFSET, ®);
252 if (ret < 0)
253 return ret;
254
255 val = sign_extend32(reg & ~PCF85063_OFFSET_MODE,
256 PCF85063_OFFSET_SIGN_BIT);
257
258 if (reg & PCF85063_OFFSET_MODE)
259 *offset = val * PCF85063_OFFSET_STEP1;
260 else
261 *offset = val * PCF85063_OFFSET_STEP0;
262
263 return 0;
264}
265
266static int pcf85063_set_offset(struct device *dev, long offset)
267{
268 struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
269 s8 mode0, mode1, reg;
270 unsigned int error0, error1;
271
272 if (offset > PCF85063_OFFSET_STEP0 * 63)
273 return -ERANGE;
274 if (offset < PCF85063_OFFSET_STEP0 * -64)
275 return -ERANGE;
276
277 mode0 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP0);
278 mode1 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP1);
279
280 error0 = abs(offset - (mode0 * PCF85063_OFFSET_STEP0));
281 error1 = abs(offset - (mode1 * PCF85063_OFFSET_STEP1));
282 if (mode1 > 63 || mode1 < -64 || error0 < error1)
283 reg = mode0 & ~PCF85063_OFFSET_MODE;
284 else
285 reg = mode1 | PCF85063_OFFSET_MODE;
286
287 return regmap_write(pcf85063->regmap, PCF85063_REG_OFFSET, reg);
288}
289
290static int pcf85063_ioctl(struct device *dev, unsigned int cmd,
291 unsigned long arg)
292{
293 struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
294 int status, ret = 0;
295
296 switch (cmd) {
297 case RTC_VL_READ:
298 ret = regmap_read(pcf85063->regmap, PCF85063_REG_SC, &status);
299 if (ret < 0)
300 return ret;
301
302 status = (status & PCF85063_REG_SC_OS) ? RTC_VL_DATA_INVALID : 0;
303
304 return put_user(status, (unsigned int __user *)arg);
305
306 default:
307 return -ENOIOCTLCMD;
308 }
309}
310
311static const struct rtc_class_ops pcf85063_rtc_ops = {
312 .read_time = pcf85063_rtc_read_time,
313 .set_time = pcf85063_rtc_set_time,
314 .read_offset = pcf85063_read_offset,
315 .set_offset = pcf85063_set_offset,
316 .read_alarm = pcf85063_rtc_read_alarm,
317 .set_alarm = pcf85063_rtc_set_alarm,
318 .alarm_irq_enable = pcf85063_rtc_alarm_irq_enable,
319 .ioctl = pcf85063_ioctl,
320};
321
322static int pcf85063_nvmem_read(void *priv, unsigned int offset,
323 void *val, size_t bytes)
324{
325 return regmap_read(priv, PCF85063_REG_RAM, val);
326}
327
328static int pcf85063_nvmem_write(void *priv, unsigned int offset,
329 void *val, size_t bytes)
330{
331 return regmap_write(priv, PCF85063_REG_RAM, *(u8 *)val);
332}
333
334static int pcf85063_load_capacitance(struct pcf85063 *pcf85063,
335 const struct device_node *np,
336 unsigned int force_cap)
337{
338 u32 load = 7000;
339 u8 reg = 0;
340
341 if (force_cap)
342 load = force_cap;
343 else
344 of_property_read_u32(np, "quartz-load-femtofarads", &load);
345
346 switch (load) {
347 default:
348 dev_warn(&pcf85063->rtc->dev, "Unknown quartz-load-femtofarads value: %d. Assuming 7000",
349 load);
350 fallthrough;
351 case 7000:
352 break;
353 case 12500:
354 reg = PCF85063_REG_CTRL1_CAP_SEL;
355 break;
356 }
357
358 return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
359 PCF85063_REG_CTRL1_CAP_SEL, reg);
360}
361
362#ifdef CONFIG_COMMON_CLK
363/*
364 * Handling of the clkout
365 */
366
367#define clkout_hw_to_pcf85063(_hw) container_of(_hw, struct pcf85063, clkout_hw)
368
369static int clkout_rates[] = {
370 32768,
371 16384,
372 8192,
373 4096,
374 2048,
375 1024,
376 1,
377 0
378};
379
380static unsigned long pcf85063_clkout_recalc_rate(struct clk_hw *hw,
381 unsigned long parent_rate)
382{
383 struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
384 unsigned int buf;
385 int ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &buf);
386
387 if (ret < 0)
388 return 0;
389
390 buf &= PCF85063_REG_CLKO_F_MASK;
391 return clkout_rates[buf];
392}
393
394static long pcf85063_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
395 unsigned long *prate)
396{
397 int i;
398
399 for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
400 if (clkout_rates[i] <= rate)
401 return clkout_rates[i];
402
403 return 0;
404}
405
406static int pcf85063_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
407 unsigned long parent_rate)
408{
409 struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
410 int i;
411
412 for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
413 if (clkout_rates[i] == rate)
414 return regmap_update_bits(pcf85063->regmap,
415 PCF85063_REG_CTRL2,
416 PCF85063_REG_CLKO_F_MASK, i);
417
418 return -EINVAL;
419}
420
421static int pcf85063_clkout_control(struct clk_hw *hw, bool enable)
422{
423 struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
424 unsigned int buf;
425 int ret;
426
427 ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &buf);
428 if (ret < 0)
429 return ret;
430 buf &= PCF85063_REG_CLKO_F_MASK;
431
432 if (enable) {
433 if (buf == PCF85063_REG_CLKO_F_OFF)
434 buf = PCF85063_REG_CLKO_F_32768HZ;
435 else
436 return 0;
437 } else {
438 if (buf != PCF85063_REG_CLKO_F_OFF)
439 buf = PCF85063_REG_CLKO_F_OFF;
440 else
441 return 0;
442 }
443
444 return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
445 PCF85063_REG_CLKO_F_MASK, buf);
446}
447
448static int pcf85063_clkout_prepare(struct clk_hw *hw)
449{
450 return pcf85063_clkout_control(hw, 1);
451}
452
453static void pcf85063_clkout_unprepare(struct clk_hw *hw)
454{
455 pcf85063_clkout_control(hw, 0);
456}
457
458static int pcf85063_clkout_is_prepared(struct clk_hw *hw)
459{
460 struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
461 unsigned int buf;
462 int ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &buf);
463
464 if (ret < 0)
465 return 0;
466
467 return (buf & PCF85063_REG_CLKO_F_MASK) != PCF85063_REG_CLKO_F_OFF;
468}
469
470static const struct clk_ops pcf85063_clkout_ops = {
471 .prepare = pcf85063_clkout_prepare,
472 .unprepare = pcf85063_clkout_unprepare,
473 .is_prepared = pcf85063_clkout_is_prepared,
474 .recalc_rate = pcf85063_clkout_recalc_rate,
475 .round_rate = pcf85063_clkout_round_rate,
476 .set_rate = pcf85063_clkout_set_rate,
477};
478
479static struct clk *pcf85063_clkout_register_clk(struct pcf85063 *pcf85063)
480{
481 struct clk *clk;
482 struct clk_init_data init;
483 struct device_node *node = pcf85063->rtc->dev.parent->of_node;
484 struct device_node *fixed_clock;
485
486 fixed_clock = of_get_child_by_name(node, "clock");
487 if (fixed_clock) {
488 /*
489 * skip registering square wave clock when a fixed
490 * clock has been registered. The fixed clock is
491 * registered automatically when being referenced.
492 */
493 of_node_put(fixed_clock);
494 return NULL;
495 }
496
497 init.name = "pcf85063-clkout";
498 init.ops = &pcf85063_clkout_ops;
499 init.flags = 0;
500 init.parent_names = NULL;
501 init.num_parents = 0;
502 pcf85063->clkout_hw.init = &init;
503
504 /* optional override of the clockname */
505 of_property_read_string(node, "clock-output-names", &init.name);
506
507 /* register the clock */
508 clk = devm_clk_register(&pcf85063->rtc->dev, &pcf85063->clkout_hw);
509
510 if (!IS_ERR(clk))
511 of_clk_add_provider(node, of_clk_src_simple_get, clk);
512
513 return clk;
514}
515#endif
516
517enum pcf85063_type {
518 PCF85063,
519 PCF85063TP,
520 PCF85063A,
521 RV8263,
522 PCF85063_LAST_ID
523};
524
525static struct pcf85063_config pcf85063_cfg[] = {
526 [PCF85063] = {
527 .regmap = {
528 .reg_bits = 8,
529 .val_bits = 8,
530 .max_register = 0x0a,
531 },
532 },
533 [PCF85063TP] = {
534 .regmap = {
535 .reg_bits = 8,
536 .val_bits = 8,
537 .max_register = 0x0a,
538 },
539 },
540 [PCF85063A] = {
541 .regmap = {
542 .reg_bits = 8,
543 .val_bits = 8,
544 .max_register = 0x11,
545 },
546 .has_alarms = 1,
547 },
548 [RV8263] = {
549 .regmap = {
550 .reg_bits = 8,
551 .val_bits = 8,
552 .max_register = 0x11,
553 },
554 .has_alarms = 1,
555 .force_cap_7000 = 1,
556 },
557};
558
559static const struct i2c_device_id pcf85063_ids[];
560
561static int pcf85063_probe(struct i2c_client *client)
562{
563 struct pcf85063 *pcf85063;
564 unsigned int tmp;
565 int err;
566 const struct pcf85063_config *config;
567 struct nvmem_config nvmem_cfg = {
568 .name = "pcf85063_nvram",
569 .reg_read = pcf85063_nvmem_read,
570 .reg_write = pcf85063_nvmem_write,
571 .type = NVMEM_TYPE_BATTERY_BACKED,
572 .size = 1,
573 };
574
575 dev_dbg(&client->dev, "%s\n", __func__);
576
577 pcf85063 = devm_kzalloc(&client->dev, sizeof(struct pcf85063),
578 GFP_KERNEL);
579 if (!pcf85063)
580 return -ENOMEM;
581
582 if (client->dev.of_node) {
583 config = of_device_get_match_data(&client->dev);
584 if (!config)
585 return -ENODEV;
586 } else {
587 enum pcf85063_type type =
588 i2c_match_id(pcf85063_ids, client)->driver_data;
589 if (type >= PCF85063_LAST_ID)
590 return -ENODEV;
591 config = &pcf85063_cfg[type];
592 }
593
594 pcf85063->regmap = devm_regmap_init_i2c(client, &config->regmap);
595 if (IS_ERR(pcf85063->regmap))
596 return PTR_ERR(pcf85063->regmap);
597
598 i2c_set_clientdata(client, pcf85063);
599
600 err = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL1, &tmp);
601 if (err) {
602 dev_err(&client->dev, "RTC chip is not present\n");
603 return err;
604 }
605
606 pcf85063->rtc = devm_rtc_allocate_device(&client->dev);
607 if (IS_ERR(pcf85063->rtc))
608 return PTR_ERR(pcf85063->rtc);
609
610 err = pcf85063_load_capacitance(pcf85063, client->dev.of_node,
611 config->force_cap_7000 ? 7000 : 0);
612 if (err < 0)
613 dev_warn(&client->dev, "failed to set xtal load capacitance: %d",
614 err);
615
616 pcf85063->rtc->ops = &pcf85063_rtc_ops;
617 pcf85063->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
618 pcf85063->rtc->range_max = RTC_TIMESTAMP_END_2099;
619 set_bit(RTC_FEATURE_ALARM_RES_2S, pcf85063->rtc->features);
620 clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, pcf85063->rtc->features);
621 clear_bit(RTC_FEATURE_ALARM, pcf85063->rtc->features);
622
623 if (config->has_alarms && client->irq > 0) {
624 err = devm_request_threaded_irq(&client->dev, client->irq,
625 NULL, pcf85063_rtc_handle_irq,
626 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
627 "pcf85063", pcf85063);
628 if (err) {
629 dev_warn(&pcf85063->rtc->dev,
630 "unable to request IRQ, alarms disabled\n");
631 } else {
632 set_bit(RTC_FEATURE_ALARM, pcf85063->rtc->features);
633 device_init_wakeup(&client->dev, true);
634 err = dev_pm_set_wake_irq(&client->dev, client->irq);
635 if (err)
636 dev_err(&pcf85063->rtc->dev,
637 "failed to enable irq wake\n");
638 }
639 }
640
641 nvmem_cfg.priv = pcf85063->regmap;
642 devm_rtc_nvmem_register(pcf85063->rtc, &nvmem_cfg);
643
644#ifdef CONFIG_COMMON_CLK
645 /* register clk in common clk framework */
646 pcf85063_clkout_register_clk(pcf85063);
647#endif
648
649 return devm_rtc_register_device(pcf85063->rtc);
650}
651
652static const struct i2c_device_id pcf85063_ids[] = {
653 { "pca85073a", PCF85063A },
654 { "pcf85063", PCF85063 },
655 { "pcf85063tp", PCF85063TP },
656 { "pcf85063a", PCF85063A },
657 { "rv8263", RV8263 },
658 {}
659};
660MODULE_DEVICE_TABLE(i2c, pcf85063_ids);
661
662#ifdef CONFIG_OF
663static const struct of_device_id pcf85063_of_match[] = {
664 { .compatible = "nxp,pca85073a", .data = &pcf85063_cfg[PCF85063A] },
665 { .compatible = "nxp,pcf85063", .data = &pcf85063_cfg[PCF85063] },
666 { .compatible = "nxp,pcf85063tp", .data = &pcf85063_cfg[PCF85063TP] },
667 { .compatible = "nxp,pcf85063a", .data = &pcf85063_cfg[PCF85063A] },
668 { .compatible = "microcrystal,rv8263", .data = &pcf85063_cfg[RV8263] },
669 {}
670};
671MODULE_DEVICE_TABLE(of, pcf85063_of_match);
672#endif
673
674static struct i2c_driver pcf85063_driver = {
675 .driver = {
676 .name = "rtc-pcf85063",
677 .of_match_table = of_match_ptr(pcf85063_of_match),
678 },
679 .probe_new = pcf85063_probe,
680 .id_table = pcf85063_ids,
681};
682
683module_i2c_driver(pcf85063_driver);
684
685MODULE_AUTHOR("Søren Andersen <san@rosetechnology.dk>");
686MODULE_DESCRIPTION("PCF85063 RTC driver");
687MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * An I2C driver for the PCF85063 RTC
4 * Copyright 2014 Rose Technology
5 *
6 * Author: Søren Andersen <san@rosetechnology.dk>
7 * Maintainers: http://www.nslu2-linux.org/
8 *
9 * Copyright (C) 2019 Micro Crystal AG
10 * Author: Alexandre Belloni <alexandre.belloni@bootlin.com>
11 */
12#include <linux/clk-provider.h>
13#include <linux/i2c.h>
14#include <linux/bcd.h>
15#include <linux/rtc.h>
16#include <linux/module.h>
17#include <linux/of_device.h>
18#include <linux/pm_wakeirq.h>
19#include <linux/regmap.h>
20
21/*
22 * Information for this driver was pulled from the following datasheets.
23 *
24 * https://www.nxp.com/documents/data_sheet/PCF85063A.pdf
25 * https://www.nxp.com/documents/data_sheet/PCF85063TP.pdf
26 *
27 * PCF85063A -- Rev. 6 — 18 November 2015
28 * PCF85063TP -- Rev. 4 — 6 May 2015
29 *
30 * https://www.microcrystal.com/fileadmin/Media/Products/RTC/App.Manual/RV-8263-C7_App-Manual.pdf
31 * RV8263 -- Rev. 1.0 — January 2019
32 */
33
34#define PCF85063_REG_CTRL1 0x00 /* status */
35#define PCF85063_REG_CTRL1_CAP_SEL BIT(0)
36#define PCF85063_REG_CTRL1_STOP BIT(5)
37
38#define PCF85063_REG_CTRL2 0x01
39#define PCF85063_CTRL2_AF BIT(6)
40#define PCF85063_CTRL2_AIE BIT(7)
41
42#define PCF85063_REG_OFFSET 0x02
43#define PCF85063_OFFSET_SIGN_BIT 6 /* 2's complement sign bit */
44#define PCF85063_OFFSET_MODE BIT(7)
45#define PCF85063_OFFSET_STEP0 4340
46#define PCF85063_OFFSET_STEP1 4069
47
48#define PCF85063_REG_CLKO_F_MASK 0x07 /* frequency mask */
49#define PCF85063_REG_CLKO_F_32768HZ 0x00
50#define PCF85063_REG_CLKO_F_OFF 0x07
51
52#define PCF85063_REG_RAM 0x03
53
54#define PCF85063_REG_SC 0x04 /* datetime */
55#define PCF85063_REG_SC_OS 0x80
56
57#define PCF85063_REG_ALM_S 0x0b
58#define PCF85063_AEN BIT(7)
59
60struct pcf85063_config {
61 struct regmap_config regmap;
62 unsigned has_alarms:1;
63 unsigned force_cap_7000:1;
64};
65
66struct pcf85063 {
67 struct rtc_device *rtc;
68 struct regmap *regmap;
69#ifdef CONFIG_COMMON_CLK
70 struct clk_hw clkout_hw;
71#endif
72};
73
74static int pcf85063_rtc_read_time(struct device *dev, struct rtc_time *tm)
75{
76 struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
77 int rc;
78 u8 regs[7];
79
80 /*
81 * while reading, the time/date registers are blocked and not updated
82 * anymore until the access is finished. To not lose a second
83 * event, the access must be finished within one second. So, read all
84 * time/date registers in one turn.
85 */
86 rc = regmap_bulk_read(pcf85063->regmap, PCF85063_REG_SC, regs,
87 sizeof(regs));
88 if (rc)
89 return rc;
90
91 /* if the clock has lost its power it makes no sense to use its time */
92 if (regs[0] & PCF85063_REG_SC_OS) {
93 dev_warn(&pcf85063->rtc->dev, "Power loss detected, invalid time\n");
94 return -EINVAL;
95 }
96
97 tm->tm_sec = bcd2bin(regs[0] & 0x7F);
98 tm->tm_min = bcd2bin(regs[1] & 0x7F);
99 tm->tm_hour = bcd2bin(regs[2] & 0x3F); /* rtc hr 0-23 */
100 tm->tm_mday = bcd2bin(regs[3] & 0x3F);
101 tm->tm_wday = regs[4] & 0x07;
102 tm->tm_mon = bcd2bin(regs[5] & 0x1F) - 1; /* rtc mn 1-12 */
103 tm->tm_year = bcd2bin(regs[6]);
104 tm->tm_year += 100;
105
106 return 0;
107}
108
109static int pcf85063_rtc_set_time(struct device *dev, struct rtc_time *tm)
110{
111 struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
112 int rc;
113 u8 regs[7];
114
115 /*
116 * to accurately set the time, reset the divider chain and keep it in
117 * reset state until all time/date registers are written
118 */
119 rc = regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
120 PCF85063_REG_CTRL1_STOP,
121 PCF85063_REG_CTRL1_STOP);
122 if (rc)
123 return rc;
124
125 /* hours, minutes and seconds */
126 regs[0] = bin2bcd(tm->tm_sec) & 0x7F; /* clear OS flag */
127
128 regs[1] = bin2bcd(tm->tm_min);
129 regs[2] = bin2bcd(tm->tm_hour);
130
131 /* Day of month, 1 - 31 */
132 regs[3] = bin2bcd(tm->tm_mday);
133
134 /* Day, 0 - 6 */
135 regs[4] = tm->tm_wday & 0x07;
136
137 /* month, 1 - 12 */
138 regs[5] = bin2bcd(tm->tm_mon + 1);
139
140 /* year and century */
141 regs[6] = bin2bcd(tm->tm_year - 100);
142
143 /* write all registers at once */
144 rc = regmap_bulk_write(pcf85063->regmap, PCF85063_REG_SC,
145 regs, sizeof(regs));
146 if (rc)
147 return rc;
148
149 /*
150 * Write the control register as a separate action since the size of
151 * the register space is different between the PCF85063TP and
152 * PCF85063A devices. The rollover point can not be used.
153 */
154 return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
155 PCF85063_REG_CTRL1_STOP, 0);
156}
157
158static int pcf85063_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
159{
160 struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
161 u8 buf[4];
162 unsigned int val;
163 int ret;
164
165 ret = regmap_bulk_read(pcf85063->regmap, PCF85063_REG_ALM_S,
166 buf, sizeof(buf));
167 if (ret)
168 return ret;
169
170 alrm->time.tm_sec = bcd2bin(buf[0]);
171 alrm->time.tm_min = bcd2bin(buf[1]);
172 alrm->time.tm_hour = bcd2bin(buf[2]);
173 alrm->time.tm_mday = bcd2bin(buf[3]);
174
175 ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &val);
176 if (ret)
177 return ret;
178
179 alrm->enabled = !!(val & PCF85063_CTRL2_AIE);
180
181 return 0;
182}
183
184static int pcf85063_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
185{
186 struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
187 u8 buf[5];
188 int ret;
189
190 buf[0] = bin2bcd(alrm->time.tm_sec);
191 buf[1] = bin2bcd(alrm->time.tm_min);
192 buf[2] = bin2bcd(alrm->time.tm_hour);
193 buf[3] = bin2bcd(alrm->time.tm_mday);
194 buf[4] = PCF85063_AEN; /* Do not match on week day */
195
196 ret = regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
197 PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF, 0);
198 if (ret)
199 return ret;
200
201 ret = regmap_bulk_write(pcf85063->regmap, PCF85063_REG_ALM_S,
202 buf, sizeof(buf));
203 if (ret)
204 return ret;
205
206 return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
207 PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF,
208 alrm->enabled ? PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF : PCF85063_CTRL2_AF);
209}
210
211static int pcf85063_rtc_alarm_irq_enable(struct device *dev,
212 unsigned int enabled)
213{
214 struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
215
216 return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
217 PCF85063_CTRL2_AIE,
218 enabled ? PCF85063_CTRL2_AIE : 0);
219}
220
221static irqreturn_t pcf85063_rtc_handle_irq(int irq, void *dev_id)
222{
223 struct pcf85063 *pcf85063 = dev_id;
224 unsigned int val;
225 int err;
226
227 err = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &val);
228 if (err)
229 return IRQ_NONE;
230
231 if (val & PCF85063_CTRL2_AF) {
232 rtc_update_irq(pcf85063->rtc, 1, RTC_IRQF | RTC_AF);
233 regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
234 PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF,
235 0);
236 return IRQ_HANDLED;
237 }
238
239 return IRQ_NONE;
240}
241
242static int pcf85063_read_offset(struct device *dev, long *offset)
243{
244 struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
245 long val;
246 u32 reg;
247 int ret;
248
249 ret = regmap_read(pcf85063->regmap, PCF85063_REG_OFFSET, ®);
250 if (ret < 0)
251 return ret;
252
253 val = sign_extend32(reg & ~PCF85063_OFFSET_MODE,
254 PCF85063_OFFSET_SIGN_BIT);
255
256 if (reg & PCF85063_OFFSET_MODE)
257 *offset = val * PCF85063_OFFSET_STEP1;
258 else
259 *offset = val * PCF85063_OFFSET_STEP0;
260
261 return 0;
262}
263
264static int pcf85063_set_offset(struct device *dev, long offset)
265{
266 struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
267 s8 mode0, mode1, reg;
268 unsigned int error0, error1;
269
270 if (offset > PCF85063_OFFSET_STEP0 * 63)
271 return -ERANGE;
272 if (offset < PCF85063_OFFSET_STEP0 * -64)
273 return -ERANGE;
274
275 mode0 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP0);
276 mode1 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP1);
277
278 error0 = abs(offset - (mode0 * PCF85063_OFFSET_STEP0));
279 error1 = abs(offset - (mode1 * PCF85063_OFFSET_STEP1));
280 if (mode1 > 63 || mode1 < -64 || error0 < error1)
281 reg = mode0 & ~PCF85063_OFFSET_MODE;
282 else
283 reg = mode1 | PCF85063_OFFSET_MODE;
284
285 return regmap_write(pcf85063->regmap, PCF85063_REG_OFFSET, reg);
286}
287
288static int pcf85063_ioctl(struct device *dev, unsigned int cmd,
289 unsigned long arg)
290{
291 struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
292 int status, ret = 0;
293
294 switch (cmd) {
295 case RTC_VL_READ:
296 ret = regmap_read(pcf85063->regmap, PCF85063_REG_SC, &status);
297 if (ret < 0)
298 return ret;
299
300 status = status & PCF85063_REG_SC_OS ? RTC_VL_DATA_INVALID : 0;
301
302 return put_user(status, (unsigned int __user *)arg);
303
304 default:
305 return -ENOIOCTLCMD;
306 }
307}
308
309static const struct rtc_class_ops pcf85063_rtc_ops = {
310 .read_time = pcf85063_rtc_read_time,
311 .set_time = pcf85063_rtc_set_time,
312 .read_offset = pcf85063_read_offset,
313 .set_offset = pcf85063_set_offset,
314 .ioctl = pcf85063_ioctl,
315};
316
317static const struct rtc_class_ops pcf85063_rtc_ops_alarm = {
318 .read_time = pcf85063_rtc_read_time,
319 .set_time = pcf85063_rtc_set_time,
320 .read_offset = pcf85063_read_offset,
321 .set_offset = pcf85063_set_offset,
322 .read_alarm = pcf85063_rtc_read_alarm,
323 .set_alarm = pcf85063_rtc_set_alarm,
324 .alarm_irq_enable = pcf85063_rtc_alarm_irq_enable,
325 .ioctl = pcf85063_ioctl,
326};
327
328static int pcf85063_nvmem_read(void *priv, unsigned int offset,
329 void *val, size_t bytes)
330{
331 return regmap_read(priv, PCF85063_REG_RAM, val);
332}
333
334static int pcf85063_nvmem_write(void *priv, unsigned int offset,
335 void *val, size_t bytes)
336{
337 return regmap_write(priv, PCF85063_REG_RAM, *(u8 *)val);
338}
339
340static int pcf85063_load_capacitance(struct pcf85063 *pcf85063,
341 const struct device_node *np,
342 unsigned int force_cap)
343{
344 u32 load = 7000;
345 u8 reg = 0;
346
347 if (force_cap)
348 load = force_cap;
349 else
350 of_property_read_u32(np, "quartz-load-femtofarads", &load);
351
352 switch (load) {
353 default:
354 dev_warn(&pcf85063->rtc->dev, "Unknown quartz-load-femtofarads value: %d. Assuming 7000",
355 load);
356 fallthrough;
357 case 7000:
358 break;
359 case 12500:
360 reg = PCF85063_REG_CTRL1_CAP_SEL;
361 break;
362 }
363
364 return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
365 PCF85063_REG_CTRL1_CAP_SEL, reg);
366}
367
368#ifdef CONFIG_COMMON_CLK
369/*
370 * Handling of the clkout
371 */
372
373#define clkout_hw_to_pcf85063(_hw) container_of(_hw, struct pcf85063, clkout_hw)
374
375static int clkout_rates[] = {
376 32768,
377 16384,
378 8192,
379 4096,
380 2048,
381 1024,
382 1,
383 0
384};
385
386static unsigned long pcf85063_clkout_recalc_rate(struct clk_hw *hw,
387 unsigned long parent_rate)
388{
389 struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
390 unsigned int buf;
391 int ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &buf);
392
393 if (ret < 0)
394 return 0;
395
396 buf &= PCF85063_REG_CLKO_F_MASK;
397 return clkout_rates[buf];
398}
399
400static long pcf85063_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
401 unsigned long *prate)
402{
403 int i;
404
405 for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
406 if (clkout_rates[i] <= rate)
407 return clkout_rates[i];
408
409 return 0;
410}
411
412static int pcf85063_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
413 unsigned long parent_rate)
414{
415 struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
416 int i;
417
418 for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
419 if (clkout_rates[i] == rate)
420 return regmap_update_bits(pcf85063->regmap,
421 PCF85063_REG_CTRL2,
422 PCF85063_REG_CLKO_F_MASK, i);
423
424 return -EINVAL;
425}
426
427static int pcf85063_clkout_control(struct clk_hw *hw, bool enable)
428{
429 struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
430 unsigned int buf;
431 int ret;
432
433 ret = regmap_read(pcf85063->regmap, PCF85063_REG_OFFSET, &buf);
434 if (ret < 0)
435 return ret;
436 buf &= PCF85063_REG_CLKO_F_MASK;
437
438 if (enable) {
439 if (buf == PCF85063_REG_CLKO_F_OFF)
440 buf = PCF85063_REG_CLKO_F_32768HZ;
441 else
442 return 0;
443 } else {
444 if (buf != PCF85063_REG_CLKO_F_OFF)
445 buf = PCF85063_REG_CLKO_F_OFF;
446 else
447 return 0;
448 }
449
450 return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
451 PCF85063_REG_CLKO_F_MASK, buf);
452}
453
454static int pcf85063_clkout_prepare(struct clk_hw *hw)
455{
456 return pcf85063_clkout_control(hw, 1);
457}
458
459static void pcf85063_clkout_unprepare(struct clk_hw *hw)
460{
461 pcf85063_clkout_control(hw, 0);
462}
463
464static int pcf85063_clkout_is_prepared(struct clk_hw *hw)
465{
466 struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
467 unsigned int buf;
468 int ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &buf);
469
470 if (ret < 0)
471 return 0;
472
473 return (buf & PCF85063_REG_CLKO_F_MASK) != PCF85063_REG_CLKO_F_OFF;
474}
475
476static const struct clk_ops pcf85063_clkout_ops = {
477 .prepare = pcf85063_clkout_prepare,
478 .unprepare = pcf85063_clkout_unprepare,
479 .is_prepared = pcf85063_clkout_is_prepared,
480 .recalc_rate = pcf85063_clkout_recalc_rate,
481 .round_rate = pcf85063_clkout_round_rate,
482 .set_rate = pcf85063_clkout_set_rate,
483};
484
485static struct clk *pcf85063_clkout_register_clk(struct pcf85063 *pcf85063)
486{
487 struct clk *clk;
488 struct clk_init_data init;
489
490 init.name = "pcf85063-clkout";
491 init.ops = &pcf85063_clkout_ops;
492 init.flags = 0;
493 init.parent_names = NULL;
494 init.num_parents = 0;
495 pcf85063->clkout_hw.init = &init;
496
497 /* optional override of the clockname */
498 of_property_read_string(pcf85063->rtc->dev.of_node,
499 "clock-output-names", &init.name);
500
501 /* register the clock */
502 clk = devm_clk_register(&pcf85063->rtc->dev, &pcf85063->clkout_hw);
503
504 if (!IS_ERR(clk))
505 of_clk_add_provider(pcf85063->rtc->dev.of_node,
506 of_clk_src_simple_get, clk);
507
508 return clk;
509}
510#endif
511
512static const struct pcf85063_config pcf85063a_config = {
513 .regmap = {
514 .reg_bits = 8,
515 .val_bits = 8,
516 .max_register = 0x11,
517 },
518 .has_alarms = 1,
519};
520
521static const struct pcf85063_config pcf85063tp_config = {
522 .regmap = {
523 .reg_bits = 8,
524 .val_bits = 8,
525 .max_register = 0x0a,
526 },
527};
528
529static const struct pcf85063_config rv8263_config = {
530 .regmap = {
531 .reg_bits = 8,
532 .val_bits = 8,
533 .max_register = 0x11,
534 },
535 .has_alarms = 1,
536 .force_cap_7000 = 1,
537};
538
539static int pcf85063_probe(struct i2c_client *client)
540{
541 struct pcf85063 *pcf85063;
542 unsigned int tmp;
543 int err;
544 const struct pcf85063_config *config = &pcf85063tp_config;
545 const void *data = of_device_get_match_data(&client->dev);
546 struct nvmem_config nvmem_cfg = {
547 .name = "pcf85063_nvram",
548 .reg_read = pcf85063_nvmem_read,
549 .reg_write = pcf85063_nvmem_write,
550 .type = NVMEM_TYPE_BATTERY_BACKED,
551 .size = 1,
552 };
553
554 dev_dbg(&client->dev, "%s\n", __func__);
555
556 pcf85063 = devm_kzalloc(&client->dev, sizeof(struct pcf85063),
557 GFP_KERNEL);
558 if (!pcf85063)
559 return -ENOMEM;
560
561 if (data)
562 config = data;
563
564 pcf85063->regmap = devm_regmap_init_i2c(client, &config->regmap);
565 if (IS_ERR(pcf85063->regmap))
566 return PTR_ERR(pcf85063->regmap);
567
568 i2c_set_clientdata(client, pcf85063);
569
570 err = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL1, &tmp);
571 if (err) {
572 dev_err(&client->dev, "RTC chip is not present\n");
573 return err;
574 }
575
576 pcf85063->rtc = devm_rtc_allocate_device(&client->dev);
577 if (IS_ERR(pcf85063->rtc))
578 return PTR_ERR(pcf85063->rtc);
579
580 err = pcf85063_load_capacitance(pcf85063, client->dev.of_node,
581 config->force_cap_7000 ? 7000 : 0);
582 if (err < 0)
583 dev_warn(&client->dev, "failed to set xtal load capacitance: %d",
584 err);
585
586 pcf85063->rtc->ops = &pcf85063_rtc_ops;
587 pcf85063->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
588 pcf85063->rtc->range_max = RTC_TIMESTAMP_END_2099;
589 pcf85063->rtc->uie_unsupported = 1;
590
591 if (config->has_alarms && client->irq > 0) {
592 err = devm_request_threaded_irq(&client->dev, client->irq,
593 NULL, pcf85063_rtc_handle_irq,
594 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
595 "pcf85063", pcf85063);
596 if (err) {
597 dev_warn(&pcf85063->rtc->dev,
598 "unable to request IRQ, alarms disabled\n");
599 } else {
600 pcf85063->rtc->ops = &pcf85063_rtc_ops_alarm;
601 device_init_wakeup(&client->dev, true);
602 err = dev_pm_set_wake_irq(&client->dev, client->irq);
603 if (err)
604 dev_err(&pcf85063->rtc->dev,
605 "failed to enable irq wake\n");
606 }
607 }
608
609 nvmem_cfg.priv = pcf85063->regmap;
610 rtc_nvmem_register(pcf85063->rtc, &nvmem_cfg);
611
612#ifdef CONFIG_COMMON_CLK
613 /* register clk in common clk framework */
614 pcf85063_clkout_register_clk(pcf85063);
615#endif
616
617 return rtc_register_device(pcf85063->rtc);
618}
619
620#ifdef CONFIG_OF
621static const struct of_device_id pcf85063_of_match[] = {
622 { .compatible = "nxp,pcf85063", .data = &pcf85063tp_config },
623 { .compatible = "nxp,pcf85063tp", .data = &pcf85063tp_config },
624 { .compatible = "nxp,pcf85063a", .data = &pcf85063a_config },
625 { .compatible = "microcrystal,rv8263", .data = &rv8263_config },
626 {}
627};
628MODULE_DEVICE_TABLE(of, pcf85063_of_match);
629#endif
630
631static struct i2c_driver pcf85063_driver = {
632 .driver = {
633 .name = "rtc-pcf85063",
634 .of_match_table = of_match_ptr(pcf85063_of_match),
635 },
636 .probe_new = pcf85063_probe,
637};
638
639module_i2c_driver(pcf85063_driver);
640
641MODULE_AUTHOR("Søren Andersen <san@rosetechnology.dk>");
642MODULE_DESCRIPTION("PCF85063 RTC driver");
643MODULE_LICENSE("GPL");