1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * drivers/i2c/busses/i2c-ibm_iic.c
  4 *
  5 * Support for the IIC peripheral on IBM PPC 4xx
  6 *
  7 * Copyright (c) 2003, 2004 Zultys Technologies.
  8 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
  9 *
 10 * Copyright (c) 2008 PIKA Technologies
 11 * Sean MacLennan <smaclennan@pikatech.com>
 12 *
 13 * Based on original work by
 14 * 	Ian DaSilva  <idasilva@mvista.com>
 15 *      Armin Kuster <akuster@mvista.com>
 16 * 	Matt Porter  <mporter@mvista.com>
 17 *
 18 *      Copyright 2000-2003 MontaVista Software Inc.
 19 *
 20 * Original driver version was highly leveraged from i2c-elektor.c
 21 *
 22 *   	Copyright 1995-97 Simon G. Vogl
 23 *                1998-99 Hans Berglund
 24 *
 25 *   	With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi>
 26 *	and even Frodo Looijaard <frodol@dds.nl>
 27 */
 28
 29#include <linux/module.h>
 30#include <linux/kernel.h>
 31#include <linux/ioport.h>
 32#include <linux/delay.h>
 33#include <linux/slab.h>
 34#include <linux/interrupt.h>
 35#include <linux/sched/signal.h>
 36
 37#include <asm/irq.h>
 38#include <linux/io.h>
 39#include <linux/i2c.h>
 40#include <linux/of_address.h>
 41#include <linux/of_irq.h>
 42#include <linux/of_platform.h>
 43
 44#include "i2c-ibm_iic.h"
 45
 46#define DRIVER_VERSION "2.2"
 47
 48MODULE_DESCRIPTION("IBM IIC driver v" DRIVER_VERSION);
 49MODULE_LICENSE("GPL");
 50
 51static bool iic_force_poll;
 52module_param(iic_force_poll, bool, 0);
 53MODULE_PARM_DESC(iic_force_poll, "Force polling mode");
 54
 55static bool iic_force_fast;
 56module_param(iic_force_fast, bool, 0);
 57MODULE_PARM_DESC(iic_force_fast, "Force fast mode (400 kHz)");
 58
 59#define DBG_LEVEL 0
 60
 61#ifdef DBG
 62#undef DBG
 63#endif
 64
 65#ifdef DBG2
 66#undef DBG2
 67#endif
 68
 69#if DBG_LEVEL > 0
 70#  define DBG(f,x...)	printk(KERN_DEBUG "ibm-iic" f, ##x)
 71#else
 72#  define DBG(f,x...)	((void)0)
 73#endif
 74#if DBG_LEVEL > 1
 75#  define DBG2(f,x...) 	DBG(f, ##x)
 76#else
 77#  define DBG2(f,x...) 	((void)0)
 78#endif
 79#if DBG_LEVEL > 2
 80static void dump_iic_regs(const char* header, struct ibm_iic_private* dev)
 81{
 82	volatile struct iic_regs __iomem *iic = dev->vaddr;
 83	printk(KERN_DEBUG "ibm-iic%d: %s\n", dev->idx, header);
 84	printk(KERN_DEBUG
 85	       "  cntl     = 0x%02x, mdcntl = 0x%02x\n"
 86	       "  sts      = 0x%02x, extsts = 0x%02x\n"
 87	       "  clkdiv   = 0x%02x, xfrcnt = 0x%02x\n"
 88	       "  xtcntlss = 0x%02x, directcntl = 0x%02x\n",
 89		in_8(&iic->cntl), in_8(&iic->mdcntl), in_8(&iic->sts),
 90		in_8(&iic->extsts), in_8(&iic->clkdiv), in_8(&iic->xfrcnt),
 91		in_8(&iic->xtcntlss), in_8(&iic->directcntl));
 92}
 93#  define DUMP_REGS(h,dev)	dump_iic_regs((h),(dev))
 94#else
 95#  define DUMP_REGS(h,dev)	((void)0)
 96#endif
 97
 98/* Bus timings (in ns) for bit-banging */
 99static struct ibm_iic_timings {
100	unsigned int hd_sta;
101	unsigned int su_sto;
102	unsigned int low;
103	unsigned int high;
104	unsigned int buf;
105} timings [] = {
106/* Standard mode (100 KHz) */
107{
108	.hd_sta	= 4000,
109	.su_sto	= 4000,
110	.low	= 4700,
111	.high	= 4000,
112	.buf	= 4700,
113},
114/* Fast mode (400 KHz) */
115{
116	.hd_sta = 600,
117	.su_sto	= 600,
118	.low 	= 1300,
119	.high 	= 600,
120	.buf	= 1300,
121}};
122
123/* Enable/disable interrupt generation */
124static inline void iic_interrupt_mode(struct ibm_iic_private* dev, int enable)
125{
126	out_8(&dev->vaddr->intmsk, enable ? INTRMSK_EIMTC : 0);
127}
128
129/*
130 * Initialize IIC interface.
131 */
132static void iic_dev_init(struct ibm_iic_private* dev)
133{
134	volatile struct iic_regs __iomem *iic = dev->vaddr;
135
136	DBG("%d: init\n", dev->idx);
137
138	/* Clear master address */
139	out_8(&iic->lmadr, 0);
140	out_8(&iic->hmadr, 0);
141
142	/* Clear slave address */
143	out_8(&iic->lsadr, 0);
144	out_8(&iic->hsadr, 0);
145
146	/* Clear status & extended status */
147	out_8(&iic->sts, STS_SCMP | STS_IRQA);
148	out_8(&iic->extsts, EXTSTS_IRQP | EXTSTS_IRQD | EXTSTS_LA
149			    | EXTSTS_ICT | EXTSTS_XFRA);
150
151	/* Set clock divider */
152	out_8(&iic->clkdiv, dev->clckdiv);
153
154	/* Clear transfer count */
155	out_8(&iic->xfrcnt, 0);
156
157	/* Clear extended control and status */
158	out_8(&iic->xtcntlss, XTCNTLSS_SRC | XTCNTLSS_SRS | XTCNTLSS_SWC
159			    | XTCNTLSS_SWS);
160
161	/* Clear control register */
162	out_8(&iic->cntl, 0);
163
164	/* Enable interrupts if possible */
165	iic_interrupt_mode(dev, dev->irq >= 0);
166
167	/* Set mode control */
168	out_8(&iic->mdcntl, MDCNTL_FMDB | MDCNTL_EINT | MDCNTL_EUBS
169			    | (dev->fast_mode ? MDCNTL_FSM : 0));
170
171	DUMP_REGS("iic_init", dev);
172}
173
174/*
175 * Reset IIC interface
176 */
177static void iic_dev_reset(struct ibm_iic_private* dev)
178{
179	volatile struct iic_regs __iomem *iic = dev->vaddr;
180	int i;
181	u8 dc;
182
183	DBG("%d: soft reset\n", dev->idx);
184	DUMP_REGS("reset", dev);
185
186    	/* Place chip in the reset state */
187	out_8(&iic->xtcntlss, XTCNTLSS_SRST);
188
189	/* Check if bus is free */
190	dc = in_8(&iic->directcntl);
191	if (!DIRCTNL_FREE(dc)){
192		DBG("%d: trying to regain bus control\n", dev->idx);
193
194		/* Try to set bus free state */
195		out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
196
197		/* Wait until we regain bus control */
198		for (i = 0; i < 100; ++i){
199			dc = in_8(&iic->directcntl);
200			if (DIRCTNL_FREE(dc))
201				break;
202
203			/* Toggle SCL line */
204			dc ^= DIRCNTL_SCC;
205			out_8(&iic->directcntl, dc);
206			udelay(10);
207			dc ^= DIRCNTL_SCC;
208			out_8(&iic->directcntl, dc);
209
210			/* be nice */
211			cond_resched();
212		}
213	}
214
215	/* Remove reset */
216	out_8(&iic->xtcntlss, 0);
217
218	/* Reinitialize interface */
219	iic_dev_init(dev);
220}
221
222/*
223 * Do 0-length transaction using bit-banging through IIC_DIRECTCNTL register.
224 */
225
226/* Wait for SCL and/or SDA to be high */
227static int iic_dc_wait(volatile struct iic_regs __iomem *iic, u8 mask)
228{
229	unsigned long x = jiffies + HZ / 28 + 2;
230	while ((in_8(&iic->directcntl) & mask) != mask){
231		if (unlikely(time_after(jiffies, x)))
232			return -1;
233		cond_resched();
234	}
235	return 0;
236}
237
238static int iic_smbus_quick(struct ibm_iic_private* dev, const struct i2c_msg* p)
239{
240	volatile struct iic_regs __iomem *iic = dev->vaddr;
241	const struct ibm_iic_timings *t = &timings[dev->fast_mode ? 1 : 0];
242	u8 mask, v, sda;
243	int i, res;
244
245	/* Only 7-bit addresses are supported */
246	if (unlikely(p->flags & I2C_M_TEN)){
247		DBG("%d: smbus_quick - 10 bit addresses are not supported\n",
248			dev->idx);
249		return -EINVAL;
250	}
251
252	DBG("%d: smbus_quick(0x%02x)\n", dev->idx, p->addr);
253
254	/* Reset IIC interface */
255	out_8(&iic->xtcntlss, XTCNTLSS_SRST);
256
257	/* Wait for bus to become free */
258	out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
259	if (unlikely(iic_dc_wait(iic, DIRCNTL_MSDA | DIRCNTL_MSC)))
260		goto err;
261	ndelay(t->buf);
262
263	/* START */
264	out_8(&iic->directcntl, DIRCNTL_SCC);
265	sda = 0;
266	ndelay(t->hd_sta);
267
268	/* Send address */
269	v = i2c_8bit_addr_from_msg(p);
270	for (i = 0, mask = 0x80; i < 8; ++i, mask >>= 1){
271		out_8(&iic->directcntl, sda);
272		ndelay(t->low / 2);
273		sda = (v & mask) ? DIRCNTL_SDAC : 0;
274		out_8(&iic->directcntl, sda);
275		ndelay(t->low / 2);
276
277		out_8(&iic->directcntl, DIRCNTL_SCC | sda);
278		if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC)))
279			goto err;
280		ndelay(t->high);
281	}
282
283	/* ACK */
284	out_8(&iic->directcntl, sda);
285	ndelay(t->low / 2);
286	out_8(&iic->directcntl, DIRCNTL_SDAC);
287	ndelay(t->low / 2);
288	out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
289	if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC)))
290		goto err;
291	res = (in_8(&iic->directcntl) & DIRCNTL_MSDA) ? -EREMOTEIO : 1;
292	ndelay(t->high);
293
294	/* STOP */
295	out_8(&iic->directcntl, 0);
296	ndelay(t->low);
297	out_8(&iic->directcntl, DIRCNTL_SCC);
298	if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC)))
299		goto err;
300	ndelay(t->su_sto);
301	out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
302
303	ndelay(t->buf);
304
305	DBG("%d: smbus_quick -> %s\n", dev->idx, res ? "NACK" : "ACK");
306out:
307	/* Remove reset */
308	out_8(&iic->xtcntlss, 0);
309
310	/* Reinitialize interface */
311	iic_dev_init(dev);
312
313	return res;
314err:
315	DBG("%d: smbus_quick - bus is stuck\n", dev->idx);
316	res = -EREMOTEIO;
317	goto out;
318}
319
320/*
321 * IIC interrupt handler
322 */
323static irqreturn_t iic_handler(int irq, void *dev_id)
324{
325	struct ibm_iic_private* dev = (struct ibm_iic_private*)dev_id;
326	volatile struct iic_regs __iomem *iic = dev->vaddr;
327
328	DBG2("%d: irq handler, STS = 0x%02x, EXTSTS = 0x%02x\n",
329	     dev->idx, in_8(&iic->sts), in_8(&iic->extsts));
330
331	/* Acknowledge IRQ and wakeup iic_wait_for_tc */
332	out_8(&iic->sts, STS_IRQA | STS_SCMP);
333	wake_up_interruptible(&dev->wq);
334
335	return IRQ_HANDLED;
336}
337
338/*
339 * Get master transfer result and clear errors if any.
340 * Returns the number of actually transferred bytes or error (<0)
341 */
342static int iic_xfer_result(struct ibm_iic_private* dev)
343{
344	volatile struct iic_regs __iomem *iic = dev->vaddr;
345
346	if (unlikely(in_8(&iic->sts) & STS_ERR)){
347		DBG("%d: xfer error, EXTSTS = 0x%02x\n", dev->idx,
348			in_8(&iic->extsts));
349
350		/* Clear errors and possible pending IRQs */
351		out_8(&iic->extsts, EXTSTS_IRQP | EXTSTS_IRQD |
352			EXTSTS_LA | EXTSTS_ICT | EXTSTS_XFRA);
353
354		/* Flush master data buffer */
355		out_8(&iic->mdcntl, in_8(&iic->mdcntl) | MDCNTL_FMDB);
356
357		/* Is bus free?
358		 * If error happened during combined xfer
359		 * IIC interface is usually stuck in some strange
360		 * state, the only way out - soft reset.
361		 */
362		if ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){
363			DBG("%d: bus is stuck, resetting\n", dev->idx);
364			iic_dev_reset(dev);
365		}
366		return -EREMOTEIO;
367	}
368	else
369		return in_8(&iic->xfrcnt) & XFRCNT_MTC_MASK;
370}
371
372/*
373 * Try to abort active transfer.
374 */
375static void iic_abort_xfer(struct ibm_iic_private* dev)
376{
377	volatile struct iic_regs __iomem *iic = dev->vaddr;
378	unsigned long x;
379
380	DBG("%d: iic_abort_xfer\n", dev->idx);
381
382	out_8(&iic->cntl, CNTL_HMT);
383
384	/*
385	 * Wait for the abort command to complete.
386	 * It's not worth to be optimized, just poll (timeout >= 1 tick)
387	 */
388	x = jiffies + 2;
389	while ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){
390		if (time_after(jiffies, x)){
391			DBG("%d: abort timeout, resetting...\n", dev->idx);
392			iic_dev_reset(dev);
393			return;
394		}
395		schedule();
396	}
397
398	/* Just to clear errors */
399	iic_xfer_result(dev);
400}
401
402/*
403 * Wait for master transfer to complete.
404 * It puts current process to sleep until we get interrupt or timeout expires.
405 * Returns the number of transferred bytes or error (<0)
406 */
407static int iic_wait_for_tc(struct ibm_iic_private* dev){
408
409	volatile struct iic_regs __iomem *iic = dev->vaddr;
410	int ret = 0;
411
412	if (dev->irq >= 0){
413		/* Interrupt mode */
414		ret = wait_event_interruptible_timeout(dev->wq,
415			!(in_8(&iic->sts) & STS_PT), dev->adap.timeout);
416
417		if (unlikely(ret < 0))
418			DBG("%d: wait interrupted\n", dev->idx);
419		else if (unlikely(in_8(&iic->sts) & STS_PT)){
420			DBG("%d: wait timeout\n", dev->idx);
421			ret = -ETIMEDOUT;
422		}
423	}
424	else {
425		/* Polling mode */
426		unsigned long x = jiffies + dev->adap.timeout;
427
428		while (in_8(&iic->sts) & STS_PT){
429			if (unlikely(time_after(jiffies, x))){
430				DBG("%d: poll timeout\n", dev->idx);
431				ret = -ETIMEDOUT;
432				break;
433			}
434
435			if (signal_pending(current)){
436				DBG("%d: poll interrupted\n", dev->idx);
437				ret = -ERESTARTSYS;
438				break;
439			}
440			schedule();
441		}
442	}
443
444	if (unlikely(ret < 0))
445		iic_abort_xfer(dev);
446	else
447		ret = iic_xfer_result(dev);
448
449	DBG2("%d: iic_wait_for_tc -> %d\n", dev->idx, ret);
450
451	return ret;
452}
453
454/*
455 * Low level master transfer routine
456 */
457static int iic_xfer_bytes(struct ibm_iic_private* dev, struct i2c_msg* pm,
458			  int combined_xfer)
459{
460	volatile struct iic_regs __iomem *iic = dev->vaddr;
461	char* buf = pm->buf;
462	int i, j, loops, ret = 0;
463	int len = pm->len;
464
465	u8 cntl = (in_8(&iic->cntl) & CNTL_AMD) | CNTL_PT;
466	if (pm->flags & I2C_M_RD)
467		cntl |= CNTL_RW;
468
469	loops = (len + 3) / 4;
470	for (i = 0; i < loops; ++i, len -= 4){
471		int count = len > 4 ? 4 : len;
472		u8 cmd = cntl | ((count - 1) << CNTL_TCT_SHIFT);
473
474		if (!(cntl & CNTL_RW))
475			for (j = 0; j < count; ++j)
476				out_8((void __iomem *)&iic->mdbuf, *buf++);
477
478		if (i < loops - 1)
479			cmd |= CNTL_CHT;
480		else if (combined_xfer)
481			cmd |= CNTL_RPST;
482
483		DBG2("%d: xfer_bytes, %d, CNTL = 0x%02x\n", dev->idx, count, cmd);
484
485		/* Start transfer */
486		out_8(&iic->cntl, cmd);
487
488		/* Wait for completion */
489		ret = iic_wait_for_tc(dev);
490
491		if (unlikely(ret < 0))
492			break;
493		else if (unlikely(ret != count)){
494			DBG("%d: xfer_bytes, requested %d, transferred %d\n",
495				dev->idx, count, ret);
496
497			/* If it's not a last part of xfer, abort it */
498			if (combined_xfer || (i < loops - 1))
499    				iic_abort_xfer(dev);
500
501			ret = -EREMOTEIO;
502			break;
503		}
504
505		if (cntl & CNTL_RW)
506			for (j = 0; j < count; ++j)
507				*buf++ = in_8((void __iomem *)&iic->mdbuf);
508	}
509
510	return ret > 0 ? 0 : ret;
511}
512
513/*
514 * Set target slave address for master transfer
515 */
516static inline void iic_address(struct ibm_iic_private* dev, struct i2c_msg* msg)
517{
518	volatile struct iic_regs __iomem *iic = dev->vaddr;
519	u16 addr = msg->addr;
520
521	DBG2("%d: iic_address, 0x%03x (%d-bit)\n", dev->idx,
522		addr, msg->flags & I2C_M_TEN ? 10 : 7);
523
524	if (msg->flags & I2C_M_TEN){
525	    out_8(&iic->cntl, CNTL_AMD);
526	    out_8(&iic->lmadr, addr);
527	    out_8(&iic->hmadr, 0xf0 | ((addr >> 7) & 0x06));
528	}
529	else {
530	    out_8(&iic->cntl, 0);
531	    out_8(&iic->lmadr, addr << 1);
532	}
533}
534
535static inline int iic_invalid_address(const struct i2c_msg* p)
536{
537	return (p->addr > 0x3ff) || (!(p->flags & I2C_M_TEN) && (p->addr > 0x7f));
538}
539
540static inline int iic_address_neq(const struct i2c_msg* p1,
541				  const struct i2c_msg* p2)
542{
543	return (p1->addr != p2->addr)
544		|| ((p1->flags & I2C_M_TEN) != (p2->flags & I2C_M_TEN));
545}
546
547/*
548 * Generic master transfer entrypoint.
549 * Returns the number of processed messages or error (<0)
550 */
551static int iic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
552{
553    	struct ibm_iic_private* dev = (struct ibm_iic_private*)(i2c_get_adapdata(adap));
554	volatile struct iic_regs __iomem *iic = dev->vaddr;
555	int i, ret = 0;
556
557	DBG2("%d: iic_xfer, %d msg(s)\n", dev->idx, num);
558
559	/* Check the sanity of the passed messages.
560	 * Uhh, generic i2c layer is more suitable place for such code...
561	 */
562	if (unlikely(iic_invalid_address(&msgs[0]))){
563		DBG("%d: invalid address 0x%03x (%d-bit)\n", dev->idx,
564			msgs[0].addr, msgs[0].flags & I2C_M_TEN ? 10 : 7);
565		return -EINVAL;
566	}
567	for (i = 0; i < num; ++i){
568		if (unlikely(msgs[i].len <= 0)){
569			if (num == 1 && !msgs[0].len){
570				/* Special case for I2C_SMBUS_QUICK emulation.
571				 * IBM IIC doesn't support 0-length transactions
572				 * so we have to emulate them using bit-banging.
573				 */
574				return iic_smbus_quick(dev, &msgs[0]);
575			}
576			DBG("%d: invalid len %d in msg[%d]\n", dev->idx,
577				msgs[i].len, i);
578			return -EINVAL;
579		}
580		if (unlikely(iic_address_neq(&msgs[0], &msgs[i]))){
581			DBG("%d: invalid addr in msg[%d]\n", dev->idx, i);
582			return -EINVAL;
583		}
584	}
585
586	/* Check bus state */
587	if (unlikely((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE)){
588		DBG("%d: iic_xfer, bus is not free\n", dev->idx);
589
590		/* Usually it means something serious has happened.
591		 * We *cannot* have unfinished previous transfer
592		 * so it doesn't make any sense to try to stop it.
593		 * Probably we were not able to recover from the
594		 * previous error.
595		 * The only *reasonable* thing I can think of here
596		 * is soft reset.  --ebs
597		 */
598		iic_dev_reset(dev);
599
600		if ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){
601			DBG("%d: iic_xfer, bus is still not free\n", dev->idx);
602			return -EREMOTEIO;
603		}
604	}
605	else {
606		/* Flush master data buffer (just in case) */
607		out_8(&iic->mdcntl, in_8(&iic->mdcntl) | MDCNTL_FMDB);
608	}
609
610	/* Load slave address */
611	iic_address(dev, &msgs[0]);
612
613	/* Do real transfer */
614    	for (i = 0; i < num && !ret; ++i)
615		ret = iic_xfer_bytes(dev, &msgs[i], i < num - 1);
616
617	return ret < 0 ? ret : num;
618}
619
620static u32 iic_func(struct i2c_adapter *adap)
621{
622	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
623}
624
625static const struct i2c_algorithm iic_algo = {
626	.master_xfer 	= iic_xfer,
627	.functionality	= iic_func
628};
629
630/*
631 * Calculates IICx_CLCKDIV value for a specific OPB clock frequency
632 */
633static inline u8 iic_clckdiv(unsigned int opb)
634{
635	/* Compatibility kludge, should go away after all cards
636	 * are fixed to fill correct value for opbfreq.
637	 * Previous driver version used hardcoded divider value 4,
638	 * it corresponds to OPB frequency from the range (40, 50] MHz
639	 */
640	if (!opb){
641		printk(KERN_WARNING "ibm-iic: using compatibility value for OPB freq,"
642			" fix your board specific setup\n");
643		opb = 50000000;
644	}
645
646	/* Convert to MHz */
647	opb /= 1000000;
648
649	if (opb < 20 || opb > 150){
650		printk(KERN_WARNING "ibm-iic: invalid OPB clock frequency %u MHz\n",
651			opb);
652		opb = opb < 20 ? 20 : 150;
653	}
654	return (u8)((opb + 9) / 10 - 1);
655}
656
657static int iic_request_irq(struct platform_device *ofdev,
658				     struct ibm_iic_private *dev)
659{
660	struct device_node *np = ofdev->dev.of_node;
661	int irq;
662
663	if (iic_force_poll)
664		return 0;
665
666	irq = irq_of_parse_and_map(np, 0);
667	if (!irq) {
668		dev_err(&ofdev->dev, "irq_of_parse_and_map failed\n");
669		return 0;
670	}
671
672	/* Disable interrupts until we finish initialization, assumes
673	 *  level-sensitive IRQ setup...
674	 */
675	iic_interrupt_mode(dev, 0);
676	if (request_irq(irq, iic_handler, 0, "IBM IIC", dev)) {
677		dev_err(&ofdev->dev, "request_irq %d failed\n", irq);
678		/* Fallback to the polling mode */
679		return 0;
680	}
681
682	return irq;
683}
684
685/*
686 * Register single IIC interface
687 */
688static int iic_probe(struct platform_device *ofdev)
689{
690	struct device_node *np = ofdev->dev.of_node;
691	struct ibm_iic_private *dev;
692	struct i2c_adapter *adap;
693	const u32 *freq;
694	int ret;
695
696	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
697	if (!dev) {
698		dev_err(&ofdev->dev, "failed to allocate device data\n");
699		return -ENOMEM;
700	}
701
702	platform_set_drvdata(ofdev, dev);
703
704	dev->vaddr = of_iomap(np, 0);
705	if (dev->vaddr == NULL) {
706		dev_err(&ofdev->dev, "failed to iomap device\n");
707		ret = -ENXIO;
708		goto error_cleanup;
709	}
710
711	init_waitqueue_head(&dev->wq);
712
713	dev->irq = iic_request_irq(ofdev, dev);
714	if (!dev->irq)
715		dev_warn(&ofdev->dev, "using polling mode\n");
716
717	/* Board specific settings */
718	if (iic_force_fast || of_get_property(np, "fast-mode", NULL))
719		dev->fast_mode = 1;
720
721	freq = of_get_property(np, "clock-frequency", NULL);
722	if (freq == NULL) {
723		freq = of_get_property(np->parent, "clock-frequency", NULL);
724		if (freq == NULL) {
725			dev_err(&ofdev->dev, "Unable to get bus frequency\n");
726			ret = -EINVAL;
727			goto error_cleanup;
728		}
729	}
730
731	dev->clckdiv = iic_clckdiv(*freq);
732	dev_dbg(&ofdev->dev, "clckdiv = %d\n", dev->clckdiv);
733
734	/* Initialize IIC interface */
735	iic_dev_init(dev);
736
737	/* Register it with i2c layer */
738	adap = &dev->adap;
739	adap->dev.parent = &ofdev->dev;
740	adap->dev.of_node = of_node_get(np);
741	strscpy(adap->name, "IBM IIC", sizeof(adap->name));
742	i2c_set_adapdata(adap, dev);
743	adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
744	adap->algo = &iic_algo;
745	adap->timeout = HZ;
746
747	ret = i2c_add_adapter(adap);
748	if (ret  < 0)
749		goto error_cleanup;
750
751	dev_info(&ofdev->dev, "using %s mode\n",
752		 dev->fast_mode ? "fast (400 kHz)" : "standard (100 kHz)");
753
754	return 0;
755
756error_cleanup:
757	if (dev->irq) {
758		iic_interrupt_mode(dev, 0);
759		free_irq(dev->irq, dev);
760	}
761
762	if (dev->vaddr)
763		iounmap(dev->vaddr);
764
765	kfree(dev);
766	return ret;
767}
768
769/*
770 * Cleanup initialized IIC interface
771 */
772static int iic_remove(struct platform_device *ofdev)
773{
774	struct ibm_iic_private *dev = platform_get_drvdata(ofdev);
775
776	i2c_del_adapter(&dev->adap);
777
778	if (dev->irq) {
779		iic_interrupt_mode(dev, 0);
780		free_irq(dev->irq, dev);
781	}
782
783	iounmap(dev->vaddr);
784	kfree(dev);
785
786	return 0;
787}
788
789static const struct of_device_id ibm_iic_match[] = {
790	{ .compatible = "ibm,iic", },
791	{}
792};
793MODULE_DEVICE_TABLE(of, ibm_iic_match);
794
795static struct platform_driver ibm_iic_driver = {
796	.driver = {
797		.name = "ibm-iic",
798		.of_match_table = ibm_iic_match,
799	},
800	.probe	= iic_probe,
801	.remove	= iic_remove,
802};
803
804module_platform_driver(ibm_iic_driver);