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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2019 American Megatrends International LLC.
4 *
5 * Author: Karthikeyan Mani <karthikeyanm@amiindia.co.in>
6 */
7
8#include <linux/bitfield.h>
9#include <linux/clk.h>
10#include <linux/gpio/driver.h>
11#include <linux/hashtable.h>
12#include <linux/init.h>
13#include <linux/io.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/platform_device.h>
17#include <linux/spinlock.h>
18#include <linux/string.h>
19
20#define ASPEED_SGPIO_CTRL 0x54
21
22#define ASPEED_SGPIO_CLK_DIV_MASK GENMASK(31, 16)
23#define ASPEED_SGPIO_ENABLE BIT(0)
24#define ASPEED_SGPIO_PINS_SHIFT 6
25
26struct aspeed_sgpio_pdata {
27 const u32 pin_mask;
28};
29
30struct aspeed_sgpio {
31 struct gpio_chip chip;
32 struct irq_chip intc;
33 struct clk *pclk;
34 raw_spinlock_t lock;
35 void __iomem *base;
36 int irq;
37};
38
39struct aspeed_sgpio_bank {
40 u16 val_regs;
41 u16 rdata_reg;
42 u16 irq_regs;
43 u16 tolerance_regs;
44 const char names[4][3];
45};
46
47/*
48 * Note: The "value" register returns the input value when the GPIO is
49 * configured as an input.
50 *
51 * The "rdata" register returns the output value when the GPIO is
52 * configured as an output.
53 */
54static const struct aspeed_sgpio_bank aspeed_sgpio_banks[] = {
55 {
56 .val_regs = 0x0000,
57 .rdata_reg = 0x0070,
58 .irq_regs = 0x0004,
59 .tolerance_regs = 0x0018,
60 .names = { "A", "B", "C", "D" },
61 },
62 {
63 .val_regs = 0x001C,
64 .rdata_reg = 0x0074,
65 .irq_regs = 0x0020,
66 .tolerance_regs = 0x0034,
67 .names = { "E", "F", "G", "H" },
68 },
69 {
70 .val_regs = 0x0038,
71 .rdata_reg = 0x0078,
72 .irq_regs = 0x003C,
73 .tolerance_regs = 0x0050,
74 .names = { "I", "J", "K", "L" },
75 },
76 {
77 .val_regs = 0x0090,
78 .rdata_reg = 0x007C,
79 .irq_regs = 0x0094,
80 .tolerance_regs = 0x00A8,
81 .names = { "M", "N", "O", "P" },
82 },
83};
84
85enum aspeed_sgpio_reg {
86 reg_val,
87 reg_rdata,
88 reg_irq_enable,
89 reg_irq_type0,
90 reg_irq_type1,
91 reg_irq_type2,
92 reg_irq_status,
93 reg_tolerance,
94};
95
96#define GPIO_VAL_VALUE 0x00
97#define GPIO_IRQ_ENABLE 0x00
98#define GPIO_IRQ_TYPE0 0x04
99#define GPIO_IRQ_TYPE1 0x08
100#define GPIO_IRQ_TYPE2 0x0C
101#define GPIO_IRQ_STATUS 0x10
102
103static void __iomem *bank_reg(struct aspeed_sgpio *gpio,
104 const struct aspeed_sgpio_bank *bank,
105 const enum aspeed_sgpio_reg reg)
106{
107 switch (reg) {
108 case reg_val:
109 return gpio->base + bank->val_regs + GPIO_VAL_VALUE;
110 case reg_rdata:
111 return gpio->base + bank->rdata_reg;
112 case reg_irq_enable:
113 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE;
114 case reg_irq_type0:
115 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0;
116 case reg_irq_type1:
117 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1;
118 case reg_irq_type2:
119 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;
120 case reg_irq_status:
121 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;
122 case reg_tolerance:
123 return gpio->base + bank->tolerance_regs;
124 default:
125 /* acturally if code runs to here, it's an error case */
126 BUG();
127 }
128}
129
130#define GPIO_BANK(x) ((x) >> 6)
131#define GPIO_OFFSET(x) ((x) & GENMASK(5, 0))
132#define GPIO_BIT(x) BIT(GPIO_OFFSET(x) >> 1)
133
134static const struct aspeed_sgpio_bank *to_bank(unsigned int offset)
135{
136 unsigned int bank;
137
138 bank = GPIO_BANK(offset);
139
140 WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks));
141 return &aspeed_sgpio_banks[bank];
142}
143
144static int aspeed_sgpio_init_valid_mask(struct gpio_chip *gc,
145 unsigned long *valid_mask, unsigned int ngpios)
146{
147 bitmap_set(valid_mask, 0, ngpios);
148 return 0;
149}
150
151static void aspeed_sgpio_irq_init_valid_mask(struct gpio_chip *gc,
152 unsigned long *valid_mask, unsigned int ngpios)
153{
154 unsigned int i;
155
156 /* input GPIOs are even bits */
157 for (i = 0; i < ngpios; i++) {
158 if (i % 2)
159 clear_bit(i, valid_mask);
160 }
161}
162
163static bool aspeed_sgpio_is_input(unsigned int offset)
164{
165 return !(offset % 2);
166}
167
168static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset)
169{
170 struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
171 const struct aspeed_sgpio_bank *bank = to_bank(offset);
172 unsigned long flags;
173 enum aspeed_sgpio_reg reg;
174 int rc = 0;
175
176 raw_spin_lock_irqsave(&gpio->lock, flags);
177
178 reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata;
179 rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset));
180
181 raw_spin_unlock_irqrestore(&gpio->lock, flags);
182
183 return rc;
184}
185
186static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, int val)
187{
188 struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
189 const struct aspeed_sgpio_bank *bank = to_bank(offset);
190 void __iomem *addr_r, *addr_w;
191 u32 reg = 0;
192
193 if (aspeed_sgpio_is_input(offset))
194 return -EINVAL;
195
196 /* Since this is an output, read the cached value from rdata, then
197 * update val. */
198 addr_r = bank_reg(gpio, bank, reg_rdata);
199 addr_w = bank_reg(gpio, bank, reg_val);
200
201 reg = ioread32(addr_r);
202
203 if (val)
204 reg |= GPIO_BIT(offset);
205 else
206 reg &= ~GPIO_BIT(offset);
207
208 iowrite32(reg, addr_w);
209
210 return 0;
211}
212
213static void aspeed_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val)
214{
215 struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
216 unsigned long flags;
217
218 raw_spin_lock_irqsave(&gpio->lock, flags);
219
220 sgpio_set_value(gc, offset, val);
221
222 raw_spin_unlock_irqrestore(&gpio->lock, flags);
223}
224
225static int aspeed_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset)
226{
227 return aspeed_sgpio_is_input(offset) ? 0 : -EINVAL;
228}
229
230static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val)
231{
232 struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
233 unsigned long flags;
234 int rc;
235
236 /* No special action is required for setting the direction; we'll
237 * error-out in sgpio_set_value if this isn't an output GPIO */
238
239 raw_spin_lock_irqsave(&gpio->lock, flags);
240 rc = sgpio_set_value(gc, offset, val);
241 raw_spin_unlock_irqrestore(&gpio->lock, flags);
242
243 return rc;
244}
245
246static int aspeed_sgpio_get_direction(struct gpio_chip *gc, unsigned int offset)
247{
248 return !!aspeed_sgpio_is_input(offset);
249}
250
251static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
252 struct aspeed_sgpio **gpio,
253 const struct aspeed_sgpio_bank **bank,
254 u32 *bit, int *offset)
255{
256 struct aspeed_sgpio *internal;
257
258 *offset = irqd_to_hwirq(d);
259 internal = irq_data_get_irq_chip_data(d);
260 WARN_ON(!internal);
261
262 *gpio = internal;
263 *bank = to_bank(*offset);
264 *bit = GPIO_BIT(*offset);
265}
266
267static void aspeed_sgpio_irq_ack(struct irq_data *d)
268{
269 const struct aspeed_sgpio_bank *bank;
270 struct aspeed_sgpio *gpio;
271 unsigned long flags;
272 void __iomem *status_addr;
273 int offset;
274 u32 bit;
275
276 irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
277
278 status_addr = bank_reg(gpio, bank, reg_irq_status);
279
280 raw_spin_lock_irqsave(&gpio->lock, flags);
281
282 iowrite32(bit, status_addr);
283
284 raw_spin_unlock_irqrestore(&gpio->lock, flags);
285}
286
287static void aspeed_sgpio_irq_set_mask(struct irq_data *d, bool set)
288{
289 const struct aspeed_sgpio_bank *bank;
290 struct aspeed_sgpio *gpio;
291 unsigned long flags;
292 u32 reg, bit;
293 void __iomem *addr;
294 int offset;
295
296 irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
297 addr = bank_reg(gpio, bank, reg_irq_enable);
298
299 raw_spin_lock_irqsave(&gpio->lock, flags);
300
301 reg = ioread32(addr);
302 if (set)
303 reg |= bit;
304 else
305 reg &= ~bit;
306
307 iowrite32(reg, addr);
308
309 raw_spin_unlock_irqrestore(&gpio->lock, flags);
310}
311
312static void aspeed_sgpio_irq_mask(struct irq_data *d)
313{
314 aspeed_sgpio_irq_set_mask(d, false);
315}
316
317static void aspeed_sgpio_irq_unmask(struct irq_data *d)
318{
319 aspeed_sgpio_irq_set_mask(d, true);
320}
321
322static int aspeed_sgpio_set_type(struct irq_data *d, unsigned int type)
323{
324 u32 type0 = 0;
325 u32 type1 = 0;
326 u32 type2 = 0;
327 u32 bit, reg;
328 const struct aspeed_sgpio_bank *bank;
329 irq_flow_handler_t handler;
330 struct aspeed_sgpio *gpio;
331 unsigned long flags;
332 void __iomem *addr;
333 int offset;
334
335 irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
336
337 switch (type & IRQ_TYPE_SENSE_MASK) {
338 case IRQ_TYPE_EDGE_BOTH:
339 type2 |= bit;
340 fallthrough;
341 case IRQ_TYPE_EDGE_RISING:
342 type0 |= bit;
343 fallthrough;
344 case IRQ_TYPE_EDGE_FALLING:
345 handler = handle_edge_irq;
346 break;
347 case IRQ_TYPE_LEVEL_HIGH:
348 type0 |= bit;
349 fallthrough;
350 case IRQ_TYPE_LEVEL_LOW:
351 type1 |= bit;
352 handler = handle_level_irq;
353 break;
354 default:
355 return -EINVAL;
356 }
357
358 raw_spin_lock_irqsave(&gpio->lock, flags);
359
360 addr = bank_reg(gpio, bank, reg_irq_type0);
361 reg = ioread32(addr);
362 reg = (reg & ~bit) | type0;
363 iowrite32(reg, addr);
364
365 addr = bank_reg(gpio, bank, reg_irq_type1);
366 reg = ioread32(addr);
367 reg = (reg & ~bit) | type1;
368 iowrite32(reg, addr);
369
370 addr = bank_reg(gpio, bank, reg_irq_type2);
371 reg = ioread32(addr);
372 reg = (reg & ~bit) | type2;
373 iowrite32(reg, addr);
374
375 raw_spin_unlock_irqrestore(&gpio->lock, flags);
376
377 irq_set_handler_locked(d, handler);
378
379 return 0;
380}
381
382static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
383{
384 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
385 struct irq_chip *ic = irq_desc_get_chip(desc);
386 struct aspeed_sgpio *data = gpiochip_get_data(gc);
387 unsigned int i, p;
388 unsigned long reg;
389
390 chained_irq_enter(ic, desc);
391
392 for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
393 const struct aspeed_sgpio_bank *bank = &aspeed_sgpio_banks[i];
394
395 reg = ioread32(bank_reg(data, bank, reg_irq_status));
396
397 for_each_set_bit(p, ®, 32)
398 generic_handle_domain_irq(gc->irq.domain, (i * 32 + p) * 2);
399 }
400
401 chained_irq_exit(ic, desc);
402}
403
404static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
405 struct platform_device *pdev)
406{
407 int rc, i;
408 const struct aspeed_sgpio_bank *bank;
409 struct gpio_irq_chip *irq;
410
411 rc = platform_get_irq(pdev, 0);
412 if (rc < 0)
413 return rc;
414
415 gpio->irq = rc;
416
417 /* Disable IRQ and clear Interrupt status registers for all SGPIO Pins. */
418 for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
419 bank = &aspeed_sgpio_banks[i];
420 /* disable irq enable bits */
421 iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_enable));
422 /* clear status bits */
423 iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_status));
424 }
425
426 gpio->intc.name = dev_name(&pdev->dev);
427 gpio->intc.irq_ack = aspeed_sgpio_irq_ack;
428 gpio->intc.irq_mask = aspeed_sgpio_irq_mask;
429 gpio->intc.irq_unmask = aspeed_sgpio_irq_unmask;
430 gpio->intc.irq_set_type = aspeed_sgpio_set_type;
431
432 irq = &gpio->chip.irq;
433 irq->chip = &gpio->intc;
434 irq->init_valid_mask = aspeed_sgpio_irq_init_valid_mask;
435 irq->handler = handle_bad_irq;
436 irq->default_type = IRQ_TYPE_NONE;
437 irq->parent_handler = aspeed_sgpio_irq_handler;
438 irq->parent_handler_data = gpio;
439 irq->parents = &gpio->irq;
440 irq->num_parents = 1;
441
442 /* Apply default IRQ settings */
443 for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
444 bank = &aspeed_sgpio_banks[i];
445 /* set falling or level-low irq */
446 iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type0));
447 /* trigger type is edge */
448 iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type1));
449 /* single edge trigger */
450 iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type2));
451 }
452
453 return 0;
454}
455
456static const struct aspeed_sgpio_pdata ast2400_sgpio_pdata = {
457 .pin_mask = GENMASK(9, 6),
458};
459
460static int aspeed_sgpio_reset_tolerance(struct gpio_chip *chip,
461 unsigned int offset, bool enable)
462{
463 struct aspeed_sgpio *gpio = gpiochip_get_data(chip);
464 unsigned long flags;
465 void __iomem *reg;
466 u32 val;
467
468 reg = bank_reg(gpio, to_bank(offset), reg_tolerance);
469
470 raw_spin_lock_irqsave(&gpio->lock, flags);
471
472 val = readl(reg);
473
474 if (enable)
475 val |= GPIO_BIT(offset);
476 else
477 val &= ~GPIO_BIT(offset);
478
479 writel(val, reg);
480
481 raw_spin_unlock_irqrestore(&gpio->lock, flags);
482
483 return 0;
484}
485
486static int aspeed_sgpio_set_config(struct gpio_chip *chip, unsigned int offset,
487 unsigned long config)
488{
489 unsigned long param = pinconf_to_config_param(config);
490 u32 arg = pinconf_to_config_argument(config);
491
492 if (param == PIN_CONFIG_PERSIST_STATE)
493 return aspeed_sgpio_reset_tolerance(chip, offset, arg);
494
495 return -ENOTSUPP;
496}
497
498static const struct aspeed_sgpio_pdata ast2600_sgpiom_pdata = {
499 .pin_mask = GENMASK(10, 6),
500};
501
502static const struct of_device_id aspeed_sgpio_of_table[] = {
503 { .compatible = "aspeed,ast2400-sgpio", .data = &ast2400_sgpio_pdata, },
504 { .compatible = "aspeed,ast2500-sgpio", .data = &ast2400_sgpio_pdata, },
505 { .compatible = "aspeed,ast2600-sgpiom", .data = &ast2600_sgpiom_pdata, },
506 {}
507};
508
509MODULE_DEVICE_TABLE(of, aspeed_sgpio_of_table);
510
511static int __init aspeed_sgpio_probe(struct platform_device *pdev)
512{
513 u32 nr_gpios, sgpio_freq, sgpio_clk_div, gpio_cnt_regval, pin_mask;
514 const struct aspeed_sgpio_pdata *pdata;
515 struct aspeed_sgpio *gpio;
516 unsigned long apb_freq;
517 int rc;
518
519 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
520 if (!gpio)
521 return -ENOMEM;
522
523 gpio->base = devm_platform_ioremap_resource(pdev, 0);
524 if (IS_ERR(gpio->base))
525 return PTR_ERR(gpio->base);
526
527 pdata = device_get_match_data(&pdev->dev);
528 if (!pdata)
529 return -EINVAL;
530
531 pin_mask = pdata->pin_mask;
532
533 rc = device_property_read_u32(&pdev->dev, "ngpios", &nr_gpios);
534 if (rc < 0) {
535 dev_err(&pdev->dev, "Could not read ngpios property\n");
536 return -EINVAL;
537 } else if (nr_gpios % 8) {
538 dev_err(&pdev->dev, "Number of GPIOs not multiple of 8: %d\n",
539 nr_gpios);
540 return -EINVAL;
541 }
542
543 rc = device_property_read_u32(&pdev->dev, "bus-frequency", &sgpio_freq);
544 if (rc < 0) {
545 dev_err(&pdev->dev, "Could not read bus-frequency property\n");
546 return -EINVAL;
547 }
548
549 gpio->pclk = devm_clk_get(&pdev->dev, NULL);
550 if (IS_ERR(gpio->pclk)) {
551 dev_err(&pdev->dev, "devm_clk_get failed\n");
552 return PTR_ERR(gpio->pclk);
553 }
554
555 apb_freq = clk_get_rate(gpio->pclk);
556
557 /*
558 * From the datasheet,
559 * SGPIO period = 1/PCLK * 2 * (GPIO254[31:16] + 1)
560 * period = 2 * (GPIO254[31:16] + 1) / PCLK
561 * frequency = 1 / (2 * (GPIO254[31:16] + 1) / PCLK)
562 * frequency = PCLK / (2 * (GPIO254[31:16] + 1))
563 * frequency * 2 * (GPIO254[31:16] + 1) = PCLK
564 * GPIO254[31:16] = PCLK / (frequency * 2) - 1
565 */
566 if (sgpio_freq == 0)
567 return -EINVAL;
568
569 sgpio_clk_div = (apb_freq / (sgpio_freq * 2)) - 1;
570
571 if (sgpio_clk_div > (1 << 16) - 1)
572 return -EINVAL;
573
574 gpio_cnt_regval = ((nr_gpios / 8) << ASPEED_SGPIO_PINS_SHIFT) & pin_mask;
575 iowrite32(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) | gpio_cnt_regval |
576 ASPEED_SGPIO_ENABLE, gpio->base + ASPEED_SGPIO_CTRL);
577
578 raw_spin_lock_init(&gpio->lock);
579
580 gpio->chip.parent = &pdev->dev;
581 gpio->chip.ngpio = nr_gpios * 2;
582 gpio->chip.init_valid_mask = aspeed_sgpio_init_valid_mask;
583 gpio->chip.direction_input = aspeed_sgpio_dir_in;
584 gpio->chip.direction_output = aspeed_sgpio_dir_out;
585 gpio->chip.get_direction = aspeed_sgpio_get_direction;
586 gpio->chip.request = NULL;
587 gpio->chip.free = NULL;
588 gpio->chip.get = aspeed_sgpio_get;
589 gpio->chip.set = aspeed_sgpio_set;
590 gpio->chip.set_config = aspeed_sgpio_set_config;
591 gpio->chip.label = dev_name(&pdev->dev);
592 gpio->chip.base = -1;
593
594 aspeed_sgpio_setup_irqs(gpio, pdev);
595
596 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
597 if (rc < 0)
598 return rc;
599
600 return 0;
601}
602
603static struct platform_driver aspeed_sgpio_driver = {
604 .driver = {
605 .name = KBUILD_MODNAME,
606 .of_match_table = aspeed_sgpio_of_table,
607 },
608};
609
610module_platform_driver_probe(aspeed_sgpio_driver, aspeed_sgpio_probe);
611MODULE_DESCRIPTION("Aspeed Serial GPIO Driver");
612MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2019 American Megatrends International LLC.
4 *
5 * Author: Karthikeyan Mani <karthikeyanm@amiindia.co.in>
6 */
7
8#include <linux/bitfield.h>
9#include <linux/clk.h>
10#include <linux/gpio/driver.h>
11#include <linux/hashtable.h>
12#include <linux/init.h>
13#include <linux/io.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/platform_device.h>
17#include <linux/spinlock.h>
18#include <linux/string.h>
19
20/*
21 * MAX_NR_HW_GPIO represents the number of actual hardware-supported GPIOs (ie,
22 * slots within the clocked serial GPIO data). Since each HW GPIO is both an
23 * input and an output, we provide MAX_NR_HW_GPIO * 2 lines on our gpiochip
24 * device.
25 *
26 * We use SGPIO_OUTPUT_OFFSET to define the split between the inputs and
27 * outputs; the inputs start at line 0, the outputs start at OUTPUT_OFFSET.
28 */
29#define MAX_NR_HW_SGPIO 80
30#define SGPIO_OUTPUT_OFFSET MAX_NR_HW_SGPIO
31
32#define ASPEED_SGPIO_CTRL 0x54
33
34#define ASPEED_SGPIO_PINS_MASK GENMASK(9, 6)
35#define ASPEED_SGPIO_CLK_DIV_MASK GENMASK(31, 16)
36#define ASPEED_SGPIO_ENABLE BIT(0)
37
38struct aspeed_sgpio {
39 struct gpio_chip chip;
40 struct clk *pclk;
41 spinlock_t lock;
42 void __iomem *base;
43 int irq;
44 int n_sgpio;
45};
46
47struct aspeed_sgpio_bank {
48 uint16_t val_regs;
49 uint16_t rdata_reg;
50 uint16_t irq_regs;
51 const char names[4][3];
52};
53
54/*
55 * Note: The "value" register returns the input value when the GPIO is
56 * configured as an input.
57 *
58 * The "rdata" register returns the output value when the GPIO is
59 * configured as an output.
60 */
61static const struct aspeed_sgpio_bank aspeed_sgpio_banks[] = {
62 {
63 .val_regs = 0x0000,
64 .rdata_reg = 0x0070,
65 .irq_regs = 0x0004,
66 .names = { "A", "B", "C", "D" },
67 },
68 {
69 .val_regs = 0x001C,
70 .rdata_reg = 0x0074,
71 .irq_regs = 0x0020,
72 .names = { "E", "F", "G", "H" },
73 },
74 {
75 .val_regs = 0x0038,
76 .rdata_reg = 0x0078,
77 .irq_regs = 0x003C,
78 .names = { "I", "J" },
79 },
80};
81
82enum aspeed_sgpio_reg {
83 reg_val,
84 reg_rdata,
85 reg_irq_enable,
86 reg_irq_type0,
87 reg_irq_type1,
88 reg_irq_type2,
89 reg_irq_status,
90};
91
92#define GPIO_VAL_VALUE 0x00
93#define GPIO_IRQ_ENABLE 0x00
94#define GPIO_IRQ_TYPE0 0x04
95#define GPIO_IRQ_TYPE1 0x08
96#define GPIO_IRQ_TYPE2 0x0C
97#define GPIO_IRQ_STATUS 0x10
98
99static void __iomem *bank_reg(struct aspeed_sgpio *gpio,
100 const struct aspeed_sgpio_bank *bank,
101 const enum aspeed_sgpio_reg reg)
102{
103 switch (reg) {
104 case reg_val:
105 return gpio->base + bank->val_regs + GPIO_VAL_VALUE;
106 case reg_rdata:
107 return gpio->base + bank->rdata_reg;
108 case reg_irq_enable:
109 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE;
110 case reg_irq_type0:
111 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0;
112 case reg_irq_type1:
113 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1;
114 case reg_irq_type2:
115 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;
116 case reg_irq_status:
117 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;
118 default:
119 /* acturally if code runs to here, it's an error case */
120 BUG();
121 }
122}
123
124#define GPIO_BANK(x) ((x % SGPIO_OUTPUT_OFFSET) >> 5)
125#define GPIO_OFFSET(x) ((x % SGPIO_OUTPUT_OFFSET) & 0x1f)
126#define GPIO_BIT(x) BIT(GPIO_OFFSET(x))
127
128static const struct aspeed_sgpio_bank *to_bank(unsigned int offset)
129{
130 unsigned int bank;
131
132 bank = GPIO_BANK(offset);
133
134 WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks));
135 return &aspeed_sgpio_banks[bank];
136}
137
138static int aspeed_sgpio_init_valid_mask(struct gpio_chip *gc,
139 unsigned long *valid_mask, unsigned int ngpios)
140{
141 struct aspeed_sgpio *sgpio = gpiochip_get_data(gc);
142 int n = sgpio->n_sgpio;
143 int c = SGPIO_OUTPUT_OFFSET - n;
144
145 WARN_ON(ngpios < MAX_NR_HW_SGPIO * 2);
146
147 /* input GPIOs in the lower range */
148 bitmap_set(valid_mask, 0, n);
149 bitmap_clear(valid_mask, n, c);
150
151 /* output GPIOS above SGPIO_OUTPUT_OFFSET */
152 bitmap_set(valid_mask, SGPIO_OUTPUT_OFFSET, n);
153 bitmap_clear(valid_mask, SGPIO_OUTPUT_OFFSET + n, c);
154
155 return 0;
156}
157
158static void aspeed_sgpio_irq_init_valid_mask(struct gpio_chip *gc,
159 unsigned long *valid_mask, unsigned int ngpios)
160{
161 struct aspeed_sgpio *sgpio = gpiochip_get_data(gc);
162 int n = sgpio->n_sgpio;
163
164 WARN_ON(ngpios < MAX_NR_HW_SGPIO * 2);
165
166 /* input GPIOs in the lower range */
167 bitmap_set(valid_mask, 0, n);
168 bitmap_clear(valid_mask, n, ngpios - n);
169}
170
171static bool aspeed_sgpio_is_input(unsigned int offset)
172{
173 return offset < SGPIO_OUTPUT_OFFSET;
174}
175
176static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset)
177{
178 struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
179 const struct aspeed_sgpio_bank *bank = to_bank(offset);
180 unsigned long flags;
181 enum aspeed_sgpio_reg reg;
182 int rc = 0;
183
184 spin_lock_irqsave(&gpio->lock, flags);
185
186 reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata;
187 rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset));
188
189 spin_unlock_irqrestore(&gpio->lock, flags);
190
191 return rc;
192}
193
194static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, int val)
195{
196 struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
197 const struct aspeed_sgpio_bank *bank = to_bank(offset);
198 void __iomem *addr_r, *addr_w;
199 u32 reg = 0;
200
201 if (aspeed_sgpio_is_input(offset))
202 return -EINVAL;
203
204 /* Since this is an output, read the cached value from rdata, then
205 * update val. */
206 addr_r = bank_reg(gpio, bank, reg_rdata);
207 addr_w = bank_reg(gpio, bank, reg_val);
208
209 reg = ioread32(addr_r);
210
211 if (val)
212 reg |= GPIO_BIT(offset);
213 else
214 reg &= ~GPIO_BIT(offset);
215
216 iowrite32(reg, addr_w);
217
218 return 0;
219}
220
221static void aspeed_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val)
222{
223 struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
224 unsigned long flags;
225
226 spin_lock_irqsave(&gpio->lock, flags);
227
228 sgpio_set_value(gc, offset, val);
229
230 spin_unlock_irqrestore(&gpio->lock, flags);
231}
232
233static int aspeed_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset)
234{
235 return aspeed_sgpio_is_input(offset) ? 0 : -EINVAL;
236}
237
238static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val)
239{
240 struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
241 unsigned long flags;
242 int rc;
243
244 /* No special action is required for setting the direction; we'll
245 * error-out in sgpio_set_value if this isn't an output GPIO */
246
247 spin_lock_irqsave(&gpio->lock, flags);
248 rc = sgpio_set_value(gc, offset, val);
249 spin_unlock_irqrestore(&gpio->lock, flags);
250
251 return rc;
252}
253
254static int aspeed_sgpio_get_direction(struct gpio_chip *gc, unsigned int offset)
255{
256 return !!aspeed_sgpio_is_input(offset);
257}
258
259static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
260 struct aspeed_sgpio **gpio,
261 const struct aspeed_sgpio_bank **bank,
262 u32 *bit, int *offset)
263{
264 struct aspeed_sgpio *internal;
265
266 *offset = irqd_to_hwirq(d);
267 internal = irq_data_get_irq_chip_data(d);
268 WARN_ON(!internal);
269
270 *gpio = internal;
271 *bank = to_bank(*offset);
272 *bit = GPIO_BIT(*offset);
273}
274
275static void aspeed_sgpio_irq_ack(struct irq_data *d)
276{
277 const struct aspeed_sgpio_bank *bank;
278 struct aspeed_sgpio *gpio;
279 unsigned long flags;
280 void __iomem *status_addr;
281 int offset;
282 u32 bit;
283
284 irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
285
286 status_addr = bank_reg(gpio, bank, reg_irq_status);
287
288 spin_lock_irqsave(&gpio->lock, flags);
289
290 iowrite32(bit, status_addr);
291
292 spin_unlock_irqrestore(&gpio->lock, flags);
293}
294
295static void aspeed_sgpio_irq_set_mask(struct irq_data *d, bool set)
296{
297 const struct aspeed_sgpio_bank *bank;
298 struct aspeed_sgpio *gpio;
299 unsigned long flags;
300 u32 reg, bit;
301 void __iomem *addr;
302 int offset;
303
304 irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
305 addr = bank_reg(gpio, bank, reg_irq_enable);
306
307 spin_lock_irqsave(&gpio->lock, flags);
308
309 reg = ioread32(addr);
310 if (set)
311 reg |= bit;
312 else
313 reg &= ~bit;
314
315 iowrite32(reg, addr);
316
317 spin_unlock_irqrestore(&gpio->lock, flags);
318}
319
320static void aspeed_sgpio_irq_mask(struct irq_data *d)
321{
322 aspeed_sgpio_irq_set_mask(d, false);
323}
324
325static void aspeed_sgpio_irq_unmask(struct irq_data *d)
326{
327 aspeed_sgpio_irq_set_mask(d, true);
328}
329
330static int aspeed_sgpio_set_type(struct irq_data *d, unsigned int type)
331{
332 u32 type0 = 0;
333 u32 type1 = 0;
334 u32 type2 = 0;
335 u32 bit, reg;
336 const struct aspeed_sgpio_bank *bank;
337 irq_flow_handler_t handler;
338 struct aspeed_sgpio *gpio;
339 unsigned long flags;
340 void __iomem *addr;
341 int offset;
342
343 irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
344
345 switch (type & IRQ_TYPE_SENSE_MASK) {
346 case IRQ_TYPE_EDGE_BOTH:
347 type2 |= bit;
348 fallthrough;
349 case IRQ_TYPE_EDGE_RISING:
350 type0 |= bit;
351 fallthrough;
352 case IRQ_TYPE_EDGE_FALLING:
353 handler = handle_edge_irq;
354 break;
355 case IRQ_TYPE_LEVEL_HIGH:
356 type0 |= bit;
357 fallthrough;
358 case IRQ_TYPE_LEVEL_LOW:
359 type1 |= bit;
360 handler = handle_level_irq;
361 break;
362 default:
363 return -EINVAL;
364 }
365
366 spin_lock_irqsave(&gpio->lock, flags);
367
368 addr = bank_reg(gpio, bank, reg_irq_type0);
369 reg = ioread32(addr);
370 reg = (reg & ~bit) | type0;
371 iowrite32(reg, addr);
372
373 addr = bank_reg(gpio, bank, reg_irq_type1);
374 reg = ioread32(addr);
375 reg = (reg & ~bit) | type1;
376 iowrite32(reg, addr);
377
378 addr = bank_reg(gpio, bank, reg_irq_type2);
379 reg = ioread32(addr);
380 reg = (reg & ~bit) | type2;
381 iowrite32(reg, addr);
382
383 spin_unlock_irqrestore(&gpio->lock, flags);
384
385 irq_set_handler_locked(d, handler);
386
387 return 0;
388}
389
390static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
391{
392 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
393 struct irq_chip *ic = irq_desc_get_chip(desc);
394 struct aspeed_sgpio *data = gpiochip_get_data(gc);
395 unsigned int i, p, girq;
396 unsigned long reg;
397
398 chained_irq_enter(ic, desc);
399
400 for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
401 const struct aspeed_sgpio_bank *bank = &aspeed_sgpio_banks[i];
402
403 reg = ioread32(bank_reg(data, bank, reg_irq_status));
404
405 for_each_set_bit(p, ®, 32) {
406 girq = irq_find_mapping(gc->irq.domain, i * 32 + p);
407 generic_handle_irq(girq);
408 }
409
410 }
411
412 chained_irq_exit(ic, desc);
413}
414
415static struct irq_chip aspeed_sgpio_irqchip = {
416 .name = "aspeed-sgpio",
417 .irq_ack = aspeed_sgpio_irq_ack,
418 .irq_mask = aspeed_sgpio_irq_mask,
419 .irq_unmask = aspeed_sgpio_irq_unmask,
420 .irq_set_type = aspeed_sgpio_set_type,
421};
422
423static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
424 struct platform_device *pdev)
425{
426 int rc, i;
427 const struct aspeed_sgpio_bank *bank;
428 struct gpio_irq_chip *irq;
429
430 rc = platform_get_irq(pdev, 0);
431 if (rc < 0)
432 return rc;
433
434 gpio->irq = rc;
435
436 /* Disable IRQ and clear Interrupt status registers for all SGPIO Pins. */
437 for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
438 bank = &aspeed_sgpio_banks[i];
439 /* disable irq enable bits */
440 iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_enable));
441 /* clear status bits */
442 iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_status));
443 }
444
445 irq = &gpio->chip.irq;
446 irq->chip = &aspeed_sgpio_irqchip;
447 irq->init_valid_mask = aspeed_sgpio_irq_init_valid_mask;
448 irq->handler = handle_bad_irq;
449 irq->default_type = IRQ_TYPE_NONE;
450 irq->parent_handler = aspeed_sgpio_irq_handler;
451 irq->parent_handler_data = gpio;
452 irq->parents = &gpio->irq;
453 irq->num_parents = 1;
454
455 /* Apply default IRQ settings */
456 for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
457 bank = &aspeed_sgpio_banks[i];
458 /* set falling or level-low irq */
459 iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type0));
460 /* trigger type is edge */
461 iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type1));
462 /* single edge trigger */
463 iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type2));
464 }
465
466 return 0;
467}
468
469static const struct of_device_id aspeed_sgpio_of_table[] = {
470 { .compatible = "aspeed,ast2400-sgpio" },
471 { .compatible = "aspeed,ast2500-sgpio" },
472 {}
473};
474
475MODULE_DEVICE_TABLE(of, aspeed_sgpio_of_table);
476
477static int __init aspeed_sgpio_probe(struct platform_device *pdev)
478{
479 struct aspeed_sgpio *gpio;
480 u32 nr_gpios, sgpio_freq, sgpio_clk_div;
481 int rc;
482 unsigned long apb_freq;
483
484 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
485 if (!gpio)
486 return -ENOMEM;
487
488 gpio->base = devm_platform_ioremap_resource(pdev, 0);
489 if (IS_ERR(gpio->base))
490 return PTR_ERR(gpio->base);
491
492 rc = of_property_read_u32(pdev->dev.of_node, "ngpios", &nr_gpios);
493 if (rc < 0) {
494 dev_err(&pdev->dev, "Could not read ngpios property\n");
495 return -EINVAL;
496 } else if (nr_gpios > MAX_NR_HW_SGPIO) {
497 dev_err(&pdev->dev, "Number of GPIOs exceeds the maximum of %d: %d\n",
498 MAX_NR_HW_SGPIO, nr_gpios);
499 return -EINVAL;
500 }
501 gpio->n_sgpio = nr_gpios;
502
503 rc = of_property_read_u32(pdev->dev.of_node, "bus-frequency", &sgpio_freq);
504 if (rc < 0) {
505 dev_err(&pdev->dev, "Could not read bus-frequency property\n");
506 return -EINVAL;
507 }
508
509 gpio->pclk = devm_clk_get(&pdev->dev, NULL);
510 if (IS_ERR(gpio->pclk)) {
511 dev_err(&pdev->dev, "devm_clk_get failed\n");
512 return PTR_ERR(gpio->pclk);
513 }
514
515 apb_freq = clk_get_rate(gpio->pclk);
516
517 /*
518 * From the datasheet,
519 * SGPIO period = 1/PCLK * 2 * (GPIO254[31:16] + 1)
520 * period = 2 * (GPIO254[31:16] + 1) / PCLK
521 * frequency = 1 / (2 * (GPIO254[31:16] + 1) / PCLK)
522 * frequency = PCLK / (2 * (GPIO254[31:16] + 1))
523 * frequency * 2 * (GPIO254[31:16] + 1) = PCLK
524 * GPIO254[31:16] = PCLK / (frequency * 2) - 1
525 */
526 if (sgpio_freq == 0)
527 return -EINVAL;
528
529 sgpio_clk_div = (apb_freq / (sgpio_freq * 2)) - 1;
530
531 if (sgpio_clk_div > (1 << 16) - 1)
532 return -EINVAL;
533
534 iowrite32(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) |
535 FIELD_PREP(ASPEED_SGPIO_PINS_MASK, (nr_gpios / 8)) |
536 ASPEED_SGPIO_ENABLE,
537 gpio->base + ASPEED_SGPIO_CTRL);
538
539 spin_lock_init(&gpio->lock);
540
541 gpio->chip.parent = &pdev->dev;
542 gpio->chip.ngpio = MAX_NR_HW_SGPIO * 2;
543 gpio->chip.init_valid_mask = aspeed_sgpio_init_valid_mask;
544 gpio->chip.direction_input = aspeed_sgpio_dir_in;
545 gpio->chip.direction_output = aspeed_sgpio_dir_out;
546 gpio->chip.get_direction = aspeed_sgpio_get_direction;
547 gpio->chip.request = NULL;
548 gpio->chip.free = NULL;
549 gpio->chip.get = aspeed_sgpio_get;
550 gpio->chip.set = aspeed_sgpio_set;
551 gpio->chip.set_config = NULL;
552 gpio->chip.label = dev_name(&pdev->dev);
553 gpio->chip.base = -1;
554
555 aspeed_sgpio_setup_irqs(gpio, pdev);
556
557 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
558 if (rc < 0)
559 return rc;
560
561 return 0;
562}
563
564static struct platform_driver aspeed_sgpio_driver = {
565 .driver = {
566 .name = KBUILD_MODNAME,
567 .of_match_table = aspeed_sgpio_of_table,
568 },
569};
570
571module_platform_driver_probe(aspeed_sgpio_driver, aspeed_sgpio_probe);
572MODULE_DESCRIPTION("Aspeed Serial GPIO Driver");
573MODULE_LICENSE("GPL");