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1/*
2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include "armv7-m.dtsi"
44#include <dt-bindings/clock/stm32fx-clock.h>
45#include <dt-bindings/mfd/stm32f7-rcc.h>
46
47/ {
48 #address-cells = <1>;
49 #size-cells = <1>;
50
51 clocks {
52 clk_hse: clk-hse {
53 #clock-cells = <0>;
54 compatible = "fixed-clock";
55 clock-frequency = <0>;
56 };
57
58 clk-lse {
59 #clock-cells = <0>;
60 compatible = "fixed-clock";
61 clock-frequency = <32768>;
62 };
63
64 clk-lsi {
65 #clock-cells = <0>;
66 compatible = "fixed-clock";
67 clock-frequency = <32000>;
68 };
69
70 clk_i2s_ckin: clk-i2s-ckin {
71 #clock-cells = <0>;
72 compatible = "fixed-clock";
73 clock-frequency = <48000000>;
74 };
75 };
76
77 soc {
78 timers2: timers@40000000 {
79 #address-cells = <1>;
80 #size-cells = <0>;
81 compatible = "st,stm32-timers";
82 reg = <0x40000000 0x400>;
83 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
84 clock-names = "int";
85 status = "disabled";
86
87 pwm {
88 compatible = "st,stm32-pwm";
89 #pwm-cells = <3>;
90 status = "disabled";
91 };
92
93 timer@1 {
94 compatible = "st,stm32-timer-trigger";
95 reg = <1>;
96 status = "disabled";
97 };
98 };
99
100 timers3: timers@40000400 {
101 #address-cells = <1>;
102 #size-cells = <0>;
103 compatible = "st,stm32-timers";
104 reg = <0x40000400 0x400>;
105 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
106 clock-names = "int";
107 status = "disabled";
108
109 pwm {
110 compatible = "st,stm32-pwm";
111 #pwm-cells = <3>;
112 status = "disabled";
113 };
114
115 timer@2 {
116 compatible = "st,stm32-timer-trigger";
117 reg = <2>;
118 status = "disabled";
119 };
120 };
121
122 timers4: timers@40000800 {
123 #address-cells = <1>;
124 #size-cells = <0>;
125 compatible = "st,stm32-timers";
126 reg = <0x40000800 0x400>;
127 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
128 clock-names = "int";
129 status = "disabled";
130
131 pwm {
132 compatible = "st,stm32-pwm";
133 #pwm-cells = <3>;
134 status = "disabled";
135 };
136
137 timer@3 {
138 compatible = "st,stm32-timer-trigger";
139 reg = <3>;
140 status = "disabled";
141 };
142 };
143
144 timers5: timers@40000c00 {
145 #address-cells = <1>;
146 #size-cells = <0>;
147 compatible = "st,stm32-timers";
148 reg = <0x40000C00 0x400>;
149 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
150 clock-names = "int";
151 status = "disabled";
152
153 pwm {
154 compatible = "st,stm32-pwm";
155 #pwm-cells = <3>;
156 status = "disabled";
157 };
158
159 timer@4 {
160 compatible = "st,stm32-timer-trigger";
161 reg = <4>;
162 status = "disabled";
163 };
164 };
165
166 timers6: timers@40001000 {
167 #address-cells = <1>;
168 #size-cells = <0>;
169 compatible = "st,stm32-timers";
170 reg = <0x40001000 0x400>;
171 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
172 clock-names = "int";
173 status = "disabled";
174
175 timer@5 {
176 compatible = "st,stm32-timer-trigger";
177 reg = <5>;
178 status = "disabled";
179 };
180 };
181
182 timers7: timers@40001400 {
183 #address-cells = <1>;
184 #size-cells = <0>;
185 compatible = "st,stm32-timers";
186 reg = <0x40001400 0x400>;
187 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
188 clock-names = "int";
189 status = "disabled";
190
191 timer@6 {
192 compatible = "st,stm32-timer-trigger";
193 reg = <6>;
194 status = "disabled";
195 };
196 };
197
198 timers12: timers@40001800 {
199 #address-cells = <1>;
200 #size-cells = <0>;
201 compatible = "st,stm32-timers";
202 reg = <0x40001800 0x400>;
203 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
204 clock-names = "int";
205 status = "disabled";
206
207 pwm {
208 compatible = "st,stm32-pwm";
209 #pwm-cells = <3>;
210 status = "disabled";
211 };
212
213 timer@11 {
214 compatible = "st,stm32-timer-trigger";
215 reg = <11>;
216 status = "disabled";
217 };
218 };
219
220 timers13: timers@40001c00 {
221 compatible = "st,stm32-timers";
222 reg = <0x40001C00 0x400>;
223 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
224 clock-names = "int";
225 status = "disabled";
226
227 pwm {
228 compatible = "st,stm32-pwm";
229 #pwm-cells = <3>;
230 status = "disabled";
231 };
232 };
233
234 timers14: timers@40002000 {
235 compatible = "st,stm32-timers";
236 reg = <0x40002000 0x400>;
237 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
238 clock-names = "int";
239 status = "disabled";
240
241 pwm {
242 compatible = "st,stm32-pwm";
243 #pwm-cells = <3>;
244 status = "disabled";
245 };
246 };
247
248 rtc: rtc@40002800 {
249 compatible = "st,stm32-rtc";
250 reg = <0x40002800 0x400>;
251 clocks = <&rcc 1 CLK_RTC>;
252 assigned-clocks = <&rcc 1 CLK_RTC>;
253 assigned-clock-parents = <&rcc 1 CLK_LSE>;
254 interrupt-parent = <&exti>;
255 interrupts = <17 1>;
256 st,syscfg = <&pwrcfg 0x00 0x100>;
257 status = "disabled";
258 };
259
260 usart2: serial@40004400 {
261 compatible = "st,stm32f7-uart";
262 reg = <0x40004400 0x400>;
263 interrupts = <38>;
264 clocks = <&rcc 1 CLK_USART2>;
265 status = "disabled";
266 };
267
268 usart3: serial@40004800 {
269 compatible = "st,stm32f7-uart";
270 reg = <0x40004800 0x400>;
271 interrupts = <39>;
272 clocks = <&rcc 1 CLK_USART3>;
273 status = "disabled";
274 };
275
276 usart4: serial@40004c00 {
277 compatible = "st,stm32f7-uart";
278 reg = <0x40004c00 0x400>;
279 interrupts = <52>;
280 clocks = <&rcc 1 CLK_UART4>;
281 status = "disabled";
282 };
283
284 usart5: serial@40005000 {
285 compatible = "st,stm32f7-uart";
286 reg = <0x40005000 0x400>;
287 interrupts = <53>;
288 clocks = <&rcc 1 CLK_UART5>;
289 status = "disabled";
290 };
291
292 i2c1: i2c@40005400 {
293 compatible = "st,stm32f7-i2c";
294 reg = <0x40005400 0x400>;
295 interrupts = <31>,
296 <32>;
297 resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
298 clocks = <&rcc 1 CLK_I2C1>;
299 #address-cells = <1>;
300 #size-cells = <0>;
301 status = "disabled";
302 };
303
304 i2c2: i2c@40005800 {
305 compatible = "st,stm32f7-i2c";
306 reg = <0x40005800 0x400>;
307 interrupts = <33>,
308 <34>;
309 resets = <&rcc STM32F7_APB1_RESET(I2C2)>;
310 clocks = <&rcc 1 CLK_I2C2>;
311 #address-cells = <1>;
312 #size-cells = <0>;
313 status = "disabled";
314 };
315
316 i2c3: i2c@40005c00 {
317 compatible = "st,stm32f7-i2c";
318 reg = <0x40005c00 0x400>;
319 interrupts = <72>,
320 <73>;
321 resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
322 clocks = <&rcc 1 CLK_I2C3>;
323 #address-cells = <1>;
324 #size-cells = <0>;
325 status = "disabled";
326 };
327
328 i2c4: i2c@40006000 {
329 compatible = "st,stm32f7-i2c";
330 reg = <0x40006000 0x400>;
331 interrupts = <95>,
332 <96>;
333 resets = <&rcc STM32F7_APB1_RESET(I2C4)>;
334 clocks = <&rcc 1 CLK_I2C4>;
335 #address-cells = <1>;
336 #size-cells = <0>;
337 status = "disabled";
338 };
339
340 cec: cec@40006c00 {
341 compatible = "st,stm32-cec";
342 reg = <0x40006C00 0x400>;
343 interrupts = <94>;
344 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
345 clock-names = "cec", "hdmi-cec";
346 status = "disabled";
347 };
348
349 usart7: serial@40007800 {
350 compatible = "st,stm32f7-uart";
351 reg = <0x40007800 0x400>;
352 interrupts = <82>;
353 clocks = <&rcc 1 CLK_UART7>;
354 status = "disabled";
355 };
356
357 usart8: serial@40007c00 {
358 compatible = "st,stm32f7-uart";
359 reg = <0x40007c00 0x400>;
360 interrupts = <83>;
361 clocks = <&rcc 1 CLK_UART8>;
362 status = "disabled";
363 };
364
365 timers1: timers@40010000 {
366 #address-cells = <1>;
367 #size-cells = <0>;
368 compatible = "st,stm32-timers";
369 reg = <0x40010000 0x400>;
370 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
371 clock-names = "int";
372 status = "disabled";
373
374 pwm {
375 compatible = "st,stm32-pwm";
376 #pwm-cells = <3>;
377 status = "disabled";
378 };
379
380 timer@0 {
381 compatible = "st,stm32-timer-trigger";
382 reg = <0>;
383 status = "disabled";
384 };
385 };
386
387 timers8: timers@40010400 {
388 #address-cells = <1>;
389 #size-cells = <0>;
390 compatible = "st,stm32-timers";
391 reg = <0x40010400 0x400>;
392 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
393 clock-names = "int";
394 status = "disabled";
395
396 pwm {
397 compatible = "st,stm32-pwm";
398 #pwm-cells = <3>;
399 status = "disabled";
400 };
401
402 timer@7 {
403 compatible = "st,stm32-timer-trigger";
404 reg = <7>;
405 status = "disabled";
406 };
407 };
408
409 usart1: serial@40011000 {
410 compatible = "st,stm32f7-uart";
411 reg = <0x40011000 0x400>;
412 interrupts = <37>;
413 clocks = <&rcc 1 CLK_USART1>;
414 status = "disabled";
415 };
416
417 usart6: serial@40011400 {
418 compatible = "st,stm32f7-uart";
419 reg = <0x40011400 0x400>;
420 interrupts = <71>;
421 clocks = <&rcc 1 CLK_USART6>;
422 status = "disabled";
423 };
424
425 sdio2: mmc@40011c00 {
426 compatible = "arm,pl180", "arm,primecell";
427 arm,primecell-periphid = <0x00880180>;
428 reg = <0x40011c00 0x400>;
429 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
430 clock-names = "apb_pclk";
431 interrupts = <103>;
432 max-frequency = <48000000>;
433 status = "disabled";
434 };
435
436 sdio1: mmc@40012c00 {
437 compatible = "arm,pl180", "arm,primecell";
438 arm,primecell-periphid = <0x00880180>;
439 reg = <0x40012c00 0x400>;
440 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
441 clock-names = "apb_pclk";
442 interrupts = <49>;
443 max-frequency = <48000000>;
444 status = "disabled";
445 };
446
447 syscfg: syscon@40013800 {
448 compatible = "st,stm32-syscfg", "syscon";
449 reg = <0x40013800 0x400>;
450 };
451
452 exti: interrupt-controller@40013c00 {
453 compatible = "st,stm32-exti";
454 interrupt-controller;
455 #interrupt-cells = <2>;
456 reg = <0x40013C00 0x400>;
457 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
458 };
459
460 timers9: timers@40014000 {
461 #address-cells = <1>;
462 #size-cells = <0>;
463 compatible = "st,stm32-timers";
464 reg = <0x40014000 0x400>;
465 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
466 clock-names = "int";
467 status = "disabled";
468
469 pwm {
470 compatible = "st,stm32-pwm";
471 #pwm-cells = <3>;
472 status = "disabled";
473 };
474
475 timer@8 {
476 compatible = "st,stm32-timer-trigger";
477 reg = <8>;
478 status = "disabled";
479 };
480 };
481
482 timers10: timers@40014400 {
483 compatible = "st,stm32-timers";
484 reg = <0x40014400 0x400>;
485 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
486 clock-names = "int";
487 status = "disabled";
488
489 pwm {
490 compatible = "st,stm32-pwm";
491 #pwm-cells = <3>;
492 status = "disabled";
493 };
494 };
495
496 timers11: timers@40014800 {
497 compatible = "st,stm32-timers";
498 reg = <0x40014800 0x400>;
499 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
500 clock-names = "int";
501 status = "disabled";
502
503 pwm {
504 compatible = "st,stm32-pwm";
505 #pwm-cells = <3>;
506 status = "disabled";
507 };
508 };
509
510 pwrcfg: power-config@40007000 {
511 compatible = "st,stm32-power-config", "syscon";
512 reg = <0x40007000 0x400>;
513 };
514
515 crc: crc@40023000 {
516 compatible = "st,stm32f7-crc";
517 reg = <0x40023000 0x400>;
518 clocks = <&rcc 0 12>;
519 status = "disabled";
520 };
521
522 rcc: rcc@40023800 {
523 #reset-cells = <1>;
524 #clock-cells = <2>;
525 compatible = "st,stm32f746-rcc", "st,stm32-rcc";
526 reg = <0x40023800 0x400>;
527 clocks = <&clk_hse>, <&clk_i2s_ckin>;
528 st,syscfg = <&pwrcfg>;
529 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
530 assigned-clock-rates = <1000000>;
531 };
532
533 dma1: dma-controller@40026000 {
534 compatible = "st,stm32-dma";
535 reg = <0x40026000 0x400>;
536 interrupts = <11>,
537 <12>,
538 <13>,
539 <14>,
540 <15>,
541 <16>,
542 <17>,
543 <47>;
544 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
545 #dma-cells = <4>;
546 status = "disabled";
547 };
548
549 dma2: dma-controller@40026400 {
550 compatible = "st,stm32-dma";
551 reg = <0x40026400 0x400>;
552 interrupts = <56>,
553 <57>,
554 <58>,
555 <59>,
556 <60>,
557 <68>,
558 <69>,
559 <70>;
560 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
561 #dma-cells = <4>;
562 st,mem2mem;
563 status = "disabled";
564 };
565
566 usbotg_hs: usb@40040000 {
567 compatible = "st,stm32f7-hsotg";
568 reg = <0x40040000 0x40000>;
569 interrupts = <77>;
570 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
571 clock-names = "otg";
572 g-rx-fifo-size = <256>;
573 g-np-tx-fifo-size = <32>;
574 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
575 status = "disabled";
576 };
577
578 usbotg_fs: usb@50000000 {
579 compatible = "st,stm32f4x9-fsotg";
580 reg = <0x50000000 0x40000>;
581 interrupts = <67>;
582 clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
583 clock-names = "otg";
584 status = "disabled";
585 };
586 };
587};
588
589&systick {
590 clocks = <&rcc 1 0>;
591 status = "okay";
592};
1/*
2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include "armv7-m.dtsi"
44#include <dt-bindings/clock/stm32fx-clock.h>
45#include <dt-bindings/mfd/stm32f7-rcc.h>
46
47/ {
48 #address-cells = <1>;
49 #size-cells = <1>;
50
51 clocks {
52 clk_hse: clk-hse {
53 #clock-cells = <0>;
54 compatible = "fixed-clock";
55 clock-frequency = <0>;
56 };
57
58 clk-lse {
59 #clock-cells = <0>;
60 compatible = "fixed-clock";
61 clock-frequency = <32768>;
62 };
63
64 clk-lsi {
65 #clock-cells = <0>;
66 compatible = "fixed-clock";
67 clock-frequency = <32000>;
68 };
69
70 clk_i2s_ckin: clk-i2s-ckin {
71 #clock-cells = <0>;
72 compatible = "fixed-clock";
73 clock-frequency = <48000000>;
74 };
75 };
76
77 soc {
78 timer2: timer@40000000 {
79 compatible = "st,stm32-timer";
80 reg = <0x40000000 0x400>;
81 interrupts = <28>;
82 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
83 status = "disabled";
84 };
85
86 timers2: timers@40000000 {
87 #address-cells = <1>;
88 #size-cells = <0>;
89 compatible = "st,stm32-timers";
90 reg = <0x40000000 0x400>;
91 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
92 clock-names = "int";
93 status = "disabled";
94
95 pwm {
96 compatible = "st,stm32-pwm";
97 #pwm-cells = <3>;
98 status = "disabled";
99 };
100
101 timer@1 {
102 compatible = "st,stm32-timer-trigger";
103 reg = <1>;
104 status = "disabled";
105 };
106 };
107
108 timer3: timer@40000400 {
109 compatible = "st,stm32-timer";
110 reg = <0x40000400 0x400>;
111 interrupts = <29>;
112 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
113 status = "disabled";
114 };
115
116 timers3: timers@40000400 {
117 #address-cells = <1>;
118 #size-cells = <0>;
119 compatible = "st,stm32-timers";
120 reg = <0x40000400 0x400>;
121 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
122 clock-names = "int";
123 status = "disabled";
124
125 pwm {
126 compatible = "st,stm32-pwm";
127 #pwm-cells = <3>;
128 status = "disabled";
129 };
130
131 timer@2 {
132 compatible = "st,stm32-timer-trigger";
133 reg = <2>;
134 status = "disabled";
135 };
136 };
137
138 timer4: timer@40000800 {
139 compatible = "st,stm32-timer";
140 reg = <0x40000800 0x400>;
141 interrupts = <30>;
142 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
143 status = "disabled";
144 };
145
146 timers4: timers@40000800 {
147 #address-cells = <1>;
148 #size-cells = <0>;
149 compatible = "st,stm32-timers";
150 reg = <0x40000800 0x400>;
151 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
152 clock-names = "int";
153 status = "disabled";
154
155 pwm {
156 compatible = "st,stm32-pwm";
157 #pwm-cells = <3>;
158 status = "disabled";
159 };
160
161 timer@3 {
162 compatible = "st,stm32-timer-trigger";
163 reg = <3>;
164 status = "disabled";
165 };
166 };
167
168 timer5: timer@40000c00 {
169 compatible = "st,stm32-timer";
170 reg = <0x40000c00 0x400>;
171 interrupts = <50>;
172 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
173 };
174
175 timers5: timers@40000c00 {
176 #address-cells = <1>;
177 #size-cells = <0>;
178 compatible = "st,stm32-timers";
179 reg = <0x40000C00 0x400>;
180 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
181 clock-names = "int";
182 status = "disabled";
183
184 pwm {
185 compatible = "st,stm32-pwm";
186 #pwm-cells = <3>;
187 status = "disabled";
188 };
189
190 timer@4 {
191 compatible = "st,stm32-timer-trigger";
192 reg = <4>;
193 status = "disabled";
194 };
195 };
196
197 timer6: timer@40001000 {
198 compatible = "st,stm32-timer";
199 reg = <0x40001000 0x400>;
200 interrupts = <54>;
201 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
202 status = "disabled";
203 };
204
205 timers6: timers@40001000 {
206 #address-cells = <1>;
207 #size-cells = <0>;
208 compatible = "st,stm32-timers";
209 reg = <0x40001000 0x400>;
210 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
211 clock-names = "int";
212 status = "disabled";
213
214 timer@5 {
215 compatible = "st,stm32-timer-trigger";
216 reg = <5>;
217 status = "disabled";
218 };
219 };
220
221 timer7: timer@40001400 {
222 compatible = "st,stm32-timer";
223 reg = <0x40001400 0x400>;
224 interrupts = <55>;
225 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
226 status = "disabled";
227 };
228
229 timers7: timers@40001400 {
230 #address-cells = <1>;
231 #size-cells = <0>;
232 compatible = "st,stm32-timers";
233 reg = <0x40001400 0x400>;
234 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
235 clock-names = "int";
236 status = "disabled";
237
238 timer@6 {
239 compatible = "st,stm32-timer-trigger";
240 reg = <6>;
241 status = "disabled";
242 };
243 };
244
245 timers12: timers@40001800 {
246 #address-cells = <1>;
247 #size-cells = <0>;
248 compatible = "st,stm32-timers";
249 reg = <0x40001800 0x400>;
250 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
251 clock-names = "int";
252 status = "disabled";
253
254 pwm {
255 compatible = "st,stm32-pwm";
256 #pwm-cells = <3>;
257 status = "disabled";
258 };
259
260 timer@11 {
261 compatible = "st,stm32-timer-trigger";
262 reg = <11>;
263 status = "disabled";
264 };
265 };
266
267 timers13: timers@40001c00 {
268 #address-cells = <1>;
269 #size-cells = <0>;
270 compatible = "st,stm32-timers";
271 reg = <0x40001C00 0x400>;
272 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
273 clock-names = "int";
274 status = "disabled";
275
276 pwm {
277 compatible = "st,stm32-pwm";
278 #pwm-cells = <3>;
279 status = "disabled";
280 };
281 };
282
283 timers14: timers@40002000 {
284 #address-cells = <1>;
285 #size-cells = <0>;
286 compatible = "st,stm32-timers";
287 reg = <0x40002000 0x400>;
288 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
289 clock-names = "int";
290 status = "disabled";
291
292 pwm {
293 compatible = "st,stm32-pwm";
294 #pwm-cells = <3>;
295 status = "disabled";
296 };
297 };
298
299 rtc: rtc@40002800 {
300 compatible = "st,stm32-rtc";
301 reg = <0x40002800 0x400>;
302 clocks = <&rcc 1 CLK_RTC>;
303 assigned-clocks = <&rcc 1 CLK_RTC>;
304 assigned-clock-parents = <&rcc 1 CLK_LSE>;
305 interrupt-parent = <&exti>;
306 interrupts = <17 1>;
307 st,syscfg = <&pwrcfg 0x00 0x100>;
308 status = "disabled";
309 };
310
311 usart2: serial@40004400 {
312 compatible = "st,stm32f7-uart";
313 reg = <0x40004400 0x400>;
314 interrupts = <38>;
315 clocks = <&rcc 1 CLK_USART2>;
316 status = "disabled";
317 };
318
319 usart3: serial@40004800 {
320 compatible = "st,stm32f7-uart";
321 reg = <0x40004800 0x400>;
322 interrupts = <39>;
323 clocks = <&rcc 1 CLK_USART3>;
324 status = "disabled";
325 };
326
327 usart4: serial@40004c00 {
328 compatible = "st,stm32f7-uart";
329 reg = <0x40004c00 0x400>;
330 interrupts = <52>;
331 clocks = <&rcc 1 CLK_UART4>;
332 status = "disabled";
333 };
334
335 usart5: serial@40005000 {
336 compatible = "st,stm32f7-uart";
337 reg = <0x40005000 0x400>;
338 interrupts = <53>;
339 clocks = <&rcc 1 CLK_UART5>;
340 status = "disabled";
341 };
342
343 i2c1: i2c@40005400 {
344 compatible = "st,stm32f7-i2c";
345 reg = <0x40005400 0x400>;
346 interrupts = <31>,
347 <32>;
348 resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
349 clocks = <&rcc 1 CLK_I2C1>;
350 #address-cells = <1>;
351 #size-cells = <0>;
352 status = "disabled";
353 };
354
355 i2c2: i2c@40005800 {
356 compatible = "st,stm32f7-i2c";
357 reg = <0x40005800 0x400>;
358 interrupts = <33>,
359 <34>;
360 resets = <&rcc STM32F7_APB1_RESET(I2C2)>;
361 clocks = <&rcc 1 CLK_I2C2>;
362 #address-cells = <1>;
363 #size-cells = <0>;
364 status = "disabled";
365 };
366
367 i2c3: i2c@40005C00 {
368 compatible = "st,stm32f7-i2c";
369 reg = <0x40005C00 0x400>;
370 interrupts = <72>,
371 <73>;
372 resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
373 clocks = <&rcc 1 CLK_I2C3>;
374 #address-cells = <1>;
375 #size-cells = <0>;
376 status = "disabled";
377 };
378
379 i2c4: i2c@40006000 {
380 compatible = "st,stm32f7-i2c";
381 reg = <0x40006000 0x400>;
382 interrupts = <95>,
383 <96>;
384 resets = <&rcc STM32F7_APB1_RESET(I2C4)>;
385 clocks = <&rcc 1 CLK_I2C4>;
386 #address-cells = <1>;
387 #size-cells = <0>;
388 status = "disabled";
389 };
390
391 cec: cec@40006c00 {
392 compatible = "st,stm32-cec";
393 reg = <0x40006C00 0x400>;
394 interrupts = <94>;
395 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
396 clock-names = "cec", "hdmi-cec";
397 status = "disabled";
398 };
399
400 usart7: serial@40007800 {
401 compatible = "st,stm32f7-uart";
402 reg = <0x40007800 0x400>;
403 interrupts = <82>;
404 clocks = <&rcc 1 CLK_UART7>;
405 status = "disabled";
406 };
407
408 usart8: serial@40007c00 {
409 compatible = "st,stm32f7-uart";
410 reg = <0x40007c00 0x400>;
411 interrupts = <83>;
412 clocks = <&rcc 1 CLK_UART8>;
413 status = "disabled";
414 };
415
416 timers1: timers@40010000 {
417 #address-cells = <1>;
418 #size-cells = <0>;
419 compatible = "st,stm32-timers";
420 reg = <0x40010000 0x400>;
421 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
422 clock-names = "int";
423 status = "disabled";
424
425 pwm {
426 compatible = "st,stm32-pwm";
427 #pwm-cells = <3>;
428 status = "disabled";
429 };
430
431 timer@0 {
432 compatible = "st,stm32-timer-trigger";
433 reg = <0>;
434 status = "disabled";
435 };
436 };
437
438 timers8: timers@40010400 {
439 #address-cells = <1>;
440 #size-cells = <0>;
441 compatible = "st,stm32-timers";
442 reg = <0x40010400 0x400>;
443 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
444 clock-names = "int";
445 status = "disabled";
446
447 pwm {
448 compatible = "st,stm32-pwm";
449 #pwm-cells = <3>;
450 status = "disabled";
451 };
452
453 timer@7 {
454 compatible = "st,stm32-timer-trigger";
455 reg = <7>;
456 status = "disabled";
457 };
458 };
459
460 usart1: serial@40011000 {
461 compatible = "st,stm32f7-uart";
462 reg = <0x40011000 0x400>;
463 interrupts = <37>;
464 clocks = <&rcc 1 CLK_USART1>;
465 status = "disabled";
466 };
467
468 usart6: serial@40011400 {
469 compatible = "st,stm32f7-uart";
470 reg = <0x40011400 0x400>;
471 interrupts = <71>;
472 clocks = <&rcc 1 CLK_USART6>;
473 status = "disabled";
474 };
475
476 sdio2: sdio2@40011c00 {
477 compatible = "arm,pl180", "arm,primecell";
478 arm,primecell-periphid = <0x00880180>;
479 reg = <0x40011c00 0x400>;
480 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
481 clock-names = "apb_pclk";
482 interrupts = <103>;
483 max-frequency = <48000000>;
484 status = "disabled";
485 };
486
487 sdio1: sdio1@40012c00 {
488 compatible = "arm,pl180", "arm,primecell";
489 arm,primecell-periphid = <0x00880180>;
490 reg = <0x40012c00 0x400>;
491 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
492 clock-names = "apb_pclk";
493 interrupts = <49>;
494 max-frequency = <48000000>;
495 status = "disabled";
496 };
497
498 syscfg: syscon@40013800 {
499 compatible = "st,stm32-syscfg", "syscon";
500 reg = <0x40013800 0x400>;
501 };
502
503 exti: interrupt-controller@40013c00 {
504 compatible = "st,stm32-exti";
505 interrupt-controller;
506 #interrupt-cells = <2>;
507 reg = <0x40013C00 0x400>;
508 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
509 };
510
511 timers9: timers@40014000 {
512 #address-cells = <1>;
513 #size-cells = <0>;
514 compatible = "st,stm32-timers";
515 reg = <0x40014000 0x400>;
516 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
517 clock-names = "int";
518 status = "disabled";
519
520 pwm {
521 compatible = "st,stm32-pwm";
522 #pwm-cells = <3>;
523 status = "disabled";
524 };
525
526 timer@8 {
527 compatible = "st,stm32-timer-trigger";
528 reg = <8>;
529 status = "disabled";
530 };
531 };
532
533 timers10: timers@40014400 {
534 #address-cells = <1>;
535 #size-cells = <0>;
536 compatible = "st,stm32-timers";
537 reg = <0x40014400 0x400>;
538 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
539 clock-names = "int";
540 status = "disabled";
541
542 pwm {
543 compatible = "st,stm32-pwm";
544 #pwm-cells = <3>;
545 status = "disabled";
546 };
547 };
548
549 timers11: timers@40014800 {
550 #address-cells = <1>;
551 #size-cells = <0>;
552 compatible = "st,stm32-timers";
553 reg = <0x40014800 0x400>;
554 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
555 clock-names = "int";
556 status = "disabled";
557
558 pwm {
559 compatible = "st,stm32-pwm";
560 #pwm-cells = <3>;
561 status = "disabled";
562 };
563 };
564
565 pwrcfg: power-config@40007000 {
566 compatible = "st,stm32-power-config", "syscon";
567 reg = <0x40007000 0x400>;
568 };
569
570 crc: crc@40023000 {
571 compatible = "st,stm32f7-crc";
572 reg = <0x40023000 0x400>;
573 clocks = <&rcc 0 12>;
574 status = "disabled";
575 };
576
577 rcc: rcc@40023800 {
578 #reset-cells = <1>;
579 #clock-cells = <2>;
580 compatible = "st,stm32f746-rcc", "st,stm32-rcc";
581 reg = <0x40023800 0x400>;
582 clocks = <&clk_hse>, <&clk_i2s_ckin>;
583 st,syscfg = <&pwrcfg>;
584 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
585 assigned-clock-rates = <1000000>;
586 };
587
588 dma1: dma-controller@40026000 {
589 compatible = "st,stm32-dma";
590 reg = <0x40026000 0x400>;
591 interrupts = <11>,
592 <12>,
593 <13>,
594 <14>,
595 <15>,
596 <16>,
597 <17>,
598 <47>;
599 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
600 #dma-cells = <4>;
601 status = "disabled";
602 };
603
604 dma2: dma-controller@40026400 {
605 compatible = "st,stm32-dma";
606 reg = <0x40026400 0x400>;
607 interrupts = <56>,
608 <57>,
609 <58>,
610 <59>,
611 <60>,
612 <68>,
613 <69>,
614 <70>;
615 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
616 #dma-cells = <4>;
617 st,mem2mem;
618 status = "disabled";
619 };
620
621 usbotg_hs: usb@40040000 {
622 compatible = "st,stm32f7-hsotg";
623 reg = <0x40040000 0x40000>;
624 interrupts = <77>;
625 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
626 clock-names = "otg";
627 g-rx-fifo-size = <256>;
628 g-np-tx-fifo-size = <32>;
629 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
630 status = "disabled";
631 };
632
633 usbotg_fs: usb@50000000 {
634 compatible = "st,stm32f4x9-fsotg";
635 reg = <0x50000000 0x40000>;
636 interrupts = <67>;
637 clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
638 clock-names = "otg";
639 status = "disabled";
640 };
641 };
642};
643
644&systick {
645 clocks = <&rcc 1 0>;
646 status = "okay";
647};